1//=- AArch64/AArch64MCCodeEmitter.cpp - Convert AArch64 code to machine code =// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the AArch64MCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mccodeemitter" 15#include "MCTargetDesc/AArch64FixupKinds.h" 16#include "MCTargetDesc/AArch64MCExpr.h" 17#include "MCTargetDesc/AArch64MCTargetDesc.h" 18#include "Utils/AArch64BaseInfo.h" 19#include "llvm/MC/MCCodeEmitter.h" 20#include "llvm/MC/MCContext.h" 21#include "llvm/MC/MCInst.h" 22#include "llvm/MC/MCInstrInfo.h" 23#include "llvm/MC/MCRegisterInfo.h" 24#include "llvm/MC/MCSubtargetInfo.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Support/raw_ostream.h" 27 28using namespace llvm; 29 30namespace { 31class AArch64MCCodeEmitter : public MCCodeEmitter { 32 AArch64MCCodeEmitter(const AArch64MCCodeEmitter &) LLVM_DELETED_FUNCTION; 33 void operator=(const AArch64MCCodeEmitter &) LLVM_DELETED_FUNCTION; 34 MCContext &Ctx; 35 36public: 37 AArch64MCCodeEmitter(MCContext &ctx) : Ctx(ctx) {} 38 39 ~AArch64MCCodeEmitter() {} 40 41 unsigned getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, 42 SmallVectorImpl<MCFixup> &Fixups) const; 43 44 unsigned getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx, 45 SmallVectorImpl<MCFixup> &Fixups) const; 46 47 template<int MemSize> 48 unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, 49 SmallVectorImpl<MCFixup> &Fixups) const { 50 return getOffsetUImm12OpValue(MI, OpIdx, Fixups, MemSize); 51 } 52 53 unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, 54 SmallVectorImpl<MCFixup> &Fixups, 55 int MemSize) const; 56 57 unsigned getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx, 58 SmallVectorImpl<MCFixup> &Fixups) const; 59 unsigned getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx, 60 SmallVectorImpl<MCFixup> &Fixups) const; 61 62 63 // Labels are handled mostly the same way: a symbol is needed, and 64 // just gets some fixup attached. 65 template<AArch64::Fixups fixupDesired> 66 unsigned getLabelOpValue(const MCInst &MI, unsigned OpIdx, 67 SmallVectorImpl<MCFixup> &Fixups) const; 68 69 unsigned getLoadLitLabelOpValue(const MCInst &MI, unsigned OpIdx, 70 SmallVectorImpl<MCFixup> &Fixups) const; 71 72 73 unsigned getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, 74 SmallVectorImpl<MCFixup> &Fixups) const; 75 76 77 unsigned getAddressWithFixup(const MCOperand &MO, 78 unsigned FixupKind, 79 SmallVectorImpl<MCFixup> &Fixups) const; 80 81 82 // getBinaryCodeForInstr - TableGen'erated function for getting the 83 // binary encoding for an instruction. 84 uint64_t getBinaryCodeForInstr(const MCInst &MI, 85 SmallVectorImpl<MCFixup> &Fixups) const; 86 87 /// getMachineOpValue - Return binary encoding of operand. If the machine 88 /// operand requires relocation, record the relocation and return zero. 89 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 90 SmallVectorImpl<MCFixup> &Fixups) const; 91 92 93 void EmitByte(unsigned char C, raw_ostream &OS) const { 94 OS << (char)C; 95 } 96 97 void EmitInstruction(uint32_t Val, raw_ostream &OS) const { 98 // Output the constant in little endian byte order. 99 for (unsigned i = 0; i != 4; ++i) { 100 EmitByte(Val & 0xff, OS); 101 Val >>= 8; 102 } 103 } 104 105 106 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 107 SmallVectorImpl<MCFixup> &Fixups) const; 108 109 template<int hasRs, int hasRt2> unsigned 110 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue) const; 111 112 unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue) const; 113 114 unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue) const; 115 116 117}; 118 119} // end anonymous namespace 120 121unsigned AArch64MCCodeEmitter::getAddressWithFixup(const MCOperand &MO, 122 unsigned FixupKind, 123 SmallVectorImpl<MCFixup> &Fixups) const { 124 if (!MO.isExpr()) { 125 // This can occur for manually decoded or constructed MCInsts, but neither 126 // the assembly-parser nor instruction selection will currently produce an 127 // MCInst that's not a symbol reference. 128 assert(MO.isImm() && "Unexpected address requested"); 129 return MO.getImm(); 130 } 131 132 const MCExpr *Expr = MO.getExpr(); 133 MCFixupKind Kind = MCFixupKind(FixupKind); 134 Fixups.push_back(MCFixup::Create(0, Expr, Kind)); 135 136 return 0; 137} 138 139unsigned AArch64MCCodeEmitter:: 140getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, 141 SmallVectorImpl<MCFixup> &Fixups, 142 int MemSize) const { 143 const MCOperand &ImmOp = MI.getOperand(OpIdx); 144 if (ImmOp.isImm()) 145 return ImmOp.getImm(); 146 147 assert(ImmOp.isExpr() && "Unexpected operand type"); 148 const AArch64MCExpr *Expr = cast<AArch64MCExpr>(ImmOp.getExpr()); 149 unsigned FixupKind; 150 151 152 switch (Expr->getKind()) { 153 default: llvm_unreachable("Unexpected operand modifier"); 154 case AArch64MCExpr::VK_AARCH64_LO12: { 155 unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_lo12, 156 AArch64::fixup_a64_ldst16_lo12, 157 AArch64::fixup_a64_ldst32_lo12, 158 AArch64::fixup_a64_ldst64_lo12, 159 AArch64::fixup_a64_ldst128_lo12 }; 160 assert(MemSize <= 16 && "Invalid fixup for operation"); 161 FixupKind = FixupsBySize[Log2_32(MemSize)]; 162 break; 163 } 164 case AArch64MCExpr::VK_AARCH64_GOT_LO12: 165 assert(MemSize == 8 && "Invalid fixup for operation"); 166 FixupKind = AArch64::fixup_a64_ld64_got_lo12_nc; 167 break; 168 case AArch64MCExpr::VK_AARCH64_DTPREL_LO12: { 169 unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_dtprel_lo12, 170 AArch64::fixup_a64_ldst16_dtprel_lo12, 171 AArch64::fixup_a64_ldst32_dtprel_lo12, 172 AArch64::fixup_a64_ldst64_dtprel_lo12 }; 173 assert(MemSize <= 8 && "Invalid fixup for operation"); 174 FixupKind = FixupsBySize[Log2_32(MemSize)]; 175 break; 176 } 177 case AArch64MCExpr::VK_AARCH64_DTPREL_LO12_NC: { 178 unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_dtprel_lo12_nc, 179 AArch64::fixup_a64_ldst16_dtprel_lo12_nc, 180 AArch64::fixup_a64_ldst32_dtprel_lo12_nc, 181 AArch64::fixup_a64_ldst64_dtprel_lo12_nc }; 182 assert(MemSize <= 8 && "Invalid fixup for operation"); 183 FixupKind = FixupsBySize[Log2_32(MemSize)]; 184 break; 185 } 186 case AArch64MCExpr::VK_AARCH64_GOTTPREL_LO12: 187 assert(MemSize == 8 && "Invalid fixup for operation"); 188 FixupKind = AArch64::fixup_a64_ld64_gottprel_lo12_nc; 189 break; 190 case AArch64MCExpr::VK_AARCH64_TPREL_LO12:{ 191 unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_tprel_lo12, 192 AArch64::fixup_a64_ldst16_tprel_lo12, 193 AArch64::fixup_a64_ldst32_tprel_lo12, 194 AArch64::fixup_a64_ldst64_tprel_lo12 }; 195 assert(MemSize <= 8 && "Invalid fixup for operation"); 196 FixupKind = FixupsBySize[Log2_32(MemSize)]; 197 break; 198 } 199 case AArch64MCExpr::VK_AARCH64_TPREL_LO12_NC: { 200 unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_tprel_lo12_nc, 201 AArch64::fixup_a64_ldst16_tprel_lo12_nc, 202 AArch64::fixup_a64_ldst32_tprel_lo12_nc, 203 AArch64::fixup_a64_ldst64_tprel_lo12_nc }; 204 assert(MemSize <= 8 && "Invalid fixup for operation"); 205 FixupKind = FixupsBySize[Log2_32(MemSize)]; 206 break; 207 } 208 case AArch64MCExpr::VK_AARCH64_TLSDESC_LO12: 209 assert(MemSize == 8 && "Invalid fixup for operation"); 210 FixupKind = AArch64::fixup_a64_tlsdesc_ld64_lo12_nc; 211 break; 212 } 213 214 return getAddressWithFixup(ImmOp, FixupKind, Fixups); 215} 216 217unsigned 218AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, 219 SmallVectorImpl<MCFixup> &Fixups) const { 220 const MCOperand &MO = MI.getOperand(OpIdx); 221 if (MO.isImm()) 222 return static_cast<unsigned>(MO.getImm()); 223 224 assert(MO.isExpr()); 225 226 unsigned FixupKind = 0; 227 switch(cast<AArch64MCExpr>(MO.getExpr())->getKind()) { 228 default: llvm_unreachable("Invalid expression modifier"); 229 case AArch64MCExpr::VK_AARCH64_LO12: 230 FixupKind = AArch64::fixup_a64_add_lo12; break; 231 case AArch64MCExpr::VK_AARCH64_DTPREL_HI12: 232 FixupKind = AArch64::fixup_a64_add_dtprel_hi12; break; 233 case AArch64MCExpr::VK_AARCH64_DTPREL_LO12: 234 FixupKind = AArch64::fixup_a64_add_dtprel_lo12; break; 235 case AArch64MCExpr::VK_AARCH64_DTPREL_LO12_NC: 236 FixupKind = AArch64::fixup_a64_add_dtprel_lo12_nc; break; 237 case AArch64MCExpr::VK_AARCH64_TPREL_HI12: 238 FixupKind = AArch64::fixup_a64_add_tprel_hi12; break; 239 case AArch64MCExpr::VK_AARCH64_TPREL_LO12: 240 FixupKind = AArch64::fixup_a64_add_tprel_lo12; break; 241 case AArch64MCExpr::VK_AARCH64_TPREL_LO12_NC: 242 FixupKind = AArch64::fixup_a64_add_tprel_lo12_nc; break; 243 case AArch64MCExpr::VK_AARCH64_TLSDESC_LO12: 244 FixupKind = AArch64::fixup_a64_tlsdesc_add_lo12_nc; break; 245 } 246 247 return getAddressWithFixup(MO, FixupKind, Fixups); 248} 249 250unsigned 251AArch64MCCodeEmitter::getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx, 252 SmallVectorImpl<MCFixup> &Fixups) const { 253 254 const MCOperand &MO = MI.getOperand(OpIdx); 255 if (MO.isImm()) 256 return static_cast<unsigned>(MO.getImm()); 257 258 assert(MO.isExpr()); 259 260 unsigned Modifier = AArch64MCExpr::VK_AARCH64_None; 261 if (const AArch64MCExpr *Expr = dyn_cast<AArch64MCExpr>(MO.getExpr())) 262 Modifier = Expr->getKind(); 263 264 unsigned FixupKind = 0; 265 switch(Modifier) { 266 case AArch64MCExpr::VK_AARCH64_None: 267 FixupKind = AArch64::fixup_a64_adr_prel_page; 268 break; 269 case AArch64MCExpr::VK_AARCH64_GOT: 270 FixupKind = AArch64::fixup_a64_adr_prel_got_page; 271 break; 272 case AArch64MCExpr::VK_AARCH64_GOTTPREL: 273 FixupKind = AArch64::fixup_a64_adr_gottprel_page; 274 break; 275 case AArch64MCExpr::VK_AARCH64_TLSDESC: 276 FixupKind = AArch64::fixup_a64_tlsdesc_adr_page; 277 break; 278 default: 279 llvm_unreachable("Unknown symbol reference kind for ADRP instruction"); 280 } 281 282 return getAddressWithFixup(MO, FixupKind, Fixups); 283} 284 285unsigned 286AArch64MCCodeEmitter::getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx, 287 SmallVectorImpl<MCFixup> &Fixups) const { 288 289 const MCOperand &MO = MI.getOperand(OpIdx); 290 assert(MO.isImm() && "Only immediate expected for shift"); 291 292 return ((32 - MO.getImm()) & 0x1f) | (31 - MO.getImm()) << 6; 293} 294 295unsigned 296AArch64MCCodeEmitter::getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx, 297 SmallVectorImpl<MCFixup> &Fixups) const { 298 299 const MCOperand &MO = MI.getOperand(OpIdx); 300 assert(MO.isImm() && "Only immediate expected for shift"); 301 302 return ((64 - MO.getImm()) & 0x3f) | (63 - MO.getImm()) << 6; 303} 304 305 306template<AArch64::Fixups fixupDesired> unsigned 307AArch64MCCodeEmitter::getLabelOpValue(const MCInst &MI, 308 unsigned OpIdx, 309 SmallVectorImpl<MCFixup> &Fixups) const { 310 const MCOperand &MO = MI.getOperand(OpIdx); 311 312 if (MO.isExpr()) 313 return getAddressWithFixup(MO, fixupDesired, Fixups); 314 315 assert(MO.isImm()); 316 return MO.getImm(); 317} 318 319unsigned 320AArch64MCCodeEmitter::getLoadLitLabelOpValue(const MCInst &MI, 321 unsigned OpIdx, 322 SmallVectorImpl<MCFixup> &Fixups) const { 323 const MCOperand &MO = MI.getOperand(OpIdx); 324 325 if (MO.isImm()) 326 return MO.getImm(); 327 328 assert(MO.isExpr()); 329 330 unsigned FixupKind; 331 if (isa<AArch64MCExpr>(MO.getExpr())) { 332 assert(dyn_cast<AArch64MCExpr>(MO.getExpr())->getKind() 333 == AArch64MCExpr::VK_AARCH64_GOTTPREL 334 && "Invalid symbol modifier for literal load"); 335 FixupKind = AArch64::fixup_a64_ld_gottprel_prel19; 336 } else { 337 FixupKind = AArch64::fixup_a64_ld_prel; 338 } 339 340 return getAddressWithFixup(MO, FixupKind, Fixups); 341} 342 343 344unsigned 345AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, 346 const MCOperand &MO, 347 SmallVectorImpl<MCFixup> &Fixups) const { 348 if (MO.isReg()) { 349 return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()); 350 } else if (MO.isImm()) { 351 return static_cast<unsigned>(MO.getImm()); 352 } 353 354 llvm_unreachable("Unable to encode MCOperand!"); 355 return 0; 356} 357 358unsigned 359AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, 360 SmallVectorImpl<MCFixup> &Fixups) const { 361 const MCOperand &UImm16MO = MI.getOperand(OpIdx); 362 const MCOperand &ShiftMO = MI.getOperand(OpIdx + 1); 363 364 unsigned Result = static_cast<unsigned>(ShiftMO.getImm()) << 16; 365 366 if (UImm16MO.isImm()) { 367 Result |= UImm16MO.getImm(); 368 return Result; 369 } 370 371 const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr()); 372 AArch64::Fixups requestedFixup; 373 switch (A64E->getKind()) { 374 default: llvm_unreachable("unexpected expression modifier"); 375 case AArch64MCExpr::VK_AARCH64_ABS_G0: 376 requestedFixup = AArch64::fixup_a64_movw_uabs_g0; break; 377 case AArch64MCExpr::VK_AARCH64_ABS_G0_NC: 378 requestedFixup = AArch64::fixup_a64_movw_uabs_g0_nc; break; 379 case AArch64MCExpr::VK_AARCH64_ABS_G1: 380 requestedFixup = AArch64::fixup_a64_movw_uabs_g1; break; 381 case AArch64MCExpr::VK_AARCH64_ABS_G1_NC: 382 requestedFixup = AArch64::fixup_a64_movw_uabs_g1_nc; break; 383 case AArch64MCExpr::VK_AARCH64_ABS_G2: 384 requestedFixup = AArch64::fixup_a64_movw_uabs_g2; break; 385 case AArch64MCExpr::VK_AARCH64_ABS_G2_NC: 386 requestedFixup = AArch64::fixup_a64_movw_uabs_g2_nc; break; 387 case AArch64MCExpr::VK_AARCH64_ABS_G3: 388 requestedFixup = AArch64::fixup_a64_movw_uabs_g3; break; 389 case AArch64MCExpr::VK_AARCH64_SABS_G0: 390 requestedFixup = AArch64::fixup_a64_movw_sabs_g0; break; 391 case AArch64MCExpr::VK_AARCH64_SABS_G1: 392 requestedFixup = AArch64::fixup_a64_movw_sabs_g1; break; 393 case AArch64MCExpr::VK_AARCH64_SABS_G2: 394 requestedFixup = AArch64::fixup_a64_movw_sabs_g2; break; 395 case AArch64MCExpr::VK_AARCH64_DTPREL_G2: 396 requestedFixup = AArch64::fixup_a64_movw_dtprel_g2; break; 397 case AArch64MCExpr::VK_AARCH64_DTPREL_G1: 398 requestedFixup = AArch64::fixup_a64_movw_dtprel_g1; break; 399 case AArch64MCExpr::VK_AARCH64_DTPREL_G1_NC: 400 requestedFixup = AArch64::fixup_a64_movw_dtprel_g1_nc; break; 401 case AArch64MCExpr::VK_AARCH64_DTPREL_G0: 402 requestedFixup = AArch64::fixup_a64_movw_dtprel_g0; break; 403 case AArch64MCExpr::VK_AARCH64_DTPREL_G0_NC: 404 requestedFixup = AArch64::fixup_a64_movw_dtprel_g0_nc; break; 405 case AArch64MCExpr::VK_AARCH64_GOTTPREL_G1: 406 requestedFixup = AArch64::fixup_a64_movw_gottprel_g1; break; 407 case AArch64MCExpr::VK_AARCH64_GOTTPREL_G0_NC: 408 requestedFixup = AArch64::fixup_a64_movw_gottprel_g0_nc; break; 409 case AArch64MCExpr::VK_AARCH64_TPREL_G2: 410 requestedFixup = AArch64::fixup_a64_movw_tprel_g2; break; 411 case AArch64MCExpr::VK_AARCH64_TPREL_G1: 412 requestedFixup = AArch64::fixup_a64_movw_tprel_g1; break; 413 case AArch64MCExpr::VK_AARCH64_TPREL_G1_NC: 414 requestedFixup = AArch64::fixup_a64_movw_tprel_g1_nc; break; 415 case AArch64MCExpr::VK_AARCH64_TPREL_G0: 416 requestedFixup = AArch64::fixup_a64_movw_tprel_g0; break; 417 case AArch64MCExpr::VK_AARCH64_TPREL_G0_NC: 418 requestedFixup = AArch64::fixup_a64_movw_tprel_g0_nc; break; 419 } 420 421 return Result | getAddressWithFixup(UImm16MO, requestedFixup, Fixups); 422} 423 424template<int hasRs, int hasRt2> unsigned 425AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI, 426 unsigned EncodedValue) const { 427 if (!hasRs) EncodedValue |= 0x001F0000; 428 if (!hasRt2) EncodedValue |= 0x00007C00; 429 430 return EncodedValue; 431} 432 433unsigned 434AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue) const { 435 // If one of the signed fixup kinds is applied to a MOVZ instruction, the 436 // eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's 437 // job to ensure that any bits possibly affected by this are 0. This means we 438 // must zero out bit 30 (essentially emitting a MOVN). 439 MCOperand UImm16MO = MI.getOperand(1); 440 441 // Nothing to do if there's no fixup. 442 if (UImm16MO.isImm()) 443 return EncodedValue; 444 445 const AArch64MCExpr *A64E = cast<AArch64MCExpr>(UImm16MO.getExpr()); 446 switch (A64E->getKind()) { 447 case AArch64MCExpr::VK_AARCH64_SABS_G0: 448 case AArch64MCExpr::VK_AARCH64_SABS_G1: 449 case AArch64MCExpr::VK_AARCH64_SABS_G2: 450 case AArch64MCExpr::VK_AARCH64_DTPREL_G2: 451 case AArch64MCExpr::VK_AARCH64_DTPREL_G1: 452 case AArch64MCExpr::VK_AARCH64_DTPREL_G0: 453 case AArch64MCExpr::VK_AARCH64_GOTTPREL_G1: 454 case AArch64MCExpr::VK_AARCH64_TPREL_G2: 455 case AArch64MCExpr::VK_AARCH64_TPREL_G1: 456 case AArch64MCExpr::VK_AARCH64_TPREL_G0: 457 return EncodedValue & ~(1u << 30); 458 default: 459 // Nothing to do for an unsigned fixup. 460 return EncodedValue; 461 } 462 463 llvm_unreachable("Should have returned by now"); 464} 465 466unsigned 467AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI, 468 unsigned EncodedValue) const { 469 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31 470 // (i.e. all bits 1) but is ignored by the processor. 471 EncodedValue |= 0x1f << 10; 472 return EncodedValue; 473} 474 475MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII, 476 const MCRegisterInfo &MRI, 477 const MCSubtargetInfo &STI, 478 MCContext &Ctx) { 479 return new AArch64MCCodeEmitter(Ctx); 480} 481 482void AArch64MCCodeEmitter:: 483EncodeInstruction(const MCInst &MI, raw_ostream &OS, 484 SmallVectorImpl<MCFixup> &Fixups) const { 485 if (MI.getOpcode() == AArch64::TLSDESCCALL) { 486 // This is a directive which applies an R_AARCH64_TLSDESC_CALL to the 487 // following (BLR) instruction. It doesn't emit any code itself so it 488 // doesn't go through the normal TableGenerated channels. 489 MCFixupKind Fixup = MCFixupKind(AArch64::fixup_a64_tlsdesc_call); 490 const MCExpr *Expr; 491 Expr = AArch64MCExpr::CreateTLSDesc(MI.getOperand(0).getExpr(), Ctx); 492 Fixups.push_back(MCFixup::Create(0, Expr, Fixup)); 493 return; 494 } 495 496 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); 497 498 EmitInstruction(Binary, OS); 499} 500 501 502#include "AArch64GenMCCodeEmitter.inc" 503