131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 3c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// The LLVM Compiler Infrastructure 4c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 5c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file is distributed under the University of Illinois Open Source 6c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// License. See LICENSE.TXT for details. 7c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 8c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 9c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 10c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file contains the base ARM implementation of TargetRegisterInfo class. 11c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 12c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 13c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 14c1f6f42049696e7357fb4837e1b25dabbaed3fe6Craig Topper#include "ARMBaseRegisterInfo.h" 15c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARM.h" 16db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin#include "ARMBaseInstrInfo.h" 1716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "ARMFrameLowering.h" 18c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMMachineFunctionInfo.h" 19c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMSubtarget.h" 20ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 21d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/BitVector.h" 22d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/SmallVector.h" 23c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineConstantPool.h" 24c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 25c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFunction.h" 26c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 27c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineRegisterInfo.h" 28c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/RegisterScavenging.h" 29303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen#include "llvm/CodeGen/VirtRegMap.h" 300b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Constants.h" 310b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/DerivedTypes.h" 320b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Function.h" 330b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/LLVMContext.h" 343dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach#include "llvm/Support/Debug.h" 35ab7c09b6b6f4516a631fd6788918c237c83939afTorok Edwin#include "llvm/Support/ErrorHandling.h" 36dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 3716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "llvm/Target/TargetFrameLowering.h" 38c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetMachine.h" 39c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetOptions.h" 4073f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng 4173f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_TARGET_DESC 42a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "ARMGenRegisterInfo.inc" 43c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 441b4886dd00578038c0ca70b3bab97382b89def26Evan Chengusing namespace llvm; 451b4886dd00578038c0ca70b3bab97382b89def26Evan Cheng 46db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 47c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const ARMSubtarget &sti) 48fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), TII(tii), STI(sti), 4965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 5065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach BasePtr(ARM::R6) { 51c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 52c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 53015f228861ef9b337366f92f637d4e8d624bb006Craig Topperconst uint16_t* 54c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 55e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher bool ghcCall = false; 56e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher 57e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher if (MF) { 58e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher const Function *F = MF->getFunction(); 59e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 60e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher } 61e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher 62e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher if (ghcCall) { 63e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher return CSR_GHC_SaveList; 64e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher } 65e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher else { 66afb3b5ebe61b480527de86311d2a0770fc857d38Evan Cheng return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 67afb3b5ebe61b480527de86311d2a0770fc857d38Evan Cheng ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 68e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher } 693ee7d15284f188672e9e429e9e5cf7b870698677Jakob Stoklund Olesen} 70c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 713ee7d15284f188672e9e429e9e5cf7b870698677Jakob Stoklund Olesenconst uint32_t* 723ee7d15284f188672e9e429e9e5cf7b870698677Jakob Stoklund OlesenARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 73afb3b5ebe61b480527de86311d2a0770fc857d38Evan Cheng return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 74afb3b5ebe61b480527de86311d2a0770fc857d38Evan Cheng ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 75c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 76c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 77e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosierconst uint32_t* 78e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad RosierARMBaseRegisterInfo::getNoPreservedMask() const { 79e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier return CSR_NoRegs_RegMask; 80e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier} 81e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier 829631864688c593711f82bb8d21f8b724c628d786Jim GrosbachBitVector ARMBaseRegisterInfo:: 839631864688c593711f82bb8d21f8b724c628d786Jim GrosbachgetReservedRegs(const MachineFunction &MF) const { 8416c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 85d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 867a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner // FIXME: avoid re-calculating this every time. 87c140c4803dc3e10e08138670829bc0494986abe9David Goodwin BitVector Reserved(getNumRegs()); 88c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::SP); 89c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::PC); 904f92b5e6163b16d63eb63269c2aec670b55ea19aLang Hames Reserved.set(ARM::FPSCR); 91d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF)) 92c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(FramePtr); 9365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (hasBasePointer(MF)) 9465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach Reserved.set(BasePtr); 95c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Some targets reserve R9. 96c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isR9Reserved()) 97c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::R9); 983b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen // Reserve D16-D31 if the subtarget doesn't support them. 993b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen if (!STI.hasVFP3() || STI.hasD16()) { 1003b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen assert(ARM::D31 == ARM::D16 + 15); 1013b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen for (unsigned i = 0; i != 16; ++i) 1023b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen Reserved.set(ARM::D16 + i); 1033b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen } 104cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 105cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 106cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 107cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen if (Reserved.test(*SI)) Reserved.set(*I); 108cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen 109c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reserved; 110c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 111c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 112c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesenconst TargetRegisterClass* 113c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund OlesenARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 114c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen const { 115c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen const TargetRegisterClass *Super = RC; 116c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 117c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen do { 118c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen switch (Super->getID()) { 119c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::GPRRegClassID: 120c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::SPRRegClassID: 121c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::DPRRegClassID: 122c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QPRRegClassID: 123c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QQPRRegClassID: 124c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QQQQPRRegClassID: 125cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen case ARM::GPRPairRegClassID: 126c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return Super; 127c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 128c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen Super = *I++; 129c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } while (Super); 130c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 131c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen} 132b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 1334f54c1293af174a8002db20faf7b4f82ba4e8514Evan Chengconst TargetRegisterClass * 134397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund OlesenARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 135397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const { 136420761a0f193e87d08ee1c51b26bba23ab4bac7fCraig Topper return &ARM::GPRRegClass; 137c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 138be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 139342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Chengconst TargetRegisterClass * 140342e3161d9dd4fa485b47788aa0266f9c91c3832Evan ChengARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 141342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng if (RC == &ARM::CCRRegClass) 142342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng return 0; // Can't copy CCR registers. 143342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng return RC; 144342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng} 145342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng 146be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarichunsigned 147be2119e8e2bc7006cfd638a24367acbfda625d16Cameron ZwarichARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 148be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 149be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 150be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 151be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich switch (RC->getID()) { 152be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich default: 153be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 154be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::tGPRRegClassID: 155be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return TFI->hasFP(MF) ? 4 : 5; 156be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::GPRRegClassID: { 157be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich unsigned FP = TFI->hasFP(MF) ? 1 : 0; 158be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 159be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 160be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 161be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::DPRRegClassID: 162be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 32 - 10; 163be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 164be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich} 165c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 166303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen// Get the other register in a GPRPair. 167303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesenstatic unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 168303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 169303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (ARM::GPRPairRegClass.contains(*Supers)) 170303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 171303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return 0; 172303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen} 173303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 174303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen// Resolve the RegPairEven / RegPairOdd register allocator hints. 175303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesenvoid 176303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund OlesenARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 177303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen ArrayRef<MCPhysReg> Order, 178303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen SmallVectorImpl<MCPhysReg> &Hints, 179303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const MachineFunction &MF, 180303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const VirtRegMap *VRM) const { 181303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MF.getRegInfo(); 182303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 183303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 184303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Odd; 185303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen switch (Hint.first) { 186303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen case ARMRI::RegPairEven: 187303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Odd = 0; 188303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen break; 189303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen case ARMRI::RegPairOdd: 190303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Odd = 1; 191303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen break; 192303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen default: 193303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 194303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return; 195303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 196303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 197303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // This register should preferably be even (Odd == 0) or odd (Odd == 1). 198303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Check if the other part of the pair has already been assigned, and provide 199303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // the paired register as the first hint. 200303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned PairedPhys = 0; 201303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (VRM && VRM->hasPhys(Hint.second)) { 202303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 203303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (PairedPhys && MRI.isReserved(PairedPhys)) 204303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen PairedPhys = 0; 205303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 206303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 207303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // First prefer the paired physreg. 2084fd4c91c40fa40ae4cd671b03056de8c3c961046Jim Grosbach if (PairedPhys && 2094fd4c91c40fa40ae4cd671b03056de8c3c961046Jim Grosbach std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 210303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Hints.push_back(PairedPhys); 211303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 212303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Then prefer even or odd registers. 213303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen for (unsigned I = 0, E = Order.size(); I != E; ++I) { 214303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Reg = Order[I]; 215303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 216303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen continue; 217303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Don't provide hints that are paired to a reserved register. 218303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Paired = getPairedGPR(Reg, !Odd, this); 219303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (!Paired || MRI.isReserved(Paired)) 220303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen continue; 221303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Hints.push_back(Reg); 222303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 223303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen} 224303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 225c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 226c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 227c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFunction &MF) const { 228c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineRegisterInfo *MRI = &MF.getRegInfo(); 229c140c4803dc3e10e08138670829bc0494986abe9David Goodwin std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 230c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 231c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.first == (unsigned)ARMRI::RegPairEven) && 232c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen TargetRegisterInfo::isVirtualRegister(Hint.second)) { 233c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If 'Reg' is one of the even / odd register pair and it's now changed 234c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // (e.g. coalesced) into a different register. The other register of the 235c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // pair allocation hint must be updated to reflect the relationship 236c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // change. 237c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned OtherReg = Hint.second; 238c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint = MRI->getRegAllocationHint(OtherReg); 239c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Hint.second == Reg) 240c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Make sure the pair has not already divorced. 241c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 242c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 243c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 244f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 245f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilsonbool 246f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob WilsonARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 247f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson // CortexA9 has a Write-after-write hazard for NEON registers. 248616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (!STI.isLikeA9()) 249f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 250f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 251f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson switch (RC->getID()) { 252f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::DPRRegClassID: 253f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::DPR_8RegClassID: 254f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::DPR_VFP2RegClassID: 255f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::QPRRegClassID: 256f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::QPR_8RegClassID: 257f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::QPR_VFP2RegClassID: 258f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::SPRRegClassID: 259f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::SPR_8RegClassID: 260f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson // Avoid reusing S, D, and Q registers. 261f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson // Don't increase register pressure for QQ and QQQQ. 262f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return true; 263f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson default: 264f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 265f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson } 266f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson} 267c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 26865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachbool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 2696a8700301ca6f8f2f5f787c8d1f5206a7dfceed6Daniel Dunbar const MachineFrameInfo *MFI = MF.getFrameInfo(); 2701755b3964f931bdd6fa9b4c0138f666ccfa12acaJim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2710f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 27265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 2730f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // When outgoing call frames are so large that we adjust the stack pointer 2740f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // around the call, we can no longer use the stack pointer to reach the 2750f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // emergency spill slot. 276055a8127c9ffee287807fe7cc1b115d0f40162b0Bob Wilson if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 27765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 27865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 27965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 28065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // negative range for ldr/str (255), and thumb1 is positive offsets only. 28165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // It's going to be better to use the SP or Base Pointer instead. When there 28265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // are variable sized objects, we can't reference off of the SP, so we 28365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // reserve a Base Pointer. 28465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 28565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // Conservatively estimate whether the negative offset from the frame 28665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // pointer will be sufficient to reach. If a function has a smallish 28765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // frame, it's less likely to have lots of spills and callee saved 28865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // space, so it's all more likely to be within range of the frame pointer. 28965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // If it's wrong, the scavenger will still enable access to work, it just 29065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // won't be optimal. 29165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 29265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 29365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 29465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach } 29565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 29665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 29765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach} 29865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 29965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachbool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 30054f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen const MachineRegisterInfo *MRI = &MF.getRegInfo(); 3016690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 30230c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // We can't realign the stack if: 30330c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // 1. Dynamic stack realignment is explicitly disabled, 3046690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 3056690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier // 3. There are VLAs in the function and the base pointer is disabled. 30654f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen if (!MF.getTarget().Options.RealignStack) 30754f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 30854f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen if (AFI->isThumb1OnlyFunction()) 30954f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 31054f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // Stack realignment requires a frame pointer. If we already started 31154f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // register allocation with frame pointer elimination, it is too late now. 31254f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen if (!MRI->canReserveReg(FramePtr)) 31354f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 314aaa1e2f820e61a2f4b878d97599b3ca093bc96edBob Wilson // We may also need a base pointer if there are dynamic allocas or stack 315aaa1e2f820e61a2f4b878d97599b3ca093bc96edBob Wilson // pointer adjustments around calls. 316aaa1e2f820e61a2f4b878d97599b3ca093bc96edBob Wilson if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 31754f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return true; 31854f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // A base pointer is required and allowed. Check that it isn't too late to 31954f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // reserve it. 32054f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return MRI->canReserveReg(BasePtr); 321e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach} 322e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach 3233dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbachbool ARMBaseRegisterInfo:: 3243dab2778571b5bb00b35a0adcb7011dc85158bebJim GrosbachneedsStackRealignment(const MachineFunction &MF) const { 3253dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 326d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher const Function *F = MF.getFunction(); 32716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 3286765834754cbb3cb0f15b4b15e98c5e73fa50066Bill Wendling bool requiresRealignment = 3296765834754cbb3cb0f15b4b15e98c5e73fa50066Bill Wendling ((MFI->getMaxAlignment() > StackAlign) || 330831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 331831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling Attribute::StackAlignment)); 3325c33f5bf67f61e3a1addda6de735d28d550dd0ebJim Grosbach 333d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher return requiresRealignment && canRealignStack(MF); 3343dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach} 3353dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 3369631864688c593711f82bb8d21f8b724c628d786Jim Grosbachbool ARMBaseRegisterInfo:: 3379631864688c593711f82bb8d21f8b724c628d786Jim GrosbachcannotEliminateFrame(const MachineFunction &MF) const { 33898a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 3398a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 34098a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return true; 34131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 34231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach || needsStackRealignment(MF); 34398a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng} 34498a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng 3455c33f5bf67f61e3a1addda6de735d28d550dd0ebJim Grosbachunsigned 3463f2bf85d14759cc4b28a86805f566ac805a54d00David GreeneARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 34716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 348d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 349d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF)) 350c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return FramePtr; 351c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::SP; 352c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 353c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 354c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 355c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception register"); 356c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 357c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 358c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 359c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception handler register"); 360c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 361c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 362db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// emitLoadConstPool - Emits a load from constpool to materialize the 363db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// specified immediate. 364db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 365db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitLoadConstPool(MachineBasicBlock &MBB, 366db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 36777521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin DebugLoc dl, 368378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, int Val, 369db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred, 3703daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov unsigned PredReg, unsigned MIFlags) const { 371db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFunction &MF = *MBB.getParent(); 372db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineConstantPool *ConstantPool = MF.getConstantPool(); 37346510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Constant *C = 3741d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 375db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 376db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 377378445303b10b092a898a75131141a8259cff50bEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 378378445303b10b092a898a75131141a8259cff50bEvan Cheng .addReg(DestReg, getDefRegState(true), SubIdx) 379db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addConstantPoolIndex(Idx) 3803daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov .addImm(0).addImm(Pred).addReg(PredReg) 3813daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov .setMIFlags(MIFlags); 382db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 383db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 384db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 385db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinrequiresRegisterScavenging(const MachineFunction &MF) const { 386db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 387db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 38841fff8c19ab6d8e28f5362481c184ad628f8c704Jim Grosbach 3897e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbachbool ARMBaseRegisterInfo:: 3906a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston GurdtrackLivenessAfterRegAlloc(const MachineFunction &MF) const { 3916a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return true; 3926a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd} 3936a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 3946a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurdbool ARMBaseRegisterInfo:: 3957e831db1d4f5dc51ca6526739cf41e59895c5c20Jim GrosbachrequiresFrameIndexScavenging(const MachineFunction &MF) const { 396ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach return true; 3977e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach} 398db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 399a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbachbool ARMBaseRegisterInfo:: 400a273442891ae20fd8192526132e3819ea9e5eda9Jim GrosbachrequiresVirtualBaseRegisters(const MachineFunction &MF) const { 401c8cd8aa9d8582d2632db8fee8b2932efcdec34f1Jim Grosbach return true; 402a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach} 403a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 404e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbachint64_t ARMBaseRegisterInfo:: 4051ab3f16f06698596716593a30545799688acccd7Jim GrosbachgetFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 406e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 407e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 40890f20044ade3712c8b0c3f4ebe47d57ad15ae6ceChad Rosier int64_t InstrOffs = 0; 409e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int Scale = 1; 410e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned ImmIdx = 0; 4111ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 412e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i8: 413e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i12: 4143e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: 415e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(Idx+1).getImm(); 416e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 1; 417e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 418e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode5: { 419e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach // VFP address mode. 420e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach const MachineOperand &OffOp = MI->getOperand(Idx+1); 421f78ee6316bc755779920ac207edc27a89c0bd2f9Jim Grosbach InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 422e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 423e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 424e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 425e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 426e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 427e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode2: { 428e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 429e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 430e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 431e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 432e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 433e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 434e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode3: { 435e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 436e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 437e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 438e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 439e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 440e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 441e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT1_s: { 442e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+1; 443e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(ImmIdx).getImm(); 444e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 445e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 446e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 447e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach default: 448e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach llvm_unreachable("Unsupported addressing mode!"); 449e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 450e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 451e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return InstrOffs * Scale; 452e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach} 453e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 4548708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// needsFrameBaseReg - Returns true if the instruction's frame index 4558708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// reference would be better served by a base register other than FP 4568708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// or SP. Used by LocalStackFrameAllocation to determine which frame index 4578708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// references it should create new base registers for. 4588708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbachbool ARMBaseRegisterInfo:: 4593197380143cdc18837722129ac888528b9fbfc2bJim GrosbachneedsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 4603197380143cdc18837722129ac888528b9fbfc2bJim Grosbach for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 4613197380143cdc18837722129ac888528b9fbfc2bJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 4623197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 4638708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 4648708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // It's the load/store FI references that cause issues, as it can be difficult 4658708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to materialize the offset if it won't fit in the literal field. Estimate 4668708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // based on the size of the local frame and some conservative assumptions 4678708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // about the rest of the stack frame (note, this is pre-regalloc, so 4688708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // we don't know everything for certain yet) whether this offset is likely 4698708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to be out of range of the immediate. Return true if so. 4708708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 471cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // We only generate virtual base registers for loads and stores, so 472cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // return false for everything else. 4738708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach unsigned Opc = MI->getOpcode(); 4748708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach switch (Opc) { 475cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 4767e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 477cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRi12: case ARM::t2LDRi8: 478cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2STRi12: case ARM::t2STRi8: 4798708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VLDRS: case ARM::VLDRD: 4808708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VSTRS: case ARM::VSTRD: 48174d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach case ARM::tSTRspi: case ARM::tLDRspi: 482cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach break; 4838708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach default: 4848708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 4858708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 486cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 487cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // Without a virtual base register, if the function has variable sized 488cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // objects, all fixed-size local references will be via the frame pointer, 4893197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Approximate the offset and see if it's legal for the instruction. 4903197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Note that the incoming offset is based on the SP value at function entry, 4913197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // so it'll be negative. 4923197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFunction &MF = *MI->getParent()->getParent(); 49316c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 4943197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 4953197380143cdc18837722129ac888528b9fbfc2bJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 4963197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 4973197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the frame pointer. 4983197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Conservatively assume all callee-saved registers get pushed. R4-R6 4993197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // will be earlier than the FP, so we ignore those. 5003197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // R7, LR 5013197380143cdc18837722129ac888528b9fbfc2bJim Grosbach int64_t FPOffset = Offset - 8; 5023197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 5033197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 5043197380143cdc18837722129ac888528b9fbfc2bJim Grosbach FPOffset -= 80; 5053197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the stack pointer. 506c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // The incoming offset is relating to the SP at the start of the function, 507c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // but when we access the local it'll be relative to the SP after local 508c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // allocation, so adjust our SP-relative offset by that allocation size. 5093197380143cdc18837722129ac888528b9fbfc2bJim Grosbach Offset = -Offset; 510c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach Offset += MFI->getLocalFrameSize(); 5113197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Assume that we'll have at least some spill slots allocated. 5123197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This is a total SWAG number. We should run some statistics 5133197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // and pick a real one. 5143197380143cdc18837722129ac888528b9fbfc2bJim Grosbach Offset += 128; // 128 bytes of spill slots 5153197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 5163197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // If there is a frame pointer, try using it. 5173197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The FP is only available if there is no dynamic realignment. We 5183197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // don't know for sure yet whether we'll need that, so we guess based 5193197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // on whether there are any local variables that would trigger it. 52016c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned StackAlign = TFI->getStackAlignment(); 521d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF) && 5223197380143cdc18837722129ac888528b9fbfc2bJim Grosbach !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 5233197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (isFrameOffsetLegal(MI, FPOffset)) 5243197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 5253197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 5263197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // If we can reference via the stack pointer, try that. 5273197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This (and the code that resolves the references) can be improved 5283197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // to only disallow SP relative references in the live range of 5293197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // the VLA(s). In practice, it's unclear how much difference that 5303197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // would make, but it may be worth doing. 5313197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 5323197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 533cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 5343197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The offset likely isn't legal, we want to allocate a virtual base register. 535cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach return true; 5368708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach} 5378708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 538976ef86689ed065361a748f81c44ca3510af2202Bill Wendling/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 539976ef86689ed065361a748f81c44ca3510af2202Bill Wendling/// be a pointer to FrameIdx at the beginning of the basic block. 540dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbachvoid ARMBaseRegisterInfo:: 541976ef86689ed065361a748f81c44ca3510af2202Bill WendlingmaterializeFrameBaseRegister(MachineBasicBlock *MBB, 542976ef86689ed065361a748f81c44ca3510af2202Bill Wendling unsigned BaseReg, int FrameIdx, 543976ef86689ed065361a748f81c44ca3510af2202Bill Wendling int64_t Offset) const { 544976ef86689ed065361a748f81c44ca3510af2202Bill Wendling ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 54574d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 54674d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 547dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 548976ef86689ed065361a748f81c44ca3510af2202Bill Wendling MachineBasicBlock::iterator Ins = MBB->begin(); 549976ef86689ed065361a748f81c44ca3510af2202Bill Wendling DebugLoc DL; // Defaults to "unknown" 550976ef86689ed065361a748f81c44ca3510af2202Bill Wendling if (Ins != MBB->end()) 551976ef86689ed065361a748f81c44ca3510af2202Bill Wendling DL = Ins->getDebugLoc(); 552976ef86689ed065361a748f81c44ca3510af2202Bill Wendling 553e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = TII.get(ADDriOpc); 55421803721d538255e4d223c29b6c8d3c9e93d4d86Cameron Zwarich MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 555397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const MachineFunction &MF = *MBB->getParent(); 556397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 55721803721d538255e4d223c29b6c8d3c9e93d4d86Cameron Zwarich 5585b81584f7403ffdb9cc6babaaeb0411c080e0f81Jim Grosbach MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 5595b81584f7403ffdb9cc6babaaeb0411c080e0f81Jim Grosbach .addFrameIndex(FrameIdx).addImm(Offset)); 560976ef86689ed065361a748f81c44ca3510af2202Bill Wendling 56174d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach if (!AFI->isThumb1OnlyFunction()) 5625b81584f7403ffdb9cc6babaaeb0411c080e0f81Jim Grosbach AddDefaultCC(MIB); 563dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 564dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 565dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbachvoid 566dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim GrosbachARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 567dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned BaseReg, int64_t Offset) const { 568dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineInstr &MI = *I; 569dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineBasicBlock &MBB = *MI.getParent(); 570dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineFunction &MF = *MBB.getParent(); 571dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 572dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach int Off = Offset; // ARM doesn't need the general 64-bit offsets 573dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned i = 0; 574dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 575dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(!AFI->isThumb1OnlyFunction() && 576dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach "This resolveFrameIndex does not support Thumb1!"); 577dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 578dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach while (!MI.getOperand(i).isFI()) { 579dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ++i; 580dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 581dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 582dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach bool Done = false; 583dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach if (!AFI->isThumbFunction()) 584dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 585dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach else { 586dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(AFI->isThumb2Function()); 587dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 588dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 589dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert (Done && "Unable to resolve frame index!"); 5901f6a329f79b3568d379142f921f59c4143ddaa14Duncan Sands (void)Done; 591dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 5928708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 593e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbachbool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 594e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 595e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 5962b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 5972b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned i = 0; 5982b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 5992b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach while (!MI->getOperand(i).isFI()) { 6002b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach ++i; 6012b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 6022b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6032b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6042b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // AddrMode4 and AddrMode6 cannot handle any offset. 6052b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 6062b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return Offset == 0; 6072b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6082b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned NumBits = 0; 6092b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Scale = 1; 610e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach bool isSigned = true; 6111ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 6122b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i8: 6132b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i12: 6142b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // i8 supports only negative, and i12 supports only positive, so 6152b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // based on Offset sign, consider the appropriate instruction 61674d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 1; 6172b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (Offset < 0) { 6182b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6192b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 6202b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } else { 6212b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 6222b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6232b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6241ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode5: 6252b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // VFP address mode. 6262b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6272b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Scale = 4; 6282b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6293e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: 6301ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode2: 6312b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 6322b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6331ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode3: 6342b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6352b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 636e575499d830008784b11499dae290ad0480c8f9dBill Wendling case ARMII::AddrModeT1_s: 637e575499d830008784b11499dae290ad0480c8f9dBill Wendling NumBits = 5; 63874d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 4; 639e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach isSigned = false; 64074d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach break; 6412b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach default: 6422b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach llvm_unreachable("Unsupported addressing mode!"); 6432b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6442b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6451ab3f16f06698596716593a30545799688acccd7Jim Grosbach Offset += getFrameIndexInstrOffset(MI, i); 646d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // Make sure the offset is encodable for instructions that scale the 647d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // immediate. 648d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach if ((Offset & (Scale-1)) != 0) 649d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach return false; 650d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach 651e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (isSigned && Offset < 0) 6522b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 6532b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6542b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Mask = (1 << NumBits) - 1; 6552b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if ((unsigned)Offset <= Mask * Scale) 6562b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return true; 65774d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 65874d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach return false; 65974d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach} 66074d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 661fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbachvoid 6626495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 663108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int SPAdj, unsigned FIOperandNum, 664108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier RegScavenger *RS) const { 6655ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineInstr &MI = *II; 6665ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineBasicBlock &MBB = *MI.getParent(); 6675ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineFunction &MF = *MBB.getParent(); 66816c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const ARMFrameLowering *TFI = 66916c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 6705ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 6716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 672a15de00f8246f19180b26ee5fe7ff8f436e0de08Bob Wilson "This eliminateFrameIndex does not support Thumb1!"); 673108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 674a37aa546224ec03ba1f1a1598e0781af4b692673Jim Grosbach unsigned FrameReg; 6755ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 67682f58740c76b42af8370247b23677a0318f6dde8Anton Korobeynikov int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 6775ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 6780f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 6790f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // call frame setup/destroy instructions have already been eliminated. That 6800f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // means the stack pointer cannot be used to access the emergency spill slot 6810f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // when !hasReservedCallFrame(). 6820f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen#ifndef NDEBUG 6830f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){ 6840f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen assert(TFI->hasReservedCallFrame(MF) && 6850f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "Cannot use SP to access the emergency spill slot in " 6860f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "functions without a reserved call frame"); 6870f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen assert(!MF.getFrameInfo()->hasVarSizedObjects() && 6880f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "Cannot use SP to access the emergency spill slot in " 6890f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "functions with variable sized frame objects"); 6900f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen } 6910f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen#endif // NDEBUG 6920f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen 69362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng // Special handling of dbg_value instructions. 69462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng if (MI.isDebugValue()) { 695108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/); 696108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 697fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 69862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng } 69962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 70048d8afab73d72418cf9505a020f621014920463cEvan Cheng // Modify MI as necessary to handle as much of 'Offset' as possible 701cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng bool Done = false; 7026495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (!AFI->isThumbFunction()) 703108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 7046495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 7056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(AFI->isThumb2Function()); 706108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 7076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 708cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Done) 709fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 7105ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 711db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we get here, the immediate doesn't fit into the instruction. We folded 712db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // as much as possible above, handle the rest, providing a register that is 713db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // SP+LargeImm. 71419bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar assert((Offset || 715a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 716a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 717cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng "This code isn't needed if offset already handled!"); 718db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 7197e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach unsigned ScratchReg = 0; 720db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int PIdx = MI.findFirstPredOperandIdx(); 721db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (PIdx == -1) 722db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 723db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 724cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Offset == 0) 725a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach // Must be addrmode4/6. 726108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 7276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 728420761a0f193e87d08ee1c51b26bba23ab4bac7fCraig Topper ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 729cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (!AFI->isThumbFunction()) 730cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 731cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 732cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng else { 733cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng assert(AFI->isThumb2Function()); 734cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 735cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 736cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng } 737cde31293d45f14ddff482d385429d256bd4e0820Jim Grosbach // Update the original instruction to use the scratch register. 738108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 7396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 740db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 741