1//===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9/// \file 10/// This file implements a TargetTransformInfo analysis pass specific to the 11/// ARM target machine. It uses the target's detailed information to provide 12/// more precise answers to certain TTI queries, while letting the target 13/// independent and default TTI implementations handle the rest. 14/// 15//===----------------------------------------------------------------------===// 16 17#define DEBUG_TYPE "armtti" 18#include "ARM.h" 19#include "ARMTargetMachine.h" 20#include "llvm/Analysis/TargetTransformInfo.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/CostTable.h" 24using namespace llvm; 25 26// Declare the pass initialization routine locally as target-specific passes 27// don't havve a target-wide initialization entry point, and so we rely on the 28// pass constructor initialization. 29namespace llvm { 30void initializeARMTTIPass(PassRegistry &); 31} 32 33namespace { 34 35class ARMTTI : public ImmutablePass, public TargetTransformInfo { 36 const ARMBaseTargetMachine *TM; 37 const ARMSubtarget *ST; 38 const ARMTargetLowering *TLI; 39 40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract 41 /// are set if the result needs to be inserted and/or extracted from vectors. 42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const; 43 44public: 45 ARMTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) { 46 llvm_unreachable("This pass cannot be directly constructed"); 47 } 48 49 ARMTTI(const ARMBaseTargetMachine *TM) 50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()), 51 TLI(TM->getTargetLowering()) { 52 initializeARMTTIPass(*PassRegistry::getPassRegistry()); 53 } 54 55 virtual void initializePass() { 56 pushTTIStack(this); 57 } 58 59 virtual void finalizePass() { 60 popTTIStack(); 61 } 62 63 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 64 TargetTransformInfo::getAnalysisUsage(AU); 65 } 66 67 /// Pass identification. 68 static char ID; 69 70 /// Provide necessary pointer adjustments for the two base classes. 71 virtual void *getAdjustedAnalysisPointer(const void *ID) { 72 if (ID == &TargetTransformInfo::ID) 73 return (TargetTransformInfo*)this; 74 return this; 75 } 76 77 /// \name Scalar TTI Implementations 78 /// @{ 79 80 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const; 81 82 /// @} 83 84 85 /// \name Vector TTI Implementations 86 /// @{ 87 88 unsigned getNumberOfRegisters(bool Vector) const { 89 if (Vector) { 90 if (ST->hasNEON()) 91 return 16; 92 return 0; 93 } 94 95 if (ST->isThumb1Only()) 96 return 8; 97 return 16; 98 } 99 100 unsigned getRegisterBitWidth(bool Vector) const { 101 if (Vector) { 102 if (ST->hasNEON()) 103 return 128; 104 return 0; 105 } 106 107 return 32; 108 } 109 110 unsigned getMaximumUnrollFactor() const { 111 // These are out of order CPUs: 112 if (ST->isCortexA15() || ST->isSwift()) 113 return 2; 114 return 1; 115 } 116 117 unsigned getShuffleCost(ShuffleKind Kind, Type *Tp, 118 int Index, Type *SubTp) const; 119 120 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, 121 Type *Src) const; 122 123 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) const; 124 125 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const; 126 127 unsigned getAddressComputationCost(Type *Val) const; 128 /// @} 129}; 130 131} // end anonymous namespace 132 133INITIALIZE_AG_PASS(ARMTTI, TargetTransformInfo, "armtti", 134 "ARM Target Transform Info", true, true, false) 135char ARMTTI::ID = 0; 136 137ImmutablePass * 138llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) { 139 return new ARMTTI(TM); 140} 141 142 143unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const { 144 assert(Ty->isIntegerTy()); 145 146 unsigned Bits = Ty->getPrimitiveSizeInBits(); 147 if (Bits == 0 || Bits > 32) 148 return 4; 149 150 int32_t SImmVal = Imm.getSExtValue(); 151 uint32_t ZImmVal = Imm.getZExtValue(); 152 if (!ST->isThumb()) { 153 if ((SImmVal >= 0 && SImmVal < 65536) || 154 (ARM_AM::getSOImmVal(ZImmVal) != -1) || 155 (ARM_AM::getSOImmVal(~ZImmVal) != -1)) 156 return 1; 157 return ST->hasV6T2Ops() ? 2 : 3; 158 } else if (ST->isThumb2()) { 159 if ((SImmVal >= 0 && SImmVal < 65536) || 160 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) || 161 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1)) 162 return 1; 163 return ST->hasV6T2Ops() ? 2 : 3; 164 } else /*Thumb1*/ { 165 if (SImmVal >= 0 && SImmVal < 256) 166 return 1; 167 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal)) 168 return 2; 169 // Load from constantpool. 170 return 3; 171 } 172 return 2; 173} 174 175unsigned ARMTTI::getCastInstrCost(unsigned Opcode, Type *Dst, 176 Type *Src) const { 177 int ISD = TLI->InstructionOpcodeToISD(Opcode); 178 assert(ISD && "Invalid opcode"); 179 180 // Single to/from double precision conversions. 181 static const CostTblEntry<MVT> NEONFltDblTbl[] = { 182 // Vector fptrunc/fpext conversions. 183 { ISD::FP_ROUND, MVT::v2f64, 2 }, 184 { ISD::FP_EXTEND, MVT::v2f32, 2 }, 185 { ISD::FP_EXTEND, MVT::v4f32, 4 } 186 }; 187 188 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || 189 ISD == ISD::FP_EXTEND)) { 190 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src); 191 int Idx = CostTableLookup<MVT>(NEONFltDblTbl, array_lengthof(NEONFltDblTbl), 192 ISD, LT.second); 193 if (Idx != -1) 194 return LT.first * NEONFltDblTbl[Idx].Cost; 195 } 196 197 EVT SrcTy = TLI->getValueType(Src); 198 EVT DstTy = TLI->getValueType(Dst); 199 200 if (!SrcTy.isSimple() || !DstTy.isSimple()) 201 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src); 202 203 // Some arithmetic, load and store operations have specific instructions 204 // to cast up/down their types automatically at no extra cost. 205 // TODO: Get these tables to know at least what the related operations are. 206 static const TypeConversionCostTblEntry<MVT> NEONVectorConversionTbl[] = { 207 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 208 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 209 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 210 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 211 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 212 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 213 214 // Operations that we legalize using load/stores to the stack. 215 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 16*2 + 4*4 }, 216 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 16*2 + 4*3 }, 217 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 8*2 + 2*4 }, 218 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 8*2 + 2*3 }, 219 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4*1 + 16*2 + 2*1 }, 220 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2*1 + 8*2 + 1 }, 221 222 // Vector float <-> i32 conversions. 223 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 224 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 225 226 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 227 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 228 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 229 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 230 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 231 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 233 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 234 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 235 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 236 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 237 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 239 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 240 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 241 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 242 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, 243 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, 244 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, 245 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, 246 247 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 248 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 249 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 250 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 251 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 252 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 253 254 // Vector double <-> i32 conversions. 255 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 256 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 257 258 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 259 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 260 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, 261 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, 262 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 263 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 264 265 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, 266 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, 267 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, 268 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, 269 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, 270 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } 271 }; 272 273 if (SrcTy.isVector() && ST->hasNEON()) { 274 int Idx = ConvertCostTableLookup<MVT>(NEONVectorConversionTbl, 275 array_lengthof(NEONVectorConversionTbl), 276 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()); 277 if (Idx != -1) 278 return NEONVectorConversionTbl[Idx].Cost; 279 } 280 281 // Scalar float to integer conversions. 282 static const TypeConversionCostTblEntry<MVT> NEONFloatConversionTbl[] = { 283 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, 284 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 }, 285 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, 286 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 }, 287 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, 288 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 }, 289 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, 290 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 }, 291 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 }, 292 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 }, 293 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 }, 294 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 }, 295 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 }, 296 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 }, 297 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 }, 298 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 }, 299 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 }, 300 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 }, 301 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 }, 302 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 } 303 }; 304 if (SrcTy.isFloatingPoint() && ST->hasNEON()) { 305 int Idx = ConvertCostTableLookup<MVT>(NEONFloatConversionTbl, 306 array_lengthof(NEONFloatConversionTbl), 307 ISD, DstTy.getSimpleVT(), 308 SrcTy.getSimpleVT()); 309 if (Idx != -1) 310 return NEONFloatConversionTbl[Idx].Cost; 311 } 312 313 // Scalar integer to float conversions. 314 static const TypeConversionCostTblEntry<MVT> NEONIntegerConversionTbl[] = { 315 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 }, 316 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 }, 317 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 }, 318 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 }, 319 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 }, 320 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 }, 321 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 }, 322 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 }, 323 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 }, 324 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 }, 325 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 }, 326 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 }, 327 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 }, 328 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 }, 329 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 }, 330 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 }, 331 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 }, 332 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 }, 333 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 }, 334 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 } 335 }; 336 337 if (SrcTy.isInteger() && ST->hasNEON()) { 338 int Idx = ConvertCostTableLookup<MVT>(NEONIntegerConversionTbl, 339 array_lengthof(NEONIntegerConversionTbl), 340 ISD, DstTy.getSimpleVT(), 341 SrcTy.getSimpleVT()); 342 if (Idx != -1) 343 return NEONIntegerConversionTbl[Idx].Cost; 344 } 345 346 // Scalar integer conversion costs. 347 static const TypeConversionCostTblEntry<MVT> ARMIntegerConversionTbl[] = { 348 // i16 -> i64 requires two dependent operations. 349 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 }, 350 351 // Truncates on i64 are assumed to be free. 352 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 }, 353 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 }, 354 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 }, 355 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 } 356 }; 357 358 if (SrcTy.isInteger()) { 359 int Idx = 360 ConvertCostTableLookup<MVT>(ARMIntegerConversionTbl, 361 array_lengthof(ARMIntegerConversionTbl), 362 ISD, DstTy.getSimpleVT(), 363 SrcTy.getSimpleVT()); 364 if (Idx != -1) 365 return ARMIntegerConversionTbl[Idx].Cost; 366 } 367 368 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src); 369} 370 371unsigned ARMTTI::getVectorInstrCost(unsigned Opcode, Type *ValTy, 372 unsigned Index) const { 373 // Penalize inserting into an D-subregister. We end up with a three times 374 // lower estimated throughput on swift. 375 if (ST->isSwift() && 376 Opcode == Instruction::InsertElement && 377 ValTy->isVectorTy() && 378 ValTy->getScalarSizeInBits() <= 32) 379 return 3; 380 381 return TargetTransformInfo::getVectorInstrCost(Opcode, ValTy, Index); 382} 383 384unsigned ARMTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 385 Type *CondTy) const { 386 387 int ISD = TLI->InstructionOpcodeToISD(Opcode); 388 // On NEON a a vector select gets lowered to vbsl. 389 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) { 390 // Lowering of some vector selects is currently far from perfect. 391 static const TypeConversionCostTblEntry<MVT> NEONVectorSelectTbl[] = { 392 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 }, 393 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 }, 394 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 }, 395 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, 396 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, 397 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 } 398 }; 399 400 EVT SelCondTy = TLI->getValueType(CondTy); 401 EVT SelValTy = TLI->getValueType(ValTy); 402 int Idx = ConvertCostTableLookup<MVT>(NEONVectorSelectTbl, 403 array_lengthof(NEONVectorSelectTbl), 404 ISD, SelCondTy.getSimpleVT(), 405 SelValTy.getSimpleVT()); 406 if (Idx != -1) 407 return NEONVectorSelectTbl[Idx].Cost; 408 409 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy); 410 return LT.first; 411 } 412 413 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy); 414} 415 416unsigned ARMTTI::getAddressComputationCost(Type *Ty) const { 417 // In many cases the address computation is not merged into the instruction 418 // addressing mode. 419 return 1; 420} 421 422unsigned ARMTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index, 423 Type *SubTp) const { 424 // We only handle costs of reverse shuffles for now. 425 if (Kind != SK_Reverse) 426 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp); 427 428 static const CostTblEntry<MVT> NEONShuffleTbl[] = { 429 // Reverse shuffle cost one instruction if we are shuffling within a double 430 // word (vrev) or two if we shuffle a quad word (vrev, vext). 431 { ISD::VECTOR_SHUFFLE, MVT::v2i32, 1 }, 432 { ISD::VECTOR_SHUFFLE, MVT::v2f32, 1 }, 433 { ISD::VECTOR_SHUFFLE, MVT::v2i64, 1 }, 434 { ISD::VECTOR_SHUFFLE, MVT::v2f64, 1 }, 435 436 { ISD::VECTOR_SHUFFLE, MVT::v4i32, 2 }, 437 { ISD::VECTOR_SHUFFLE, MVT::v4f32, 2 }, 438 { ISD::VECTOR_SHUFFLE, MVT::v8i16, 2 }, 439 { ISD::VECTOR_SHUFFLE, MVT::v16i8, 2 } 440 }; 441 442 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp); 443 444 int Idx = CostTableLookup<MVT>(NEONShuffleTbl, array_lengthof(NEONShuffleTbl), 445 ISD::VECTOR_SHUFFLE, LT.second); 446 if (Idx == -1) 447 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp); 448 449 return LT.first * NEONShuffleTbl[Idx].Cost; 450} 451