ARMDisassembler.cpp revision 0d09499cf3e2d927cdc53ec79895303ac12808ac
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "ARMDisassembler.h" 13#include "ARM.h" 14#include "ARMRegisterInfo.h" 15#include "MCTargetDesc/ARMAddressingModes.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "llvm/MC/EDInstInfo.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCContext.h" 21#include "llvm/Target/TargetRegistry.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/MemoryObject.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/raw_ostream.h" 26 27// Forward declare these because the autogenerated code will reference them. 28// Definitions are further down. 29static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 137 uint64_t Address, const void *Decoder); 138static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 139 uint64_t Address, const void *Decoder); 140static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 145 146static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 147 uint64_t Address, const void *Decoder); 148static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 149 uint64_t Address, const void *Decoder); 150static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 151 uint64_t Address, const void *Decoder); 152static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 153 uint64_t Address, const void *Decoder); 154static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 155 uint64_t Address, const void *Decoder); 156static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 157 uint64_t Address, const void *Decoder); 158static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 159 uint64_t Address, const void *Decoder); 160static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 161 uint64_t Address, const void *Decoder); 162static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 163 uint64_t Address, const void *Decoder); 164static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 167 uint64_t Address, const void *Decoder); 168static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 169 uint64_t Address, const void *Decoder); 170static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 171 uint64_t Address, const void *Decoder); 172static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 173 uint64_t Address, const void *Decoder); 174static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 175 uint64_t Address, const void *Decoder); 176static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 177 uint64_t Address, const void *Decoder); 178static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 179 uint64_t Address, const void *Decoder); 180static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 181 uint64_t Address, const void *Decoder); 182static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 195#include "ARMGenDisassemblerTables.inc" 196#include "ARMGenInstrInfo.inc" 197#include "ARMGenEDInfo.inc" 198 199using namespace llvm; 200 201static MCDisassembler *createARMDisassembler(const Target &T) { 202 return new ARMDisassembler; 203} 204 205static MCDisassembler *createThumbDisassembler(const Target &T) { 206 return new ThumbDisassembler; 207} 208 209EDInstInfo *ARMDisassembler::getEDInfo() const { 210 return instInfoARM; 211} 212 213EDInstInfo *ThumbDisassembler::getEDInfo() const { 214 return instInfoARM; 215} 216 217 218bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 219 const MemoryObject &Region, 220 uint64_t Address,raw_ostream &os) const { 221 uint8_t bytes[4]; 222 223 // We want to read exactly 4 bytes of data. 224 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 225 return false; 226 227 // Encoded as a small-endian 32-bit word in the stream. 228 uint32_t insn = (bytes[3] << 24) | 229 (bytes[2] << 16) | 230 (bytes[1] << 8) | 231 (bytes[0] << 0); 232 233 // Calling the auto-generated decoder function. 234 bool result = decodeARMInstruction32(MI, insn, Address, this); 235 if (result) { 236 Size = 4; 237 return true; 238 } 239 240 // Instructions that are shared between ARM and Thumb modes. 241 // FIXME: This shouldn't really exist. It's an artifact of the 242 // fact that we fail to encode a few instructions properly for Thumb. 243 MI.clear(); 244 result = decodeCommonInstruction32(MI, insn, Address, this); 245 if (result) { 246 Size = 4; 247 return true; 248 } 249 250 // VFP and NEON instructions, similarly, are shared between ARM 251 // and Thumb modes. 252 MI.clear(); 253 result = decodeVFPInstruction32(MI, insn, Address, this); 254 if (result) { 255 Size = 4; 256 return true; 257 } 258 259 MI.clear(); 260 result = decodeNEONDataInstruction32(MI, insn, Address, this); 261 if (result) { 262 Size = 4; 263 // Add a fake predicate operand, because we share these instruction 264 // definitions with Thumb2 where these instructions are predicable. 265 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 266 return true; 267 } 268 269 MI.clear(); 270 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 271 if (result) { 272 Size = 4; 273 // Add a fake predicate operand, because we share these instruction 274 // definitions with Thumb2 where these instructions are predicable. 275 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 276 return true; 277 } 278 279 MI.clear(); 280 result = decodeNEONDupInstruction32(MI, insn, Address, this); 281 if (result) { 282 Size = 4; 283 // Add a fake predicate operand, because we share these instruction 284 // definitions with Thumb2 where these instructions are predicable. 285 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 286 return true; 287 } 288 289 MI.clear(); 290 291 return false; 292} 293 294namespace llvm { 295extern MCInstrDesc ARMInsts[]; 296} 297 298// Thumb1 instructions don't have explicit S bits. Rather, they 299// implicitly set CPSR. Since it's not represented in the encoding, the 300// auto-generated decoder won't inject the CPSR operand. We need to fix 301// that as a post-pass. 302static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 303 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 304 MCInst::iterator I = MI.begin(); 305 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 306 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 307 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 308 return; 309 } 310 } 311 312 if (OpInfo[MI.size()].isOptionalDef() && 313 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 314 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 315} 316 317// Most Thumb instructions don't have explicit predicates in the 318// encoding, but rather get their predicates from IT context. We need 319// to fix up the predicate operands using this context information as a 320// post-pass. 321void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 322 // A few instructions actually have predicates encoded in them. Don't 323 // try to overwrite it if we're seeing one of those. 324 switch (MI.getOpcode()) { 325 case ARM::tBcc: 326 case ARM::t2Bcc: 327 return; 328 default: 329 break; 330 } 331 332 // If we're in an IT block, base the predicate on that. Otherwise, 333 // assume a predicate of AL. 334 unsigned CC; 335 if (!ITBlock.empty()) { 336 CC = ITBlock.back(); 337 ITBlock.pop_back(); 338 } else 339 CC = ARMCC::AL; 340 341 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 342 MCInst::iterator I = MI.begin(); 343 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 344 if (OpInfo[i].isPredicate()) { 345 I = MI.insert(I, MCOperand::CreateImm(CC)); 346 ++I; 347 if (CC == ARMCC::AL) 348 MI.insert(I, MCOperand::CreateReg(0)); 349 else 350 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 351 return; 352 } 353 } 354 355 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 356 if (CC == ARMCC::AL) 357 MI.insert(MI.end(), MCOperand::CreateReg(0)); 358 else 359 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 360} 361 362// Thumb VFP instructions are a special case. Because we share their 363// encodings between ARM and Thumb modes, and they are predicable in ARM 364// mode, the auto-generated decoder will give them an (incorrect) 365// predicate operand. We need to rewrite these operands based on the IT 366// context as a post-pass. 367void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 368 unsigned CC; 369 if (!ITBlock.empty()) { 370 CC = ITBlock.back(); 371 ITBlock.pop_back(); 372 } else 373 CC = ARMCC::AL; 374 375 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 376 MCInst::iterator I = MI.begin(); 377 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 378 if (OpInfo[i].isPredicate() ) { 379 I->setImm(CC); 380 ++I; 381 if (CC == ARMCC::AL) 382 I->setReg(0); 383 else 384 I->setReg(ARM::CPSR); 385 return; 386 } 387 } 388} 389 390 391bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 392 const MemoryObject &Region, 393 uint64_t Address,raw_ostream &os) const { 394 uint8_t bytes[4]; 395 396 // We want to read exactly 2 bytes of data. 397 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 398 return false; 399 400 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 401 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 402 if (result) { 403 Size = 2; 404 bool InITBlock = !ITBlock.empty(); 405 AddThumbPredicate(MI); 406 AddThumb1SBit(MI, InITBlock); 407 return true; 408 } 409 410 MI.clear(); 411 result = decodeThumb2Instruction16(MI, insn16, Address, this); 412 if (result) { 413 Size = 2; 414 AddThumbPredicate(MI); 415 416 // If we find an IT instruction, we need to parse its condition 417 // code and mask operands so that we can apply them correctly 418 // to the subsequent instructions. 419 if (MI.getOpcode() == ARM::t2IT) { 420 unsigned firstcond = MI.getOperand(0).getImm(); 421 uint32_t mask = MI.getOperand(1).getImm(); 422 unsigned zeros = CountTrailingZeros_32(mask); 423 mask >>= zeros+1; 424 425 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 426 if (firstcond ^ (mask & 1)) 427 ITBlock.push_back(firstcond ^ 1); 428 else 429 ITBlock.push_back(firstcond); 430 mask >>= 1; 431 } 432 ITBlock.push_back(firstcond); 433 } 434 435 return true; 436 } 437 438 // We want to read exactly 4 bytes of data. 439 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 440 return false; 441 442 uint32_t insn32 = (bytes[3] << 8) | 443 (bytes[2] << 0) | 444 (bytes[1] << 24) | 445 (bytes[0] << 16); 446 MI.clear(); 447 result = decodeThumbInstruction32(MI, insn32, Address, this); 448 if (result) { 449 Size = 4; 450 bool InITBlock = ITBlock.size(); 451 AddThumbPredicate(MI); 452 AddThumb1SBit(MI, InITBlock); 453 return true; 454 } 455 456 MI.clear(); 457 result = decodeThumb2Instruction32(MI, insn32, Address, this); 458 if (result) { 459 Size = 4; 460 AddThumbPredicate(MI); 461 return true; 462 } 463 464 MI.clear(); 465 result = decodeCommonInstruction32(MI, insn32, Address, this); 466 if (result) { 467 Size = 4; 468 AddThumbPredicate(MI); 469 return true; 470 } 471 472 MI.clear(); 473 result = decodeVFPInstruction32(MI, insn32, Address, this); 474 if (result) { 475 Size = 4; 476 UpdateThumbVFPPredicate(MI); 477 return true; 478 } 479 480 MI.clear(); 481 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 482 uint32_t NEONDataInsn = insn32; 483 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 484 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 485 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 486 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 487 if (result) { 488 Size = 4; 489 AddThumbPredicate(MI); 490 return true; 491 } 492 } 493 494 MI.clear(); 495 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); 496 if (result) { 497 Size = 4; 498 AddThumbPredicate(MI); 499 return true; 500 } 501 502 MI.clear(); 503 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 504 if (result) { 505 Size = 4; 506 AddThumbPredicate(MI); 507 return true; 508 } 509 510 return false; 511} 512 513 514extern "C" void LLVMInitializeARMDisassembler() { 515 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 516 createARMDisassembler); 517 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 518 createThumbDisassembler); 519} 520 521static const unsigned GPRDecoderTable[] = { 522 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 523 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 524 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 525 ARM::R12, ARM::SP, ARM::LR, ARM::PC 526}; 527 528static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 529 uint64_t Address, const void *Decoder) { 530 if (RegNo > 15) 531 return false; 532 533 unsigned Register = GPRDecoderTable[RegNo]; 534 Inst.addOperand(MCOperand::CreateReg(Register)); 535 return true; 536} 537 538static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 539 uint64_t Address, const void *Decoder) { 540 if (RegNo == 15) return false; 541 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 542} 543 544static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 545 uint64_t Address, const void *Decoder) { 546 if (RegNo > 7) 547 return false; 548 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 549} 550 551static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 552 uint64_t Address, const void *Decoder) { 553 unsigned Register = 0; 554 switch (RegNo) { 555 case 0: 556 Register = ARM::R0; 557 break; 558 case 1: 559 Register = ARM::R1; 560 break; 561 case 2: 562 Register = ARM::R2; 563 break; 564 case 3: 565 Register = ARM::R3; 566 break; 567 case 9: 568 Register = ARM::R9; 569 break; 570 case 12: 571 Register = ARM::R12; 572 break; 573 default: 574 return false; 575 } 576 577 Inst.addOperand(MCOperand::CreateReg(Register)); 578 return true; 579} 580 581static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 582 uint64_t Address, const void *Decoder) { 583 if (RegNo == 13 || RegNo == 15) return false; 584 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 585} 586 587static const unsigned SPRDecoderTable[] = { 588 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 589 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 590 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 591 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 592 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 593 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 594 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 595 ARM::S28, ARM::S29, ARM::S30, ARM::S31 596}; 597 598static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 599 uint64_t Address, const void *Decoder) { 600 if (RegNo > 31) 601 return false; 602 603 unsigned Register = SPRDecoderTable[RegNo]; 604 Inst.addOperand(MCOperand::CreateReg(Register)); 605 return true; 606} 607 608static const unsigned DPRDecoderTable[] = { 609 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 610 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 611 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 612 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 613 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 614 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 615 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 616 ARM::D28, ARM::D29, ARM::D30, ARM::D31 617}; 618 619static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 620 uint64_t Address, const void *Decoder) { 621 if (RegNo > 31) 622 return false; 623 624 unsigned Register = DPRDecoderTable[RegNo]; 625 Inst.addOperand(MCOperand::CreateReg(Register)); 626 return true; 627} 628 629static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 630 uint64_t Address, const void *Decoder) { 631 if (RegNo > 7) 632 return false; 633 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 634} 635 636static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 637 uint64_t Address, const void *Decoder) { 638 if (RegNo > 15) 639 return false; 640 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 641} 642 643static const unsigned QPRDecoderTable[] = { 644 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 645 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 646 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 647 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 648}; 649 650 651static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 652 uint64_t Address, const void *Decoder) { 653 if (RegNo > 31) 654 return false; 655 RegNo >>= 1; 656 657 unsigned Register = QPRDecoderTable[RegNo]; 658 Inst.addOperand(MCOperand::CreateReg(Register)); 659 return true; 660} 661 662static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 663 uint64_t Address, const void *Decoder) { 664 if (Val == 0xF) return false; 665 // AL predicate is not allowed on Thumb1 branches. 666 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 667 return false; 668 Inst.addOperand(MCOperand::CreateImm(Val)); 669 if (Val == ARMCC::AL) { 670 Inst.addOperand(MCOperand::CreateReg(0)); 671 } else 672 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 673 return true; 674} 675 676static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 677 uint64_t Address, const void *Decoder) { 678 if (Val) 679 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 680 else 681 Inst.addOperand(MCOperand::CreateReg(0)); 682 return true; 683} 684 685static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 686 uint64_t Address, const void *Decoder) { 687 uint32_t imm = Val & 0xFF; 688 uint32_t rot = (Val & 0xF00) >> 7; 689 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 690 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 691 return true; 692} 693 694static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 695 uint64_t Address, const void *Decoder) { 696 Val <<= 2; 697 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 698 return true; 699} 700 701static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 702 uint64_t Address, const void *Decoder) { 703 704 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 705 unsigned type = fieldFromInstruction32(Val, 5, 2); 706 unsigned imm = fieldFromInstruction32(Val, 7, 5); 707 708 // Register-immediate 709 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 710 711 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 712 switch (type) { 713 case 0: 714 Shift = ARM_AM::lsl; 715 break; 716 case 1: 717 Shift = ARM_AM::lsr; 718 break; 719 case 2: 720 Shift = ARM_AM::asr; 721 break; 722 case 3: 723 Shift = ARM_AM::ror; 724 break; 725 } 726 727 if (Shift == ARM_AM::ror && imm == 0) 728 Shift = ARM_AM::rrx; 729 730 unsigned Op = Shift | (imm << 3); 731 Inst.addOperand(MCOperand::CreateImm(Op)); 732 733 return true; 734} 735 736static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 737 uint64_t Address, const void *Decoder) { 738 739 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 740 unsigned type = fieldFromInstruction32(Val, 5, 2); 741 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 742 743 // Register-register 744 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 745 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 746 747 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 748 switch (type) { 749 case 0: 750 Shift = ARM_AM::lsl; 751 break; 752 case 1: 753 Shift = ARM_AM::lsr; 754 break; 755 case 2: 756 Shift = ARM_AM::asr; 757 break; 758 case 3: 759 Shift = ARM_AM::ror; 760 break; 761 } 762 763 Inst.addOperand(MCOperand::CreateImm(Shift)); 764 765 return true; 766} 767 768static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 769 uint64_t Address, const void *Decoder) { 770 // Empty register lists are not allowed. 771 if (CountPopulation_32(Val) == 0) return false; 772 for (unsigned i = 0; i < 16; ++i) { 773 if (Val & (1 << i)) { 774 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 775 } 776 } 777 778 return true; 779} 780 781static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 782 uint64_t Address, const void *Decoder) { 783 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 784 unsigned regs = Val & 0xFF; 785 786 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 787 for (unsigned i = 0; i < (regs - 1); ++i) { 788 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 789 } 790 791 return true; 792} 793 794static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 795 uint64_t Address, const void *Decoder) { 796 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 797 unsigned regs = (Val & 0xFF) / 2; 798 799 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 800 for (unsigned i = 0; i < (regs - 1); ++i) { 801 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 802 } 803 804 return true; 805} 806 807static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 808 uint64_t Address, const void *Decoder) { 809 // This operand encodes a mask of contiguous zeros between a specified MSB 810 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 811 // the mask of all bits LSB-and-lower, and then xor them to create 812 // the mask of that's all ones on [msb, lsb]. Finally we not it to 813 // create the final mask. 814 unsigned msb = fieldFromInstruction32(Val, 5, 5); 815 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 816 uint32_t msb_mask = (1 << (msb+1)) - 1; 817 uint32_t lsb_mask = (1 << lsb) - 1; 818 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 819 return true; 820} 821 822static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 823 uint64_t Address, const void *Decoder) { 824 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 825 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 826 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 827 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 828 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 829 unsigned U = fieldFromInstruction32(Insn, 23, 1); 830 831 switch (Inst.getOpcode()) { 832 case ARM::LDC_OFFSET: 833 case ARM::LDC_PRE: 834 case ARM::LDC_POST: 835 case ARM::LDC_OPTION: 836 case ARM::LDCL_OFFSET: 837 case ARM::LDCL_PRE: 838 case ARM::LDCL_POST: 839 case ARM::LDCL_OPTION: 840 case ARM::STC_OFFSET: 841 case ARM::STC_PRE: 842 case ARM::STC_POST: 843 case ARM::STC_OPTION: 844 case ARM::STCL_OFFSET: 845 case ARM::STCL_PRE: 846 case ARM::STCL_POST: 847 case ARM::STCL_OPTION: 848 if (coproc == 0xA || coproc == 0xB) 849 return false; 850 break; 851 default: 852 break; 853 } 854 855 Inst.addOperand(MCOperand::CreateImm(coproc)); 856 Inst.addOperand(MCOperand::CreateImm(CRd)); 857 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 858 switch (Inst.getOpcode()) { 859 case ARM::LDC_OPTION: 860 case ARM::LDCL_OPTION: 861 case ARM::LDC2_OPTION: 862 case ARM::LDC2L_OPTION: 863 case ARM::STC_OPTION: 864 case ARM::STCL_OPTION: 865 case ARM::STC2_OPTION: 866 case ARM::STC2L_OPTION: 867 case ARM::LDCL_POST: 868 case ARM::STCL_POST: 869 break; 870 default: 871 Inst.addOperand(MCOperand::CreateReg(0)); 872 break; 873 } 874 875 unsigned P = fieldFromInstruction32(Insn, 24, 1); 876 unsigned W = fieldFromInstruction32(Insn, 21, 1); 877 878 bool writeback = (P == 0) || (W == 1); 879 unsigned idx_mode = 0; 880 if (P && writeback) 881 idx_mode = ARMII::IndexModePre; 882 else if (!P && writeback) 883 idx_mode = ARMII::IndexModePost; 884 885 switch (Inst.getOpcode()) { 886 case ARM::LDCL_POST: 887 case ARM::STCL_POST: 888 imm |= U << 8; 889 case ARM::LDC_OPTION: 890 case ARM::LDCL_OPTION: 891 case ARM::LDC2_OPTION: 892 case ARM::LDC2L_OPTION: 893 case ARM::STC_OPTION: 894 case ARM::STCL_OPTION: 895 case ARM::STC2_OPTION: 896 case ARM::STC2L_OPTION: 897 Inst.addOperand(MCOperand::CreateImm(imm)); 898 break; 899 default: 900 if (U) 901 Inst.addOperand(MCOperand::CreateImm( 902 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 903 else 904 Inst.addOperand(MCOperand::CreateImm( 905 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 906 break; 907 } 908 909 switch (Inst.getOpcode()) { 910 case ARM::LDC_OFFSET: 911 case ARM::LDC_PRE: 912 case ARM::LDC_POST: 913 case ARM::LDC_OPTION: 914 case ARM::LDCL_OFFSET: 915 case ARM::LDCL_PRE: 916 case ARM::LDCL_POST: 917 case ARM::LDCL_OPTION: 918 case ARM::STC_OFFSET: 919 case ARM::STC_PRE: 920 case ARM::STC_POST: 921 case ARM::STC_OPTION: 922 case ARM::STCL_OFFSET: 923 case ARM::STCL_PRE: 924 case ARM::STCL_POST: 925 case ARM::STCL_OPTION: 926 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 927 break; 928 default: 929 break; 930 } 931 932 return true; 933} 934 935static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 936 uint64_t Address, const void *Decoder) { 937 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 938 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 939 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 940 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 941 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 942 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 943 unsigned P = fieldFromInstruction32(Insn, 24, 1); 944 unsigned W = fieldFromInstruction32(Insn, 21, 1); 945 946 // On stores, the writeback operand precedes Rt. 947 switch (Inst.getOpcode()) { 948 case ARM::STR_POST_IMM: 949 case ARM::STR_POST_REG: 950 case ARM::STRB_POST_IMM: 951 case ARM::STRB_POST_REG: 952 case ARM::STRT_POST_REG: 953 case ARM::STRT_POST_IMM: 954 case ARM::STRBT_POST_REG: 955 case ARM::STRBT_POST_IMM: 956 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 957 break; 958 default: 959 break; 960 } 961 962 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 963 964 // On loads, the writeback operand comes after Rt. 965 switch (Inst.getOpcode()) { 966 case ARM::LDR_POST_IMM: 967 case ARM::LDR_POST_REG: 968 case ARM::LDRB_POST_IMM: 969 case ARM::LDRB_POST_REG: 970 case ARM::LDR_PRE: 971 case ARM::LDRB_PRE: 972 case ARM::LDRBT_POST_REG: 973 case ARM::LDRBT_POST_IMM: 974 case ARM::LDRT_POST_REG: 975 case ARM::LDRT_POST_IMM: 976 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 977 return false; 978 break; 979 default: 980 break; 981 } 982 983 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 984 985 ARM_AM::AddrOpc Op = ARM_AM::add; 986 if (!fieldFromInstruction32(Insn, 23, 1)) 987 Op = ARM_AM::sub; 988 989 bool writeback = (P == 0) || (W == 1); 990 unsigned idx_mode = 0; 991 if (P && writeback) 992 idx_mode = ARMII::IndexModePre; 993 else if (!P && writeback) 994 idx_mode = ARMII::IndexModePost; 995 996 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE 997 998 if (reg) { 999 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 1000 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1001 switch( fieldFromInstruction32(Insn, 5, 2)) { 1002 case 0: 1003 Opc = ARM_AM::lsl; 1004 break; 1005 case 1: 1006 Opc = ARM_AM::lsr; 1007 break; 1008 case 2: 1009 Opc = ARM_AM::asr; 1010 break; 1011 case 3: 1012 Opc = ARM_AM::ror; 1013 break; 1014 default: 1015 return false; 1016 } 1017 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1018 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1019 1020 Inst.addOperand(MCOperand::CreateImm(imm)); 1021 } else { 1022 Inst.addOperand(MCOperand::CreateReg(0)); 1023 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1024 Inst.addOperand(MCOperand::CreateImm(tmp)); 1025 } 1026 1027 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1028 1029 return true; 1030} 1031 1032static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1033 uint64_t Address, const void *Decoder) { 1034 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1035 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1036 unsigned type = fieldFromInstruction32(Val, 5, 2); 1037 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1038 unsigned U = fieldFromInstruction32(Val, 12, 1); 1039 1040 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1041 switch (type) { 1042 case 0: 1043 ShOp = ARM_AM::lsl; 1044 break; 1045 case 1: 1046 ShOp = ARM_AM::lsr; 1047 break; 1048 case 2: 1049 ShOp = ARM_AM::asr; 1050 break; 1051 case 3: 1052 ShOp = ARM_AM::ror; 1053 break; 1054 } 1055 1056 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1057 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1058 unsigned shift; 1059 if (U) 1060 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1061 else 1062 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1063 Inst.addOperand(MCOperand::CreateImm(shift)); 1064 1065 return true; 1066} 1067 1068static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1069 uint64_t Address, const void *Decoder) { 1070 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1071 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1072 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1073 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1074 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1075 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1076 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1077 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1078 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1079 1080 bool writeback = (W == 1) | (P == 0); 1081 if (writeback) { // Writeback 1082 if (P) 1083 U |= ARMII::IndexModePre << 9; 1084 else 1085 U |= ARMII::IndexModePost << 9; 1086 1087 // On stores, the writeback operand precedes Rt. 1088 switch (Inst.getOpcode()) { 1089 case ARM::STRD: 1090 case ARM::STRD_PRE: 1091 case ARM::STRD_POST: 1092 case ARM::STRH: 1093 case ARM::STRH_PRE: 1094 case ARM::STRH_POST: 1095 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1096 return false; 1097 break; 1098 default: 1099 break; 1100 } 1101 } 1102 1103 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1104 return false; 1105 switch (Inst.getOpcode()) { 1106 case ARM::STRD: 1107 case ARM::STRD_PRE: 1108 case ARM::STRD_POST: 1109 case ARM::LDRD: 1110 case ARM::LDRD_PRE: 1111 case ARM::LDRD_POST: 1112 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1113 return false; 1114 break; 1115 default: 1116 break; 1117 } 1118 1119 if (writeback) { 1120 // On loads, the writeback operand comes after Rt. 1121 switch (Inst.getOpcode()) { 1122 case ARM::LDRD: 1123 case ARM::LDRD_PRE: 1124 case ARM::LDRD_POST: 1125 case ARM::LDRH: 1126 case ARM::LDRH_PRE: 1127 case ARM::LDRH_POST: 1128 case ARM::LDRSH: 1129 case ARM::LDRSH_PRE: 1130 case ARM::LDRSH_POST: 1131 case ARM::LDRSB: 1132 case ARM::LDRSB_PRE: 1133 case ARM::LDRSB_POST: 1134 case ARM::LDRHTr: 1135 case ARM::LDRSBTr: 1136 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1137 return false; 1138 break; 1139 default: 1140 break; 1141 } 1142 } 1143 1144 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1145 return false; 1146 1147 if (type) { 1148 Inst.addOperand(MCOperand::CreateReg(0)); 1149 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1150 } else { 1151 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1152 return false; 1153 Inst.addOperand(MCOperand::CreateImm(U)); 1154 } 1155 1156 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1157 1158 return true; 1159} 1160 1161static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1162 uint64_t Address, const void *Decoder) { 1163 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1164 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1165 1166 switch (mode) { 1167 case 0: 1168 mode = ARM_AM::da; 1169 break; 1170 case 1: 1171 mode = ARM_AM::ia; 1172 break; 1173 case 2: 1174 mode = ARM_AM::db; 1175 break; 1176 case 3: 1177 mode = ARM_AM::ib; 1178 break; 1179 } 1180 1181 Inst.addOperand(MCOperand::CreateImm(mode)); 1182 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1183 1184 return true; 1185} 1186 1187static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1188 unsigned Insn, 1189 uint64_t Address, const void *Decoder) { 1190 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1191 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1192 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1193 1194 if (pred == 0xF) { 1195 switch (Inst.getOpcode()) { 1196 case ARM::STMDA: 1197 Inst.setOpcode(ARM::RFEDA); 1198 break; 1199 case ARM::STMDA_UPD: 1200 Inst.setOpcode(ARM::RFEDA_UPD); 1201 break; 1202 case ARM::STMDB: 1203 Inst.setOpcode(ARM::RFEDB); 1204 break; 1205 case ARM::STMDB_UPD: 1206 Inst.setOpcode(ARM::RFEDB_UPD); 1207 break; 1208 case ARM::STMIA: 1209 Inst.setOpcode(ARM::RFEIA); 1210 break; 1211 case ARM::STMIA_UPD: 1212 Inst.setOpcode(ARM::RFEIA_UPD); 1213 break; 1214 case ARM::STMIB: 1215 Inst.setOpcode(ARM::RFEIB); 1216 break; 1217 case ARM::STMIB_UPD: 1218 Inst.setOpcode(ARM::RFEIB_UPD); 1219 break; 1220 } 1221 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1222 } 1223 1224 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1225 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1226 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1227 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1228 return false; 1229 1230 return true; 1231} 1232 1233static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1234 uint64_t Address, const void *Decoder) { 1235 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1236 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1237 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1238 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1239 1240 // imod == '01' --> UNPREDICTABLE 1241 if (imod == 1) return false; 1242 1243 if (M && mode && imod && iflags) { 1244 Inst.setOpcode(ARM::CPS3p); 1245 Inst.addOperand(MCOperand::CreateImm(imod)); 1246 Inst.addOperand(MCOperand::CreateImm(iflags)); 1247 Inst.addOperand(MCOperand::CreateImm(mode)); 1248 return true; 1249 } else if (!mode && !M) { 1250 Inst.setOpcode(ARM::CPS2p); 1251 Inst.addOperand(MCOperand::CreateImm(imod)); 1252 Inst.addOperand(MCOperand::CreateImm(iflags)); 1253 return true; 1254 } else if (!imod && !iflags && M) { 1255 Inst.setOpcode(ARM::CPS1p); 1256 Inst.addOperand(MCOperand::CreateImm(mode)); 1257 return true; 1258 } 1259 1260 return false; 1261} 1262 1263static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1264 uint64_t Address, const void *Decoder) { 1265 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1266 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1267 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1268 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1269 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1270 1271 if (pred == 0xF) 1272 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1273 1274 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1275 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1276 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1277 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1278 return false; 1279 1280 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1281 1282 return true; 1283} 1284 1285static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1286 uint64_t Address, const void *Decoder) { 1287 unsigned add = fieldFromInstruction32(Val, 12, 1); 1288 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1289 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1290 1291 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1292 return false; 1293 1294 if (!add) imm *= -1; 1295 if (imm == 0 && !add) imm = INT32_MIN; 1296 Inst.addOperand(MCOperand::CreateImm(imm)); 1297 1298 return true; 1299} 1300 1301static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1302 uint64_t Address, const void *Decoder) { 1303 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1304 unsigned U = fieldFromInstruction32(Val, 8, 1); 1305 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1306 1307 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1308 return false; 1309 1310 if (U) 1311 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1312 else 1313 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1314 1315 return true; 1316} 1317 1318static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1319 uint64_t Address, const void *Decoder) { 1320 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1321} 1322 1323static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1324 uint64_t Address, const void *Decoder) { 1325 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1326 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1327 1328 if (pred == 0xF) { 1329 Inst.setOpcode(ARM::BLXi); 1330 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1331 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1332 return true; 1333 } 1334 1335 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1336 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1337 1338 return true; 1339} 1340 1341 1342static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1343 uint64_t Address, const void *Decoder) { 1344 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1345 return true; 1346} 1347 1348static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1349 uint64_t Address, const void *Decoder) { 1350 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1351 unsigned align = fieldFromInstruction32(Val, 4, 2); 1352 1353 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1354 return false; 1355 if (!align) 1356 Inst.addOperand(MCOperand::CreateImm(0)); 1357 else 1358 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1359 1360 return true; 1361} 1362 1363static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1364 uint64_t Address, const void *Decoder) { 1365 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1366 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1367 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1368 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1369 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1370 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1371 1372 // First output register 1373 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1374 1375 // Second output register 1376 switch (Inst.getOpcode()) { 1377 case ARM::VLD1q8: 1378 case ARM::VLD1q16: 1379 case ARM::VLD1q32: 1380 case ARM::VLD1q64: 1381 case ARM::VLD1q8_UPD: 1382 case ARM::VLD1q16_UPD: 1383 case ARM::VLD1q32_UPD: 1384 case ARM::VLD1q64_UPD: 1385 case ARM::VLD1d8T: 1386 case ARM::VLD1d16T: 1387 case ARM::VLD1d32T: 1388 case ARM::VLD1d64T: 1389 case ARM::VLD1d8T_UPD: 1390 case ARM::VLD1d16T_UPD: 1391 case ARM::VLD1d32T_UPD: 1392 case ARM::VLD1d64T_UPD: 1393 case ARM::VLD1d8Q: 1394 case ARM::VLD1d16Q: 1395 case ARM::VLD1d32Q: 1396 case ARM::VLD1d64Q: 1397 case ARM::VLD1d8Q_UPD: 1398 case ARM::VLD1d16Q_UPD: 1399 case ARM::VLD1d32Q_UPD: 1400 case ARM::VLD1d64Q_UPD: 1401 case ARM::VLD2d8: 1402 case ARM::VLD2d16: 1403 case ARM::VLD2d32: 1404 case ARM::VLD2d8_UPD: 1405 case ARM::VLD2d16_UPD: 1406 case ARM::VLD2d32_UPD: 1407 case ARM::VLD2q8: 1408 case ARM::VLD2q16: 1409 case ARM::VLD2q32: 1410 case ARM::VLD2q8_UPD: 1411 case ARM::VLD2q16_UPD: 1412 case ARM::VLD2q32_UPD: 1413 case ARM::VLD3d8: 1414 case ARM::VLD3d16: 1415 case ARM::VLD3d32: 1416 case ARM::VLD3d8_UPD: 1417 case ARM::VLD3d16_UPD: 1418 case ARM::VLD3d32_UPD: 1419 case ARM::VLD4d8: 1420 case ARM::VLD4d16: 1421 case ARM::VLD4d32: 1422 case ARM::VLD4d8_UPD: 1423 case ARM::VLD4d16_UPD: 1424 case ARM::VLD4d32_UPD: 1425 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1426 break; 1427 case ARM::VLD2b8: 1428 case ARM::VLD2b16: 1429 case ARM::VLD2b32: 1430 case ARM::VLD2b8_UPD: 1431 case ARM::VLD2b16_UPD: 1432 case ARM::VLD2b32_UPD: 1433 case ARM::VLD3q8: 1434 case ARM::VLD3q16: 1435 case ARM::VLD3q32: 1436 case ARM::VLD3q8_UPD: 1437 case ARM::VLD3q16_UPD: 1438 case ARM::VLD3q32_UPD: 1439 case ARM::VLD4q8: 1440 case ARM::VLD4q16: 1441 case ARM::VLD4q32: 1442 case ARM::VLD4q8_UPD: 1443 case ARM::VLD4q16_UPD: 1444 case ARM::VLD4q32_UPD: 1445 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1446 default: 1447 break; 1448 } 1449 1450 // Third output register 1451 switch(Inst.getOpcode()) { 1452 case ARM::VLD1d8T: 1453 case ARM::VLD1d16T: 1454 case ARM::VLD1d32T: 1455 case ARM::VLD1d64T: 1456 case ARM::VLD1d8T_UPD: 1457 case ARM::VLD1d16T_UPD: 1458 case ARM::VLD1d32T_UPD: 1459 case ARM::VLD1d64T_UPD: 1460 case ARM::VLD1d8Q: 1461 case ARM::VLD1d16Q: 1462 case ARM::VLD1d32Q: 1463 case ARM::VLD1d64Q: 1464 case ARM::VLD1d8Q_UPD: 1465 case ARM::VLD1d16Q_UPD: 1466 case ARM::VLD1d32Q_UPD: 1467 case ARM::VLD1d64Q_UPD: 1468 case ARM::VLD2q8: 1469 case ARM::VLD2q16: 1470 case ARM::VLD2q32: 1471 case ARM::VLD2q8_UPD: 1472 case ARM::VLD2q16_UPD: 1473 case ARM::VLD2q32_UPD: 1474 case ARM::VLD3d8: 1475 case ARM::VLD3d16: 1476 case ARM::VLD3d32: 1477 case ARM::VLD3d8_UPD: 1478 case ARM::VLD3d16_UPD: 1479 case ARM::VLD3d32_UPD: 1480 case ARM::VLD4d8: 1481 case ARM::VLD4d16: 1482 case ARM::VLD4d32: 1483 case ARM::VLD4d8_UPD: 1484 case ARM::VLD4d16_UPD: 1485 case ARM::VLD4d32_UPD: 1486 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1487 break; 1488 case ARM::VLD3q8: 1489 case ARM::VLD3q16: 1490 case ARM::VLD3q32: 1491 case ARM::VLD3q8_UPD: 1492 case ARM::VLD3q16_UPD: 1493 case ARM::VLD3q32_UPD: 1494 case ARM::VLD4q8: 1495 case ARM::VLD4q16: 1496 case ARM::VLD4q32: 1497 case ARM::VLD4q8_UPD: 1498 case ARM::VLD4q16_UPD: 1499 case ARM::VLD4q32_UPD: 1500 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1501 break; 1502 default: 1503 break; 1504 } 1505 1506 // Fourth output register 1507 switch (Inst.getOpcode()) { 1508 case ARM::VLD1d8Q: 1509 case ARM::VLD1d16Q: 1510 case ARM::VLD1d32Q: 1511 case ARM::VLD1d64Q: 1512 case ARM::VLD1d8Q_UPD: 1513 case ARM::VLD1d16Q_UPD: 1514 case ARM::VLD1d32Q_UPD: 1515 case ARM::VLD1d64Q_UPD: 1516 case ARM::VLD2q8: 1517 case ARM::VLD2q16: 1518 case ARM::VLD2q32: 1519 case ARM::VLD2q8_UPD: 1520 case ARM::VLD2q16_UPD: 1521 case ARM::VLD2q32_UPD: 1522 case ARM::VLD4d8: 1523 case ARM::VLD4d16: 1524 case ARM::VLD4d32: 1525 case ARM::VLD4d8_UPD: 1526 case ARM::VLD4d16_UPD: 1527 case ARM::VLD4d32_UPD: 1528 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1529 break; 1530 case ARM::VLD4q8: 1531 case ARM::VLD4q16: 1532 case ARM::VLD4q32: 1533 case ARM::VLD4q8_UPD: 1534 case ARM::VLD4q16_UPD: 1535 case ARM::VLD4q32_UPD: 1536 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1537 break; 1538 default: 1539 break; 1540 } 1541 1542 // Writeback operand 1543 switch (Inst.getOpcode()) { 1544 case ARM::VLD1d8_UPD: 1545 case ARM::VLD1d16_UPD: 1546 case ARM::VLD1d32_UPD: 1547 case ARM::VLD1d64_UPD: 1548 case ARM::VLD1q8_UPD: 1549 case ARM::VLD1q16_UPD: 1550 case ARM::VLD1q32_UPD: 1551 case ARM::VLD1q64_UPD: 1552 case ARM::VLD1d8T_UPD: 1553 case ARM::VLD1d16T_UPD: 1554 case ARM::VLD1d32T_UPD: 1555 case ARM::VLD1d64T_UPD: 1556 case ARM::VLD1d8Q_UPD: 1557 case ARM::VLD1d16Q_UPD: 1558 case ARM::VLD1d32Q_UPD: 1559 case ARM::VLD1d64Q_UPD: 1560 case ARM::VLD2d8_UPD: 1561 case ARM::VLD2d16_UPD: 1562 case ARM::VLD2d32_UPD: 1563 case ARM::VLD2q8_UPD: 1564 case ARM::VLD2q16_UPD: 1565 case ARM::VLD2q32_UPD: 1566 case ARM::VLD2b8_UPD: 1567 case ARM::VLD2b16_UPD: 1568 case ARM::VLD2b32_UPD: 1569 case ARM::VLD3d8_UPD: 1570 case ARM::VLD3d16_UPD: 1571 case ARM::VLD3d32_UPD: 1572 case ARM::VLD3q8_UPD: 1573 case ARM::VLD3q16_UPD: 1574 case ARM::VLD3q32_UPD: 1575 case ARM::VLD4d8_UPD: 1576 case ARM::VLD4d16_UPD: 1577 case ARM::VLD4d32_UPD: 1578 case ARM::VLD4q8_UPD: 1579 case ARM::VLD4q16_UPD: 1580 case ARM::VLD4q32_UPD: 1581 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1582 break; 1583 default: 1584 break; 1585 } 1586 1587 // AddrMode6 Base (register+alignment) 1588 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1589 1590 // AddrMode6 Offset (register) 1591 if (Rm == 0xD) 1592 Inst.addOperand(MCOperand::CreateReg(0)); 1593 else if (Rm != 0xF) { 1594 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1595 return false; 1596 } 1597 1598 return true; 1599} 1600 1601static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1602 uint64_t Address, const void *Decoder) { 1603 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1604 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1605 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1606 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1607 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1608 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1609 1610 // Writeback Operand 1611 switch (Inst.getOpcode()) { 1612 case ARM::VST1d8_UPD: 1613 case ARM::VST1d16_UPD: 1614 case ARM::VST1d32_UPD: 1615 case ARM::VST1d64_UPD: 1616 case ARM::VST1q8_UPD: 1617 case ARM::VST1q16_UPD: 1618 case ARM::VST1q32_UPD: 1619 case ARM::VST1q64_UPD: 1620 case ARM::VST1d8T_UPD: 1621 case ARM::VST1d16T_UPD: 1622 case ARM::VST1d32T_UPD: 1623 case ARM::VST1d64T_UPD: 1624 case ARM::VST1d8Q_UPD: 1625 case ARM::VST1d16Q_UPD: 1626 case ARM::VST1d32Q_UPD: 1627 case ARM::VST1d64Q_UPD: 1628 case ARM::VST2d8_UPD: 1629 case ARM::VST2d16_UPD: 1630 case ARM::VST2d32_UPD: 1631 case ARM::VST2q8_UPD: 1632 case ARM::VST2q16_UPD: 1633 case ARM::VST2q32_UPD: 1634 case ARM::VST2b8_UPD: 1635 case ARM::VST2b16_UPD: 1636 case ARM::VST2b32_UPD: 1637 case ARM::VST3d8_UPD: 1638 case ARM::VST3d16_UPD: 1639 case ARM::VST3d32_UPD: 1640 case ARM::VST3q8_UPD: 1641 case ARM::VST3q16_UPD: 1642 case ARM::VST3q32_UPD: 1643 case ARM::VST4d8_UPD: 1644 case ARM::VST4d16_UPD: 1645 case ARM::VST4d32_UPD: 1646 case ARM::VST4q8_UPD: 1647 case ARM::VST4q16_UPD: 1648 case ARM::VST4q32_UPD: 1649 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1650 return false; 1651 break; 1652 default: 1653 break; 1654 } 1655 1656 // AddrMode6 Base (register+alignment) 1657 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1658 1659 // AddrMode6 Offset (register) 1660 if (Rm == 0xD) 1661 Inst.addOperand(MCOperand::CreateReg(0)); 1662 else if (Rm != 0xF) { 1663 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1664 } 1665 1666 // First input register 1667 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1668 1669 // Second input register 1670 switch (Inst.getOpcode()) { 1671 case ARM::VST1q8: 1672 case ARM::VST1q16: 1673 case ARM::VST1q32: 1674 case ARM::VST1q64: 1675 case ARM::VST1q8_UPD: 1676 case ARM::VST1q16_UPD: 1677 case ARM::VST1q32_UPD: 1678 case ARM::VST1q64_UPD: 1679 case ARM::VST1d8T: 1680 case ARM::VST1d16T: 1681 case ARM::VST1d32T: 1682 case ARM::VST1d64T: 1683 case ARM::VST1d8T_UPD: 1684 case ARM::VST1d16T_UPD: 1685 case ARM::VST1d32T_UPD: 1686 case ARM::VST1d64T_UPD: 1687 case ARM::VST1d8Q: 1688 case ARM::VST1d16Q: 1689 case ARM::VST1d32Q: 1690 case ARM::VST1d64Q: 1691 case ARM::VST1d8Q_UPD: 1692 case ARM::VST1d16Q_UPD: 1693 case ARM::VST1d32Q_UPD: 1694 case ARM::VST1d64Q_UPD: 1695 case ARM::VST2d8: 1696 case ARM::VST2d16: 1697 case ARM::VST2d32: 1698 case ARM::VST2d8_UPD: 1699 case ARM::VST2d16_UPD: 1700 case ARM::VST2d32_UPD: 1701 case ARM::VST2q8: 1702 case ARM::VST2q16: 1703 case ARM::VST2q32: 1704 case ARM::VST2q8_UPD: 1705 case ARM::VST2q16_UPD: 1706 case ARM::VST2q32_UPD: 1707 case ARM::VST3d8: 1708 case ARM::VST3d16: 1709 case ARM::VST3d32: 1710 case ARM::VST3d8_UPD: 1711 case ARM::VST3d16_UPD: 1712 case ARM::VST3d32_UPD: 1713 case ARM::VST4d8: 1714 case ARM::VST4d16: 1715 case ARM::VST4d32: 1716 case ARM::VST4d8_UPD: 1717 case ARM::VST4d16_UPD: 1718 case ARM::VST4d32_UPD: 1719 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1720 break; 1721 case ARM::VST2b8: 1722 case ARM::VST2b16: 1723 case ARM::VST2b32: 1724 case ARM::VST2b8_UPD: 1725 case ARM::VST2b16_UPD: 1726 case ARM::VST2b32_UPD: 1727 case ARM::VST3q8: 1728 case ARM::VST3q16: 1729 case ARM::VST3q32: 1730 case ARM::VST3q8_UPD: 1731 case ARM::VST3q16_UPD: 1732 case ARM::VST3q32_UPD: 1733 case ARM::VST4q8: 1734 case ARM::VST4q16: 1735 case ARM::VST4q32: 1736 case ARM::VST4q8_UPD: 1737 case ARM::VST4q16_UPD: 1738 case ARM::VST4q32_UPD: 1739 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1740 break; 1741 default: 1742 break; 1743 } 1744 1745 // Third input register 1746 switch (Inst.getOpcode()) { 1747 case ARM::VST1d8T: 1748 case ARM::VST1d16T: 1749 case ARM::VST1d32T: 1750 case ARM::VST1d64T: 1751 case ARM::VST1d8T_UPD: 1752 case ARM::VST1d16T_UPD: 1753 case ARM::VST1d32T_UPD: 1754 case ARM::VST1d64T_UPD: 1755 case ARM::VST1d8Q: 1756 case ARM::VST1d16Q: 1757 case ARM::VST1d32Q: 1758 case ARM::VST1d64Q: 1759 case ARM::VST1d8Q_UPD: 1760 case ARM::VST1d16Q_UPD: 1761 case ARM::VST1d32Q_UPD: 1762 case ARM::VST1d64Q_UPD: 1763 case ARM::VST2q8: 1764 case ARM::VST2q16: 1765 case ARM::VST2q32: 1766 case ARM::VST2q8_UPD: 1767 case ARM::VST2q16_UPD: 1768 case ARM::VST2q32_UPD: 1769 case ARM::VST3d8: 1770 case ARM::VST3d16: 1771 case ARM::VST3d32: 1772 case ARM::VST3d8_UPD: 1773 case ARM::VST3d16_UPD: 1774 case ARM::VST3d32_UPD: 1775 case ARM::VST4d8: 1776 case ARM::VST4d16: 1777 case ARM::VST4d32: 1778 case ARM::VST4d8_UPD: 1779 case ARM::VST4d16_UPD: 1780 case ARM::VST4d32_UPD: 1781 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1782 break; 1783 case ARM::VST3q8: 1784 case ARM::VST3q16: 1785 case ARM::VST3q32: 1786 case ARM::VST3q8_UPD: 1787 case ARM::VST3q16_UPD: 1788 case ARM::VST3q32_UPD: 1789 case ARM::VST4q8: 1790 case ARM::VST4q16: 1791 case ARM::VST4q32: 1792 case ARM::VST4q8_UPD: 1793 case ARM::VST4q16_UPD: 1794 case ARM::VST4q32_UPD: 1795 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1796 break; 1797 default: 1798 break; 1799 } 1800 1801 // Fourth input register 1802 switch (Inst.getOpcode()) { 1803 case ARM::VST1d8Q: 1804 case ARM::VST1d16Q: 1805 case ARM::VST1d32Q: 1806 case ARM::VST1d64Q: 1807 case ARM::VST1d8Q_UPD: 1808 case ARM::VST1d16Q_UPD: 1809 case ARM::VST1d32Q_UPD: 1810 case ARM::VST1d64Q_UPD: 1811 case ARM::VST2q8: 1812 case ARM::VST2q16: 1813 case ARM::VST2q32: 1814 case ARM::VST2q8_UPD: 1815 case ARM::VST2q16_UPD: 1816 case ARM::VST2q32_UPD: 1817 case ARM::VST4d8: 1818 case ARM::VST4d16: 1819 case ARM::VST4d32: 1820 case ARM::VST4d8_UPD: 1821 case ARM::VST4d16_UPD: 1822 case ARM::VST4d32_UPD: 1823 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1824 break; 1825 case ARM::VST4q8: 1826 case ARM::VST4q16: 1827 case ARM::VST4q32: 1828 case ARM::VST4q8_UPD: 1829 case ARM::VST4q16_UPD: 1830 case ARM::VST4q32_UPD: 1831 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1832 break; 1833 default: 1834 break; 1835 } 1836 1837 return true; 1838} 1839 1840static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1841 uint64_t Address, const void *Decoder) { 1842 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1843 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1844 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1845 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1846 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1847 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1848 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1849 1850 align *= (1 << size); 1851 1852 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1853 if (regs == 2) { 1854 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1855 } 1856 if (Rm == 0xD) { 1857 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1858 } 1859 1860 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1861 Inst.addOperand(MCOperand::CreateImm(align)); 1862 1863 if (Rm == 0xD) 1864 Inst.addOperand(MCOperand::CreateReg(0)); 1865 else if (Rm != 0xF) { 1866 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1867 } 1868 1869 return true; 1870} 1871 1872static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1873 uint64_t Address, const void *Decoder) { 1874 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1875 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1876 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1877 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1878 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1879 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1880 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1881 align *= 2*size; 1882 1883 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1884 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1885 if (Rm == 0xD) { 1886 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1887 } 1888 1889 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1890 Inst.addOperand(MCOperand::CreateImm(align)); 1891 1892 if (Rm == 0xD) 1893 Inst.addOperand(MCOperand::CreateReg(0)); 1894 else if (Rm != 0xF) { 1895 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1896 } 1897 1898 return true; 1899} 1900 1901static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1902 uint64_t Address, const void *Decoder) { 1903 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1904 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1905 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1906 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1907 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1908 1909 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1910 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1911 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1912 return false; 1913 if (Rm == 0xD) { 1914 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1915 } 1916 1917 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1918 Inst.addOperand(MCOperand::CreateImm(0)); 1919 1920 if (Rm == 0xD) 1921 Inst.addOperand(MCOperand::CreateReg(0)); 1922 else if (Rm != 0xF) { 1923 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1924 } 1925 1926 return true; 1927} 1928 1929static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1930 uint64_t Address, const void *Decoder) { 1931 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1932 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1933 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1934 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1935 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1936 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1937 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1938 1939 if (size == 0x3) { 1940 size = 4; 1941 align = 16; 1942 } else { 1943 if (size == 2) { 1944 size = 1 << size; 1945 align *= 8; 1946 } else { 1947 size = 1 << size; 1948 align *= 4*size; 1949 } 1950 } 1951 1952 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1953 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1954 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1955 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 1956 return false; 1957 if (Rm == 0xD) { 1958 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1959 } 1960 1961 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1962 Inst.addOperand(MCOperand::CreateImm(align)); 1963 1964 if (Rm == 0xD) 1965 Inst.addOperand(MCOperand::CreateReg(0)); 1966 else if (Rm != 0xF) { 1967 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1968 } 1969 1970 return true; 1971} 1972 1973static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1974 uint64_t Address, const void *Decoder) { 1975 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1976 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1977 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1978 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1979 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1980 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1981 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1982 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1983 1984 if (Q) { 1985 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1986 } else { 1987 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1988 } 1989 1990 Inst.addOperand(MCOperand::CreateImm(imm)); 1991 1992 switch (Inst.getOpcode()) { 1993 case ARM::VORRiv4i16: 1994 case ARM::VORRiv2i32: 1995 case ARM::VBICiv4i16: 1996 case ARM::VBICiv2i32: 1997 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1998 break; 1999 case ARM::VORRiv8i16: 2000 case ARM::VORRiv4i32: 2001 case ARM::VBICiv8i16: 2002 case ARM::VBICiv4i32: 2003 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2004 break; 2005 default: 2006 break; 2007 } 2008 2009 return true; 2010} 2011 2012static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2013 uint64_t Address, const void *Decoder) { 2014 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2015 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2016 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2017 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2018 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2019 2020 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2021 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2022 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2023 2024 return true; 2025} 2026 2027static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2028 uint64_t Address, const void *Decoder) { 2029 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2030 return true; 2031} 2032 2033static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2034 uint64_t Address, const void *Decoder) { 2035 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2036 return true; 2037} 2038 2039static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2040 uint64_t Address, const void *Decoder) { 2041 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2042 return true; 2043} 2044 2045static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2046 uint64_t Address, const void *Decoder) { 2047 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2048 return true; 2049} 2050 2051static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2052 uint64_t Address, const void *Decoder) { 2053 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2054 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2055 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2056 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2057 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2058 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2059 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2060 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2061 2062 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2063 if (op) { 2064 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2065 } 2066 2067 for (unsigned i = 0; i < length; ++i) { 2068 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2069 } 2070 2071 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2072 2073 return true; 2074} 2075 2076static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2077 uint64_t Address, const void *Decoder) { 2078 // The immediate needs to be a fully instantiated float. However, the 2079 // auto-generated decoder is only able to fill in some of the bits 2080 // necessary. For instance, the 'b' bit is replicated multiple times, 2081 // and is even present in inverted form in one bit. We do a little 2082 // binary parsing here to fill in those missing bits, and then 2083 // reinterpret it all as a float. 2084 union { 2085 uint32_t integer; 2086 float fp; 2087 } fp_conv; 2088 2089 fp_conv.integer = Val; 2090 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2091 fp_conv.integer |= b << 26; 2092 fp_conv.integer |= b << 27; 2093 fp_conv.integer |= b << 28; 2094 fp_conv.integer |= b << 29; 2095 fp_conv.integer |= (~b & 0x1) << 30; 2096 2097 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2098 return true; 2099} 2100 2101static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2102 uint64_t Address, const void *Decoder) { 2103 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2104 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2105 2106 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2107 2108 if (Inst.getOpcode() == ARM::tADR) 2109 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2110 else if (Inst.getOpcode() == ARM::tADDrSPi) 2111 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2112 else 2113 return false; 2114 2115 Inst.addOperand(MCOperand::CreateImm(imm)); 2116 return true; 2117} 2118 2119static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2120 uint64_t Address, const void *Decoder) { 2121 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2122 return true; 2123} 2124 2125static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2126 uint64_t Address, const void *Decoder) { 2127 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2128 return true; 2129} 2130 2131static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2132 uint64_t Address, const void *Decoder) { 2133 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2134 return true; 2135} 2136 2137static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2138 uint64_t Address, const void *Decoder) { 2139 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2140 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2141 2142 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2143 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2144 return false; 2145 2146 return true; 2147} 2148 2149static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2150 uint64_t Address, const void *Decoder) { 2151 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2152 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2153 2154 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2155 Inst.addOperand(MCOperand::CreateImm(imm)); 2156 2157 return true; 2158} 2159 2160static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2161 uint64_t Address, const void *Decoder) { 2162 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2163 2164 return true; 2165} 2166 2167static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2168 uint64_t Address, const void *Decoder) { 2169 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2170 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2171 2172 return true; 2173} 2174 2175static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2176 uint64_t Address, const void *Decoder) { 2177 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2178 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2179 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2180 2181 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2182 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2183 return false; 2184 Inst.addOperand(MCOperand::CreateImm(imm)); 2185 2186 return true; 2187} 2188 2189static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2190 uint64_t Address, const void *Decoder) { 2191 if (Inst.getOpcode() != ARM::t2PLDs) { 2192 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2193 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2194 } 2195 2196 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2197 if (Rn == 0xF) { 2198 switch (Inst.getOpcode()) { 2199 case ARM::t2LDRBs: 2200 Inst.setOpcode(ARM::t2LDRBpci); 2201 break; 2202 case ARM::t2LDRHs: 2203 Inst.setOpcode(ARM::t2LDRHpci); 2204 break; 2205 case ARM::t2LDRSHs: 2206 Inst.setOpcode(ARM::t2LDRSHpci); 2207 break; 2208 case ARM::t2LDRSBs: 2209 Inst.setOpcode(ARM::t2LDRSBpci); 2210 break; 2211 case ARM::t2PLDs: 2212 Inst.setOpcode(ARM::t2PLDi12); 2213 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2214 break; 2215 default: 2216 return false; 2217 } 2218 2219 int imm = fieldFromInstruction32(Insn, 0, 12); 2220 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2221 Inst.addOperand(MCOperand::CreateImm(imm)); 2222 2223 return true; 2224 } 2225 2226 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2227 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2228 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2229 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2230 2231 return true; 2232} 2233 2234static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2235 uint64_t Address, const void *Decoder) { 2236 int imm = Val & 0xFF; 2237 if (!(Val & 0x100)) imm *= -1; 2238 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2239 2240 return true; 2241} 2242 2243static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2244 uint64_t Address, const void *Decoder) { 2245 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2246 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2247 2248 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2249 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2250 return false; 2251 2252 return true; 2253} 2254 2255static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2256 uint64_t Address, const void *Decoder) { 2257 int imm = Val & 0xFF; 2258 if (!(Val & 0x100)) imm *= -1; 2259 Inst.addOperand(MCOperand::CreateImm(imm)); 2260 2261 return true; 2262} 2263 2264 2265static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2266 uint64_t Address, const void *Decoder) { 2267 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2268 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2269 2270 // Some instructions always use an additive offset. 2271 switch (Inst.getOpcode()) { 2272 case ARM::t2LDRT: 2273 case ARM::t2LDRBT: 2274 case ARM::t2LDRHT: 2275 case ARM::t2LDRSBT: 2276 case ARM::t2LDRSHT: 2277 imm |= 0x100; 2278 break; 2279 default: 2280 break; 2281 } 2282 2283 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2284 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2285 return false; 2286 2287 return true; 2288} 2289 2290 2291static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2292 uint64_t Address, const void *Decoder) { 2293 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2294 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2295 2296 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2297 Inst.addOperand(MCOperand::CreateImm(imm)); 2298 2299 return true; 2300} 2301 2302 2303static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2304 uint64_t Address, const void *Decoder) { 2305 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2306 2307 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2308 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2309 Inst.addOperand(MCOperand::CreateImm(imm)); 2310 2311 return true; 2312} 2313 2314static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2315 uint64_t Address, const void *Decoder) { 2316 if (Inst.getOpcode() == ARM::tADDrSP) { 2317 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2318 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2319 2320 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2321 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2322 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2323 } else if (Inst.getOpcode() == ARM::tADDspr) { 2324 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2325 2326 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2327 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2328 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2329 } 2330 2331 return true; 2332} 2333 2334static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2335 uint64_t Address, const void *Decoder) { 2336 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2337 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2338 2339 Inst.addOperand(MCOperand::CreateImm(imod)); 2340 Inst.addOperand(MCOperand::CreateImm(flags)); 2341 2342 return true; 2343} 2344 2345static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2346 uint64_t Address, const void *Decoder) { 2347 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2348 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2349 2350 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2351 Inst.addOperand(MCOperand::CreateImm(add)); 2352 2353 return true; 2354} 2355 2356static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2357 uint64_t Address, const void *Decoder) { 2358 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2359 return true; 2360} 2361 2362static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2363 uint64_t Address, const void *Decoder) { 2364 if (Val == 0xA || Val == 0xB) 2365 return false; 2366 2367 Inst.addOperand(MCOperand::CreateImm(Val)); 2368 return true; 2369} 2370 2371static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2372 uint64_t Address, const void *Decoder) { 2373 if (Val == 0) 2374 Inst.addOperand(MCOperand::CreateImm(32)); 2375 else 2376 Inst.addOperand(MCOperand::CreateImm(Val)); 2377 return true; 2378} 2379 2380static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2381 uint64_t Address, const void *Decoder) { 2382 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2383 if (pred == 0xE || pred == 0xF) { 2384 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2385 switch (opc) { 2386 default: 2387 return false; 2388 case 0: 2389 Inst.setOpcode(ARM::t2DSB); 2390 break; 2391 case 1: 2392 Inst.setOpcode(ARM::t2DMB); 2393 break; 2394 case 2: 2395 Inst.setOpcode(ARM::t2ISB); 2396 return true; 2397 } 2398 2399 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2400 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2401 } 2402 2403 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2404 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2405 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2406 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2407 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2408 2409 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2410 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2411 return false; 2412 2413 return true; 2414} 2415 2416// Decode a shifted immediate operand. These basically consist 2417// of an 8-bit value, and a 4-bit directive that specifies either 2418// a splat operation or a rotation. 2419static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2420 uint64_t Address, const void *Decoder) { 2421 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2422 if (ctrl == 0) { 2423 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2424 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2425 switch (byte) { 2426 case 0: 2427 Inst.addOperand(MCOperand::CreateImm(imm)); 2428 break; 2429 case 1: 2430 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2431 break; 2432 case 2: 2433 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2434 break; 2435 case 3: 2436 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2437 (imm << 8) | imm)); 2438 break; 2439 } 2440 } else { 2441 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2442 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2443 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2444 Inst.addOperand(MCOperand::CreateImm(imm)); 2445 } 2446 2447 return true; 2448} 2449 2450static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2451 uint64_t Address, const void *Decoder){ 2452 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2453 return true; 2454} 2455 2456static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2457 uint64_t Address, const void *Decoder){ 2458 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2459 return true; 2460} 2461 2462static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2463 uint64_t Address, const void *Decoder) { 2464 switch (Val) { 2465 default: 2466 return false; 2467 case 0xF: // SY 2468 case 0xE: // ST 2469 case 0xB: // ISH 2470 case 0xA: // ISHST 2471 case 0x7: // NSH 2472 case 0x6: // NSHST 2473 case 0x3: // OSH 2474 case 0x2: // OSHST 2475 break; 2476 } 2477 2478 Inst.addOperand(MCOperand::CreateImm(Val)); 2479 return true; 2480} 2481 2482static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2483 uint64_t Address, const void *Decoder) { 2484 if (!Val) return false; 2485 Inst.addOperand(MCOperand::CreateImm(Val)); 2486 return true; 2487} 2488 2489static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2490 uint64_t Address, const void *Decoder) { 2491 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2492 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2493 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2494 2495 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2496 2497 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2498 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2499 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2500 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2501 2502 return true; 2503} 2504 2505 2506static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2507 uint64_t Address, const void *Decoder) { 2508 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2509 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2510 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2511 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2512 2513 if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2514 2515 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2516 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; 2517 2518 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2519 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2520 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2521 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2522 2523 return true; 2524} 2525 2526static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2527 uint64_t Address, const void *Decoder) { 2528 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2529 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2530 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2531 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2532 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2533 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2534 2535 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2536 2537 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2538 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2539 if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false; 2540 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2541 2542 return true; 2543} 2544 2545static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2546 uint64_t Address, const void *Decoder) { 2547 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2548 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2549 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2550 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2551 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2552 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2553 2554 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2555 2556 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2557 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2558 if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false; 2559 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2560 2561 return true; 2562} 2563