ARMDisassembler.cpp revision 1af7f7291d0689e2d58f900c9b5ecaddec56caa1 
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE "arm-disassembler"
11
12#include "ARMDisassembler.h"
13#include "ARM.h"
14#include "ARMRegisterInfo.h"
15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "llvm/MC/EDInstInfo.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Support/MemoryObject.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/TargetRegistry.h"
25#include "llvm/Support/raw_ostream.h"
26
27// Pull DecodeStatus and its enum values into the global namespace.
28typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
29#define Success llvm::MCDisassembler::Success
30#define Unpredictable llvm::MCDisassembler::SoftFail
31#define Fail llvm::MCDisassembler::Fail
32
33// Helper macro to perform setwise reduction of the current running status
34// and another status, and return if the new status is Fail.
35#define CHECK(S,X) do {                           \
36    S = (DecodeStatus) ((int)S & (X));            \
37    if (S == Fail) return Fail;                   \
38  } while(0)
39
40// Forward declare these because the autogenerated code will reference them.
41// Definitions are further down.
42static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43                                   uint64_t Address, const void *Decoder);
44static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
45                                               unsigned RegNo, uint64_t Address,
46                                               const void *Decoder);
47static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
48                                   uint64_t Address, const void *Decoder);
49static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
50                                   uint64_t Address, const void *Decoder);
51static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52                                   uint64_t Address, const void *Decoder);
53static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
54                                   uint64_t Address, const void *Decoder);
55static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
56                                   uint64_t Address, const void *Decoder);
57static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
58                                   uint64_t Address, const void *Decoder);
59static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
60                                                unsigned RegNo,
61                                                uint64_t Address,
62                                                const void *Decoder);
63static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
64                                   uint64_t Address, const void *Decoder);
65
66static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
67                               uint64_t Address, const void *Decoder);
68static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
69                               uint64_t Address, const void *Decoder);
70static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
71                               uint64_t Address, const void *Decoder);
72static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
73                               uint64_t Address, const void *Decoder);
74static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
75                               uint64_t Address, const void *Decoder);
76static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
77                               uint64_t Address, const void *Decoder);
78static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
79                               uint64_t Address, const void *Decoder);
80
81static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
82                               uint64_t Address, const void *Decoder);
83static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
84                               uint64_t Address, const void *Decoder);
85static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
86                                                  unsigned Insn,
87                                                  uint64_t Address,
88                                                  const void *Decoder);
89static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
90                               uint64_t Address, const void *Decoder);
91static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
92                               uint64_t Address, const void *Decoder);
93static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
94                               uint64_t Address, const void *Decoder);
95static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
96                               uint64_t Address, const void *Decoder);
97
98static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
99                                                  unsigned Insn,
100                                                  uint64_t Adddress,
101                                                  const void *Decoder);
102static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
103                               uint64_t Address, const void *Decoder);
104static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
105                               uint64_t Address, const void *Decoder);
106static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
107                               uint64_t Address, const void *Decoder);
108static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
109                               uint64_t Address, const void *Decoder);
110static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
111                               uint64_t Address, const void *Decoder);
112static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
113                               uint64_t Address, const void *Decoder);
114static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
115                               uint64_t Address, const void *Decoder);
116static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
117                               uint64_t Address, const void *Decoder);
118static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
119                               uint64_t Address, const void *Decoder);
120static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
121                               uint64_t Address, const void *Decoder);
122static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
123                               uint64_t Address, const void *Decoder);
124static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
125                               uint64_t Address, const void *Decoder);
126static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
127                               uint64_t Address, const void *Decoder);
128static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
129                               uint64_t Address, const void *Decoder);
130static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
131                               uint64_t Address, const void *Decoder);
132static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
133                               uint64_t Address, const void *Decoder);
134static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
135                               uint64_t Address, const void *Decoder);
136static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
137                               uint64_t Address, const void *Decoder);
138static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
139                               uint64_t Address, const void *Decoder);
140static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
141                               uint64_t Address, const void *Decoder);
142static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
143                               uint64_t Address, const void *Decoder);
144static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
145                               uint64_t Address, const void *Decoder);
146static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
147                               uint64_t Address, const void *Decoder);
148static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
149                               uint64_t Address, const void *Decoder);
150static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
151                               uint64_t Address, const void *Decoder);
152static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
153                               uint64_t Address, const void *Decoder);
154static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
155                               uint64_t Address, const void *Decoder);
156static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
157                               uint64_t Address, const void *Decoder);
158static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
159                               uint64_t Address, const void *Decoder);
160static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
161                               uint64_t Address, const void *Decoder);
162static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
163                               uint64_t Address, const void *Decoder);
164static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
165                               uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
167                               uint64_t Address, const void *Decoder);
168static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
169                               uint64_t Address, const void *Decoder);
170static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
171                               uint64_t Address, const void *Decoder);
172static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
173                               uint64_t Address, const void *Decoder);
174static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
175                               uint64_t Address, const void *Decoder);
176static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
177                               uint64_t Address, const void *Decoder);
178static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
179                               uint64_t Address, const void *Decoder);
180static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
181                               uint64_t Address, const void *Decoder);
182static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
183                               uint64_t Address, const void *Decoder);
184
185static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
186                               uint64_t Address, const void *Decoder);
187static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
188                               uint64_t Address, const void *Decoder);
189static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
190                               uint64_t Address, const void *Decoder);
191static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
192                               uint64_t Address, const void *Decoder);
193static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
194                               uint64_t Address, const void *Decoder);
195static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
196                               uint64_t Address, const void *Decoder);
197static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
198                               uint64_t Address, const void *Decoder);
199static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
200                               uint64_t Address, const void *Decoder);
201static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
202                               uint64_t Address, const void *Decoder);
203static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
204                               uint64_t Address, const void *Decoder);
205static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
206                               uint64_t Address, const void *Decoder);
207static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
208                               uint64_t Address, const void *Decoder);
209static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
210                               uint64_t Address, const void *Decoder);
211static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
212                               uint64_t Address, const void *Decoder);
213static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
214                               uint64_t Address, const void *Decoder);
215static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
216                                uint64_t Address, const void *Decoder);
217static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
218                                uint64_t Address, const void *Decoder);
219static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
220                                uint64_t Address, const void *Decoder);
221static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
222                                uint64_t Address, const void *Decoder);
223static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
224                                uint64_t Address, const void *Decoder);
225static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
226                                uint64_t Address, const void *Decoder);
227static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
228                                uint64_t Address, const void *Decoder);
229static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
230                                uint64_t Address, const void *Decoder);
231static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
232                                uint64_t Address, const void *Decoder);
233static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val,
234                                uint64_t Address, const void *Decoder);
235
236#include "ARMGenDisassemblerTables.inc"
237#include "ARMGenInstrInfo.inc"
238#include "ARMGenEDInfo.inc"
239
240using namespace llvm;
241
242static MCDisassembler *createARMDisassembler(const Target &T) {
243  return new ARMDisassembler;
244}
245
246static MCDisassembler *createThumbDisassembler(const Target &T) {
247  return new ThumbDisassembler;
248}
249
250EDInstInfo *ARMDisassembler::getEDInfo() const {
251  return instInfoARM;
252}
253
254EDInstInfo *ThumbDisassembler::getEDInfo() const {
255  return instInfoARM;
256}
257
258DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
259                                             const MemoryObject &Region,
260                                             uint64_t Address,
261                                             raw_ostream &os) const {
262  uint8_t bytes[4];
263
264  // We want to read exactly 4 bytes of data.
265  if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
266    Size = 0;
267    return Fail;
268  }
269
270  // Encoded as a small-endian 32-bit word in the stream.
271  uint32_t insn = (bytes[3] << 24) |
272                  (bytes[2] << 16) |
273                  (bytes[1] <<  8) |
274                  (bytes[0] <<  0);
275
276  // Calling the auto-generated decoder function.
277  DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
278  if (result != Fail) {
279    Size = 4;
280    return result;
281  }
282
283  // Instructions that are shared between ARM and Thumb modes.
284  // FIXME: This shouldn't really exist.  It's an artifact of the
285  // fact that we fail to encode a few instructions properly for Thumb.
286  MI.clear();
287  result = decodeCommonInstruction32(MI, insn, Address, this);
288  if (result != Fail) {
289    Size = 4;
290    return result;
291  }
292
293  // VFP and NEON instructions, similarly, are shared between ARM
294  // and Thumb modes.
295  MI.clear();
296  result = decodeVFPInstruction32(MI, insn, Address, this);
297  if (result != Fail) {
298    Size = 4;
299    return result;
300  }
301
302  MI.clear();
303  result = decodeNEONDataInstruction32(MI, insn, Address, this);
304  if (result != Fail) {
305    Size = 4;
306    // Add a fake predicate operand, because we share these instruction
307    // definitions with Thumb2 where these instructions are predicable.
308    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
309    return result;
310  }
311
312  MI.clear();
313  result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
314  if (result != Fail) {
315    Size = 4;
316    // Add a fake predicate operand, because we share these instruction
317    // definitions with Thumb2 where these instructions are predicable.
318    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
319    return result;
320  }
321
322  MI.clear();
323  result = decodeNEONDupInstruction32(MI, insn, Address, this);
324  if (result != Fail) {
325    Size = 4;
326    // Add a fake predicate operand, because we share these instruction
327    // definitions with Thumb2 where these instructions are predicable.
328    if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
329    return result;
330  }
331
332  MI.clear();
333
334  Size = 0;
335  return Fail;
336}
337
338namespace llvm {
339extern MCInstrDesc ARMInsts[];
340}
341
342// Thumb1 instructions don't have explicit S bits.  Rather, they
343// implicitly set CPSR.  Since it's not represented in the encoding, the
344// auto-generated decoder won't inject the CPSR operand.  We need to fix
345// that as a post-pass.
346static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
347  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
348  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
349  MCInst::iterator I = MI.begin();
350  for (unsigned i = 0; i < NumOps; ++i, ++I) {
351    if (I == MI.end()) break;
352    if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
353      if (i > 0 && OpInfo[i-1].isPredicate()) continue;
354      MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
355      return;
356    }
357  }
358
359  MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
360}
361
362// Most Thumb instructions don't have explicit predicates in the
363// encoding, but rather get their predicates from IT context.  We need
364// to fix up the predicate operands using this context information as a
365// post-pass.
366void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
367  // A few instructions actually have predicates encoded in them.  Don't
368  // try to overwrite it if we're seeing one of those.
369  switch (MI.getOpcode()) {
370    case ARM::tBcc:
371    case ARM::t2Bcc:
372      return;
373    default:
374      break;
375  }
376
377  // If we're in an IT block, base the predicate on that.  Otherwise,
378  // assume a predicate of AL.
379  unsigned CC;
380  if (!ITBlock.empty()) {
381    CC = ITBlock.back();
382    if (CC == 0xF)
383      CC = ARMCC::AL;
384    ITBlock.pop_back();
385  } else
386    CC = ARMCC::AL;
387
388  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
389  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
390  MCInst::iterator I = MI.begin();
391  for (unsigned i = 0; i < NumOps; ++i, ++I) {
392    if (I == MI.end()) break;
393    if (OpInfo[i].isPredicate()) {
394      I = MI.insert(I, MCOperand::CreateImm(CC));
395      ++I;
396      if (CC == ARMCC::AL)
397        MI.insert(I, MCOperand::CreateReg(0));
398      else
399        MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
400      return;
401    }
402  }
403
404  I = MI.insert(I, MCOperand::CreateImm(CC));
405  ++I;
406  if (CC == ARMCC::AL)
407    MI.insert(I, MCOperand::CreateReg(0));
408  else
409    MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
410}
411
412// Thumb VFP instructions are a special case.  Because we share their
413// encodings between ARM and Thumb modes, and they are predicable in ARM
414// mode, the auto-generated decoder will give them an (incorrect)
415// predicate operand.  We need to rewrite these operands based on the IT
416// context as a post-pass.
417void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
418  unsigned CC;
419  if (!ITBlock.empty()) {
420    CC = ITBlock.back();
421    ITBlock.pop_back();
422  } else
423    CC = ARMCC::AL;
424
425  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
426  MCInst::iterator I = MI.begin();
427  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
428  for (unsigned i = 0; i < NumOps; ++i, ++I) {
429    if (OpInfo[i].isPredicate() ) {
430      I->setImm(CC);
431      ++I;
432      if (CC == ARMCC::AL)
433        I->setReg(0);
434      else
435        I->setReg(ARM::CPSR);
436      return;
437    }
438  }
439}
440
441DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
442                                               const MemoryObject &Region,
443                                               uint64_t Address,
444                                               raw_ostream &os) const {
445  uint8_t bytes[4];
446
447  // We want to read exactly 2 bytes of data.
448  if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
449    Size = 0;
450    return Fail;
451  }
452
453  uint16_t insn16 = (bytes[1] << 8) | bytes[0];
454  DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
455  if (result != Fail) {
456    Size = 2;
457    AddThumbPredicate(MI);
458    return result;
459  }
460
461  MI.clear();
462  result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
463  if (result) {
464    Size = 2;
465    bool InITBlock = !ITBlock.empty();
466    AddThumbPredicate(MI);
467    AddThumb1SBit(MI, InITBlock);
468    return result;
469  }
470
471  MI.clear();
472  result = decodeThumb2Instruction16(MI, insn16, Address, this);
473  if (result != Fail) {
474    Size = 2;
475    AddThumbPredicate(MI);
476
477    // If we find an IT instruction, we need to parse its condition
478    // code and mask operands so that we can apply them correctly
479    // to the subsequent instructions.
480    if (MI.getOpcode() == ARM::t2IT) {
481      unsigned firstcond = MI.getOperand(0).getImm();
482      uint32_t mask = MI.getOperand(1).getImm();
483      unsigned zeros = CountTrailingZeros_32(mask);
484      mask >>= zeros+1;
485
486      for (unsigned i = 0; i < 4 - (zeros+1); ++i) {
487        if (firstcond ^ (mask & 1))
488          ITBlock.push_back(firstcond ^ 1);
489        else
490          ITBlock.push_back(firstcond);
491        mask >>= 1;
492      }
493      ITBlock.push_back(firstcond);
494    }
495
496    return result;
497  }
498
499  // We want to read exactly 4 bytes of data.
500  if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
501    Size = 0;
502    return Fail;
503  }
504
505  uint32_t insn32 = (bytes[3] <<  8) |
506                    (bytes[2] <<  0) |
507                    (bytes[1] << 24) |
508                    (bytes[0] << 16);
509  MI.clear();
510  result = decodeThumbInstruction32(MI, insn32, Address, this);
511  if (result != Fail) {
512    Size = 4;
513    bool InITBlock = ITBlock.size();
514    AddThumbPredicate(MI);
515    AddThumb1SBit(MI, InITBlock);
516    return result;
517  }
518
519  MI.clear();
520  result = decodeThumb2Instruction32(MI, insn32, Address, this);
521  if (result != Fail) {
522    Size = 4;
523    AddThumbPredicate(MI);
524    return result;
525  }
526
527  MI.clear();
528  result = decodeCommonInstruction32(MI, insn32, Address, this);
529  if (result != Fail) {
530    Size = 4;
531    AddThumbPredicate(MI);
532    return result;
533  }
534
535  MI.clear();
536  result = decodeVFPInstruction32(MI, insn32, Address, this);
537  if (result != Fail) {
538    Size = 4;
539    UpdateThumbVFPPredicate(MI);
540    return result;
541  }
542
543  MI.clear();
544  result = decodeNEONDupInstruction32(MI, insn32, Address, this);
545  if (result != Fail) {
546    Size = 4;
547    AddThumbPredicate(MI);
548    return result;
549  }
550
551  if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
552    MI.clear();
553    uint32_t NEONLdStInsn = insn32;
554    NEONLdStInsn &= 0xF0FFFFFF;
555    NEONLdStInsn |= 0x04000000;
556    result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
557    if (result != Fail) {
558      Size = 4;
559      AddThumbPredicate(MI);
560      return result;
561    }
562  }
563
564  if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
565    MI.clear();
566    uint32_t NEONDataInsn = insn32;
567    NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
568    NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
569    NEONDataInsn |= 0x12000000; // Set bits 28 and 25
570    result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
571    if (result != Fail) {
572      Size = 4;
573      AddThumbPredicate(MI);
574      return result;
575    }
576  }
577
578  Size = 0;
579  return Fail;
580}
581
582
583extern "C" void LLVMInitializeARMDisassembler() {
584  TargetRegistry::RegisterMCDisassembler(TheARMTarget,
585                                         createARMDisassembler);
586  TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
587                                         createThumbDisassembler);
588}
589
590static const unsigned GPRDecoderTable[] = {
591  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
592  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
593  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
594  ARM::R12, ARM::SP, ARM::LR, ARM::PC
595};
596
597static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
598                                   uint64_t Address, const void *Decoder) {
599  if (RegNo > 15)
600    return Fail;
601
602  unsigned Register = GPRDecoderTable[RegNo];
603  Inst.addOperand(MCOperand::CreateReg(Register));
604  return Success;
605}
606
607static DecodeStatus
608DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
609                           uint64_t Address, const void *Decoder) {
610  if (RegNo == 15) return Fail;
611  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
612}
613
614static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
615                                   uint64_t Address, const void *Decoder) {
616  if (RegNo > 7)
617    return Fail;
618  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
619}
620
621static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
622                                   uint64_t Address, const void *Decoder) {
623  unsigned Register = 0;
624  switch (RegNo) {
625    case 0:
626      Register = ARM::R0;
627      break;
628    case 1:
629      Register = ARM::R1;
630      break;
631    case 2:
632      Register = ARM::R2;
633      break;
634    case 3:
635      Register = ARM::R3;
636      break;
637    case 9:
638      Register = ARM::R9;
639      break;
640    case 12:
641      Register = ARM::R12;
642      break;
643    default:
644      return Fail;
645    }
646
647  Inst.addOperand(MCOperand::CreateReg(Register));
648  return Success;
649}
650
651static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
652                                   uint64_t Address, const void *Decoder) {
653  if (RegNo == 13 || RegNo == 15) return Fail;
654  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
655}
656
657static const unsigned SPRDecoderTable[] = {
658     ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
659     ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
660     ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
661    ARM::S12, ARM::S13, ARM::S14, ARM::S15,
662    ARM::S16, ARM::S17, ARM::S18, ARM::S19,
663    ARM::S20, ARM::S21, ARM::S22, ARM::S23,
664    ARM::S24, ARM::S25, ARM::S26, ARM::S27,
665    ARM::S28, ARM::S29, ARM::S30, ARM::S31
666};
667
668static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
669                                   uint64_t Address, const void *Decoder) {
670  if (RegNo > 31)
671    return Fail;
672
673  unsigned Register = SPRDecoderTable[RegNo];
674  Inst.addOperand(MCOperand::CreateReg(Register));
675  return Success;
676}
677
678static const unsigned DPRDecoderTable[] = {
679     ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
680     ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
681     ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
682    ARM::D12, ARM::D13, ARM::D14, ARM::D15,
683    ARM::D16, ARM::D17, ARM::D18, ARM::D19,
684    ARM::D20, ARM::D21, ARM::D22, ARM::D23,
685    ARM::D24, ARM::D25, ARM::D26, ARM::D27,
686    ARM::D28, ARM::D29, ARM::D30, ARM::D31
687};
688
689static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
690                                   uint64_t Address, const void *Decoder) {
691  if (RegNo > 31)
692    return Fail;
693
694  unsigned Register = DPRDecoderTable[RegNo];
695  Inst.addOperand(MCOperand::CreateReg(Register));
696  return Success;
697}
698
699static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
700                                   uint64_t Address, const void *Decoder) {
701  if (RegNo > 7)
702    return Fail;
703  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
704}
705
706static DecodeStatus
707DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
708                            uint64_t Address, const void *Decoder) {
709  if (RegNo > 15)
710    return Fail;
711  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
712}
713
714static const unsigned QPRDecoderTable[] = {
715     ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
716     ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
717     ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
718    ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
719};
720
721
722static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
723                                   uint64_t Address, const void *Decoder) {
724  if (RegNo > 31)
725    return Fail;
726  RegNo >>= 1;
727
728  unsigned Register = QPRDecoderTable[RegNo];
729  Inst.addOperand(MCOperand::CreateReg(Register));
730  return Success;
731}
732
733static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
734                               uint64_t Address, const void *Decoder) {
735  if (Val == 0xF) return Fail;
736  // AL predicate is not allowed on Thumb1 branches.
737  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
738    return Fail;
739  Inst.addOperand(MCOperand::CreateImm(Val));
740  if (Val == ARMCC::AL) {
741    Inst.addOperand(MCOperand::CreateReg(0));
742  } else
743    Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
744  return Success;
745}
746
747static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
748                               uint64_t Address, const void *Decoder) {
749  if (Val)
750    Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
751  else
752    Inst.addOperand(MCOperand::CreateReg(0));
753  return Success;
754}
755
756static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
757                               uint64_t Address, const void *Decoder) {
758  uint32_t imm = Val & 0xFF;
759  uint32_t rot = (Val & 0xF00) >> 7;
760  uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
761  Inst.addOperand(MCOperand::CreateImm(rot_imm));
762  return Success;
763}
764
765static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
766                               uint64_t Address, const void *Decoder) {
767  Val <<= 2;
768  Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
769  return Success;
770}
771
772static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
773                               uint64_t Address, const void *Decoder) {
774  DecodeStatus S = Success;
775
776  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
777  unsigned type = fieldFromInstruction32(Val, 5, 2);
778  unsigned imm = fieldFromInstruction32(Val, 7, 5);
779
780  // Register-immediate
781  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
782
783  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
784  switch (type) {
785    case 0:
786      Shift = ARM_AM::lsl;
787      break;
788    case 1:
789      Shift = ARM_AM::lsr;
790      break;
791    case 2:
792      Shift = ARM_AM::asr;
793      break;
794    case 3:
795      Shift = ARM_AM::ror;
796      break;
797  }
798
799  if (Shift == ARM_AM::ror && imm == 0)
800    Shift = ARM_AM::rrx;
801
802  unsigned Op = Shift | (imm << 3);
803  Inst.addOperand(MCOperand::CreateImm(Op));
804
805  return S;
806}
807
808static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
809                               uint64_t Address, const void *Decoder) {
810  DecodeStatus S = Success;
811
812  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
813  unsigned type = fieldFromInstruction32(Val, 5, 2);
814  unsigned Rs = fieldFromInstruction32(Val, 8, 4);
815
816  // Register-register
817  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
818  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));
819
820  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
821  switch (type) {
822    case 0:
823      Shift = ARM_AM::lsl;
824      break;
825    case 1:
826      Shift = ARM_AM::lsr;
827      break;
828    case 2:
829      Shift = ARM_AM::asr;
830      break;
831    case 3:
832      Shift = ARM_AM::ror;
833      break;
834  }
835
836  Inst.addOperand(MCOperand::CreateImm(Shift));
837
838  return S;
839}
840
841static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
842                                 uint64_t Address, const void *Decoder) {
843  DecodeStatus S = Success;
844
845  // Empty register lists are not allowed.
846  if (CountPopulation_32(Val) == 0) return Fail;
847  for (unsigned i = 0; i < 16; ++i) {
848    if (Val & (1 << i)) {
849      CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));
850    }
851  }
852
853  return S;
854}
855
856static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
857                                 uint64_t Address, const void *Decoder) {
858  DecodeStatus S = Success;
859
860  unsigned Vd = fieldFromInstruction32(Val, 8, 4);
861  unsigned regs = Val & 0xFF;
862
863  CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));
864  for (unsigned i = 0; i < (regs - 1); ++i) {
865    CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));
866  }
867
868  return S;
869}
870
871static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
872                                 uint64_t Address, const void *Decoder) {
873  DecodeStatus S = Success;
874
875  unsigned Vd = fieldFromInstruction32(Val, 8, 4);
876  unsigned regs = (Val & 0xFF) / 2;
877
878  CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));
879  for (unsigned i = 0; i < (regs - 1); ++i) {
880    CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));
881  }
882
883  return S;
884}
885
886static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
887                                      uint64_t Address, const void *Decoder) {
888  // This operand encodes a mask of contiguous zeros between a specified MSB
889  // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
890  // the mask of all bits LSB-and-lower, and then xor them to create
891  // the mask of that's all ones on [msb, lsb].  Finally we not it to
892  // create the final mask.
893  unsigned msb = fieldFromInstruction32(Val, 5, 5);
894  unsigned lsb = fieldFromInstruction32(Val, 0, 5);
895  uint32_t msb_mask = (1 << (msb+1)) - 1;
896  uint32_t lsb_mask = (1 << lsb) - 1;
897  Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
898  return Success;
899}
900
901static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
902                                  uint64_t Address, const void *Decoder) {
903  DecodeStatus S = Success;
904
905  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
906  unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
907  unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
908  unsigned imm = fieldFromInstruction32(Insn, 0, 8);
909  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
910  unsigned U = fieldFromInstruction32(Insn, 23, 1);
911
912  switch (Inst.getOpcode()) {
913    case ARM::LDC_OFFSET:
914    case ARM::LDC_PRE:
915    case ARM::LDC_POST:
916    case ARM::LDC_OPTION:
917    case ARM::LDCL_OFFSET:
918    case ARM::LDCL_PRE:
919    case ARM::LDCL_POST:
920    case ARM::LDCL_OPTION:
921    case ARM::STC_OFFSET:
922    case ARM::STC_PRE:
923    case ARM::STC_POST:
924    case ARM::STC_OPTION:
925    case ARM::STCL_OFFSET:
926    case ARM::STCL_PRE:
927    case ARM::STCL_POST:
928    case ARM::STCL_OPTION:
929      if (coproc == 0xA || coproc == 0xB)
930        return Fail;
931      break;
932    default:
933      break;
934  }
935
936  Inst.addOperand(MCOperand::CreateImm(coproc));
937  Inst.addOperand(MCOperand::CreateImm(CRd));
938  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
939  switch (Inst.getOpcode()) {
940    case ARM::LDC_OPTION:
941    case ARM::LDCL_OPTION:
942    case ARM::LDC2_OPTION:
943    case ARM::LDC2L_OPTION:
944    case ARM::STC_OPTION:
945    case ARM::STCL_OPTION:
946    case ARM::STC2_OPTION:
947    case ARM::STC2L_OPTION:
948    case ARM::LDCL_POST:
949    case ARM::STCL_POST:
950    case ARM::LDC2L_POST:
951    case ARM::STC2L_POST:
952      break;
953    default:
954      Inst.addOperand(MCOperand::CreateReg(0));
955      break;
956  }
957
958  unsigned P = fieldFromInstruction32(Insn, 24, 1);
959  unsigned W = fieldFromInstruction32(Insn, 21, 1);
960
961  bool writeback = (P == 0) || (W == 1);
962  unsigned idx_mode = 0;
963  if (P && writeback)
964    idx_mode = ARMII::IndexModePre;
965  else if (!P && writeback)
966    idx_mode = ARMII::IndexModePost;
967
968  switch (Inst.getOpcode()) {
969    case ARM::LDCL_POST:
970    case ARM::STCL_POST:
971    case ARM::LDC2L_POST:
972    case ARM::STC2L_POST:
973      imm |= U << 8;
974    case ARM::LDC_OPTION:
975    case ARM::LDCL_OPTION:
976    case ARM::LDC2_OPTION:
977    case ARM::LDC2L_OPTION:
978    case ARM::STC_OPTION:
979    case ARM::STCL_OPTION:
980    case ARM::STC2_OPTION:
981    case ARM::STC2L_OPTION:
982      Inst.addOperand(MCOperand::CreateImm(imm));
983      break;
984    default:
985      if (U)
986        Inst.addOperand(MCOperand::CreateImm(
987            ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
988      else
989        Inst.addOperand(MCOperand::CreateImm(
990            ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
991      break;
992  }
993
994  switch (Inst.getOpcode()) {
995    case ARM::LDC_OFFSET:
996    case ARM::LDC_PRE:
997    case ARM::LDC_POST:
998    case ARM::LDC_OPTION:
999    case ARM::LDCL_OFFSET:
1000    case ARM::LDCL_PRE:
1001    case ARM::LDCL_POST:
1002    case ARM::LDCL_OPTION:
1003    case ARM::STC_OFFSET:
1004    case ARM::STC_PRE:
1005    case ARM::STC_POST:
1006    case ARM::STC_OPTION:
1007    case ARM::STCL_OFFSET:
1008    case ARM::STCL_PRE:
1009    case ARM::STCL_POST:
1010    case ARM::STCL_OPTION:
1011      CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1012      break;
1013    default:
1014      break;
1015  }
1016
1017  return S;
1018}
1019
1020static DecodeStatus
1021DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1022                              uint64_t Address, const void *Decoder) {
1023  DecodeStatus S = Success;
1024
1025  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1026  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1027  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1028  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1029  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1030  unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1031  unsigned P = fieldFromInstruction32(Insn, 24, 1);
1032  unsigned W = fieldFromInstruction32(Insn, 21, 1);
1033
1034  // On stores, the writeback operand precedes Rt.
1035  switch (Inst.getOpcode()) {
1036    case ARM::STR_POST_IMM:
1037    case ARM::STR_POST_REG:
1038    case ARM::STRB_POST_IMM:
1039    case ARM::STRB_POST_REG:
1040    case ARM::STRT_POST_REG:
1041    case ARM::STRT_POST_IMM:
1042    case ARM::STRBT_POST_REG:
1043    case ARM::STRBT_POST_IMM:
1044      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1045      break;
1046    default:
1047      break;
1048  }
1049
1050  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1051
1052  // On loads, the writeback operand comes after Rt.
1053  switch (Inst.getOpcode()) {
1054    case ARM::LDR_POST_IMM:
1055    case ARM::LDR_POST_REG:
1056    case ARM::LDRB_POST_IMM:
1057    case ARM::LDRB_POST_REG:
1058    case ARM::LDR_PRE:
1059    case ARM::LDRB_PRE:
1060    case ARM::LDRBT_POST_REG:
1061    case ARM::LDRBT_POST_IMM:
1062    case ARM::LDRT_POST_REG:
1063    case ARM::LDRT_POST_IMM:
1064      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1065      break;
1066    default:
1067      break;
1068  }
1069
1070  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1071
1072  ARM_AM::AddrOpc Op = ARM_AM::add;
1073  if (!fieldFromInstruction32(Insn, 23, 1))
1074    Op = ARM_AM::sub;
1075
1076  bool writeback = (P == 0) || (W == 1);
1077  unsigned idx_mode = 0;
1078  if (P && writeback)
1079    idx_mode = ARMII::IndexModePre;
1080  else if (!P && writeback)
1081    idx_mode = ARMII::IndexModePost;
1082
1083  if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE
1084
1085  if (reg) {
1086    CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1087    ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1088    switch( fieldFromInstruction32(Insn, 5, 2)) {
1089      case 0:
1090        Opc = ARM_AM::lsl;
1091        break;
1092      case 1:
1093        Opc = ARM_AM::lsr;
1094        break;
1095      case 2:
1096        Opc = ARM_AM::asr;
1097        break;
1098      case 3:
1099        Opc = ARM_AM::ror;
1100        break;
1101      default:
1102        return Fail;
1103    }
1104    unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1105    unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1106
1107    Inst.addOperand(MCOperand::CreateImm(imm));
1108  } else {
1109    Inst.addOperand(MCOperand::CreateReg(0));
1110    unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1111    Inst.addOperand(MCOperand::CreateImm(tmp));
1112  }
1113
1114  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1115
1116  return S;
1117}
1118
1119static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1120                                  uint64_t Address, const void *Decoder) {
1121  DecodeStatus S = Success;
1122
1123  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1124  unsigned Rm = fieldFromInstruction32(Val,  0, 4);
1125  unsigned type = fieldFromInstruction32(Val, 5, 2);
1126  unsigned imm = fieldFromInstruction32(Val, 7, 5);
1127  unsigned U = fieldFromInstruction32(Val, 12, 1);
1128
1129  ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1130  switch (type) {
1131    case 0:
1132      ShOp = ARM_AM::lsl;
1133      break;
1134    case 1:
1135      ShOp = ARM_AM::lsr;
1136      break;
1137    case 2:
1138      ShOp = ARM_AM::asr;
1139      break;
1140    case 3:
1141      ShOp = ARM_AM::ror;
1142      break;
1143  }
1144
1145  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1146  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1147  unsigned shift;
1148  if (U)
1149    shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1150  else
1151    shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1152  Inst.addOperand(MCOperand::CreateImm(shift));
1153
1154  return S;
1155}
1156
1157static DecodeStatus
1158DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1159                           uint64_t Address, const void *Decoder) {
1160  DecodeStatus S = Success;
1161
1162  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1163  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1164  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1165  unsigned type = fieldFromInstruction32(Insn, 22, 1);
1166  unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1167  unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1168  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1169  unsigned W = fieldFromInstruction32(Insn, 21, 1);
1170  unsigned P = fieldFromInstruction32(Insn, 24, 1);
1171
1172  bool writeback = (W == 1) | (P == 0);
1173
1174  // For {LD,ST}RD, Rt must be even, else undefined.
1175  switch (Inst.getOpcode()) {
1176    case ARM::STRD:
1177    case ARM::STRD_PRE:
1178    case ARM::STRD_POST:
1179    case ARM::LDRD:
1180    case ARM::LDRD_PRE:
1181    case ARM::LDRD_POST:
1182      if (Rt & 0x1) return Fail;
1183      break;
1184  default:
1185    break;
1186  }
1187
1188  if (writeback) { // Writeback
1189    if (P)
1190      U |= ARMII::IndexModePre << 9;
1191    else
1192      U |= ARMII::IndexModePost << 9;
1193
1194    // On stores, the writeback operand precedes Rt.
1195    switch (Inst.getOpcode()) {
1196    case ARM::STRD:
1197    case ARM::STRD_PRE:
1198    case ARM::STRD_POST:
1199    case ARM::STRH:
1200    case ARM::STRH_PRE:
1201    case ARM::STRH_POST:
1202      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1203      break;
1204    default:
1205      break;
1206    }
1207  }
1208
1209  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1210  switch (Inst.getOpcode()) {
1211    case ARM::STRD:
1212    case ARM::STRD_PRE:
1213    case ARM::STRD_POST:
1214    case ARM::LDRD:
1215    case ARM::LDRD_PRE:
1216    case ARM::LDRD_POST:
1217      CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
1218      break;
1219    default:
1220      break;
1221  }
1222
1223  if (writeback) {
1224    // On loads, the writeback operand comes after Rt.
1225    switch (Inst.getOpcode()) {
1226    case ARM::LDRD:
1227    case ARM::LDRD_PRE:
1228    case ARM::LDRD_POST:
1229    case ARM::LDRH:
1230    case ARM::LDRH_PRE:
1231    case ARM::LDRH_POST:
1232    case ARM::LDRSH:
1233    case ARM::LDRSH_PRE:
1234    case ARM::LDRSH_POST:
1235    case ARM::LDRSB:
1236    case ARM::LDRSB_PRE:
1237    case ARM::LDRSB_POST:
1238    case ARM::LDRHTr:
1239    case ARM::LDRSBTr:
1240      CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1241      break;
1242    default:
1243      break;
1244    }
1245  }
1246
1247  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1248
1249  if (type) {
1250    Inst.addOperand(MCOperand::CreateReg(0));
1251    Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1252  } else {
1253    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1254    Inst.addOperand(MCOperand::CreateImm(U));
1255  }
1256
1257  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1258
1259  return S;
1260}
1261
1262static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1263                                 uint64_t Address, const void *Decoder) {
1264  DecodeStatus S = Success;
1265
1266  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1267  unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1268
1269  switch (mode) {
1270    case 0:
1271      mode = ARM_AM::da;
1272      break;
1273    case 1:
1274      mode = ARM_AM::ia;
1275      break;
1276    case 2:
1277      mode = ARM_AM::db;
1278      break;
1279    case 3:
1280      mode = ARM_AM::ib;
1281      break;
1282  }
1283
1284  Inst.addOperand(MCOperand::CreateImm(mode));
1285  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1286
1287  return S;
1288}
1289
1290static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1291                                  unsigned Insn,
1292                                  uint64_t Address, const void *Decoder) {
1293  DecodeStatus S = Success;
1294
1295  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1296  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1297  unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1298
1299  if (pred == 0xF) {
1300    switch (Inst.getOpcode()) {
1301      case ARM::LDMDA:
1302        Inst.setOpcode(ARM::RFEDA);
1303        break;
1304      case ARM::LDMDA_UPD:
1305        Inst.setOpcode(ARM::RFEDA_UPD);
1306        break;
1307      case ARM::LDMDB:
1308        Inst.setOpcode(ARM::RFEDB);
1309        break;
1310      case ARM::LDMDB_UPD:
1311        Inst.setOpcode(ARM::RFEDB_UPD);
1312        break;
1313      case ARM::LDMIA:
1314        Inst.setOpcode(ARM::RFEIA);
1315        break;
1316      case ARM::LDMIA_UPD:
1317        Inst.setOpcode(ARM::RFEIA_UPD);
1318        break;
1319      case ARM::LDMIB:
1320        Inst.setOpcode(ARM::RFEIB);
1321        break;
1322      case ARM::LDMIB_UPD:
1323        Inst.setOpcode(ARM::RFEIB_UPD);
1324        break;
1325      case ARM::STMDA:
1326        Inst.setOpcode(ARM::SRSDA);
1327        break;
1328      case ARM::STMDA_UPD:
1329        Inst.setOpcode(ARM::SRSDA_UPD);
1330        break;
1331      case ARM::STMDB:
1332        Inst.setOpcode(ARM::SRSDB);
1333        break;
1334      case ARM::STMDB_UPD:
1335        Inst.setOpcode(ARM::SRSDB_UPD);
1336        break;
1337      case ARM::STMIA:
1338        Inst.setOpcode(ARM::SRSIA);
1339        break;
1340      case ARM::STMIA_UPD:
1341        Inst.setOpcode(ARM::SRSIA_UPD);
1342        break;
1343      case ARM::STMIB:
1344        Inst.setOpcode(ARM::SRSIB);
1345        break;
1346      case ARM::STMIB_UPD:
1347        Inst.setOpcode(ARM::SRSIB_UPD);
1348        break;
1349      default:
1350        CHECK(S, Fail);
1351    }
1352
1353    // For stores (which become SRS's, the only operand is the mode.
1354    if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1355      Inst.addOperand(
1356          MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1357      return S;
1358    }
1359
1360    return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1361  }
1362
1363  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1364  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied
1365  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1366  CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));
1367
1368  return S;
1369}
1370
1371static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1372                                 uint64_t Address, const void *Decoder) {
1373  unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1374  unsigned M = fieldFromInstruction32(Insn, 17, 1);
1375  unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1376  unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1377
1378  DecodeStatus S = Success;
1379
1380  // imod == '01' --> UNPREDICTABLE
1381  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1382  // return failure here.  The '01' imod value is unprintable, so there's
1383  // nothing useful we could do even if we returned UNPREDICTABLE.
1384
1385  if (imod == 1) CHECK(S, Fail);
1386
1387  if (imod && M) {
1388    Inst.setOpcode(ARM::CPS3p);
1389    Inst.addOperand(MCOperand::CreateImm(imod));
1390    Inst.addOperand(MCOperand::CreateImm(iflags));
1391    Inst.addOperand(MCOperand::CreateImm(mode));
1392  } else if (imod && !M) {
1393    Inst.setOpcode(ARM::CPS2p);
1394    Inst.addOperand(MCOperand::CreateImm(imod));
1395    Inst.addOperand(MCOperand::CreateImm(iflags));
1396    if (mode) CHECK(S, Unpredictable);
1397  } else if (!imod && M) {
1398    Inst.setOpcode(ARM::CPS1p);
1399    Inst.addOperand(MCOperand::CreateImm(mode));
1400    if (iflags) CHECK(S, Unpredictable);
1401  } else {
1402    // imod == '00' && M == '0' --> UNPREDICTABLE
1403    Inst.setOpcode(ARM::CPS1p);
1404    Inst.addOperand(MCOperand::CreateImm(mode));
1405    CHECK(S, Unpredictable);
1406  }
1407
1408  return S;
1409}
1410
1411static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1412                                 uint64_t Address, const void *Decoder) {
1413  unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1414  unsigned M = fieldFromInstruction32(Insn, 8, 1);
1415  unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1416  unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1417
1418  DecodeStatus S = Success;
1419
1420  // imod == '01' --> UNPREDICTABLE
1421  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1422  // return failure here.  The '01' imod value is unprintable, so there's
1423  // nothing useful we could do even if we returned UNPREDICTABLE.
1424
1425  if (imod == 1) CHECK(S, Fail);
1426
1427  if (imod && M) {
1428    Inst.setOpcode(ARM::t2CPS3p);
1429    Inst.addOperand(MCOperand::CreateImm(imod));
1430    Inst.addOperand(MCOperand::CreateImm(iflags));
1431    Inst.addOperand(MCOperand::CreateImm(mode));
1432  } else if (imod && !M) {
1433    Inst.setOpcode(ARM::t2CPS2p);
1434    Inst.addOperand(MCOperand::CreateImm(imod));
1435    Inst.addOperand(MCOperand::CreateImm(iflags));
1436    if (mode) CHECK(S, Unpredictable);
1437  } else if (!imod && M) {
1438    Inst.setOpcode(ARM::t2CPS1p);
1439    Inst.addOperand(MCOperand::CreateImm(mode));
1440    if (iflags) CHECK(S, Unpredictable);
1441  } else {
1442    // imod == '00' && M == '0' --> UNPREDICTABLE
1443    Inst.setOpcode(ARM::t2CPS1p);
1444    Inst.addOperand(MCOperand::CreateImm(mode));
1445    CHECK(S, Unpredictable);
1446  }
1447
1448  return S;
1449}
1450
1451
1452static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1453                                 uint64_t Address, const void *Decoder) {
1454  DecodeStatus S = Success;
1455
1456  unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1457  unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1458  unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1459  unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1460  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1461
1462  if (pred == 0xF)
1463    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1464
1465  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));
1466  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));
1467  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1468  CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));
1469
1470  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1471
1472  return S;
1473}
1474
1475static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1476                           uint64_t Address, const void *Decoder) {
1477  DecodeStatus S = Success;
1478
1479  unsigned add = fieldFromInstruction32(Val, 12, 1);
1480  unsigned imm = fieldFromInstruction32(Val, 0, 12);
1481  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1482
1483  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1484
1485  if (!add) imm *= -1;
1486  if (imm == 0 && !add) imm = INT32_MIN;
1487  Inst.addOperand(MCOperand::CreateImm(imm));
1488
1489  return S;
1490}
1491
1492static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1493                                   uint64_t Address, const void *Decoder) {
1494  DecodeStatus S = Success;
1495
1496  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1497  unsigned U = fieldFromInstruction32(Val, 8, 1);
1498  unsigned imm = fieldFromInstruction32(Val, 0, 8);
1499
1500  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1501
1502  if (U)
1503    Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1504  else
1505    Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1506
1507  return S;
1508}
1509
1510static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1511                                   uint64_t Address, const void *Decoder) {
1512  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1513}
1514
1515static DecodeStatus
1516DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1517                           uint64_t Address, const void *Decoder) {
1518  DecodeStatus S = Success;
1519
1520  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1521  unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1522
1523  if (pred == 0xF) {
1524    Inst.setOpcode(ARM::BLXi);
1525    imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1526    Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1527    return S;
1528  }
1529
1530  Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1531  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1532
1533  return S;
1534}
1535
1536
1537static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1538                                 uint64_t Address, const void *Decoder) {
1539  Inst.addOperand(MCOperand::CreateImm(64 - Val));
1540  return Success;
1541}
1542
1543static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1544                                   uint64_t Address, const void *Decoder) {
1545  DecodeStatus S = Success;
1546
1547  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1548  unsigned align = fieldFromInstruction32(Val, 4, 2);
1549
1550  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1551  if (!align)
1552    Inst.addOperand(MCOperand::CreateImm(0));
1553  else
1554    Inst.addOperand(MCOperand::CreateImm(4 << align));
1555
1556  return S;
1557}
1558
1559static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1560                                   uint64_t Address, const void *Decoder) {
1561  DecodeStatus S = Success;
1562
1563  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1564  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1565  unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1566  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1567  Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1568  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1569
1570  // First output register
1571  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1572
1573  // Second output register
1574  switch (Inst.getOpcode()) {
1575    case ARM::VLD1q8:
1576    case ARM::VLD1q16:
1577    case ARM::VLD1q32:
1578    case ARM::VLD1q64:
1579    case ARM::VLD1q8_UPD:
1580    case ARM::VLD1q16_UPD:
1581    case ARM::VLD1q32_UPD:
1582    case ARM::VLD1q64_UPD:
1583    case ARM::VLD1d8T:
1584    case ARM::VLD1d16T:
1585    case ARM::VLD1d32T:
1586    case ARM::VLD1d64T:
1587    case ARM::VLD1d8T_UPD:
1588    case ARM::VLD1d16T_UPD:
1589    case ARM::VLD1d32T_UPD:
1590    case ARM::VLD1d64T_UPD:
1591    case ARM::VLD1d8Q:
1592    case ARM::VLD1d16Q:
1593    case ARM::VLD1d32Q:
1594    case ARM::VLD1d64Q:
1595    case ARM::VLD1d8Q_UPD:
1596    case ARM::VLD1d16Q_UPD:
1597    case ARM::VLD1d32Q_UPD:
1598    case ARM::VLD1d64Q_UPD:
1599    case ARM::VLD2d8:
1600    case ARM::VLD2d16:
1601    case ARM::VLD2d32:
1602    case ARM::VLD2d8_UPD:
1603    case ARM::VLD2d16_UPD:
1604    case ARM::VLD2d32_UPD:
1605    case ARM::VLD2q8:
1606    case ARM::VLD2q16:
1607    case ARM::VLD2q32:
1608    case ARM::VLD2q8_UPD:
1609    case ARM::VLD2q16_UPD:
1610    case ARM::VLD2q32_UPD:
1611    case ARM::VLD3d8:
1612    case ARM::VLD3d16:
1613    case ARM::VLD3d32:
1614    case ARM::VLD3d8_UPD:
1615    case ARM::VLD3d16_UPD:
1616    case ARM::VLD3d32_UPD:
1617    case ARM::VLD4d8:
1618    case ARM::VLD4d16:
1619    case ARM::VLD4d32:
1620    case ARM::VLD4d8_UPD:
1621    case ARM::VLD4d16_UPD:
1622    case ARM::VLD4d32_UPD:
1623      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1624      break;
1625    case ARM::VLD2b8:
1626    case ARM::VLD2b16:
1627    case ARM::VLD2b32:
1628    case ARM::VLD2b8_UPD:
1629    case ARM::VLD2b16_UPD:
1630    case ARM::VLD2b32_UPD:
1631    case ARM::VLD3q8:
1632    case ARM::VLD3q16:
1633    case ARM::VLD3q32:
1634    case ARM::VLD3q8_UPD:
1635    case ARM::VLD3q16_UPD:
1636    case ARM::VLD3q32_UPD:
1637    case ARM::VLD4q8:
1638    case ARM::VLD4q16:
1639    case ARM::VLD4q32:
1640    case ARM::VLD4q8_UPD:
1641    case ARM::VLD4q16_UPD:
1642    case ARM::VLD4q32_UPD:
1643      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1644    default:
1645      break;
1646  }
1647
1648  // Third output register
1649  switch(Inst.getOpcode()) {
1650    case ARM::VLD1d8T:
1651    case ARM::VLD1d16T:
1652    case ARM::VLD1d32T:
1653    case ARM::VLD1d64T:
1654    case ARM::VLD1d8T_UPD:
1655    case ARM::VLD1d16T_UPD:
1656    case ARM::VLD1d32T_UPD:
1657    case ARM::VLD1d64T_UPD:
1658    case ARM::VLD1d8Q:
1659    case ARM::VLD1d16Q:
1660    case ARM::VLD1d32Q:
1661    case ARM::VLD1d64Q:
1662    case ARM::VLD1d8Q_UPD:
1663    case ARM::VLD1d16Q_UPD:
1664    case ARM::VLD1d32Q_UPD:
1665    case ARM::VLD1d64Q_UPD:
1666    case ARM::VLD2q8:
1667    case ARM::VLD2q16:
1668    case ARM::VLD2q32:
1669    case ARM::VLD2q8_UPD:
1670    case ARM::VLD2q16_UPD:
1671    case ARM::VLD2q32_UPD:
1672    case ARM::VLD3d8:
1673    case ARM::VLD3d16:
1674    case ARM::VLD3d32:
1675    case ARM::VLD3d8_UPD:
1676    case ARM::VLD3d16_UPD:
1677    case ARM::VLD3d32_UPD:
1678    case ARM::VLD4d8:
1679    case ARM::VLD4d16:
1680    case ARM::VLD4d32:
1681    case ARM::VLD4d8_UPD:
1682    case ARM::VLD4d16_UPD:
1683    case ARM::VLD4d32_UPD:
1684      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1685      break;
1686    case ARM::VLD3q8:
1687    case ARM::VLD3q16:
1688    case ARM::VLD3q32:
1689    case ARM::VLD3q8_UPD:
1690    case ARM::VLD3q16_UPD:
1691    case ARM::VLD3q32_UPD:
1692    case ARM::VLD4q8:
1693    case ARM::VLD4q16:
1694    case ARM::VLD4q32:
1695    case ARM::VLD4q8_UPD:
1696    case ARM::VLD4q16_UPD:
1697    case ARM::VLD4q32_UPD:
1698      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1699      break;
1700    default:
1701      break;
1702  }
1703
1704  // Fourth output register
1705  switch (Inst.getOpcode()) {
1706    case ARM::VLD1d8Q:
1707    case ARM::VLD1d16Q:
1708    case ARM::VLD1d32Q:
1709    case ARM::VLD1d64Q:
1710    case ARM::VLD1d8Q_UPD:
1711    case ARM::VLD1d16Q_UPD:
1712    case ARM::VLD1d32Q_UPD:
1713    case ARM::VLD1d64Q_UPD:
1714    case ARM::VLD2q8:
1715    case ARM::VLD2q16:
1716    case ARM::VLD2q32:
1717    case ARM::VLD2q8_UPD:
1718    case ARM::VLD2q16_UPD:
1719    case ARM::VLD2q32_UPD:
1720    case ARM::VLD4d8:
1721    case ARM::VLD4d16:
1722    case ARM::VLD4d32:
1723    case ARM::VLD4d8_UPD:
1724    case ARM::VLD4d16_UPD:
1725    case ARM::VLD4d32_UPD:
1726      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
1727      break;
1728    case ARM::VLD4q8:
1729    case ARM::VLD4q16:
1730    case ARM::VLD4q32:
1731    case ARM::VLD4q8_UPD:
1732    case ARM::VLD4q16_UPD:
1733    case ARM::VLD4q32_UPD:
1734      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
1735      break;
1736    default:
1737      break;
1738  }
1739
1740  // Writeback operand
1741  switch (Inst.getOpcode()) {
1742    case ARM::VLD1d8_UPD:
1743    case ARM::VLD1d16_UPD:
1744    case ARM::VLD1d32_UPD:
1745    case ARM::VLD1d64_UPD:
1746    case ARM::VLD1q8_UPD:
1747    case ARM::VLD1q16_UPD:
1748    case ARM::VLD1q32_UPD:
1749    case ARM::VLD1q64_UPD:
1750    case ARM::VLD1d8T_UPD:
1751    case ARM::VLD1d16T_UPD:
1752    case ARM::VLD1d32T_UPD:
1753    case ARM::VLD1d64T_UPD:
1754    case ARM::VLD1d8Q_UPD:
1755    case ARM::VLD1d16Q_UPD:
1756    case ARM::VLD1d32Q_UPD:
1757    case ARM::VLD1d64Q_UPD:
1758    case ARM::VLD2d8_UPD:
1759    case ARM::VLD2d16_UPD:
1760    case ARM::VLD2d32_UPD:
1761    case ARM::VLD2q8_UPD:
1762    case ARM::VLD2q16_UPD:
1763    case ARM::VLD2q32_UPD:
1764    case ARM::VLD2b8_UPD:
1765    case ARM::VLD2b16_UPD:
1766    case ARM::VLD2b32_UPD:
1767    case ARM::VLD3d8_UPD:
1768    case ARM::VLD3d16_UPD:
1769    case ARM::VLD3d32_UPD:
1770    case ARM::VLD3q8_UPD:
1771    case ARM::VLD3q16_UPD:
1772    case ARM::VLD3q32_UPD:
1773    case ARM::VLD4d8_UPD:
1774    case ARM::VLD4d16_UPD:
1775    case ARM::VLD4d32_UPD:
1776    case ARM::VLD4q8_UPD:
1777    case ARM::VLD4q16_UPD:
1778    case ARM::VLD4q32_UPD:
1779      CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1780      break;
1781    default:
1782      break;
1783  }
1784
1785  // AddrMode6 Base (register+alignment)
1786  CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1787
1788  // AddrMode6 Offset (register)
1789  if (Rm == 0xD)
1790    Inst.addOperand(MCOperand::CreateReg(0));
1791  else if (Rm != 0xF) {
1792    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1793  }
1794
1795  return S;
1796}
1797
1798static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
1799                                 uint64_t Address, const void *Decoder) {
1800  DecodeStatus S = Success;
1801
1802  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1803  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1804  unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1805  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1806  Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1807  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1808
1809  // Writeback Operand
1810  switch (Inst.getOpcode()) {
1811    case ARM::VST1d8_UPD:
1812    case ARM::VST1d16_UPD:
1813    case ARM::VST1d32_UPD:
1814    case ARM::VST1d64_UPD:
1815    case ARM::VST1q8_UPD:
1816    case ARM::VST1q16_UPD:
1817    case ARM::VST1q32_UPD:
1818    case ARM::VST1q64_UPD:
1819    case ARM::VST1d8T_UPD:
1820    case ARM::VST1d16T_UPD:
1821    case ARM::VST1d32T_UPD:
1822    case ARM::VST1d64T_UPD:
1823    case ARM::VST1d8Q_UPD:
1824    case ARM::VST1d16Q_UPD:
1825    case ARM::VST1d32Q_UPD:
1826    case ARM::VST1d64Q_UPD:
1827    case ARM::VST2d8_UPD:
1828    case ARM::VST2d16_UPD:
1829    case ARM::VST2d32_UPD:
1830    case ARM::VST2q8_UPD:
1831    case ARM::VST2q16_UPD:
1832    case ARM::VST2q32_UPD:
1833    case ARM::VST2b8_UPD:
1834    case ARM::VST2b16_UPD:
1835    case ARM::VST2b32_UPD:
1836    case ARM::VST3d8_UPD:
1837    case ARM::VST3d16_UPD:
1838    case ARM::VST3d32_UPD:
1839    case ARM::VST3q8_UPD:
1840    case ARM::VST3q16_UPD:
1841    case ARM::VST3q32_UPD:
1842    case ARM::VST4d8_UPD:
1843    case ARM::VST4d16_UPD:
1844    case ARM::VST4d32_UPD:
1845    case ARM::VST4q8_UPD:
1846    case ARM::VST4q16_UPD:
1847    case ARM::VST4q32_UPD:
1848      CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1849      break;
1850    default:
1851      break;
1852  }
1853
1854  // AddrMode6 Base (register+alignment)
1855  CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1856
1857  // AddrMode6 Offset (register)
1858  if (Rm == 0xD)
1859    Inst.addOperand(MCOperand::CreateReg(0));
1860  else if (Rm != 0xF) {
1861    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1862  }
1863
1864  // First input register
1865  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1866
1867  // Second input register
1868  switch (Inst.getOpcode()) {
1869    case ARM::VST1q8:
1870    case ARM::VST1q16:
1871    case ARM::VST1q32:
1872    case ARM::VST1q64:
1873    case ARM::VST1q8_UPD:
1874    case ARM::VST1q16_UPD:
1875    case ARM::VST1q32_UPD:
1876    case ARM::VST1q64_UPD:
1877    case ARM::VST1d8T:
1878    case ARM::VST1d16T:
1879    case ARM::VST1d32T:
1880    case ARM::VST1d64T:
1881    case ARM::VST1d8T_UPD:
1882    case ARM::VST1d16T_UPD:
1883    case ARM::VST1d32T_UPD:
1884    case ARM::VST1d64T_UPD:
1885    case ARM::VST1d8Q:
1886    case ARM::VST1d16Q:
1887    case ARM::VST1d32Q:
1888    case ARM::VST1d64Q:
1889    case ARM::VST1d8Q_UPD:
1890    case ARM::VST1d16Q_UPD:
1891    case ARM::VST1d32Q_UPD:
1892    case ARM::VST1d64Q_UPD:
1893    case ARM::VST2d8:
1894    case ARM::VST2d16:
1895    case ARM::VST2d32:
1896    case ARM::VST2d8_UPD:
1897    case ARM::VST2d16_UPD:
1898    case ARM::VST2d32_UPD:
1899    case ARM::VST2q8:
1900    case ARM::VST2q16:
1901    case ARM::VST2q32:
1902    case ARM::VST2q8_UPD:
1903    case ARM::VST2q16_UPD:
1904    case ARM::VST2q32_UPD:
1905    case ARM::VST3d8:
1906    case ARM::VST3d16:
1907    case ARM::VST3d32:
1908    case ARM::VST3d8_UPD:
1909    case ARM::VST3d16_UPD:
1910    case ARM::VST3d32_UPD:
1911    case ARM::VST4d8:
1912    case ARM::VST4d16:
1913    case ARM::VST4d32:
1914    case ARM::VST4d8_UPD:
1915    case ARM::VST4d16_UPD:
1916    case ARM::VST4d32_UPD:
1917      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1918      break;
1919    case ARM::VST2b8:
1920    case ARM::VST2b16:
1921    case ARM::VST2b32:
1922    case ARM::VST2b8_UPD:
1923    case ARM::VST2b16_UPD:
1924    case ARM::VST2b32_UPD:
1925    case ARM::VST3q8:
1926    case ARM::VST3q16:
1927    case ARM::VST3q32:
1928    case ARM::VST3q8_UPD:
1929    case ARM::VST3q16_UPD:
1930    case ARM::VST3q32_UPD:
1931    case ARM::VST4q8:
1932    case ARM::VST4q16:
1933    case ARM::VST4q32:
1934    case ARM::VST4q8_UPD:
1935    case ARM::VST4q16_UPD:
1936    case ARM::VST4q32_UPD:
1937      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1938      break;
1939    default:
1940      break;
1941  }
1942
1943  // Third input register
1944  switch (Inst.getOpcode()) {
1945    case ARM::VST1d8T:
1946    case ARM::VST1d16T:
1947    case ARM::VST1d32T:
1948    case ARM::VST1d64T:
1949    case ARM::VST1d8T_UPD:
1950    case ARM::VST1d16T_UPD:
1951    case ARM::VST1d32T_UPD:
1952    case ARM::VST1d64T_UPD:
1953    case ARM::VST1d8Q:
1954    case ARM::VST1d16Q:
1955    case ARM::VST1d32Q:
1956    case ARM::VST1d64Q:
1957    case ARM::VST1d8Q_UPD:
1958    case ARM::VST1d16Q_UPD:
1959    case ARM::VST1d32Q_UPD:
1960    case ARM::VST1d64Q_UPD:
1961    case ARM::VST2q8:
1962    case ARM::VST2q16:
1963    case ARM::VST2q32:
1964    case ARM::VST2q8_UPD:
1965    case ARM::VST2q16_UPD:
1966    case ARM::VST2q32_UPD:
1967    case ARM::VST3d8:
1968    case ARM::VST3d16:
1969    case ARM::VST3d32:
1970    case ARM::VST3d8_UPD:
1971    case ARM::VST3d16_UPD:
1972    case ARM::VST3d32_UPD:
1973    case ARM::VST4d8:
1974    case ARM::VST4d16:
1975    case ARM::VST4d32:
1976    case ARM::VST4d8_UPD:
1977    case ARM::VST4d16_UPD:
1978    case ARM::VST4d32_UPD:
1979      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1980      break;
1981    case ARM::VST3q8:
1982    case ARM::VST3q16:
1983    case ARM::VST3q32:
1984    case ARM::VST3q8_UPD:
1985    case ARM::VST3q16_UPD:
1986    case ARM::VST3q32_UPD:
1987    case ARM::VST4q8:
1988    case ARM::VST4q16:
1989    case ARM::VST4q32:
1990    case ARM::VST4q8_UPD:
1991    case ARM::VST4q16_UPD:
1992    case ARM::VST4q32_UPD:
1993      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1994      break;
1995    default:
1996      break;
1997  }
1998
1999  // Fourth input register
2000  switch (Inst.getOpcode()) {
2001    case ARM::VST1d8Q:
2002    case ARM::VST1d16Q:
2003    case ARM::VST1d32Q:
2004    case ARM::VST1d64Q:
2005    case ARM::VST1d8Q_UPD:
2006    case ARM::VST1d16Q_UPD:
2007    case ARM::VST1d32Q_UPD:
2008    case ARM::VST1d64Q_UPD:
2009    case ARM::VST2q8:
2010    case ARM::VST2q16:
2011    case ARM::VST2q32:
2012    case ARM::VST2q8_UPD:
2013    case ARM::VST2q16_UPD:
2014    case ARM::VST2q32_UPD:
2015    case ARM::VST4d8:
2016    case ARM::VST4d16:
2017    case ARM::VST4d32:
2018    case ARM::VST4d8_UPD:
2019    case ARM::VST4d16_UPD:
2020    case ARM::VST4d32_UPD:
2021      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
2022      break;
2023    case ARM::VST4q8:
2024    case ARM::VST4q16:
2025    case ARM::VST4q32:
2026    case ARM::VST4q8_UPD:
2027    case ARM::VST4q16_UPD:
2028    case ARM::VST4q32_UPD:
2029      CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
2030      break;
2031    default:
2032      break;
2033  }
2034
2035  return S;
2036}
2037
2038static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2039                                    uint64_t Address, const void *Decoder) {
2040  DecodeStatus S = Success;
2041
2042  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2043  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2044  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2045  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2046  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2047  unsigned size = fieldFromInstruction32(Insn, 6, 2);
2048  unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2049
2050  align *= (1 << size);
2051
2052  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2053  if (regs == 2) {
2054    CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
2055  }
2056  if (Rm != 0xF) {
2057    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2058  }
2059
2060  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2061  Inst.addOperand(MCOperand::CreateImm(align));
2062
2063  if (Rm == 0xD)
2064    Inst.addOperand(MCOperand::CreateReg(0));
2065  else if (Rm != 0xF) {
2066    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2067  }
2068
2069  return S;
2070}
2071
2072static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2073                                    uint64_t Address, const void *Decoder) {
2074  DecodeStatus S = Success;
2075
2076  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2077  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2078  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2079  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2080  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2081  unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2082  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2083  align *= 2*size;
2084
2085  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2086  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2087  if (Rm != 0xF) {
2088    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2089  }
2090
2091  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2092  Inst.addOperand(MCOperand::CreateImm(align));
2093
2094  if (Rm == 0xD)
2095    Inst.addOperand(MCOperand::CreateReg(0));
2096  else if (Rm != 0xF) {
2097    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2098  }
2099
2100  return S;
2101}
2102
2103static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2104                                    uint64_t Address, const void *Decoder) {
2105  DecodeStatus S = Success;
2106
2107  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2108  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2109  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2110  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2111  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2112
2113  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2114  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2115  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2116  if (Rm != 0xF) {
2117    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2118  }
2119
2120  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2121  Inst.addOperand(MCOperand::CreateImm(0));
2122
2123  if (Rm == 0xD)
2124    Inst.addOperand(MCOperand::CreateReg(0));
2125  else if (Rm != 0xF) {
2126    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2127  }
2128
2129  return S;
2130}
2131
2132static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2133                                    uint64_t Address, const void *Decoder) {
2134  DecodeStatus S = Success;
2135
2136  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2137  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2138  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2139  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2140  unsigned size = fieldFromInstruction32(Insn, 6, 2);
2141  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2142  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2143
2144  if (size == 0x3) {
2145    size = 4;
2146    align = 16;
2147  } else {
2148    if (size == 2) {
2149      size = 1 << size;
2150      align *= 8;
2151    } else {
2152      size = 1 << size;
2153      align *= 4*size;
2154    }
2155  }
2156
2157  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2158  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2159  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2160  CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
2161  if (Rm != 0xF) {
2162    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2163  }
2164
2165  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2166  Inst.addOperand(MCOperand::CreateImm(align));
2167
2168  if (Rm == 0xD)
2169    Inst.addOperand(MCOperand::CreateReg(0));
2170  else if (Rm != 0xF) {
2171    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2172  }
2173
2174  return S;
2175}
2176
2177static DecodeStatus
2178DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2179                            uint64_t Address, const void *Decoder) {
2180  DecodeStatus S = Success;
2181
2182  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2183  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2184  unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2185  imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2186  imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2187  imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2188  imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2189  unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2190
2191  if (Q) {
2192    CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2193  } else {
2194    CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2195  }
2196
2197  Inst.addOperand(MCOperand::CreateImm(imm));
2198
2199  switch (Inst.getOpcode()) {
2200    case ARM::VORRiv4i16:
2201    case ARM::VORRiv2i32:
2202    case ARM::VBICiv4i16:
2203    case ARM::VBICiv2i32:
2204      CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2205      break;
2206    case ARM::VORRiv8i16:
2207    case ARM::VORRiv4i32:
2208    case ARM::VBICiv8i16:
2209    case ARM::VBICiv4i32:
2210      CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2211      break;
2212    default:
2213      break;
2214  }
2215
2216  return S;
2217}
2218
2219static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2220                                        uint64_t Address, const void *Decoder) {
2221  DecodeStatus S = Success;
2222
2223  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2224  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2225  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2226  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2227  unsigned size = fieldFromInstruction32(Insn, 18, 2);
2228
2229  CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2230  CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2231  Inst.addOperand(MCOperand::CreateImm(8 << size));
2232
2233  return S;
2234}
2235
2236static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2237                               uint64_t Address, const void *Decoder) {
2238  Inst.addOperand(MCOperand::CreateImm(8 - Val));
2239  return Success;
2240}
2241
2242static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2243                               uint64_t Address, const void *Decoder) {
2244  Inst.addOperand(MCOperand::CreateImm(16 - Val));
2245  return Success;
2246}
2247
2248static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2249                               uint64_t Address, const void *Decoder) {
2250  Inst.addOperand(MCOperand::CreateImm(32 - Val));
2251  return Success;
2252}
2253
2254static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2255                               uint64_t Address, const void *Decoder) {
2256  Inst.addOperand(MCOperand::CreateImm(64 - Val));
2257  return Success;
2258}
2259
2260static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2261                               uint64_t Address, const void *Decoder) {
2262  DecodeStatus S = Success;
2263
2264  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2265  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2266  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2267  Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2268  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2269  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2270  unsigned op = fieldFromInstruction32(Insn, 6, 1);
2271  unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2272
2273  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2274  if (op) {
2275    CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback
2276  }
2277
2278  for (unsigned i = 0; i < length; ++i) {
2279    CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));
2280  }
2281
2282  CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2283
2284  return S;
2285}
2286
2287static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
2288                            uint64_t Address, const void *Decoder) {
2289  // The immediate needs to be a fully instantiated float.  However, the
2290  // auto-generated decoder is only able to fill in some of the bits
2291  // necessary.  For instance, the 'b' bit is replicated multiple times,
2292  // and is even present in inverted form in one bit.  We do a little
2293  // binary parsing here to fill in those missing bits, and then
2294  // reinterpret it all as a float.
2295  union {
2296    uint32_t integer;
2297    float fp;
2298  } fp_conv;
2299
2300  fp_conv.integer = Val;
2301  uint32_t b = fieldFromInstruction32(Val, 25, 1);
2302  fp_conv.integer |= b << 26;
2303  fp_conv.integer |= b << 27;
2304  fp_conv.integer |= b << 28;
2305  fp_conv.integer |= b << 29;
2306  fp_conv.integer |= (~b & 0x1) << 30;
2307
2308  Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
2309  return Success;
2310}
2311
2312static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2313                                     uint64_t Address, const void *Decoder) {
2314  DecodeStatus S = Success;
2315
2316  unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2317  unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2318
2319  CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
2320
2321  switch(Inst.getOpcode()) {
2322    default:
2323      return Fail;
2324    case ARM::tADR:
2325      break; // tADR does not explicitly represent the PC as an oeprand.
2326    case ARM::tADDrSPi:
2327      Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2328      break;
2329  }
2330
2331  Inst.addOperand(MCOperand::CreateImm(imm));
2332  return S;
2333}
2334
2335static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2336                                 uint64_t Address, const void *Decoder) {
2337  Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2338  return Success;
2339}
2340
2341static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2342                                 uint64_t Address, const void *Decoder) {
2343  Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2344  return Success;
2345}
2346
2347static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2348                                 uint64_t Address, const void *Decoder) {
2349  Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2350  return Success;
2351}
2352
2353static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2354                                 uint64_t Address, const void *Decoder) {
2355  DecodeStatus S = Success;
2356
2357  unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2358  unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2359
2360  CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2361  CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));
2362
2363  return S;
2364}
2365
2366static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2367                                  uint64_t Address, const void *Decoder) {
2368  DecodeStatus S = Success;
2369
2370  unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2371  unsigned imm = fieldFromInstruction32(Val, 3, 5);
2372
2373  CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2374  Inst.addOperand(MCOperand::CreateImm(imm));
2375
2376  return S;
2377}
2378
2379static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2380                                  uint64_t Address, const void *Decoder) {
2381  Inst.addOperand(MCOperand::CreateImm(Val << 2));
2382
2383  return Success;
2384}
2385
2386static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2387                                  uint64_t Address, const void *Decoder) {
2388  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2389  Inst.addOperand(MCOperand::CreateImm(Val));
2390
2391  return Success;
2392}
2393
2394static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2395                                  uint64_t Address, const void *Decoder) {
2396  DecodeStatus S = Success;
2397
2398  unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2399  unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2400  unsigned imm = fieldFromInstruction32(Val, 0, 2);
2401
2402  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2403  CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));
2404  Inst.addOperand(MCOperand::CreateImm(imm));
2405
2406  return S;
2407}
2408
2409static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2410                              uint64_t Address, const void *Decoder) {
2411  DecodeStatus S = Success;
2412
2413  switch (Inst.getOpcode()) {
2414    case ARM::t2PLDs:
2415    case ARM::t2PLDWs:
2416    case ARM::t2PLIs:
2417      break;
2418    default: {
2419      unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2420      CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2421    }
2422  }
2423
2424  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2425  if (Rn == 0xF) {
2426    switch (Inst.getOpcode()) {
2427      case ARM::t2LDRBs:
2428        Inst.setOpcode(ARM::t2LDRBpci);
2429        break;
2430      case ARM::t2LDRHs:
2431        Inst.setOpcode(ARM::t2LDRHpci);
2432        break;
2433      case ARM::t2LDRSHs:
2434        Inst.setOpcode(ARM::t2LDRSHpci);
2435        break;
2436      case ARM::t2LDRSBs:
2437        Inst.setOpcode(ARM::t2LDRSBpci);
2438        break;
2439      case ARM::t2PLDs:
2440        Inst.setOpcode(ARM::t2PLDi12);
2441        Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2442        break;
2443      default:
2444        return Fail;
2445    }
2446
2447    int imm = fieldFromInstruction32(Insn, 0, 12);
2448    if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2449    Inst.addOperand(MCOperand::CreateImm(imm));
2450
2451    return S;
2452  }
2453
2454  unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2455  addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2456  addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2457  CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));
2458
2459  return S;
2460}
2461
2462static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2463                           uint64_t Address, const void *Decoder) {
2464  int imm = Val & 0xFF;
2465  if (!(Val & 0x100)) imm *= -1;
2466  Inst.addOperand(MCOperand::CreateImm(imm << 2));
2467
2468  return Success;
2469}
2470
2471static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2472                                   uint64_t Address, const void *Decoder) {
2473  DecodeStatus S = Success;
2474
2475  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2476  unsigned imm = fieldFromInstruction32(Val, 0, 9);
2477
2478  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2479  CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));
2480
2481  return S;
2482}
2483
2484static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2485                         uint64_t Address, const void *Decoder) {
2486  int imm = Val & 0xFF;
2487  if (!(Val & 0x100)) imm *= -1;
2488  Inst.addOperand(MCOperand::CreateImm(imm));
2489
2490  return Success;
2491}
2492
2493
2494static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2495                                 uint64_t Address, const void *Decoder) {
2496  DecodeStatus S = Success;
2497
2498  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2499  unsigned imm = fieldFromInstruction32(Val, 0, 9);
2500
2501  // Some instructions always use an additive offset.
2502  switch (Inst.getOpcode()) {
2503    case ARM::t2LDRT:
2504    case ARM::t2LDRBT:
2505    case ARM::t2LDRHT:
2506    case ARM::t2LDRSBT:
2507    case ARM::t2LDRSHT:
2508      imm |= 0x100;
2509      break;
2510    default:
2511      break;
2512  }
2513
2514  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2515  CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));
2516
2517  return S;
2518}
2519
2520
2521static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2522                                  uint64_t Address, const void *Decoder) {
2523  DecodeStatus S = Success;
2524
2525  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2526  unsigned imm = fieldFromInstruction32(Val, 0, 12);
2527
2528  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2529  Inst.addOperand(MCOperand::CreateImm(imm));
2530
2531  return S;
2532}
2533
2534
2535static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2536                                uint64_t Address, const void *Decoder) {
2537  unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2538
2539  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2540  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2541  Inst.addOperand(MCOperand::CreateImm(imm));
2542
2543  return Success;
2544}
2545
2546static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
2547                                uint64_t Address, const void *Decoder) {
2548  DecodeStatus S = Success;
2549
2550  if (Inst.getOpcode() == ARM::tADDrSP) {
2551    unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2552    Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2553
2554    CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2555    CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2556    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2557  } else if (Inst.getOpcode() == ARM::tADDspr) {
2558    unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2559
2560    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2561    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2562    CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2563  }
2564
2565  return S;
2566}
2567
2568static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
2569                           uint64_t Address, const void *Decoder) {
2570  unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2571  unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2572
2573  Inst.addOperand(MCOperand::CreateImm(imod));
2574  Inst.addOperand(MCOperand::CreateImm(flags));
2575
2576  return Success;
2577}
2578
2579static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
2580                             uint64_t Address, const void *Decoder) {
2581  DecodeStatus S = Success;
2582  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2583  unsigned add = fieldFromInstruction32(Insn, 4, 1);
2584
2585  CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;
2586  Inst.addOperand(MCOperand::CreateImm(add));
2587
2588  return S;
2589}
2590
2591static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
2592                                 uint64_t Address, const void *Decoder) {
2593  Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2594  return Success;
2595}
2596
2597static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
2598                              uint64_t Address, const void *Decoder) {
2599  if (Val == 0xA || Val == 0xB)
2600    return Fail;
2601
2602  Inst.addOperand(MCOperand::CreateImm(Val));
2603  return Success;
2604}
2605
2606static DecodeStatus
2607DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2608                           uint64_t Address, const void *Decoder) {
2609  DecodeStatus S = Success;
2610
2611  unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2612  if (pred == 0xE || pred == 0xF) {
2613    unsigned opc = fieldFromInstruction32(Insn, 4, 2);
2614    switch (opc) {
2615      default:
2616        return Fail;
2617      case 0:
2618        Inst.setOpcode(ARM::t2DSB);
2619        break;
2620      case 1:
2621        Inst.setOpcode(ARM::t2DMB);
2622        break;
2623      case 2:
2624        Inst.setOpcode(ARM::t2ISB);
2625        return Success;
2626    }
2627
2628    unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2629    return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
2630  }
2631
2632  unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2633  brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2634  brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2635  brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2636  brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2637
2638  CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));
2639  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2640
2641  return S;
2642}
2643
2644// Decode a shifted immediate operand.  These basically consist
2645// of an 8-bit value, and a 4-bit directive that specifies either
2646// a splat operation or a rotation.
2647static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
2648                          uint64_t Address, const void *Decoder) {
2649  unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2650  if (ctrl == 0) {
2651    unsigned byte = fieldFromInstruction32(Val, 8, 2);
2652    unsigned imm = fieldFromInstruction32(Val, 0, 8);
2653    switch (byte) {
2654      case 0:
2655        Inst.addOperand(MCOperand::CreateImm(imm));
2656        break;
2657      case 1:
2658        Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2659        break;
2660      case 2:
2661        Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2662        break;
2663      case 3:
2664        Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2665                                             (imm << 8)  |  imm));
2666        break;
2667    }
2668  } else {
2669    unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2670    unsigned rot = fieldFromInstruction32(Val, 7, 5);
2671    unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2672    Inst.addOperand(MCOperand::CreateImm(imm));
2673  }
2674
2675  return Success;
2676}
2677
2678static DecodeStatus
2679DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2680                            uint64_t Address, const void *Decoder){
2681  Inst.addOperand(MCOperand::CreateImm(Val << 1));
2682  return Success;
2683}
2684
2685static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
2686                                       uint64_t Address, const void *Decoder){
2687  Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2688  return Success;
2689}
2690
2691static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
2692                                   uint64_t Address, const void *Decoder) {
2693  switch (Val) {
2694  default:
2695    return Fail;
2696  case 0xF: // SY
2697  case 0xE: // ST
2698  case 0xB: // ISH
2699  case 0xA: // ISHST
2700  case 0x7: // NSH
2701  case 0x6: // NSHST
2702  case 0x3: // OSH
2703  case 0x2: // OSHST
2704    break;
2705  }
2706
2707  Inst.addOperand(MCOperand::CreateImm(Val));
2708  return Success;
2709}
2710
2711static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
2712                          uint64_t Address, const void *Decoder) {
2713  if (!Val) return Fail;
2714  Inst.addOperand(MCOperand::CreateImm(Val));
2715  return Success;
2716}
2717
2718static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
2719                                        uint64_t Address, const void *Decoder) {
2720  DecodeStatus S = Success;
2721
2722  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2723  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2724  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2725
2726  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2727
2728  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2729  CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2730  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2731  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2732
2733  return S;
2734}
2735
2736
2737static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
2738                                         uint64_t Address, const void *Decoder){
2739  DecodeStatus S = Success;
2740
2741  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2742  unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2743  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2744  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2745
2746  CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));
2747
2748  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2749  if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;
2750
2751  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2752  CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2753  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2754  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2755
2756  return S;
2757}
2758
2759static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
2760                            uint64_t Address, const void *Decoder) {
2761  DecodeStatus S = Success;
2762
2763  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2764  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2765  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2766  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2767  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2768  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2769
2770  if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2771
2772  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2773  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2774  CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
2775  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2776
2777  return S;
2778}
2779
2780static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
2781                            uint64_t Address, const void *Decoder) {
2782  DecodeStatus S = Success;
2783
2784  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2785  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2786  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2787  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2788  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2789  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2790
2791  if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2792
2793  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2794  CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2795  CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
2796  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2797
2798  return S;
2799}
2800
2801static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
2802                         uint64_t Address, const void *Decoder) {
2803  DecodeStatus S = Success;
2804
2805  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2806  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2807  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2808  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2809  unsigned size = fieldFromInstruction32(Insn, 10, 2);
2810
2811  unsigned align = 0;
2812  unsigned index = 0;
2813  switch (size) {
2814    default:
2815      return Fail;
2816    case 0:
2817      if (fieldFromInstruction32(Insn, 4, 1))
2818        return Fail; // UNDEFINED
2819      index = fieldFromInstruction32(Insn, 5, 3);
2820      break;
2821    case 1:
2822      if (fieldFromInstruction32(Insn, 5, 1))
2823        return Fail; // UNDEFINED
2824      index = fieldFromInstruction32(Insn, 6, 2);
2825      if (fieldFromInstruction32(Insn, 4, 1))
2826        align = 2;
2827      break;
2828    case 2:
2829      if (fieldFromInstruction32(Insn, 6, 1))
2830        return Fail; // UNDEFINED
2831      index = fieldFromInstruction32(Insn, 7, 1);
2832      if (fieldFromInstruction32(Insn, 4, 2) != 0)
2833        align = 4;
2834  }
2835
2836  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2837  if (Rm != 0xF) { // Writeback
2838    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2839  }
2840  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2841  Inst.addOperand(MCOperand::CreateImm(align));
2842  if (Rm != 0xF) {
2843    if (Rm != 0xD)
2844      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2845    else
2846      Inst.addOperand(MCOperand::CreateReg(0));
2847  }
2848
2849  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2850  Inst.addOperand(MCOperand::CreateImm(index));
2851
2852  return S;
2853}
2854
2855static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
2856                         uint64_t Address, const void *Decoder) {
2857  DecodeStatus S = Success;
2858
2859  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2860  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2861  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2862  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2863  unsigned size = fieldFromInstruction32(Insn, 10, 2);
2864
2865  unsigned align = 0;
2866  unsigned index = 0;
2867  switch (size) {
2868    default:
2869      return Fail;
2870    case 0:
2871      if (fieldFromInstruction32(Insn, 4, 1))
2872        return Fail; // UNDEFINED
2873      index = fieldFromInstruction32(Insn, 5, 3);
2874      break;
2875    case 1:
2876      if (fieldFromInstruction32(Insn, 5, 1))
2877        return Fail; // UNDEFINED
2878      index = fieldFromInstruction32(Insn, 6, 2);
2879      if (fieldFromInstruction32(Insn, 4, 1))
2880        align = 2;
2881      break;
2882    case 2:
2883      if (fieldFromInstruction32(Insn, 6, 1))
2884        return Fail; // UNDEFINED
2885      index = fieldFromInstruction32(Insn, 7, 1);
2886      if (fieldFromInstruction32(Insn, 4, 2) != 0)
2887        align = 4;
2888  }
2889
2890  if (Rm != 0xF) { // Writeback
2891    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2892  }
2893  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2894  Inst.addOperand(MCOperand::CreateImm(align));
2895  if (Rm != 0xF) {
2896    if (Rm != 0xD)
2897      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2898    else
2899      Inst.addOperand(MCOperand::CreateReg(0));
2900  }
2901
2902  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2903  Inst.addOperand(MCOperand::CreateImm(index));
2904
2905  return S;
2906}
2907
2908
2909static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
2910                         uint64_t Address, const void *Decoder) {
2911  DecodeStatus S = Success;
2912
2913  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2914  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2915  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2916  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2917  unsigned size = fieldFromInstruction32(Insn, 10, 2);
2918
2919  unsigned align = 0;
2920  unsigned index = 0;
2921  unsigned inc = 1;
2922  switch (size) {
2923    default:
2924      return Fail;
2925    case 0:
2926      index = fieldFromInstruction32(Insn, 5, 3);
2927      if (fieldFromInstruction32(Insn, 4, 1))
2928        align = 2;
2929      break;
2930    case 1:
2931      index = fieldFromInstruction32(Insn, 6, 2);
2932      if (fieldFromInstruction32(Insn, 4, 1))
2933        align = 4;
2934      if (fieldFromInstruction32(Insn, 5, 1))
2935        inc = 2;
2936      break;
2937    case 2:
2938      if (fieldFromInstruction32(Insn, 5, 1))
2939        return Fail; // UNDEFINED
2940      index = fieldFromInstruction32(Insn, 7, 1);
2941      if (fieldFromInstruction32(Insn, 4, 1) != 0)
2942        align = 8;
2943      if (fieldFromInstruction32(Insn, 6, 1))
2944        inc = 2;
2945      break;
2946  }
2947
2948  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2949  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2950  if (Rm != 0xF) { // Writeback
2951    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2952  }
2953  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2954  Inst.addOperand(MCOperand::CreateImm(align));
2955  if (Rm != 0xF) {
2956    if (Rm != 0xD)
2957      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2958    else
2959      Inst.addOperand(MCOperand::CreateReg(0));
2960  }
2961
2962  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2963  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2964  Inst.addOperand(MCOperand::CreateImm(index));
2965
2966  return S;
2967}
2968
2969static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
2970                         uint64_t Address, const void *Decoder) {
2971  DecodeStatus S = Success;
2972
2973  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2974  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2975  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2976  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2977  unsigned size = fieldFromInstruction32(Insn, 10, 2);
2978
2979  unsigned align = 0;
2980  unsigned index = 0;
2981  unsigned inc = 1;
2982  switch (size) {
2983    default:
2984      return Fail;
2985    case 0:
2986      index = fieldFromInstruction32(Insn, 5, 3);
2987      if (fieldFromInstruction32(Insn, 4, 1))
2988        align = 2;
2989      break;
2990    case 1:
2991      index = fieldFromInstruction32(Insn, 6, 2);
2992      if (fieldFromInstruction32(Insn, 4, 1))
2993        align = 4;
2994      if (fieldFromInstruction32(Insn, 5, 1))
2995        inc = 2;
2996      break;
2997    case 2:
2998      if (fieldFromInstruction32(Insn, 5, 1))
2999        return Fail; // UNDEFINED
3000      index = fieldFromInstruction32(Insn, 7, 1);
3001      if (fieldFromInstruction32(Insn, 4, 1) != 0)
3002        align = 8;
3003      if (fieldFromInstruction32(Insn, 6, 1))
3004        inc = 2;
3005      break;
3006  }
3007
3008  if (Rm != 0xF) { // Writeback
3009    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3010  }
3011  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3012  Inst.addOperand(MCOperand::CreateImm(align));
3013  if (Rm != 0xF) {
3014    if (Rm != 0xD)
3015      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3016    else
3017      Inst.addOperand(MCOperand::CreateReg(0));
3018  }
3019
3020  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3021  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3022  Inst.addOperand(MCOperand::CreateImm(index));
3023
3024  return S;
3025}
3026
3027
3028static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3029                         uint64_t Address, const void *Decoder) {
3030  DecodeStatus S = Success;
3031
3032  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3033  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3034  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3035  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3036  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3037
3038  unsigned align = 0;
3039  unsigned index = 0;
3040  unsigned inc = 1;
3041  switch (size) {
3042    default:
3043      return Fail;
3044    case 0:
3045      if (fieldFromInstruction32(Insn, 4, 1))
3046        return Fail; // UNDEFINED
3047      index = fieldFromInstruction32(Insn, 5, 3);
3048      break;
3049    case 1:
3050      if (fieldFromInstruction32(Insn, 4, 1))
3051        return Fail; // UNDEFINED
3052      index = fieldFromInstruction32(Insn, 6, 2);
3053      if (fieldFromInstruction32(Insn, 5, 1))
3054        inc = 2;
3055      break;
3056    case 2:
3057      if (fieldFromInstruction32(Insn, 4, 2))
3058        return Fail; // UNDEFINED
3059      index = fieldFromInstruction32(Insn, 7, 1);
3060      if (fieldFromInstruction32(Insn, 6, 1))
3061        inc = 2;
3062      break;
3063  }
3064
3065  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3066  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3067  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3068
3069  if (Rm != 0xF) { // Writeback
3070    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3071  }
3072  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3073  Inst.addOperand(MCOperand::CreateImm(align));
3074  if (Rm != 0xF) {
3075    if (Rm != 0xD)
3076      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3077    else
3078      Inst.addOperand(MCOperand::CreateReg(0));
3079  }
3080
3081  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3082  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3083  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3084  Inst.addOperand(MCOperand::CreateImm(index));
3085
3086  return S;
3087}
3088
3089static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3090                         uint64_t Address, const void *Decoder) {
3091  DecodeStatus S = Success;
3092
3093  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3094  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3095  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3096  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3097  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3098
3099  unsigned align = 0;
3100  unsigned index = 0;
3101  unsigned inc = 1;
3102  switch (size) {
3103    default:
3104      return Fail;
3105    case 0:
3106      if (fieldFromInstruction32(Insn, 4, 1))
3107        return Fail; // UNDEFINED
3108      index = fieldFromInstruction32(Insn, 5, 3);
3109      break;
3110    case 1:
3111      if (fieldFromInstruction32(Insn, 4, 1))
3112        return Fail; // UNDEFINED
3113      index = fieldFromInstruction32(Insn, 6, 2);
3114      if (fieldFromInstruction32(Insn, 5, 1))
3115        inc = 2;
3116      break;
3117    case 2:
3118      if (fieldFromInstruction32(Insn, 4, 2))
3119        return Fail; // UNDEFINED
3120      index = fieldFromInstruction32(Insn, 7, 1);
3121      if (fieldFromInstruction32(Insn, 6, 1))
3122        inc = 2;
3123      break;
3124  }
3125
3126  if (Rm != 0xF) { // Writeback
3127    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3128  }
3129  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3130  Inst.addOperand(MCOperand::CreateImm(align));
3131  if (Rm != 0xF) {
3132    if (Rm != 0xD)
3133      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3134    else
3135      Inst.addOperand(MCOperand::CreateReg(0));
3136  }
3137
3138  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3139  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3140  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3141  Inst.addOperand(MCOperand::CreateImm(index));
3142
3143  return S;
3144}
3145
3146
3147static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3148                         uint64_t Address, const void *Decoder) {
3149  DecodeStatus S = Success;
3150
3151  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3152  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3153  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3154  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3155  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3156
3157  unsigned align = 0;
3158  unsigned index = 0;
3159  unsigned inc = 1;
3160  switch (size) {
3161    default:
3162      return Fail;
3163    case 0:
3164      if (fieldFromInstruction32(Insn, 4, 1))
3165        align = 4;
3166      index = fieldFromInstruction32(Insn, 5, 3);
3167      break;
3168    case 1:
3169      if (fieldFromInstruction32(Insn, 4, 1))
3170        align = 8;
3171      index = fieldFromInstruction32(Insn, 6, 2);
3172      if (fieldFromInstruction32(Insn, 5, 1))
3173        inc = 2;
3174      break;
3175    case 2:
3176      if (fieldFromInstruction32(Insn, 4, 2))
3177        align = 4 << fieldFromInstruction32(Insn, 4, 2);
3178      index = fieldFromInstruction32(Insn, 7, 1);
3179      if (fieldFromInstruction32(Insn, 6, 1))
3180        inc = 2;
3181      break;
3182  }
3183
3184  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3185  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3186  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3187  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3188
3189  if (Rm != 0xF) { // Writeback
3190    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3191  }
3192  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3193  Inst.addOperand(MCOperand::CreateImm(align));
3194  if (Rm != 0xF) {
3195    if (Rm != 0xD)
3196      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3197    else
3198      Inst.addOperand(MCOperand::CreateReg(0));
3199  }
3200
3201  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3202  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3203  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3204  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3205  Inst.addOperand(MCOperand::CreateImm(index));
3206
3207  return S;
3208}
3209
3210static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3211                         uint64_t Address, const void *Decoder) {
3212  DecodeStatus S = Success;
3213
3214  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3215  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3216  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3217  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3218  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3219
3220  unsigned align = 0;
3221  unsigned index = 0;
3222  unsigned inc = 1;
3223  switch (size) {
3224    default:
3225      return Fail;
3226    case 0:
3227      if (fieldFromInstruction32(Insn, 4, 1))
3228        align = 4;
3229      index = fieldFromInstruction32(Insn, 5, 3);
3230      break;
3231    case 1:
3232      if (fieldFromInstruction32(Insn, 4, 1))
3233        align = 8;
3234      index = fieldFromInstruction32(Insn, 6, 2);
3235      if (fieldFromInstruction32(Insn, 5, 1))
3236        inc = 2;
3237      break;
3238    case 2:
3239      if (fieldFromInstruction32(Insn, 4, 2))
3240        align = 4 << fieldFromInstruction32(Insn, 4, 2);
3241      index = fieldFromInstruction32(Insn, 7, 1);
3242      if (fieldFromInstruction32(Insn, 6, 1))
3243        inc = 2;
3244      break;
3245  }
3246
3247  if (Rm != 0xF) { // Writeback
3248    CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3249  }
3250  CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3251  Inst.addOperand(MCOperand::CreateImm(align));
3252  if (Rm != 0xF) {
3253    if (Rm != 0xD)
3254      CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3255    else
3256      Inst.addOperand(MCOperand::CreateReg(0));
3257  }
3258
3259  CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3260  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3261  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3262  CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3263  Inst.addOperand(MCOperand::CreateImm(index));
3264
3265  return S;
3266}
3267
3268static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3269                                  uint64_t Address, const void *Decoder) {
3270  DecodeStatus S = Success;
3271  unsigned Rt  = fieldFromInstruction32(Insn, 12, 4);
3272  unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3273  unsigned Rm  = fieldFromInstruction32(Insn,  0, 4);
3274  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3275  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3276
3277  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3278    CHECK(S, Unpredictable);
3279
3280  CHECK(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder));
3281  CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3282  CHECK(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder));
3283  CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3284  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3285
3286  return S;
3287}
3288
3289static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
3290                                  uint64_t Address, const void *Decoder) {
3291  DecodeStatus S = Success;
3292  unsigned Rt  = fieldFromInstruction32(Insn, 12, 4);
3293  unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3294  unsigned Rm  = fieldFromInstruction32(Insn,  0, 4);
3295  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3296  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3297
3298  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3299    CHECK(S, Unpredictable);
3300
3301  CHECK(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder));
3302  CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3303  CHECK(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder));
3304  CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3305  CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3306
3307  return S;
3308}
3309
3310static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond,
3311                                 uint64_t Address, const void *Decoder) {
3312  DecodeStatus S = Success;
3313  if (Cond == 0xF) {
3314    Cond = 0xE;
3315    CHECK(S, Unpredictable);
3316  }
3317
3318  Inst.addOperand(MCOperand::CreateImm(Cond));
3319  return S;
3320}
3321
3322static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask,
3323                                 uint64_t Address, const void *Decoder) {
3324  DecodeStatus S = Success;
3325  if (Mask == 0) {
3326    Mask = 0x8;
3327    CHECK(S, Unpredictable);
3328  }
3329  Inst.addOperand(MCOperand::CreateImm(Mask));
3330  return S;
3331}
3332
3333