ARMDisassembler.cpp revision 6153a036f544beb03dfc4d58edc28cf42712743d
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "ARMDisassembler.h" 13#include "ARM.h" 14#include "ARMRegisterInfo.h" 15#include "MCTargetDesc/ARMAddressingModes.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "llvm/MC/EDInstInfo.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCContext.h" 21#include "llvm/Target/TargetRegistry.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/MemoryObject.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/raw_ostream.h" 26 27// Pull DecodeStatus and its enum values into the global namespace. 28typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 29#define Success llvm::MCDisassembler::Success 30#define Unpredictable llvm::MCDisassembler::SoftFail 31#define Fail llvm::MCDisassembler::Fail 32 33// Helper macro to perform setwise reduction of the current running status 34// and another status, and return if the new status is Fail. 35#define CHECK(S,X) do { \ 36 S = (DecodeStatus) ((int)S & (X)); \ 37 if (S == Fail) return Fail; \ 38 } while(0) 39 40// Forward declare these because the autogenerated code will reference them. 41// Definitions are further down. 42static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 43 uint64_t Address, const void *Decoder); 44static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 45 unsigned RegNo, uint64_t Address, 46 const void *Decoder); 47static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 50 uint64_t Address, const void *Decoder); 51static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 52 uint64_t Address, const void *Decoder); 53static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 54 uint64_t Address, const void *Decoder); 55static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 56 uint64_t Address, const void *Decoder); 57static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 58 uint64_t Address, const void *Decoder); 59static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 60 unsigned RegNo, 61 uint64_t Address, 62 const void *Decoder); 63static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 64 uint64_t Address, const void *Decoder); 65 66static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 67 uint64_t Address, const void *Decoder); 68static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 69 uint64_t Address, const void *Decoder); 70static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 71 uint64_t Address, const void *Decoder); 72static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 73 uint64_t Address, const void *Decoder); 74static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 75 uint64_t Address, const void *Decoder); 76static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 77 uint64_t Address, const void *Decoder); 78static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 79 uint64_t Address, const void *Decoder); 80 81static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 82 uint64_t Address, const void *Decoder); 83static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 84 uint64_t Address, const void *Decoder); 85static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 86 unsigned Insn, 87 uint64_t Address, 88 const void *Decoder); 89static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 90 uint64_t Address, const void *Decoder); 91static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 92 uint64_t Address, const void *Decoder); 93static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 94 uint64_t Address, const void *Decoder); 95static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 96 uint64_t Address, const void *Decoder); 97 98static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 99 unsigned Insn, 100 uint64_t Adddress, 101 const void *Decoder); 102static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 103 uint64_t Address, const void *Decoder); 104static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 105 uint64_t Address, const void *Decoder); 106static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 107 uint64_t Address, const void *Decoder); 108static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 115 uint64_t Address, const void *Decoder); 116static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 125 uint64_t Address, const void *Decoder); 126static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 129 uint64_t Address, const void *Decoder); 130static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 131 uint64_t Address, const void *Decoder); 132static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 133 uint64_t Address, const void *Decoder); 134static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 145 uint64_t Address, const void *Decoder); 146static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 147 uint64_t Address, const void *Decoder); 148static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 159 uint64_t Address, const void *Decoder); 160static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 179 uint64_t Address, const void *Decoder); 180static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 181 uint64_t Address, const void *Decoder); 182static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 183 uint64_t Address, const void *Decoder); 184 185static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 186 uint64_t Address, const void *Decoder); 187static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 204 uint64_t Address, const void *Decoder); 205static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 208 uint64_t Address, const void *Decoder); 209static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 210 uint64_t Address, const void *Decoder); 211static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 212 uint64_t Address, const void *Decoder); 213static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 214 uint64_t Address, const void *Decoder); 215static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 216 uint64_t Address, const void *Decoder); 217static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 218 uint64_t Address, const void *Decoder); 219static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 222 uint64_t Address, const void *Decoder); 223static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 224 uint64_t Address, const void *Decoder); 225static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 226 uint64_t Address, const void *Decoder); 227static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 228 uint64_t Address, const void *Decoder); 229static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 232#include "ARMGenDisassemblerTables.inc" 233#include "ARMGenInstrInfo.inc" 234#include "ARMGenEDInfo.inc" 235 236using namespace llvm; 237 238static MCDisassembler *createARMDisassembler(const Target &T) { 239 return new ARMDisassembler; 240} 241 242static MCDisassembler *createThumbDisassembler(const Target &T) { 243 return new ThumbDisassembler; 244} 245 246EDInstInfo *ARMDisassembler::getEDInfo() const { 247 return instInfoARM; 248} 249 250EDInstInfo *ThumbDisassembler::getEDInfo() const { 251 return instInfoARM; 252} 253 254DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 255 const MemoryObject &Region, 256 uint64_t Address, 257 raw_ostream &os) const { 258 uint8_t bytes[4]; 259 260 // We want to read exactly 4 bytes of data. 261 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 262 return Fail; 263 264 // Encoded as a small-endian 32-bit word in the stream. 265 uint32_t insn = (bytes[3] << 24) | 266 (bytes[2] << 16) | 267 (bytes[1] << 8) | 268 (bytes[0] << 0); 269 270 // Calling the auto-generated decoder function. 271 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); 272 if (result != Fail) { 273 Size = 4; 274 return result; 275 } 276 277 // Instructions that are shared between ARM and Thumb modes. 278 // FIXME: This shouldn't really exist. It's an artifact of the 279 // fact that we fail to encode a few instructions properly for Thumb. 280 MI.clear(); 281 result = decodeCommonInstruction32(MI, insn, Address, this); 282 if (result != Fail) { 283 Size = 4; 284 return result; 285 } 286 287 // VFP and NEON instructions, similarly, are shared between ARM 288 // and Thumb modes. 289 MI.clear(); 290 result = decodeVFPInstruction32(MI, insn, Address, this); 291 if (result != Fail) { 292 Size = 4; 293 return result; 294 } 295 296 MI.clear(); 297 result = decodeNEONDataInstruction32(MI, insn, Address, this); 298 if (result != Fail) { 299 Size = 4; 300 // Add a fake predicate operand, because we share these instruction 301 // definitions with Thumb2 where these instructions are predicable. 302 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 303 return result; 304 } 305 306 MI.clear(); 307 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 308 if (result != Fail) { 309 Size = 4; 310 // Add a fake predicate operand, because we share these instruction 311 // definitions with Thumb2 where these instructions are predicable. 312 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 313 return result; 314 } 315 316 MI.clear(); 317 result = decodeNEONDupInstruction32(MI, insn, Address, this); 318 if (result != Fail) { 319 Size = 4; 320 // Add a fake predicate operand, because we share these instruction 321 // definitions with Thumb2 where these instructions are predicable. 322 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 323 return result; 324 } 325 326 MI.clear(); 327 328 return Fail; 329} 330 331namespace llvm { 332extern MCInstrDesc ARMInsts[]; 333} 334 335// Thumb1 instructions don't have explicit S bits. Rather, they 336// implicitly set CPSR. Since it's not represented in the encoding, the 337// auto-generated decoder won't inject the CPSR operand. We need to fix 338// that as a post-pass. 339static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 340 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 341 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 342 MCInst::iterator I = MI.begin(); 343 for (unsigned i = 0; i < NumOps; ++i, ++I) { 344 if (I == MI.end()) break; 345 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 346 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 347 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 348 return; 349 } 350 } 351 352 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 353} 354 355// Most Thumb instructions don't have explicit predicates in the 356// encoding, but rather get their predicates from IT context. We need 357// to fix up the predicate operands using this context information as a 358// post-pass. 359void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 360 // A few instructions actually have predicates encoded in them. Don't 361 // try to overwrite it if we're seeing one of those. 362 switch (MI.getOpcode()) { 363 case ARM::tBcc: 364 case ARM::t2Bcc: 365 return; 366 default: 367 break; 368 } 369 370 // If we're in an IT block, base the predicate on that. Otherwise, 371 // assume a predicate of AL. 372 unsigned CC; 373 if (!ITBlock.empty()) { 374 CC = ITBlock.back(); 375 ITBlock.pop_back(); 376 } else 377 CC = ARMCC::AL; 378 379 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 380 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 381 MCInst::iterator I = MI.begin(); 382 for (unsigned i = 0; i < NumOps; ++i, ++I) { 383 if (I == MI.end()) break; 384 if (OpInfo[i].isPredicate()) { 385 I = MI.insert(I, MCOperand::CreateImm(CC)); 386 ++I; 387 if (CC == ARMCC::AL) 388 MI.insert(I, MCOperand::CreateReg(0)); 389 else 390 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 391 return; 392 } 393 } 394 395 I = MI.insert(I, MCOperand::CreateImm(CC)); 396 ++I; 397 if (CC == ARMCC::AL) 398 MI.insert(I, MCOperand::CreateReg(0)); 399 else 400 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 401} 402 403// Thumb VFP instructions are a special case. Because we share their 404// encodings between ARM and Thumb modes, and they are predicable in ARM 405// mode, the auto-generated decoder will give them an (incorrect) 406// predicate operand. We need to rewrite these operands based on the IT 407// context as a post-pass. 408void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 409 unsigned CC; 410 if (!ITBlock.empty()) { 411 CC = ITBlock.back(); 412 ITBlock.pop_back(); 413 } else 414 CC = ARMCC::AL; 415 416 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 417 MCInst::iterator I = MI.begin(); 418 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 419 if (OpInfo[i].isPredicate() ) { 420 I->setImm(CC); 421 ++I; 422 if (CC == ARMCC::AL) 423 I->setReg(0); 424 else 425 I->setReg(ARM::CPSR); 426 return; 427 } 428 } 429} 430 431DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 432 const MemoryObject &Region, 433 uint64_t Address, 434 raw_ostream &os) const { 435 uint8_t bytes[4]; 436 437 // We want to read exactly 2 bytes of data. 438 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 439 return Fail; 440 441 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 442 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); 443 if (result != Fail) { 444 Size = 2; 445 AddThumbPredicate(MI); 446 return result; 447 } 448 449 MI.clear(); 450 result = decodeThumbSBitInstruction16(MI, insn16, Address, this); 451 if (result) { 452 Size = 2; 453 bool InITBlock = !ITBlock.empty(); 454 AddThumbPredicate(MI); 455 AddThumb1SBit(MI, InITBlock); 456 return result; 457 } 458 459 MI.clear(); 460 result = decodeThumb2Instruction16(MI, insn16, Address, this); 461 if (result != Fail) { 462 Size = 2; 463 AddThumbPredicate(MI); 464 465 // If we find an IT instruction, we need to parse its condition 466 // code and mask operands so that we can apply them correctly 467 // to the subsequent instructions. 468 if (MI.getOpcode() == ARM::t2IT) { 469 unsigned firstcond = MI.getOperand(0).getImm(); 470 uint32_t mask = MI.getOperand(1).getImm(); 471 unsigned zeros = CountTrailingZeros_32(mask); 472 mask >>= zeros+1; 473 474 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 475 if (firstcond ^ (mask & 1)) 476 ITBlock.push_back(firstcond ^ 1); 477 else 478 ITBlock.push_back(firstcond); 479 mask >>= 1; 480 } 481 ITBlock.push_back(firstcond); 482 } 483 484 return result; 485 } 486 487 // We want to read exactly 4 bytes of data. 488 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 489 return Fail; 490 491 uint32_t insn32 = (bytes[3] << 8) | 492 (bytes[2] << 0) | 493 (bytes[1] << 24) | 494 (bytes[0] << 16); 495 MI.clear(); 496 result = decodeThumbInstruction32(MI, insn32, Address, this); 497 if (result != Fail) { 498 Size = 4; 499 bool InITBlock = ITBlock.size(); 500 AddThumbPredicate(MI); 501 AddThumb1SBit(MI, InITBlock); 502 return result; 503 } 504 505 MI.clear(); 506 result = decodeThumb2Instruction32(MI, insn32, Address, this); 507 if (result != Fail) { 508 Size = 4; 509 AddThumbPredicate(MI); 510 return result; 511 } 512 513 MI.clear(); 514 result = decodeCommonInstruction32(MI, insn32, Address, this); 515 if (result != Fail) { 516 Size = 4; 517 AddThumbPredicate(MI); 518 return result; 519 } 520 521 MI.clear(); 522 result = decodeVFPInstruction32(MI, insn32, Address, this); 523 if (result != Fail) { 524 Size = 4; 525 UpdateThumbVFPPredicate(MI); 526 return result; 527 } 528 529 MI.clear(); 530 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 531 if (result != Fail) { 532 Size = 4; 533 AddThumbPredicate(MI); 534 return result; 535 } 536 537 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 538 MI.clear(); 539 uint32_t NEONLdStInsn = insn32; 540 NEONLdStInsn &= 0xF0FFFFFF; 541 NEONLdStInsn |= 0x04000000; 542 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 543 if (result != Fail) { 544 Size = 4; 545 AddThumbPredicate(MI); 546 return result; 547 } 548 } 549 550 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 551 MI.clear(); 552 uint32_t NEONDataInsn = insn32; 553 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 554 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 555 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 556 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 557 if (result != Fail) { 558 Size = 4; 559 AddThumbPredicate(MI); 560 return result; 561 } 562 } 563 564 return Fail; 565} 566 567 568extern "C" void LLVMInitializeARMDisassembler() { 569 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 570 createARMDisassembler); 571 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 572 createThumbDisassembler); 573} 574 575static const unsigned GPRDecoderTable[] = { 576 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 577 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 578 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 579 ARM::R12, ARM::SP, ARM::LR, ARM::PC 580}; 581 582static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 583 uint64_t Address, const void *Decoder) { 584 if (RegNo > 15) 585 return Fail; 586 587 unsigned Register = GPRDecoderTable[RegNo]; 588 Inst.addOperand(MCOperand::CreateReg(Register)); 589 return Success; 590} 591 592static DecodeStatus 593DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 594 uint64_t Address, const void *Decoder) { 595 if (RegNo == 15) return Fail; 596 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 597} 598 599static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 600 uint64_t Address, const void *Decoder) { 601 if (RegNo > 7) 602 return Fail; 603 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 604} 605 606static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 607 uint64_t Address, const void *Decoder) { 608 unsigned Register = 0; 609 switch (RegNo) { 610 case 0: 611 Register = ARM::R0; 612 break; 613 case 1: 614 Register = ARM::R1; 615 break; 616 case 2: 617 Register = ARM::R2; 618 break; 619 case 3: 620 Register = ARM::R3; 621 break; 622 case 9: 623 Register = ARM::R9; 624 break; 625 case 12: 626 Register = ARM::R12; 627 break; 628 default: 629 return Fail; 630 } 631 632 Inst.addOperand(MCOperand::CreateReg(Register)); 633 return Success; 634} 635 636static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 637 uint64_t Address, const void *Decoder) { 638 if (RegNo == 13 || RegNo == 15) return Fail; 639 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 640} 641 642static const unsigned SPRDecoderTable[] = { 643 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 644 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 645 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 646 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 647 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 648 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 649 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 650 ARM::S28, ARM::S29, ARM::S30, ARM::S31 651}; 652 653static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 654 uint64_t Address, const void *Decoder) { 655 if (RegNo > 31) 656 return Fail; 657 658 unsigned Register = SPRDecoderTable[RegNo]; 659 Inst.addOperand(MCOperand::CreateReg(Register)); 660 return Success; 661} 662 663static const unsigned DPRDecoderTable[] = { 664 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 665 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 666 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 667 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 668 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 669 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 670 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 671 ARM::D28, ARM::D29, ARM::D30, ARM::D31 672}; 673 674static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 675 uint64_t Address, const void *Decoder) { 676 if (RegNo > 31) 677 return Fail; 678 679 unsigned Register = DPRDecoderTable[RegNo]; 680 Inst.addOperand(MCOperand::CreateReg(Register)); 681 return Success; 682} 683 684static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 685 uint64_t Address, const void *Decoder) { 686 if (RegNo > 7) 687 return Fail; 688 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 689} 690 691static DecodeStatus 692DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 693 uint64_t Address, const void *Decoder) { 694 if (RegNo > 15) 695 return Fail; 696 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 697} 698 699static const unsigned QPRDecoderTable[] = { 700 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 701 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 702 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 703 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 704}; 705 706 707static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 708 uint64_t Address, const void *Decoder) { 709 if (RegNo > 31) 710 return Fail; 711 RegNo >>= 1; 712 713 unsigned Register = QPRDecoderTable[RegNo]; 714 Inst.addOperand(MCOperand::CreateReg(Register)); 715 return Success; 716} 717 718static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 719 uint64_t Address, const void *Decoder) { 720 if (Val == 0xF) return Fail; 721 // AL predicate is not allowed on Thumb1 branches. 722 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 723 return Fail; 724 Inst.addOperand(MCOperand::CreateImm(Val)); 725 if (Val == ARMCC::AL) { 726 Inst.addOperand(MCOperand::CreateReg(0)); 727 } else 728 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 729 return Success; 730} 731 732static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 733 uint64_t Address, const void *Decoder) { 734 if (Val) 735 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 736 else 737 Inst.addOperand(MCOperand::CreateReg(0)); 738 return Success; 739} 740 741static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 742 uint64_t Address, const void *Decoder) { 743 uint32_t imm = Val & 0xFF; 744 uint32_t rot = (Val & 0xF00) >> 7; 745 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 746 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 747 return Success; 748} 749 750static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 751 uint64_t Address, const void *Decoder) { 752 Val <<= 2; 753 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 754 return Success; 755} 756 757static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 758 uint64_t Address, const void *Decoder) { 759 DecodeStatus S = Success; 760 761 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 762 unsigned type = fieldFromInstruction32(Val, 5, 2); 763 unsigned imm = fieldFromInstruction32(Val, 7, 5); 764 765 // Register-immediate 766 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 767 768 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 769 switch (type) { 770 case 0: 771 Shift = ARM_AM::lsl; 772 break; 773 case 1: 774 Shift = ARM_AM::lsr; 775 break; 776 case 2: 777 Shift = ARM_AM::asr; 778 break; 779 case 3: 780 Shift = ARM_AM::ror; 781 break; 782 } 783 784 if (Shift == ARM_AM::ror && imm == 0) 785 Shift = ARM_AM::rrx; 786 787 unsigned Op = Shift | (imm << 3); 788 Inst.addOperand(MCOperand::CreateImm(Op)); 789 790 return S; 791} 792 793static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 794 uint64_t Address, const void *Decoder) { 795 DecodeStatus S = Success; 796 797 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 798 unsigned type = fieldFromInstruction32(Val, 5, 2); 799 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 800 801 // Register-register 802 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 803 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); 804 805 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 806 switch (type) { 807 case 0: 808 Shift = ARM_AM::lsl; 809 break; 810 case 1: 811 Shift = ARM_AM::lsr; 812 break; 813 case 2: 814 Shift = ARM_AM::asr; 815 break; 816 case 3: 817 Shift = ARM_AM::ror; 818 break; 819 } 820 821 Inst.addOperand(MCOperand::CreateImm(Shift)); 822 823 return S; 824} 825 826static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 827 uint64_t Address, const void *Decoder) { 828 DecodeStatus S = Success; 829 830 // Empty register lists are not allowed. 831 if (CountPopulation_32(Val) == 0) return Fail; 832 for (unsigned i = 0; i < 16; ++i) { 833 if (Val & (1 << i)) { 834 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); 835 } 836 } 837 838 return S; 839} 840 841static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 842 uint64_t Address, const void *Decoder) { 843 DecodeStatus S = Success; 844 845 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 846 unsigned regs = Val & 0xFF; 847 848 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); 849 for (unsigned i = 0; i < (regs - 1); ++i) { 850 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); 851 } 852 853 return S; 854} 855 856static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 857 uint64_t Address, const void *Decoder) { 858 DecodeStatus S = Success; 859 860 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 861 unsigned regs = (Val & 0xFF) / 2; 862 863 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); 864 for (unsigned i = 0; i < (regs - 1); ++i) { 865 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); 866 } 867 868 return S; 869} 870 871static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 872 uint64_t Address, const void *Decoder) { 873 // This operand encodes a mask of contiguous zeros between a specified MSB 874 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 875 // the mask of all bits LSB-and-lower, and then xor them to create 876 // the mask of that's all ones on [msb, lsb]. Finally we not it to 877 // create the final mask. 878 unsigned msb = fieldFromInstruction32(Val, 5, 5); 879 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 880 uint32_t msb_mask = (1 << (msb+1)) - 1; 881 uint32_t lsb_mask = (1 << lsb) - 1; 882 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 883 return Success; 884} 885 886static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 887 uint64_t Address, const void *Decoder) { 888 DecodeStatus S = Success; 889 890 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 891 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 892 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 893 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 894 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 895 unsigned U = fieldFromInstruction32(Insn, 23, 1); 896 897 switch (Inst.getOpcode()) { 898 case ARM::LDC_OFFSET: 899 case ARM::LDC_PRE: 900 case ARM::LDC_POST: 901 case ARM::LDC_OPTION: 902 case ARM::LDCL_OFFSET: 903 case ARM::LDCL_PRE: 904 case ARM::LDCL_POST: 905 case ARM::LDCL_OPTION: 906 case ARM::STC_OFFSET: 907 case ARM::STC_PRE: 908 case ARM::STC_POST: 909 case ARM::STC_OPTION: 910 case ARM::STCL_OFFSET: 911 case ARM::STCL_PRE: 912 case ARM::STCL_POST: 913 case ARM::STCL_OPTION: 914 if (coproc == 0xA || coproc == 0xB) 915 return Fail; 916 break; 917 default: 918 break; 919 } 920 921 Inst.addOperand(MCOperand::CreateImm(coproc)); 922 Inst.addOperand(MCOperand::CreateImm(CRd)); 923 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 924 switch (Inst.getOpcode()) { 925 case ARM::LDC_OPTION: 926 case ARM::LDCL_OPTION: 927 case ARM::LDC2_OPTION: 928 case ARM::LDC2L_OPTION: 929 case ARM::STC_OPTION: 930 case ARM::STCL_OPTION: 931 case ARM::STC2_OPTION: 932 case ARM::STC2L_OPTION: 933 case ARM::LDCL_POST: 934 case ARM::STCL_POST: 935 case ARM::LDC2L_POST: 936 case ARM::STC2L_POST: 937 break; 938 default: 939 Inst.addOperand(MCOperand::CreateReg(0)); 940 break; 941 } 942 943 unsigned P = fieldFromInstruction32(Insn, 24, 1); 944 unsigned W = fieldFromInstruction32(Insn, 21, 1); 945 946 bool writeback = (P == 0) || (W == 1); 947 unsigned idx_mode = 0; 948 if (P && writeback) 949 idx_mode = ARMII::IndexModePre; 950 else if (!P && writeback) 951 idx_mode = ARMII::IndexModePost; 952 953 switch (Inst.getOpcode()) { 954 case ARM::LDCL_POST: 955 case ARM::STCL_POST: 956 case ARM::LDC2L_POST: 957 case ARM::STC2L_POST: 958 imm |= U << 8; 959 case ARM::LDC_OPTION: 960 case ARM::LDCL_OPTION: 961 case ARM::LDC2_OPTION: 962 case ARM::LDC2L_OPTION: 963 case ARM::STC_OPTION: 964 case ARM::STCL_OPTION: 965 case ARM::STC2_OPTION: 966 case ARM::STC2L_OPTION: 967 Inst.addOperand(MCOperand::CreateImm(imm)); 968 break; 969 default: 970 if (U) 971 Inst.addOperand(MCOperand::CreateImm( 972 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 973 else 974 Inst.addOperand(MCOperand::CreateImm( 975 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 976 break; 977 } 978 979 switch (Inst.getOpcode()) { 980 case ARM::LDC_OFFSET: 981 case ARM::LDC_PRE: 982 case ARM::LDC_POST: 983 case ARM::LDC_OPTION: 984 case ARM::LDCL_OFFSET: 985 case ARM::LDCL_PRE: 986 case ARM::LDCL_POST: 987 case ARM::LDCL_OPTION: 988 case ARM::STC_OFFSET: 989 case ARM::STC_PRE: 990 case ARM::STC_POST: 991 case ARM::STC_OPTION: 992 case ARM::STCL_OFFSET: 993 case ARM::STCL_PRE: 994 case ARM::STCL_POST: 995 case ARM::STCL_OPTION: 996 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 997 break; 998 default: 999 break; 1000 } 1001 1002 return S; 1003} 1004 1005static DecodeStatus 1006DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1007 uint64_t Address, const void *Decoder) { 1008 DecodeStatus S = Success; 1009 1010 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1011 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1012 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1013 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1014 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1015 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1016 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1017 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1018 1019 // On stores, the writeback operand precedes Rt. 1020 switch (Inst.getOpcode()) { 1021 case ARM::STR_POST_IMM: 1022 case ARM::STR_POST_REG: 1023 case ARM::STRB_POST_IMM: 1024 case ARM::STRB_POST_REG: 1025 case ARM::STRT_POST_REG: 1026 case ARM::STRT_POST_IMM: 1027 case ARM::STRBT_POST_REG: 1028 case ARM::STRBT_POST_IMM: 1029 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1030 break; 1031 default: 1032 break; 1033 } 1034 1035 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1036 1037 // On loads, the writeback operand comes after Rt. 1038 switch (Inst.getOpcode()) { 1039 case ARM::LDR_POST_IMM: 1040 case ARM::LDR_POST_REG: 1041 case ARM::LDRB_POST_IMM: 1042 case ARM::LDRB_POST_REG: 1043 case ARM::LDR_PRE: 1044 case ARM::LDRB_PRE: 1045 case ARM::LDRBT_POST_REG: 1046 case ARM::LDRBT_POST_IMM: 1047 case ARM::LDRT_POST_REG: 1048 case ARM::LDRT_POST_IMM: 1049 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1050 break; 1051 default: 1052 break; 1053 } 1054 1055 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1056 1057 ARM_AM::AddrOpc Op = ARM_AM::add; 1058 if (!fieldFromInstruction32(Insn, 23, 1)) 1059 Op = ARM_AM::sub; 1060 1061 bool writeback = (P == 0) || (W == 1); 1062 unsigned idx_mode = 0; 1063 if (P && writeback) 1064 idx_mode = ARMII::IndexModePre; 1065 else if (!P && writeback) 1066 idx_mode = ARMII::IndexModePost; 1067 1068 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE 1069 1070 if (reg) { 1071 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1072 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1073 switch( fieldFromInstruction32(Insn, 5, 2)) { 1074 case 0: 1075 Opc = ARM_AM::lsl; 1076 break; 1077 case 1: 1078 Opc = ARM_AM::lsr; 1079 break; 1080 case 2: 1081 Opc = ARM_AM::asr; 1082 break; 1083 case 3: 1084 Opc = ARM_AM::ror; 1085 break; 1086 default: 1087 return Fail; 1088 } 1089 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1090 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1091 1092 Inst.addOperand(MCOperand::CreateImm(imm)); 1093 } else { 1094 Inst.addOperand(MCOperand::CreateReg(0)); 1095 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1096 Inst.addOperand(MCOperand::CreateImm(tmp)); 1097 } 1098 1099 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1100 1101 return S; 1102} 1103 1104static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1105 uint64_t Address, const void *Decoder) { 1106 DecodeStatus S = Success; 1107 1108 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1109 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1110 unsigned type = fieldFromInstruction32(Val, 5, 2); 1111 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1112 unsigned U = fieldFromInstruction32(Val, 12, 1); 1113 1114 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1115 switch (type) { 1116 case 0: 1117 ShOp = ARM_AM::lsl; 1118 break; 1119 case 1: 1120 ShOp = ARM_AM::lsr; 1121 break; 1122 case 2: 1123 ShOp = ARM_AM::asr; 1124 break; 1125 case 3: 1126 ShOp = ARM_AM::ror; 1127 break; 1128 } 1129 1130 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1131 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1132 unsigned shift; 1133 if (U) 1134 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1135 else 1136 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1137 Inst.addOperand(MCOperand::CreateImm(shift)); 1138 1139 return S; 1140} 1141 1142static DecodeStatus 1143DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1144 uint64_t Address, const void *Decoder) { 1145 DecodeStatus S = Success; 1146 1147 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1148 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1149 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1150 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1151 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1152 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1153 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1154 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1155 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1156 1157 bool writeback = (W == 1) | (P == 0); 1158 1159 // For {LD,ST}RD, Rt must be even, else undefined. 1160 switch (Inst.getOpcode()) { 1161 case ARM::STRD: 1162 case ARM::STRD_PRE: 1163 case ARM::STRD_POST: 1164 case ARM::LDRD: 1165 case ARM::LDRD_PRE: 1166 case ARM::LDRD_POST: 1167 if (Rt & 0x1) return Fail; 1168 break; 1169 default: 1170 break; 1171 } 1172 1173 if (writeback) { // Writeback 1174 if (P) 1175 U |= ARMII::IndexModePre << 9; 1176 else 1177 U |= ARMII::IndexModePost << 9; 1178 1179 // On stores, the writeback operand precedes Rt. 1180 switch (Inst.getOpcode()) { 1181 case ARM::STRD: 1182 case ARM::STRD_PRE: 1183 case ARM::STRD_POST: 1184 case ARM::STRH: 1185 case ARM::STRH_PRE: 1186 case ARM::STRH_POST: 1187 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1188 break; 1189 default: 1190 break; 1191 } 1192 } 1193 1194 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1195 switch (Inst.getOpcode()) { 1196 case ARM::STRD: 1197 case ARM::STRD_PRE: 1198 case ARM::STRD_POST: 1199 case ARM::LDRD: 1200 case ARM::LDRD_PRE: 1201 case ARM::LDRD_POST: 1202 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 1203 break; 1204 default: 1205 break; 1206 } 1207 1208 if (writeback) { 1209 // On loads, the writeback operand comes after Rt. 1210 switch (Inst.getOpcode()) { 1211 case ARM::LDRD: 1212 case ARM::LDRD_PRE: 1213 case ARM::LDRD_POST: 1214 case ARM::LDRH: 1215 case ARM::LDRH_PRE: 1216 case ARM::LDRH_POST: 1217 case ARM::LDRSH: 1218 case ARM::LDRSH_PRE: 1219 case ARM::LDRSH_POST: 1220 case ARM::LDRSB: 1221 case ARM::LDRSB_PRE: 1222 case ARM::LDRSB_POST: 1223 case ARM::LDRHTr: 1224 case ARM::LDRSBTr: 1225 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1226 break; 1227 default: 1228 break; 1229 } 1230 } 1231 1232 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1233 1234 if (type) { 1235 Inst.addOperand(MCOperand::CreateReg(0)); 1236 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1237 } else { 1238 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1239 Inst.addOperand(MCOperand::CreateImm(U)); 1240 } 1241 1242 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1243 1244 return S; 1245} 1246 1247static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1248 uint64_t Address, const void *Decoder) { 1249 DecodeStatus S = Success; 1250 1251 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1252 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1253 1254 switch (mode) { 1255 case 0: 1256 mode = ARM_AM::da; 1257 break; 1258 case 1: 1259 mode = ARM_AM::ia; 1260 break; 1261 case 2: 1262 mode = ARM_AM::db; 1263 break; 1264 case 3: 1265 mode = ARM_AM::ib; 1266 break; 1267 } 1268 1269 Inst.addOperand(MCOperand::CreateImm(mode)); 1270 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1271 1272 return S; 1273} 1274 1275static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1276 unsigned Insn, 1277 uint64_t Address, const void *Decoder) { 1278 DecodeStatus S = Success; 1279 1280 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1281 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1282 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1283 1284 if (pred == 0xF) { 1285 switch (Inst.getOpcode()) { 1286 case ARM::LDMDA: 1287 Inst.setOpcode(ARM::RFEDA); 1288 break; 1289 case ARM::LDMDA_UPD: 1290 Inst.setOpcode(ARM::RFEDA_UPD); 1291 break; 1292 case ARM::LDMDB: 1293 Inst.setOpcode(ARM::RFEDB); 1294 break; 1295 case ARM::LDMDB_UPD: 1296 Inst.setOpcode(ARM::RFEDB_UPD); 1297 break; 1298 case ARM::LDMIA: 1299 Inst.setOpcode(ARM::RFEIA); 1300 break; 1301 case ARM::LDMIA_UPD: 1302 Inst.setOpcode(ARM::RFEIA_UPD); 1303 break; 1304 case ARM::LDMIB: 1305 Inst.setOpcode(ARM::RFEIB); 1306 break; 1307 case ARM::LDMIB_UPD: 1308 Inst.setOpcode(ARM::RFEIB_UPD); 1309 break; 1310 case ARM::STMDA: 1311 Inst.setOpcode(ARM::SRSDA); 1312 break; 1313 case ARM::STMDA_UPD: 1314 Inst.setOpcode(ARM::SRSDA_UPD); 1315 break; 1316 case ARM::STMDB: 1317 Inst.setOpcode(ARM::SRSDB); 1318 break; 1319 case ARM::STMDB_UPD: 1320 Inst.setOpcode(ARM::SRSDB_UPD); 1321 break; 1322 case ARM::STMIA: 1323 Inst.setOpcode(ARM::SRSIA); 1324 break; 1325 case ARM::STMIA_UPD: 1326 Inst.setOpcode(ARM::SRSIA_UPD); 1327 break; 1328 case ARM::STMIB: 1329 Inst.setOpcode(ARM::SRSIB); 1330 break; 1331 case ARM::STMIB_UPD: 1332 Inst.setOpcode(ARM::SRSIB_UPD); 1333 break; 1334 default: 1335 CHECK(S, Fail); 1336 } 1337 1338 // For stores (which become SRS's, the only operand is the mode. 1339 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1340 Inst.addOperand( 1341 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1342 return S; 1343 } 1344 1345 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1346 } 1347 1348 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1349 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied 1350 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1351 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); 1352 1353 return S; 1354} 1355 1356static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1357 uint64_t Address, const void *Decoder) { 1358 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1359 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1360 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1361 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1362 1363 DecodeStatus S = Success; 1364 1365 // imod == '01' --> UNPREDICTABLE 1366 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1367 // return failure here. The '01' imod value is unprintable, so there's 1368 // nothing useful we could do even if we returned UNPREDICTABLE. 1369 1370 if (imod == 1) CHECK(S, Fail); 1371 1372 if (imod && M) { 1373 Inst.setOpcode(ARM::CPS3p); 1374 Inst.addOperand(MCOperand::CreateImm(imod)); 1375 Inst.addOperand(MCOperand::CreateImm(iflags)); 1376 Inst.addOperand(MCOperand::CreateImm(mode)); 1377 } else if (imod && !M) { 1378 Inst.setOpcode(ARM::CPS2p); 1379 Inst.addOperand(MCOperand::CreateImm(imod)); 1380 Inst.addOperand(MCOperand::CreateImm(iflags)); 1381 if (mode) CHECK(S, Unpredictable); 1382 } else if (!imod && M) { 1383 Inst.setOpcode(ARM::CPS1p); 1384 Inst.addOperand(MCOperand::CreateImm(mode)); 1385 if (iflags) CHECK(S, Unpredictable); 1386 } else { 1387 // imod == '00' && M == '0' --> UNPREDICTABLE 1388 Inst.setOpcode(ARM::CPS1p); 1389 Inst.addOperand(MCOperand::CreateImm(mode)); 1390 CHECK(S, Unpredictable); 1391 } 1392 1393 return S; 1394} 1395 1396static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1397 uint64_t Address, const void *Decoder) { 1398 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1399 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1400 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1401 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1402 1403 DecodeStatus S = Success; 1404 1405 // imod == '01' --> UNPREDICTABLE 1406 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1407 // return failure here. The '01' imod value is unprintable, so there's 1408 // nothing useful we could do even if we returned UNPREDICTABLE. 1409 1410 if (imod == 1) CHECK(S, Fail); 1411 1412 if (imod && M) { 1413 Inst.setOpcode(ARM::t2CPS3p); 1414 Inst.addOperand(MCOperand::CreateImm(imod)); 1415 Inst.addOperand(MCOperand::CreateImm(iflags)); 1416 Inst.addOperand(MCOperand::CreateImm(mode)); 1417 } else if (imod && !M) { 1418 Inst.setOpcode(ARM::t2CPS2p); 1419 Inst.addOperand(MCOperand::CreateImm(imod)); 1420 Inst.addOperand(MCOperand::CreateImm(iflags)); 1421 if (mode) CHECK(S, Unpredictable); 1422 } else if (!imod && M) { 1423 Inst.setOpcode(ARM::t2CPS1p); 1424 Inst.addOperand(MCOperand::CreateImm(mode)); 1425 if (iflags) CHECK(S, Unpredictable); 1426 } else { 1427 // imod == '00' && M == '0' --> UNPREDICTABLE 1428 Inst.setOpcode(ARM::t2CPS1p); 1429 Inst.addOperand(MCOperand::CreateImm(mode)); 1430 CHECK(S, Unpredictable); 1431 } 1432 1433 return S; 1434} 1435 1436 1437static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1438 uint64_t Address, const void *Decoder) { 1439 DecodeStatus S = Success; 1440 1441 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1442 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1443 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1444 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1445 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1446 1447 if (pred == 0xF) 1448 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1449 1450 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); 1451 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); 1452 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1453 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); 1454 1455 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1456 1457 return S; 1458} 1459 1460static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1461 uint64_t Address, const void *Decoder) { 1462 DecodeStatus S = Success; 1463 1464 unsigned add = fieldFromInstruction32(Val, 12, 1); 1465 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1466 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1467 1468 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1469 1470 if (!add) imm *= -1; 1471 if (imm == 0 && !add) imm = INT32_MIN; 1472 Inst.addOperand(MCOperand::CreateImm(imm)); 1473 1474 return S; 1475} 1476 1477static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1478 uint64_t Address, const void *Decoder) { 1479 DecodeStatus S = Success; 1480 1481 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1482 unsigned U = fieldFromInstruction32(Val, 8, 1); 1483 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1484 1485 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1486 1487 if (U) 1488 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1489 else 1490 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1491 1492 return S; 1493} 1494 1495static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1496 uint64_t Address, const void *Decoder) { 1497 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1498} 1499 1500static DecodeStatus 1501DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1502 uint64_t Address, const void *Decoder) { 1503 DecodeStatus S = Success; 1504 1505 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1506 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1507 1508 if (pred == 0xF) { 1509 Inst.setOpcode(ARM::BLXi); 1510 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1511 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1512 return S; 1513 } 1514 1515 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1516 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1517 1518 return S; 1519} 1520 1521 1522static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1523 uint64_t Address, const void *Decoder) { 1524 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1525 return Success; 1526} 1527 1528static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1529 uint64_t Address, const void *Decoder) { 1530 DecodeStatus S = Success; 1531 1532 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1533 unsigned align = fieldFromInstruction32(Val, 4, 2); 1534 1535 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1536 if (!align) 1537 Inst.addOperand(MCOperand::CreateImm(0)); 1538 else 1539 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1540 1541 return S; 1542} 1543 1544static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1545 uint64_t Address, const void *Decoder) { 1546 DecodeStatus S = Success; 1547 1548 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1549 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1550 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1551 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1552 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1553 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1554 1555 // First output register 1556 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1557 1558 // Second output register 1559 switch (Inst.getOpcode()) { 1560 case ARM::VLD1q8: 1561 case ARM::VLD1q16: 1562 case ARM::VLD1q32: 1563 case ARM::VLD1q64: 1564 case ARM::VLD1q8_UPD: 1565 case ARM::VLD1q16_UPD: 1566 case ARM::VLD1q32_UPD: 1567 case ARM::VLD1q64_UPD: 1568 case ARM::VLD1d8T: 1569 case ARM::VLD1d16T: 1570 case ARM::VLD1d32T: 1571 case ARM::VLD1d64T: 1572 case ARM::VLD1d8T_UPD: 1573 case ARM::VLD1d16T_UPD: 1574 case ARM::VLD1d32T_UPD: 1575 case ARM::VLD1d64T_UPD: 1576 case ARM::VLD1d8Q: 1577 case ARM::VLD1d16Q: 1578 case ARM::VLD1d32Q: 1579 case ARM::VLD1d64Q: 1580 case ARM::VLD1d8Q_UPD: 1581 case ARM::VLD1d16Q_UPD: 1582 case ARM::VLD1d32Q_UPD: 1583 case ARM::VLD1d64Q_UPD: 1584 case ARM::VLD2d8: 1585 case ARM::VLD2d16: 1586 case ARM::VLD2d32: 1587 case ARM::VLD2d8_UPD: 1588 case ARM::VLD2d16_UPD: 1589 case ARM::VLD2d32_UPD: 1590 case ARM::VLD2q8: 1591 case ARM::VLD2q16: 1592 case ARM::VLD2q32: 1593 case ARM::VLD2q8_UPD: 1594 case ARM::VLD2q16_UPD: 1595 case ARM::VLD2q32_UPD: 1596 case ARM::VLD3d8: 1597 case ARM::VLD3d16: 1598 case ARM::VLD3d32: 1599 case ARM::VLD3d8_UPD: 1600 case ARM::VLD3d16_UPD: 1601 case ARM::VLD3d32_UPD: 1602 case ARM::VLD4d8: 1603 case ARM::VLD4d16: 1604 case ARM::VLD4d32: 1605 case ARM::VLD4d8_UPD: 1606 case ARM::VLD4d16_UPD: 1607 case ARM::VLD4d32_UPD: 1608 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1609 break; 1610 case ARM::VLD2b8: 1611 case ARM::VLD2b16: 1612 case ARM::VLD2b32: 1613 case ARM::VLD2b8_UPD: 1614 case ARM::VLD2b16_UPD: 1615 case ARM::VLD2b32_UPD: 1616 case ARM::VLD3q8: 1617 case ARM::VLD3q16: 1618 case ARM::VLD3q32: 1619 case ARM::VLD3q8_UPD: 1620 case ARM::VLD3q16_UPD: 1621 case ARM::VLD3q32_UPD: 1622 case ARM::VLD4q8: 1623 case ARM::VLD4q16: 1624 case ARM::VLD4q32: 1625 case ARM::VLD4q8_UPD: 1626 case ARM::VLD4q16_UPD: 1627 case ARM::VLD4q32_UPD: 1628 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1629 default: 1630 break; 1631 } 1632 1633 // Third output register 1634 switch(Inst.getOpcode()) { 1635 case ARM::VLD1d8T: 1636 case ARM::VLD1d16T: 1637 case ARM::VLD1d32T: 1638 case ARM::VLD1d64T: 1639 case ARM::VLD1d8T_UPD: 1640 case ARM::VLD1d16T_UPD: 1641 case ARM::VLD1d32T_UPD: 1642 case ARM::VLD1d64T_UPD: 1643 case ARM::VLD1d8Q: 1644 case ARM::VLD1d16Q: 1645 case ARM::VLD1d32Q: 1646 case ARM::VLD1d64Q: 1647 case ARM::VLD1d8Q_UPD: 1648 case ARM::VLD1d16Q_UPD: 1649 case ARM::VLD1d32Q_UPD: 1650 case ARM::VLD1d64Q_UPD: 1651 case ARM::VLD2q8: 1652 case ARM::VLD2q16: 1653 case ARM::VLD2q32: 1654 case ARM::VLD2q8_UPD: 1655 case ARM::VLD2q16_UPD: 1656 case ARM::VLD2q32_UPD: 1657 case ARM::VLD3d8: 1658 case ARM::VLD3d16: 1659 case ARM::VLD3d32: 1660 case ARM::VLD3d8_UPD: 1661 case ARM::VLD3d16_UPD: 1662 case ARM::VLD3d32_UPD: 1663 case ARM::VLD4d8: 1664 case ARM::VLD4d16: 1665 case ARM::VLD4d32: 1666 case ARM::VLD4d8_UPD: 1667 case ARM::VLD4d16_UPD: 1668 case ARM::VLD4d32_UPD: 1669 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1670 break; 1671 case ARM::VLD3q8: 1672 case ARM::VLD3q16: 1673 case ARM::VLD3q32: 1674 case ARM::VLD3q8_UPD: 1675 case ARM::VLD3q16_UPD: 1676 case ARM::VLD3q32_UPD: 1677 case ARM::VLD4q8: 1678 case ARM::VLD4q16: 1679 case ARM::VLD4q32: 1680 case ARM::VLD4q8_UPD: 1681 case ARM::VLD4q16_UPD: 1682 case ARM::VLD4q32_UPD: 1683 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1684 break; 1685 default: 1686 break; 1687 } 1688 1689 // Fourth output register 1690 switch (Inst.getOpcode()) { 1691 case ARM::VLD1d8Q: 1692 case ARM::VLD1d16Q: 1693 case ARM::VLD1d32Q: 1694 case ARM::VLD1d64Q: 1695 case ARM::VLD1d8Q_UPD: 1696 case ARM::VLD1d16Q_UPD: 1697 case ARM::VLD1d32Q_UPD: 1698 case ARM::VLD1d64Q_UPD: 1699 case ARM::VLD2q8: 1700 case ARM::VLD2q16: 1701 case ARM::VLD2q32: 1702 case ARM::VLD2q8_UPD: 1703 case ARM::VLD2q16_UPD: 1704 case ARM::VLD2q32_UPD: 1705 case ARM::VLD4d8: 1706 case ARM::VLD4d16: 1707 case ARM::VLD4d32: 1708 case ARM::VLD4d8_UPD: 1709 case ARM::VLD4d16_UPD: 1710 case ARM::VLD4d32_UPD: 1711 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1712 break; 1713 case ARM::VLD4q8: 1714 case ARM::VLD4q16: 1715 case ARM::VLD4q32: 1716 case ARM::VLD4q8_UPD: 1717 case ARM::VLD4q16_UPD: 1718 case ARM::VLD4q32_UPD: 1719 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1720 break; 1721 default: 1722 break; 1723 } 1724 1725 // Writeback operand 1726 switch (Inst.getOpcode()) { 1727 case ARM::VLD1d8_UPD: 1728 case ARM::VLD1d16_UPD: 1729 case ARM::VLD1d32_UPD: 1730 case ARM::VLD1d64_UPD: 1731 case ARM::VLD1q8_UPD: 1732 case ARM::VLD1q16_UPD: 1733 case ARM::VLD1q32_UPD: 1734 case ARM::VLD1q64_UPD: 1735 case ARM::VLD1d8T_UPD: 1736 case ARM::VLD1d16T_UPD: 1737 case ARM::VLD1d32T_UPD: 1738 case ARM::VLD1d64T_UPD: 1739 case ARM::VLD1d8Q_UPD: 1740 case ARM::VLD1d16Q_UPD: 1741 case ARM::VLD1d32Q_UPD: 1742 case ARM::VLD1d64Q_UPD: 1743 case ARM::VLD2d8_UPD: 1744 case ARM::VLD2d16_UPD: 1745 case ARM::VLD2d32_UPD: 1746 case ARM::VLD2q8_UPD: 1747 case ARM::VLD2q16_UPD: 1748 case ARM::VLD2q32_UPD: 1749 case ARM::VLD2b8_UPD: 1750 case ARM::VLD2b16_UPD: 1751 case ARM::VLD2b32_UPD: 1752 case ARM::VLD3d8_UPD: 1753 case ARM::VLD3d16_UPD: 1754 case ARM::VLD3d32_UPD: 1755 case ARM::VLD3q8_UPD: 1756 case ARM::VLD3q16_UPD: 1757 case ARM::VLD3q32_UPD: 1758 case ARM::VLD4d8_UPD: 1759 case ARM::VLD4d16_UPD: 1760 case ARM::VLD4d32_UPD: 1761 case ARM::VLD4q8_UPD: 1762 case ARM::VLD4q16_UPD: 1763 case ARM::VLD4q32_UPD: 1764 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1765 break; 1766 default: 1767 break; 1768 } 1769 1770 // AddrMode6 Base (register+alignment) 1771 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1772 1773 // AddrMode6 Offset (register) 1774 if (Rm == 0xD) 1775 Inst.addOperand(MCOperand::CreateReg(0)); 1776 else if (Rm != 0xF) { 1777 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1778 } 1779 1780 return S; 1781} 1782 1783static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1784 uint64_t Address, const void *Decoder) { 1785 DecodeStatus S = Success; 1786 1787 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1788 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1789 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1790 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1791 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1792 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1793 1794 // Writeback Operand 1795 switch (Inst.getOpcode()) { 1796 case ARM::VST1d8_UPD: 1797 case ARM::VST1d16_UPD: 1798 case ARM::VST1d32_UPD: 1799 case ARM::VST1d64_UPD: 1800 case ARM::VST1q8_UPD: 1801 case ARM::VST1q16_UPD: 1802 case ARM::VST1q32_UPD: 1803 case ARM::VST1q64_UPD: 1804 case ARM::VST1d8T_UPD: 1805 case ARM::VST1d16T_UPD: 1806 case ARM::VST1d32T_UPD: 1807 case ARM::VST1d64T_UPD: 1808 case ARM::VST1d8Q_UPD: 1809 case ARM::VST1d16Q_UPD: 1810 case ARM::VST1d32Q_UPD: 1811 case ARM::VST1d64Q_UPD: 1812 case ARM::VST2d8_UPD: 1813 case ARM::VST2d16_UPD: 1814 case ARM::VST2d32_UPD: 1815 case ARM::VST2q8_UPD: 1816 case ARM::VST2q16_UPD: 1817 case ARM::VST2q32_UPD: 1818 case ARM::VST2b8_UPD: 1819 case ARM::VST2b16_UPD: 1820 case ARM::VST2b32_UPD: 1821 case ARM::VST3d8_UPD: 1822 case ARM::VST3d16_UPD: 1823 case ARM::VST3d32_UPD: 1824 case ARM::VST3q8_UPD: 1825 case ARM::VST3q16_UPD: 1826 case ARM::VST3q32_UPD: 1827 case ARM::VST4d8_UPD: 1828 case ARM::VST4d16_UPD: 1829 case ARM::VST4d32_UPD: 1830 case ARM::VST4q8_UPD: 1831 case ARM::VST4q16_UPD: 1832 case ARM::VST4q32_UPD: 1833 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1834 break; 1835 default: 1836 break; 1837 } 1838 1839 // AddrMode6 Base (register+alignment) 1840 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1841 1842 // AddrMode6 Offset (register) 1843 if (Rm == 0xD) 1844 Inst.addOperand(MCOperand::CreateReg(0)); 1845 else if (Rm != 0xF) { 1846 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1847 } 1848 1849 // First input register 1850 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1851 1852 // Second input register 1853 switch (Inst.getOpcode()) { 1854 case ARM::VST1q8: 1855 case ARM::VST1q16: 1856 case ARM::VST1q32: 1857 case ARM::VST1q64: 1858 case ARM::VST1q8_UPD: 1859 case ARM::VST1q16_UPD: 1860 case ARM::VST1q32_UPD: 1861 case ARM::VST1q64_UPD: 1862 case ARM::VST1d8T: 1863 case ARM::VST1d16T: 1864 case ARM::VST1d32T: 1865 case ARM::VST1d64T: 1866 case ARM::VST1d8T_UPD: 1867 case ARM::VST1d16T_UPD: 1868 case ARM::VST1d32T_UPD: 1869 case ARM::VST1d64T_UPD: 1870 case ARM::VST1d8Q: 1871 case ARM::VST1d16Q: 1872 case ARM::VST1d32Q: 1873 case ARM::VST1d64Q: 1874 case ARM::VST1d8Q_UPD: 1875 case ARM::VST1d16Q_UPD: 1876 case ARM::VST1d32Q_UPD: 1877 case ARM::VST1d64Q_UPD: 1878 case ARM::VST2d8: 1879 case ARM::VST2d16: 1880 case ARM::VST2d32: 1881 case ARM::VST2d8_UPD: 1882 case ARM::VST2d16_UPD: 1883 case ARM::VST2d32_UPD: 1884 case ARM::VST2q8: 1885 case ARM::VST2q16: 1886 case ARM::VST2q32: 1887 case ARM::VST2q8_UPD: 1888 case ARM::VST2q16_UPD: 1889 case ARM::VST2q32_UPD: 1890 case ARM::VST3d8: 1891 case ARM::VST3d16: 1892 case ARM::VST3d32: 1893 case ARM::VST3d8_UPD: 1894 case ARM::VST3d16_UPD: 1895 case ARM::VST3d32_UPD: 1896 case ARM::VST4d8: 1897 case ARM::VST4d16: 1898 case ARM::VST4d32: 1899 case ARM::VST4d8_UPD: 1900 case ARM::VST4d16_UPD: 1901 case ARM::VST4d32_UPD: 1902 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1903 break; 1904 case ARM::VST2b8: 1905 case ARM::VST2b16: 1906 case ARM::VST2b32: 1907 case ARM::VST2b8_UPD: 1908 case ARM::VST2b16_UPD: 1909 case ARM::VST2b32_UPD: 1910 case ARM::VST3q8: 1911 case ARM::VST3q16: 1912 case ARM::VST3q32: 1913 case ARM::VST3q8_UPD: 1914 case ARM::VST3q16_UPD: 1915 case ARM::VST3q32_UPD: 1916 case ARM::VST4q8: 1917 case ARM::VST4q16: 1918 case ARM::VST4q32: 1919 case ARM::VST4q8_UPD: 1920 case ARM::VST4q16_UPD: 1921 case ARM::VST4q32_UPD: 1922 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1923 break; 1924 default: 1925 break; 1926 } 1927 1928 // Third input register 1929 switch (Inst.getOpcode()) { 1930 case ARM::VST1d8T: 1931 case ARM::VST1d16T: 1932 case ARM::VST1d32T: 1933 case ARM::VST1d64T: 1934 case ARM::VST1d8T_UPD: 1935 case ARM::VST1d16T_UPD: 1936 case ARM::VST1d32T_UPD: 1937 case ARM::VST1d64T_UPD: 1938 case ARM::VST1d8Q: 1939 case ARM::VST1d16Q: 1940 case ARM::VST1d32Q: 1941 case ARM::VST1d64Q: 1942 case ARM::VST1d8Q_UPD: 1943 case ARM::VST1d16Q_UPD: 1944 case ARM::VST1d32Q_UPD: 1945 case ARM::VST1d64Q_UPD: 1946 case ARM::VST2q8: 1947 case ARM::VST2q16: 1948 case ARM::VST2q32: 1949 case ARM::VST2q8_UPD: 1950 case ARM::VST2q16_UPD: 1951 case ARM::VST2q32_UPD: 1952 case ARM::VST3d8: 1953 case ARM::VST3d16: 1954 case ARM::VST3d32: 1955 case ARM::VST3d8_UPD: 1956 case ARM::VST3d16_UPD: 1957 case ARM::VST3d32_UPD: 1958 case ARM::VST4d8: 1959 case ARM::VST4d16: 1960 case ARM::VST4d32: 1961 case ARM::VST4d8_UPD: 1962 case ARM::VST4d16_UPD: 1963 case ARM::VST4d32_UPD: 1964 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1965 break; 1966 case ARM::VST3q8: 1967 case ARM::VST3q16: 1968 case ARM::VST3q32: 1969 case ARM::VST3q8_UPD: 1970 case ARM::VST3q16_UPD: 1971 case ARM::VST3q32_UPD: 1972 case ARM::VST4q8: 1973 case ARM::VST4q16: 1974 case ARM::VST4q32: 1975 case ARM::VST4q8_UPD: 1976 case ARM::VST4q16_UPD: 1977 case ARM::VST4q32_UPD: 1978 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1979 break; 1980 default: 1981 break; 1982 } 1983 1984 // Fourth input register 1985 switch (Inst.getOpcode()) { 1986 case ARM::VST1d8Q: 1987 case ARM::VST1d16Q: 1988 case ARM::VST1d32Q: 1989 case ARM::VST1d64Q: 1990 case ARM::VST1d8Q_UPD: 1991 case ARM::VST1d16Q_UPD: 1992 case ARM::VST1d32Q_UPD: 1993 case ARM::VST1d64Q_UPD: 1994 case ARM::VST2q8: 1995 case ARM::VST2q16: 1996 case ARM::VST2q32: 1997 case ARM::VST2q8_UPD: 1998 case ARM::VST2q16_UPD: 1999 case ARM::VST2q32_UPD: 2000 case ARM::VST4d8: 2001 case ARM::VST4d16: 2002 case ARM::VST4d32: 2003 case ARM::VST4d8_UPD: 2004 case ARM::VST4d16_UPD: 2005 case ARM::VST4d32_UPD: 2006 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 2007 break; 2008 case ARM::VST4q8: 2009 case ARM::VST4q16: 2010 case ARM::VST4q32: 2011 case ARM::VST4q8_UPD: 2012 case ARM::VST4q16_UPD: 2013 case ARM::VST4q32_UPD: 2014 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 2015 break; 2016 default: 2017 break; 2018 } 2019 2020 return S; 2021} 2022 2023static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2024 uint64_t Address, const void *Decoder) { 2025 DecodeStatus S = Success; 2026 2027 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2028 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2029 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2030 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2031 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2032 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2033 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2034 2035 align *= (1 << size); 2036 2037 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2038 if (regs == 2) { 2039 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 2040 } 2041 if (Rm != 0xF) { 2042 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2043 } 2044 2045 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2046 Inst.addOperand(MCOperand::CreateImm(align)); 2047 2048 if (Rm == 0xD) 2049 Inst.addOperand(MCOperand::CreateReg(0)); 2050 else if (Rm != 0xF) { 2051 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2052 } 2053 2054 return S; 2055} 2056 2057static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2058 uint64_t Address, const void *Decoder) { 2059 DecodeStatus S = Success; 2060 2061 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2062 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2063 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2064 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2065 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2066 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2067 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2068 align *= 2*size; 2069 2070 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2071 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2072 if (Rm != 0xF) { 2073 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2074 } 2075 2076 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2077 Inst.addOperand(MCOperand::CreateImm(align)); 2078 2079 if (Rm == 0xD) 2080 Inst.addOperand(MCOperand::CreateReg(0)); 2081 else if (Rm != 0xF) { 2082 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2083 } 2084 2085 return S; 2086} 2087 2088static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2089 uint64_t Address, const void *Decoder) { 2090 DecodeStatus S = Success; 2091 2092 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2093 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2094 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2095 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2096 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2097 2098 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2099 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2100 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2101 if (Rm != 0xF) { 2102 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2103 } 2104 2105 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2106 Inst.addOperand(MCOperand::CreateImm(0)); 2107 2108 if (Rm == 0xD) 2109 Inst.addOperand(MCOperand::CreateReg(0)); 2110 else if (Rm != 0xF) { 2111 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2112 } 2113 2114 return S; 2115} 2116 2117static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2118 uint64_t Address, const void *Decoder) { 2119 DecodeStatus S = Success; 2120 2121 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2122 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2123 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2124 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2125 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2126 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2127 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2128 2129 if (size == 0x3) { 2130 size = 4; 2131 align = 16; 2132 } else { 2133 if (size == 2) { 2134 size = 1 << size; 2135 align *= 8; 2136 } else { 2137 size = 1 << size; 2138 align *= 4*size; 2139 } 2140 } 2141 2142 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2143 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2144 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2145 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); 2146 if (Rm != 0xF) { 2147 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2148 } 2149 2150 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2151 Inst.addOperand(MCOperand::CreateImm(align)); 2152 2153 if (Rm == 0xD) 2154 Inst.addOperand(MCOperand::CreateReg(0)); 2155 else if (Rm != 0xF) { 2156 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2157 } 2158 2159 return S; 2160} 2161 2162static DecodeStatus 2163DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2164 uint64_t Address, const void *Decoder) { 2165 DecodeStatus S = Success; 2166 2167 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2168 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2169 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2170 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2171 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2172 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2173 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2174 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2175 2176 if (Q) { 2177 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2178 } else { 2179 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2180 } 2181 2182 Inst.addOperand(MCOperand::CreateImm(imm)); 2183 2184 switch (Inst.getOpcode()) { 2185 case ARM::VORRiv4i16: 2186 case ARM::VORRiv2i32: 2187 case ARM::VBICiv4i16: 2188 case ARM::VBICiv2i32: 2189 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2190 break; 2191 case ARM::VORRiv8i16: 2192 case ARM::VORRiv4i32: 2193 case ARM::VBICiv8i16: 2194 case ARM::VBICiv4i32: 2195 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2196 break; 2197 default: 2198 break; 2199 } 2200 2201 return S; 2202} 2203 2204static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2205 uint64_t Address, const void *Decoder) { 2206 DecodeStatus S = Success; 2207 2208 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2209 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2210 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2211 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2212 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2213 2214 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2215 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2216 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2217 2218 return S; 2219} 2220 2221static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2222 uint64_t Address, const void *Decoder) { 2223 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2224 return Success; 2225} 2226 2227static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2228 uint64_t Address, const void *Decoder) { 2229 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2230 return Success; 2231} 2232 2233static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2234 uint64_t Address, const void *Decoder) { 2235 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2236 return Success; 2237} 2238 2239static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2240 uint64_t Address, const void *Decoder) { 2241 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2242 return Success; 2243} 2244 2245static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2246 uint64_t Address, const void *Decoder) { 2247 DecodeStatus S = Success; 2248 2249 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2250 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2251 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2252 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2253 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2254 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2255 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2256 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2257 2258 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2259 if (op) { 2260 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback 2261 } 2262 2263 for (unsigned i = 0; i < length; ++i) { 2264 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)); 2265 } 2266 2267 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2268 2269 return S; 2270} 2271 2272static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2273 uint64_t Address, const void *Decoder) { 2274 // The immediate needs to be a fully instantiated float. However, the 2275 // auto-generated decoder is only able to fill in some of the bits 2276 // necessary. For instance, the 'b' bit is replicated multiple times, 2277 // and is even present in inverted form in one bit. We do a little 2278 // binary parsing here to fill in those missing bits, and then 2279 // reinterpret it all as a float. 2280 union { 2281 uint32_t integer; 2282 float fp; 2283 } fp_conv; 2284 2285 fp_conv.integer = Val; 2286 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2287 fp_conv.integer |= b << 26; 2288 fp_conv.integer |= b << 27; 2289 fp_conv.integer |= b << 28; 2290 fp_conv.integer |= b << 29; 2291 fp_conv.integer |= (~b & 0x1) << 30; 2292 2293 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2294 return Success; 2295} 2296 2297static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2298 uint64_t Address, const void *Decoder) { 2299 DecodeStatus S = Success; 2300 2301 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2302 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2303 2304 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); 2305 2306 if (Inst.getOpcode() == ARM::tADR) 2307 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2308 else if (Inst.getOpcode() == ARM::tADDrSPi) 2309 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2310 else 2311 return Fail; 2312 2313 Inst.addOperand(MCOperand::CreateImm(imm)); 2314 return S; 2315} 2316 2317static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2318 uint64_t Address, const void *Decoder) { 2319 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2320 return Success; 2321} 2322 2323static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2324 uint64_t Address, const void *Decoder) { 2325 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2326 return Success; 2327} 2328 2329static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2330 uint64_t Address, const void *Decoder) { 2331 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2332 return Success; 2333} 2334 2335static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2336 uint64_t Address, const void *Decoder) { 2337 DecodeStatus S = Success; 2338 2339 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2340 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2341 2342 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2343 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); 2344 2345 return S; 2346} 2347 2348static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2349 uint64_t Address, const void *Decoder) { 2350 DecodeStatus S = Success; 2351 2352 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2353 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2354 2355 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2356 Inst.addOperand(MCOperand::CreateImm(imm)); 2357 2358 return S; 2359} 2360 2361static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2362 uint64_t Address, const void *Decoder) { 2363 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2364 2365 return Success; 2366} 2367 2368static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2369 uint64_t Address, const void *Decoder) { 2370 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2371 Inst.addOperand(MCOperand::CreateImm(Val)); 2372 2373 return Success; 2374} 2375 2376static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2377 uint64_t Address, const void *Decoder) { 2378 DecodeStatus S = Success; 2379 2380 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2381 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2382 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2383 2384 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2385 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); 2386 Inst.addOperand(MCOperand::CreateImm(imm)); 2387 2388 return S; 2389} 2390 2391static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2392 uint64_t Address, const void *Decoder) { 2393 DecodeStatus S = Success; 2394 2395 if (Inst.getOpcode() != ARM::t2PLDs) { 2396 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2397 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2398 } 2399 2400 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2401 if (Rn == 0xF) { 2402 switch (Inst.getOpcode()) { 2403 case ARM::t2LDRBs: 2404 Inst.setOpcode(ARM::t2LDRBpci); 2405 break; 2406 case ARM::t2LDRHs: 2407 Inst.setOpcode(ARM::t2LDRHpci); 2408 break; 2409 case ARM::t2LDRSHs: 2410 Inst.setOpcode(ARM::t2LDRSHpci); 2411 break; 2412 case ARM::t2LDRSBs: 2413 Inst.setOpcode(ARM::t2LDRSBpci); 2414 break; 2415 case ARM::t2PLDs: 2416 Inst.setOpcode(ARM::t2PLDi12); 2417 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2418 break; 2419 default: 2420 return Fail; 2421 } 2422 2423 int imm = fieldFromInstruction32(Insn, 0, 12); 2424 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2425 Inst.addOperand(MCOperand::CreateImm(imm)); 2426 2427 return S; 2428 } 2429 2430 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2431 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2432 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2433 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); 2434 2435 return S; 2436} 2437 2438static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2439 uint64_t Address, const void *Decoder) { 2440 int imm = Val & 0xFF; 2441 if (!(Val & 0x100)) imm *= -1; 2442 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2443 2444 return Success; 2445} 2446 2447static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2448 uint64_t Address, const void *Decoder) { 2449 DecodeStatus S = Success; 2450 2451 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2452 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2453 2454 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2455 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); 2456 2457 return S; 2458} 2459 2460static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2461 uint64_t Address, const void *Decoder) { 2462 int imm = Val & 0xFF; 2463 if (!(Val & 0x100)) imm *= -1; 2464 Inst.addOperand(MCOperand::CreateImm(imm)); 2465 2466 return Success; 2467} 2468 2469 2470static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2471 uint64_t Address, const void *Decoder) { 2472 DecodeStatus S = Success; 2473 2474 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2475 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2476 2477 // Some instructions always use an additive offset. 2478 switch (Inst.getOpcode()) { 2479 case ARM::t2LDRT: 2480 case ARM::t2LDRBT: 2481 case ARM::t2LDRHT: 2482 case ARM::t2LDRSBT: 2483 case ARM::t2LDRSHT: 2484 imm |= 0x100; 2485 break; 2486 default: 2487 break; 2488 } 2489 2490 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2491 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); 2492 2493 return S; 2494} 2495 2496 2497static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2498 uint64_t Address, const void *Decoder) { 2499 DecodeStatus S = Success; 2500 2501 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2502 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2503 2504 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2505 Inst.addOperand(MCOperand::CreateImm(imm)); 2506 2507 return S; 2508} 2509 2510 2511static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2512 uint64_t Address, const void *Decoder) { 2513 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2514 2515 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2516 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2517 Inst.addOperand(MCOperand::CreateImm(imm)); 2518 2519 return Success; 2520} 2521 2522static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2523 uint64_t Address, const void *Decoder) { 2524 DecodeStatus S = Success; 2525 2526 if (Inst.getOpcode() == ARM::tADDrSP) { 2527 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2528 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2529 2530 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2531 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2532 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2533 } else if (Inst.getOpcode() == ARM::tADDspr) { 2534 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2535 2536 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2537 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2538 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2539 } 2540 2541 return S; 2542} 2543 2544static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2545 uint64_t Address, const void *Decoder) { 2546 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2547 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2548 2549 Inst.addOperand(MCOperand::CreateImm(imod)); 2550 Inst.addOperand(MCOperand::CreateImm(flags)); 2551 2552 return Success; 2553} 2554 2555static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2556 uint64_t Address, const void *Decoder) { 2557 DecodeStatus S = Success; 2558 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2559 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2560 2561 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; 2562 Inst.addOperand(MCOperand::CreateImm(add)); 2563 2564 return S; 2565} 2566 2567static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2568 uint64_t Address, const void *Decoder) { 2569 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2570 return Success; 2571} 2572 2573static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2574 uint64_t Address, const void *Decoder) { 2575 if (Val == 0xA || Val == 0xB) 2576 return Fail; 2577 2578 Inst.addOperand(MCOperand::CreateImm(Val)); 2579 return Success; 2580} 2581 2582static DecodeStatus 2583DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2584 uint64_t Address, const void *Decoder) { 2585 DecodeStatus S = Success; 2586 2587 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2588 if (pred == 0xE || pred == 0xF) { 2589 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2590 switch (opc) { 2591 default: 2592 return Fail; 2593 case 0: 2594 Inst.setOpcode(ARM::t2DSB); 2595 break; 2596 case 1: 2597 Inst.setOpcode(ARM::t2DMB); 2598 break; 2599 case 2: 2600 Inst.setOpcode(ARM::t2ISB); 2601 return Success; 2602 } 2603 2604 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2605 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2606 } 2607 2608 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2609 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2610 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2611 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2612 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2613 2614 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); 2615 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2616 2617 return S; 2618} 2619 2620// Decode a shifted immediate operand. These basically consist 2621// of an 8-bit value, and a 4-bit directive that specifies either 2622// a splat operation or a rotation. 2623static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2624 uint64_t Address, const void *Decoder) { 2625 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2626 if (ctrl == 0) { 2627 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2628 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2629 switch (byte) { 2630 case 0: 2631 Inst.addOperand(MCOperand::CreateImm(imm)); 2632 break; 2633 case 1: 2634 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2635 break; 2636 case 2: 2637 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2638 break; 2639 case 3: 2640 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2641 (imm << 8) | imm)); 2642 break; 2643 } 2644 } else { 2645 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2646 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2647 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2648 Inst.addOperand(MCOperand::CreateImm(imm)); 2649 } 2650 2651 return Success; 2652} 2653 2654static DecodeStatus 2655DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2656 uint64_t Address, const void *Decoder){ 2657 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2658 return Success; 2659} 2660 2661static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2662 uint64_t Address, const void *Decoder){ 2663 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2664 return Success; 2665} 2666 2667static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2668 uint64_t Address, const void *Decoder) { 2669 switch (Val) { 2670 default: 2671 return Fail; 2672 case 0xF: // SY 2673 case 0xE: // ST 2674 case 0xB: // ISH 2675 case 0xA: // ISHST 2676 case 0x7: // NSH 2677 case 0x6: // NSHST 2678 case 0x3: // OSH 2679 case 0x2: // OSHST 2680 break; 2681 } 2682 2683 Inst.addOperand(MCOperand::CreateImm(Val)); 2684 return Success; 2685} 2686 2687static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2688 uint64_t Address, const void *Decoder) { 2689 if (!Val) return Fail; 2690 Inst.addOperand(MCOperand::CreateImm(Val)); 2691 return Success; 2692} 2693 2694static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2695 uint64_t Address, const void *Decoder) { 2696 DecodeStatus S = Success; 2697 2698 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2699 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2700 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2701 2702 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2703 2704 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2705 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2706 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2707 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2708 2709 return S; 2710} 2711 2712 2713static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2714 uint64_t Address, const void *Decoder){ 2715 DecodeStatus S = Success; 2716 2717 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2718 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2719 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2720 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2721 2722 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); 2723 2724 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2725 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; 2726 2727 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2728 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2729 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2730 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2731 2732 return S; 2733} 2734 2735static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2736 uint64_t Address, const void *Decoder) { 2737 DecodeStatus S = Success; 2738 2739 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2740 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2741 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2742 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2743 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2744 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2745 2746 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2747 2748 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2749 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2750 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); 2751 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2752 2753 return S; 2754} 2755 2756static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2757 uint64_t Address, const void *Decoder) { 2758 DecodeStatus S = Success; 2759 2760 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2761 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2762 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2763 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2764 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2765 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2766 2767 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2768 2769 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2770 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2771 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); 2772 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2773 2774 return S; 2775} 2776 2777static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2778 uint64_t Address, const void *Decoder) { 2779 DecodeStatus S = Success; 2780 2781 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2782 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2783 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2784 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2785 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2786 2787 unsigned align = 0; 2788 unsigned index = 0; 2789 switch (size) { 2790 default: 2791 return Fail; 2792 case 0: 2793 if (fieldFromInstruction32(Insn, 4, 1)) 2794 return Fail; // UNDEFINED 2795 index = fieldFromInstruction32(Insn, 5, 3); 2796 break; 2797 case 1: 2798 if (fieldFromInstruction32(Insn, 5, 1)) 2799 return Fail; // UNDEFINED 2800 index = fieldFromInstruction32(Insn, 6, 2); 2801 if (fieldFromInstruction32(Insn, 4, 1)) 2802 align = 2; 2803 break; 2804 case 2: 2805 if (fieldFromInstruction32(Insn, 6, 1)) 2806 return Fail; // UNDEFINED 2807 index = fieldFromInstruction32(Insn, 7, 1); 2808 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2809 align = 4; 2810 } 2811 2812 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2813 if (Rm != 0xF) { // Writeback 2814 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2815 } 2816 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2817 Inst.addOperand(MCOperand::CreateImm(align)); 2818 if (Rm != 0xF) { 2819 if (Rm != 0xD) 2820 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2821 else 2822 Inst.addOperand(MCOperand::CreateReg(0)); 2823 } 2824 2825 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2826 Inst.addOperand(MCOperand::CreateImm(index)); 2827 2828 return S; 2829} 2830 2831static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2832 uint64_t Address, const void *Decoder) { 2833 DecodeStatus S = Success; 2834 2835 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2836 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2837 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2838 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2839 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2840 2841 unsigned align = 0; 2842 unsigned index = 0; 2843 switch (size) { 2844 default: 2845 return Fail; 2846 case 0: 2847 if (fieldFromInstruction32(Insn, 4, 1)) 2848 return Fail; // UNDEFINED 2849 index = fieldFromInstruction32(Insn, 5, 3); 2850 break; 2851 case 1: 2852 if (fieldFromInstruction32(Insn, 5, 1)) 2853 return Fail; // UNDEFINED 2854 index = fieldFromInstruction32(Insn, 6, 2); 2855 if (fieldFromInstruction32(Insn, 4, 1)) 2856 align = 2; 2857 break; 2858 case 2: 2859 if (fieldFromInstruction32(Insn, 6, 1)) 2860 return Fail; // UNDEFINED 2861 index = fieldFromInstruction32(Insn, 7, 1); 2862 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2863 align = 4; 2864 } 2865 2866 if (Rm != 0xF) { // Writeback 2867 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2868 } 2869 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2870 Inst.addOperand(MCOperand::CreateImm(align)); 2871 if (Rm != 0xF) { 2872 if (Rm != 0xD) 2873 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2874 else 2875 Inst.addOperand(MCOperand::CreateReg(0)); 2876 } 2877 2878 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2879 Inst.addOperand(MCOperand::CreateImm(index)); 2880 2881 return S; 2882} 2883 2884 2885static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2886 uint64_t Address, const void *Decoder) { 2887 DecodeStatus S = Success; 2888 2889 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2890 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2891 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2892 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2893 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2894 2895 unsigned align = 0; 2896 unsigned index = 0; 2897 unsigned inc = 1; 2898 switch (size) { 2899 default: 2900 return Fail; 2901 case 0: 2902 index = fieldFromInstruction32(Insn, 5, 3); 2903 if (fieldFromInstruction32(Insn, 4, 1)) 2904 align = 2; 2905 break; 2906 case 1: 2907 index = fieldFromInstruction32(Insn, 6, 2); 2908 if (fieldFromInstruction32(Insn, 4, 1)) 2909 align = 4; 2910 if (fieldFromInstruction32(Insn, 5, 1)) 2911 inc = 2; 2912 break; 2913 case 2: 2914 if (fieldFromInstruction32(Insn, 5, 1)) 2915 return Fail; // UNDEFINED 2916 index = fieldFromInstruction32(Insn, 7, 1); 2917 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2918 align = 8; 2919 if (fieldFromInstruction32(Insn, 6, 1)) 2920 inc = 2; 2921 break; 2922 } 2923 2924 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2925 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2926 if (Rm != 0xF) { // Writeback 2927 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2928 } 2929 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2930 Inst.addOperand(MCOperand::CreateImm(align)); 2931 if (Rm != 0xF) { 2932 if (Rm != 0xD) 2933 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2934 else 2935 Inst.addOperand(MCOperand::CreateReg(0)); 2936 } 2937 2938 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2939 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2940 Inst.addOperand(MCOperand::CreateImm(index)); 2941 2942 return S; 2943} 2944 2945static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2946 uint64_t Address, const void *Decoder) { 2947 DecodeStatus S = Success; 2948 2949 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2950 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2951 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2952 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2953 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2954 2955 unsigned align = 0; 2956 unsigned index = 0; 2957 unsigned inc = 1; 2958 switch (size) { 2959 default: 2960 return Fail; 2961 case 0: 2962 index = fieldFromInstruction32(Insn, 5, 3); 2963 if (fieldFromInstruction32(Insn, 4, 1)) 2964 align = 2; 2965 break; 2966 case 1: 2967 index = fieldFromInstruction32(Insn, 6, 2); 2968 if (fieldFromInstruction32(Insn, 4, 1)) 2969 align = 4; 2970 if (fieldFromInstruction32(Insn, 5, 1)) 2971 inc = 2; 2972 break; 2973 case 2: 2974 if (fieldFromInstruction32(Insn, 5, 1)) 2975 return Fail; // UNDEFINED 2976 index = fieldFromInstruction32(Insn, 7, 1); 2977 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2978 align = 8; 2979 if (fieldFromInstruction32(Insn, 6, 1)) 2980 inc = 2; 2981 break; 2982 } 2983 2984 if (Rm != 0xF) { // Writeback 2985 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2986 } 2987 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2988 Inst.addOperand(MCOperand::CreateImm(align)); 2989 if (Rm != 0xF) { 2990 if (Rm != 0xD) 2991 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2992 else 2993 Inst.addOperand(MCOperand::CreateReg(0)); 2994 } 2995 2996 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2997 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2998 Inst.addOperand(MCOperand::CreateImm(index)); 2999 3000 return S; 3001} 3002 3003 3004static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3005 uint64_t Address, const void *Decoder) { 3006 DecodeStatus S = Success; 3007 3008 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3009 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3010 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3011 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3012 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3013 3014 unsigned align = 0; 3015 unsigned index = 0; 3016 unsigned inc = 1; 3017 switch (size) { 3018 default: 3019 return Fail; 3020 case 0: 3021 if (fieldFromInstruction32(Insn, 4, 1)) 3022 return Fail; // UNDEFINED 3023 index = fieldFromInstruction32(Insn, 5, 3); 3024 break; 3025 case 1: 3026 if (fieldFromInstruction32(Insn, 4, 1)) 3027 return Fail; // UNDEFINED 3028 index = fieldFromInstruction32(Insn, 6, 2); 3029 if (fieldFromInstruction32(Insn, 5, 1)) 3030 inc = 2; 3031 break; 3032 case 2: 3033 if (fieldFromInstruction32(Insn, 4, 2)) 3034 return Fail; // UNDEFINED 3035 index = fieldFromInstruction32(Insn, 7, 1); 3036 if (fieldFromInstruction32(Insn, 6, 1)) 3037 inc = 2; 3038 break; 3039 } 3040 3041 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3042 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3043 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3044 3045 if (Rm != 0xF) { // Writeback 3046 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3047 } 3048 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3049 Inst.addOperand(MCOperand::CreateImm(align)); 3050 if (Rm != 0xF) { 3051 if (Rm != 0xD) 3052 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3053 else 3054 Inst.addOperand(MCOperand::CreateReg(0)); 3055 } 3056 3057 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3058 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3059 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3060 Inst.addOperand(MCOperand::CreateImm(index)); 3061 3062 return S; 3063} 3064 3065static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3066 uint64_t Address, const void *Decoder) { 3067 DecodeStatus S = Success; 3068 3069 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3070 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3071 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3072 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3073 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3074 3075 unsigned align = 0; 3076 unsigned index = 0; 3077 unsigned inc = 1; 3078 switch (size) { 3079 default: 3080 return Fail; 3081 case 0: 3082 if (fieldFromInstruction32(Insn, 4, 1)) 3083 return Fail; // UNDEFINED 3084 index = fieldFromInstruction32(Insn, 5, 3); 3085 break; 3086 case 1: 3087 if (fieldFromInstruction32(Insn, 4, 1)) 3088 return Fail; // UNDEFINED 3089 index = fieldFromInstruction32(Insn, 6, 2); 3090 if (fieldFromInstruction32(Insn, 5, 1)) 3091 inc = 2; 3092 break; 3093 case 2: 3094 if (fieldFromInstruction32(Insn, 4, 2)) 3095 return Fail; // UNDEFINED 3096 index = fieldFromInstruction32(Insn, 7, 1); 3097 if (fieldFromInstruction32(Insn, 6, 1)) 3098 inc = 2; 3099 break; 3100 } 3101 3102 if (Rm != 0xF) { // Writeback 3103 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3104 } 3105 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3106 Inst.addOperand(MCOperand::CreateImm(align)); 3107 if (Rm != 0xF) { 3108 if (Rm != 0xD) 3109 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3110 else 3111 Inst.addOperand(MCOperand::CreateReg(0)); 3112 } 3113 3114 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3115 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3116 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3117 Inst.addOperand(MCOperand::CreateImm(index)); 3118 3119 return S; 3120} 3121 3122 3123static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3124 uint64_t Address, const void *Decoder) { 3125 DecodeStatus S = Success; 3126 3127 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3128 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3129 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3130 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3131 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3132 3133 unsigned align = 0; 3134 unsigned index = 0; 3135 unsigned inc = 1; 3136 switch (size) { 3137 default: 3138 return Fail; 3139 case 0: 3140 if (fieldFromInstruction32(Insn, 4, 1)) 3141 align = 4; 3142 index = fieldFromInstruction32(Insn, 5, 3); 3143 break; 3144 case 1: 3145 if (fieldFromInstruction32(Insn, 4, 1)) 3146 align = 8; 3147 index = fieldFromInstruction32(Insn, 6, 2); 3148 if (fieldFromInstruction32(Insn, 5, 1)) 3149 inc = 2; 3150 break; 3151 case 2: 3152 if (fieldFromInstruction32(Insn, 4, 2)) 3153 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3154 index = fieldFromInstruction32(Insn, 7, 1); 3155 if (fieldFromInstruction32(Insn, 6, 1)) 3156 inc = 2; 3157 break; 3158 } 3159 3160 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3161 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3162 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3163 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3164 3165 if (Rm != 0xF) { // Writeback 3166 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3167 } 3168 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3169 Inst.addOperand(MCOperand::CreateImm(align)); 3170 if (Rm != 0xF) { 3171 if (Rm != 0xD) 3172 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3173 else 3174 Inst.addOperand(MCOperand::CreateReg(0)); 3175 } 3176 3177 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3178 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3179 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3180 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3181 Inst.addOperand(MCOperand::CreateImm(index)); 3182 3183 return S; 3184} 3185 3186static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3187 uint64_t Address, const void *Decoder) { 3188 DecodeStatus S = Success; 3189 3190 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3191 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3192 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3193 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3194 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3195 3196 unsigned align = 0; 3197 unsigned index = 0; 3198 unsigned inc = 1; 3199 switch (size) { 3200 default: 3201 return Fail; 3202 case 0: 3203 if (fieldFromInstruction32(Insn, 4, 1)) 3204 align = 4; 3205 index = fieldFromInstruction32(Insn, 5, 3); 3206 break; 3207 case 1: 3208 if (fieldFromInstruction32(Insn, 4, 1)) 3209 align = 8; 3210 index = fieldFromInstruction32(Insn, 6, 2); 3211 if (fieldFromInstruction32(Insn, 5, 1)) 3212 inc = 2; 3213 break; 3214 case 2: 3215 if (fieldFromInstruction32(Insn, 4, 2)) 3216 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3217 index = fieldFromInstruction32(Insn, 7, 1); 3218 if (fieldFromInstruction32(Insn, 6, 1)) 3219 inc = 2; 3220 break; 3221 } 3222 3223 if (Rm != 0xF) { // Writeback 3224 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3225 } 3226 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3227 Inst.addOperand(MCOperand::CreateImm(align)); 3228 if (Rm != 0xF) { 3229 if (Rm != 0xD) 3230 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3231 else 3232 Inst.addOperand(MCOperand::CreateReg(0)); 3233 } 3234 3235 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3236 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3237 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3238 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3239 Inst.addOperand(MCOperand::CreateImm(index)); 3240 3241 return S; 3242} 3243 3244static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3245 uint64_t Address, const void *Decoder) { 3246 DecodeStatus S = Success; 3247 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3248 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3249 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3250 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3251 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3252 3253 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3254 CHECK(S, Unpredictable); 3255 3256 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)); 3257 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)); 3258 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)); 3259 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)); 3260 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 3261 3262 return S; 3263} 3264 3265static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3266 uint64_t Address, const void *Decoder) { 3267 DecodeStatus S = Success; 3268 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3269 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3270 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3271 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3272 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3273 3274 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3275 CHECK(S, Unpredictable); 3276 3277 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)); 3278 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)); 3279 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)); 3280 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)); 3281 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 3282 3283 return S; 3284} 3285 3286