ARMDisassembler.cpp revision 7cdbf086e4676494fc6a5b26c169285ae0bb740b
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "ARMDisassembler.h" 13#include "ARM.h" 14#include "ARMRegisterInfo.h" 15#include "MCTargetDesc/ARMAddressingModes.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "llvm/MC/EDInstInfo.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCContext.h" 21#include "llvm/Target/TargetRegistry.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/MemoryObject.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/raw_ostream.h" 26 27// Forward declare these because the autogenerated code will reference them. 28// Definitions are further down. 29static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 137 uint64_t Address, const void *Decoder); 138static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 139 uint64_t Address, const void *Decoder); 140static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 145 uint64_t Address, const void *Decoder); 146 147 148static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 149 uint64_t Address, const void *Decoder); 150static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 151 uint64_t Address, const void *Decoder); 152static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 153 uint64_t Address, const void *Decoder); 154static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 155 uint64_t Address, const void *Decoder); 156static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 157 uint64_t Address, const void *Decoder); 158static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 159 uint64_t Address, const void *Decoder); 160static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 161 uint64_t Address, const void *Decoder); 162static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 163 uint64_t Address, const void *Decoder); 164static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 167 uint64_t Address, const void *Decoder); 168static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 169 uint64_t Address, const void *Decoder); 170static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 171 uint64_t Address, const void *Decoder); 172static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 173 uint64_t Address, const void *Decoder); 174static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 177 uint64_t Address, const void *Decoder); 178static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 179 uint64_t Address, const void *Decoder); 180static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 181 uint64_t Address, const void *Decoder); 182static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 183 uint64_t Address, const void *Decoder); 184static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 197#include "ARMGenDisassemblerTables.inc" 198#include "ARMGenInstrInfo.inc" 199#include "ARMGenEDInfo.inc" 200 201using namespace llvm; 202 203static MCDisassembler *createARMDisassembler(const Target &T) { 204 return new ARMDisassembler; 205} 206 207static MCDisassembler *createThumbDisassembler(const Target &T) { 208 return new ThumbDisassembler; 209} 210 211EDInstInfo *ARMDisassembler::getEDInfo() const { 212 return instInfoARM; 213} 214 215EDInstInfo *ThumbDisassembler::getEDInfo() const { 216 return instInfoARM; 217} 218 219 220bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 221 const MemoryObject &Region, 222 uint64_t Address,raw_ostream &os) const { 223 uint8_t bytes[4]; 224 225 // We want to read exactly 4 bytes of data. 226 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 227 return false; 228 229 // Encoded as a small-endian 32-bit word in the stream. 230 uint32_t insn = (bytes[3] << 24) | 231 (bytes[2] << 16) | 232 (bytes[1] << 8) | 233 (bytes[0] << 0); 234 235 // Calling the auto-generated decoder function. 236 bool result = decodeARMInstruction32(MI, insn, Address, this); 237 if (result) { 238 Size = 4; 239 return true; 240 } 241 242 // Instructions that are shared between ARM and Thumb modes. 243 // FIXME: This shouldn't really exist. It's an artifact of the 244 // fact that we fail to encode a few instructions properly for Thumb. 245 MI.clear(); 246 result = decodeCommonInstruction32(MI, insn, Address, this); 247 if (result) { 248 Size = 4; 249 return true; 250 } 251 252 // VFP and NEON instructions, similarly, are shared between ARM 253 // and Thumb modes. 254 MI.clear(); 255 result = decodeVFPInstruction32(MI, insn, Address, this); 256 if (result) { 257 Size = 4; 258 return true; 259 } 260 261 MI.clear(); 262 result = decodeNEONDataInstruction32(MI, insn, Address, this); 263 if (result) { 264 Size = 4; 265 // Add a fake predicate operand, because we share these instruction 266 // definitions with Thumb2 where these instructions are predicable. 267 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 268 return true; 269 } 270 271 MI.clear(); 272 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 273 if (result) { 274 Size = 4; 275 // Add a fake predicate operand, because we share these instruction 276 // definitions with Thumb2 where these instructions are predicable. 277 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 278 return true; 279 } 280 281 MI.clear(); 282 result = decodeNEONDupInstruction32(MI, insn, Address, this); 283 if (result) { 284 Size = 4; 285 // Add a fake predicate operand, because we share these instruction 286 // definitions with Thumb2 where these instructions are predicable. 287 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 288 return true; 289 } 290 291 MI.clear(); 292 293 return false; 294} 295 296namespace llvm { 297extern MCInstrDesc ARMInsts[]; 298} 299 300// Thumb1 instructions don't have explicit S bits. Rather, they 301// implicitly set CPSR. Since it's not represented in the encoding, the 302// auto-generated decoder won't inject the CPSR operand. We need to fix 303// that as a post-pass. 304static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 305 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 306 MCInst::iterator I = MI.begin(); 307 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 308 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 309 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 310 return; 311 } 312 } 313 314 if (OpInfo[MI.size()].isOptionalDef() && 315 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 316 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 317} 318 319// Most Thumb instructions don't have explicit predicates in the 320// encoding, but rather get their predicates from IT context. We need 321// to fix up the predicate operands using this context information as a 322// post-pass. 323void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 324 // A few instructions actually have predicates encoded in them. Don't 325 // try to overwrite it if we're seeing one of those. 326 switch (MI.getOpcode()) { 327 case ARM::tBcc: 328 case ARM::t2Bcc: 329 return; 330 default: 331 break; 332 } 333 334 // If we're in an IT block, base the predicate on that. Otherwise, 335 // assume a predicate of AL. 336 unsigned CC; 337 if (!ITBlock.empty()) { 338 CC = ITBlock.back(); 339 ITBlock.pop_back(); 340 } else 341 CC = ARMCC::AL; 342 343 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 344 MCInst::iterator I = MI.begin(); 345 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 346 if (OpInfo[i].isPredicate()) { 347 I = MI.insert(I, MCOperand::CreateImm(CC)); 348 ++I; 349 if (CC == ARMCC::AL) 350 MI.insert(I, MCOperand::CreateReg(0)); 351 else 352 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 353 return; 354 } 355 } 356 357 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 358 if (CC == ARMCC::AL) 359 MI.insert(MI.end(), MCOperand::CreateReg(0)); 360 else 361 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 362} 363 364// Thumb VFP instructions are a special case. Because we share their 365// encodings between ARM and Thumb modes, and they are predicable in ARM 366// mode, the auto-generated decoder will give them an (incorrect) 367// predicate operand. We need to rewrite these operands based on the IT 368// context as a post-pass. 369void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 370 unsigned CC; 371 if (!ITBlock.empty()) { 372 CC = ITBlock.back(); 373 ITBlock.pop_back(); 374 } else 375 CC = ARMCC::AL; 376 377 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 378 MCInst::iterator I = MI.begin(); 379 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 380 if (OpInfo[i].isPredicate() ) { 381 I->setImm(CC); 382 ++I; 383 if (CC == ARMCC::AL) 384 I->setReg(0); 385 else 386 I->setReg(ARM::CPSR); 387 return; 388 } 389 } 390} 391 392 393bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 394 const MemoryObject &Region, 395 uint64_t Address,raw_ostream &os) const { 396 uint8_t bytes[4]; 397 398 // We want to read exactly 2 bytes of data. 399 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 400 return false; 401 402 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 403 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 404 if (result) { 405 Size = 2; 406 bool InITBlock = !ITBlock.empty(); 407 AddThumbPredicate(MI); 408 AddThumb1SBit(MI, InITBlock); 409 return true; 410 } 411 412 MI.clear(); 413 result = decodeThumb2Instruction16(MI, insn16, Address, this); 414 if (result) { 415 Size = 2; 416 AddThumbPredicate(MI); 417 418 // If we find an IT instruction, we need to parse its condition 419 // code and mask operands so that we can apply them correctly 420 // to the subsequent instructions. 421 if (MI.getOpcode() == ARM::t2IT) { 422 unsigned firstcond = MI.getOperand(0).getImm(); 423 uint32_t mask = MI.getOperand(1).getImm(); 424 unsigned zeros = CountTrailingZeros_32(mask); 425 mask >>= zeros+1; 426 427 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 428 if (firstcond ^ (mask & 1)) 429 ITBlock.push_back(firstcond ^ 1); 430 else 431 ITBlock.push_back(firstcond); 432 mask >>= 1; 433 } 434 ITBlock.push_back(firstcond); 435 } 436 437 return true; 438 } 439 440 // We want to read exactly 4 bytes of data. 441 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 442 return false; 443 444 uint32_t insn32 = (bytes[3] << 8) | 445 (bytes[2] << 0) | 446 (bytes[1] << 24) | 447 (bytes[0] << 16); 448 MI.clear(); 449 result = decodeThumbInstruction32(MI, insn32, Address, this); 450 if (result) { 451 Size = 4; 452 bool InITBlock = ITBlock.size(); 453 AddThumbPredicate(MI); 454 AddThumb1SBit(MI, InITBlock); 455 return true; 456 } 457 458 MI.clear(); 459 result = decodeThumb2Instruction32(MI, insn32, Address, this); 460 if (result) { 461 Size = 4; 462 AddThumbPredicate(MI); 463 return true; 464 } 465 466 MI.clear(); 467 result = decodeCommonInstruction32(MI, insn32, Address, this); 468 if (result) { 469 Size = 4; 470 AddThumbPredicate(MI); 471 return true; 472 } 473 474 MI.clear(); 475 result = decodeVFPInstruction32(MI, insn32, Address, this); 476 if (result) { 477 Size = 4; 478 UpdateThumbVFPPredicate(MI); 479 return true; 480 } 481 482 MI.clear(); 483 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 484 uint32_t NEONDataInsn = insn32; 485 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 486 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 487 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 488 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 489 if (result) { 490 Size = 4; 491 AddThumbPredicate(MI); 492 return true; 493 } 494 } 495 496 MI.clear(); 497 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); 498 if (result) { 499 Size = 4; 500 AddThumbPredicate(MI); 501 return true; 502 } 503 504 MI.clear(); 505 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 506 if (result) { 507 Size = 4; 508 AddThumbPredicate(MI); 509 return true; 510 } 511 512 return false; 513} 514 515 516extern "C" void LLVMInitializeARMDisassembler() { 517 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 518 createARMDisassembler); 519 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 520 createThumbDisassembler); 521} 522 523static const unsigned GPRDecoderTable[] = { 524 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 525 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 526 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 527 ARM::R12, ARM::SP, ARM::LR, ARM::PC 528}; 529 530static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 531 uint64_t Address, const void *Decoder) { 532 if (RegNo > 15) 533 return false; 534 535 unsigned Register = GPRDecoderTable[RegNo]; 536 Inst.addOperand(MCOperand::CreateReg(Register)); 537 return true; 538} 539 540static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 541 uint64_t Address, const void *Decoder) { 542 if (RegNo == 15) return false; 543 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 544} 545 546static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 547 uint64_t Address, const void *Decoder) { 548 if (RegNo > 7) 549 return false; 550 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 551} 552 553static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 554 uint64_t Address, const void *Decoder) { 555 unsigned Register = 0; 556 switch (RegNo) { 557 case 0: 558 Register = ARM::R0; 559 break; 560 case 1: 561 Register = ARM::R1; 562 break; 563 case 2: 564 Register = ARM::R2; 565 break; 566 case 3: 567 Register = ARM::R3; 568 break; 569 case 9: 570 Register = ARM::R9; 571 break; 572 case 12: 573 Register = ARM::R12; 574 break; 575 default: 576 return false; 577 } 578 579 Inst.addOperand(MCOperand::CreateReg(Register)); 580 return true; 581} 582 583static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 584 uint64_t Address, const void *Decoder) { 585 if (RegNo == 13 || RegNo == 15) return false; 586 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 587} 588 589static const unsigned SPRDecoderTable[] = { 590 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 591 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 592 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 593 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 594 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 595 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 596 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 597 ARM::S28, ARM::S29, ARM::S30, ARM::S31 598}; 599 600static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 601 uint64_t Address, const void *Decoder) { 602 if (RegNo > 31) 603 return false; 604 605 unsigned Register = SPRDecoderTable[RegNo]; 606 Inst.addOperand(MCOperand::CreateReg(Register)); 607 return true; 608} 609 610static const unsigned DPRDecoderTable[] = { 611 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 612 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 613 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 614 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 615 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 616 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 617 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 618 ARM::D28, ARM::D29, ARM::D30, ARM::D31 619}; 620 621static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 622 uint64_t Address, const void *Decoder) { 623 if (RegNo > 31) 624 return false; 625 626 unsigned Register = DPRDecoderTable[RegNo]; 627 Inst.addOperand(MCOperand::CreateReg(Register)); 628 return true; 629} 630 631static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 632 uint64_t Address, const void *Decoder) { 633 if (RegNo > 7) 634 return false; 635 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 636} 637 638static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 639 uint64_t Address, const void *Decoder) { 640 if (RegNo > 15) 641 return false; 642 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 643} 644 645static const unsigned QPRDecoderTable[] = { 646 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 647 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 648 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 649 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 650}; 651 652 653static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 654 uint64_t Address, const void *Decoder) { 655 if (RegNo > 31) 656 return false; 657 RegNo >>= 1; 658 659 unsigned Register = QPRDecoderTable[RegNo]; 660 Inst.addOperand(MCOperand::CreateReg(Register)); 661 return true; 662} 663 664static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 665 uint64_t Address, const void *Decoder) { 666 if (Val == 0xF) return false; 667 // AL predicate is not allowed on Thumb1 branches. 668 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 669 return false; 670 Inst.addOperand(MCOperand::CreateImm(Val)); 671 if (Val == ARMCC::AL) { 672 Inst.addOperand(MCOperand::CreateReg(0)); 673 } else 674 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 675 return true; 676} 677 678static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 679 uint64_t Address, const void *Decoder) { 680 if (Val) 681 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 682 else 683 Inst.addOperand(MCOperand::CreateReg(0)); 684 return true; 685} 686 687static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 688 uint64_t Address, const void *Decoder) { 689 uint32_t imm = Val & 0xFF; 690 uint32_t rot = (Val & 0xF00) >> 7; 691 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 692 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 693 return true; 694} 695 696static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 697 uint64_t Address, const void *Decoder) { 698 Val <<= 2; 699 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 700 return true; 701} 702 703static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 704 uint64_t Address, const void *Decoder) { 705 706 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 707 unsigned type = fieldFromInstruction32(Val, 5, 2); 708 unsigned imm = fieldFromInstruction32(Val, 7, 5); 709 710 // Register-immediate 711 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 712 713 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 714 switch (type) { 715 case 0: 716 Shift = ARM_AM::lsl; 717 break; 718 case 1: 719 Shift = ARM_AM::lsr; 720 break; 721 case 2: 722 Shift = ARM_AM::asr; 723 break; 724 case 3: 725 Shift = ARM_AM::ror; 726 break; 727 } 728 729 if (Shift == ARM_AM::ror && imm == 0) 730 Shift = ARM_AM::rrx; 731 732 unsigned Op = Shift | (imm << 3); 733 Inst.addOperand(MCOperand::CreateImm(Op)); 734 735 return true; 736} 737 738static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 739 uint64_t Address, const void *Decoder) { 740 741 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 742 unsigned type = fieldFromInstruction32(Val, 5, 2); 743 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 744 745 // Register-register 746 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 747 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 748 749 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 750 switch (type) { 751 case 0: 752 Shift = ARM_AM::lsl; 753 break; 754 case 1: 755 Shift = ARM_AM::lsr; 756 break; 757 case 2: 758 Shift = ARM_AM::asr; 759 break; 760 case 3: 761 Shift = ARM_AM::ror; 762 break; 763 } 764 765 Inst.addOperand(MCOperand::CreateImm(Shift)); 766 767 return true; 768} 769 770static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 771 uint64_t Address, const void *Decoder) { 772 // Empty register lists are not allowed. 773 if (CountPopulation_32(Val) == 0) return false; 774 for (unsigned i = 0; i < 16; ++i) { 775 if (Val & (1 << i)) { 776 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 777 } 778 } 779 780 return true; 781} 782 783static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 784 uint64_t Address, const void *Decoder) { 785 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 786 unsigned regs = Val & 0xFF; 787 788 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 789 for (unsigned i = 0; i < (regs - 1); ++i) { 790 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 791 } 792 793 return true; 794} 795 796static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 797 uint64_t Address, const void *Decoder) { 798 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 799 unsigned regs = (Val & 0xFF) / 2; 800 801 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 802 for (unsigned i = 0; i < (regs - 1); ++i) { 803 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 804 } 805 806 return true; 807} 808 809static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 810 uint64_t Address, const void *Decoder) { 811 // This operand encodes a mask of contiguous zeros between a specified MSB 812 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 813 // the mask of all bits LSB-and-lower, and then xor them to create 814 // the mask of that's all ones on [msb, lsb]. Finally we not it to 815 // create the final mask. 816 unsigned msb = fieldFromInstruction32(Val, 5, 5); 817 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 818 uint32_t msb_mask = (1 << (msb+1)) - 1; 819 uint32_t lsb_mask = (1 << lsb) - 1; 820 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 821 return true; 822} 823 824static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 825 uint64_t Address, const void *Decoder) { 826 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 827 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 828 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 829 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 830 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 831 unsigned U = fieldFromInstruction32(Insn, 23, 1); 832 833 switch (Inst.getOpcode()) { 834 case ARM::LDC_OFFSET: 835 case ARM::LDC_PRE: 836 case ARM::LDC_POST: 837 case ARM::LDC_OPTION: 838 case ARM::LDCL_OFFSET: 839 case ARM::LDCL_PRE: 840 case ARM::LDCL_POST: 841 case ARM::LDCL_OPTION: 842 case ARM::STC_OFFSET: 843 case ARM::STC_PRE: 844 case ARM::STC_POST: 845 case ARM::STC_OPTION: 846 case ARM::STCL_OFFSET: 847 case ARM::STCL_PRE: 848 case ARM::STCL_POST: 849 case ARM::STCL_OPTION: 850 if (coproc == 0xA || coproc == 0xB) 851 return false; 852 break; 853 default: 854 break; 855 } 856 857 Inst.addOperand(MCOperand::CreateImm(coproc)); 858 Inst.addOperand(MCOperand::CreateImm(CRd)); 859 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 860 switch (Inst.getOpcode()) { 861 case ARM::LDC_OPTION: 862 case ARM::LDCL_OPTION: 863 case ARM::LDC2_OPTION: 864 case ARM::LDC2L_OPTION: 865 case ARM::STC_OPTION: 866 case ARM::STCL_OPTION: 867 case ARM::STC2_OPTION: 868 case ARM::STC2L_OPTION: 869 case ARM::LDCL_POST: 870 case ARM::STCL_POST: 871 break; 872 default: 873 Inst.addOperand(MCOperand::CreateReg(0)); 874 break; 875 } 876 877 unsigned P = fieldFromInstruction32(Insn, 24, 1); 878 unsigned W = fieldFromInstruction32(Insn, 21, 1); 879 880 bool writeback = (P == 0) || (W == 1); 881 unsigned idx_mode = 0; 882 if (P && writeback) 883 idx_mode = ARMII::IndexModePre; 884 else if (!P && writeback) 885 idx_mode = ARMII::IndexModePost; 886 887 switch (Inst.getOpcode()) { 888 case ARM::LDCL_POST: 889 case ARM::STCL_POST: 890 imm |= U << 8; 891 case ARM::LDC_OPTION: 892 case ARM::LDCL_OPTION: 893 case ARM::LDC2_OPTION: 894 case ARM::LDC2L_OPTION: 895 case ARM::STC_OPTION: 896 case ARM::STCL_OPTION: 897 case ARM::STC2_OPTION: 898 case ARM::STC2L_OPTION: 899 Inst.addOperand(MCOperand::CreateImm(imm)); 900 break; 901 default: 902 if (U) 903 Inst.addOperand(MCOperand::CreateImm( 904 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 905 else 906 Inst.addOperand(MCOperand::CreateImm( 907 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 908 break; 909 } 910 911 switch (Inst.getOpcode()) { 912 case ARM::LDC_OFFSET: 913 case ARM::LDC_PRE: 914 case ARM::LDC_POST: 915 case ARM::LDC_OPTION: 916 case ARM::LDCL_OFFSET: 917 case ARM::LDCL_PRE: 918 case ARM::LDCL_POST: 919 case ARM::LDCL_OPTION: 920 case ARM::STC_OFFSET: 921 case ARM::STC_PRE: 922 case ARM::STC_POST: 923 case ARM::STC_OPTION: 924 case ARM::STCL_OFFSET: 925 case ARM::STCL_PRE: 926 case ARM::STCL_POST: 927 case ARM::STCL_OPTION: 928 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 929 break; 930 default: 931 break; 932 } 933 934 return true; 935} 936 937static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 938 uint64_t Address, const void *Decoder) { 939 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 940 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 941 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 942 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 943 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 944 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 945 unsigned P = fieldFromInstruction32(Insn, 24, 1); 946 unsigned W = fieldFromInstruction32(Insn, 21, 1); 947 948 // On stores, the writeback operand precedes Rt. 949 switch (Inst.getOpcode()) { 950 case ARM::STR_POST_IMM: 951 case ARM::STR_POST_REG: 952 case ARM::STRB_POST_IMM: 953 case ARM::STRB_POST_REG: 954 case ARM::STRT_POST_REG: 955 case ARM::STRT_POST_IMM: 956 case ARM::STRBT_POST_REG: 957 case ARM::STRBT_POST_IMM: 958 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 959 break; 960 default: 961 break; 962 } 963 964 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 965 966 // On loads, the writeback operand comes after Rt. 967 switch (Inst.getOpcode()) { 968 case ARM::LDR_POST_IMM: 969 case ARM::LDR_POST_REG: 970 case ARM::LDRB_POST_IMM: 971 case ARM::LDRB_POST_REG: 972 case ARM::LDR_PRE: 973 case ARM::LDRBT_POST_REG: 974 case ARM::LDRBT_POST_IMM: 975 case ARM::LDRT_POST_REG: 976 case ARM::LDRT_POST_IMM: 977 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 978 return false; 979 break; 980 default: 981 break; 982 } 983 984 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 985 986 ARM_AM::AddrOpc Op = ARM_AM::add; 987 if (!fieldFromInstruction32(Insn, 23, 1)) 988 Op = ARM_AM::sub; 989 990 bool writeback = (P == 0) || (W == 1); 991 unsigned idx_mode = 0; 992 if (P && writeback) 993 idx_mode = ARMII::IndexModePre; 994 else if (!P && writeback) 995 idx_mode = ARMII::IndexModePost; 996 997 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE 998 999 if (reg) { 1000 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 1001 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1002 switch( fieldFromInstruction32(Insn, 5, 2)) { 1003 case 0: 1004 Opc = ARM_AM::lsl; 1005 break; 1006 case 1: 1007 Opc = ARM_AM::lsr; 1008 break; 1009 case 2: 1010 Opc = ARM_AM::asr; 1011 break; 1012 case 3: 1013 Opc = ARM_AM::ror; 1014 break; 1015 default: 1016 return false; 1017 } 1018 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1019 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1020 1021 Inst.addOperand(MCOperand::CreateImm(imm)); 1022 } else { 1023 Inst.addOperand(MCOperand::CreateReg(0)); 1024 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1025 Inst.addOperand(MCOperand::CreateImm(tmp)); 1026 } 1027 1028 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1029 1030 return true; 1031} 1032 1033static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1034 uint64_t Address, const void *Decoder) { 1035 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1036 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1037 unsigned type = fieldFromInstruction32(Val, 5, 2); 1038 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1039 unsigned U = fieldFromInstruction32(Val, 12, 1); 1040 1041 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1042 switch (type) { 1043 case 0: 1044 ShOp = ARM_AM::lsl; 1045 break; 1046 case 1: 1047 ShOp = ARM_AM::lsr; 1048 break; 1049 case 2: 1050 ShOp = ARM_AM::asr; 1051 break; 1052 case 3: 1053 ShOp = ARM_AM::ror; 1054 break; 1055 } 1056 1057 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1058 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1059 unsigned shift; 1060 if (U) 1061 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1062 else 1063 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1064 Inst.addOperand(MCOperand::CreateImm(shift)); 1065 1066 return true; 1067} 1068 1069static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1070 uint64_t Address, const void *Decoder) { 1071 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1072 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1073 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1074 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1075 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1076 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1077 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1078 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1079 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1080 1081 bool writeback = (W == 1) | (P == 0); 1082 if (writeback) { // Writeback 1083 if (P) 1084 U |= ARMII::IndexModePre << 9; 1085 else 1086 U |= ARMII::IndexModePost << 9; 1087 1088 // On stores, the writeback operand precedes Rt. 1089 switch (Inst.getOpcode()) { 1090 case ARM::STRD: 1091 case ARM::STRD_PRE: 1092 case ARM::STRD_POST: 1093 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1094 return false; 1095 break; 1096 default: 1097 break; 1098 } 1099 } 1100 1101 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1102 return false; 1103 switch (Inst.getOpcode()) { 1104 case ARM::STRD: 1105 case ARM::STRD_PRE: 1106 case ARM::STRD_POST: 1107 case ARM::LDRD: 1108 case ARM::LDRD_PRE: 1109 case ARM::LDRD_POST: 1110 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1111 return false; 1112 break; 1113 default: 1114 break; 1115 } 1116 1117 if (writeback) { 1118 // On loads, the writeback operand comes after Rt. 1119 switch (Inst.getOpcode()) { 1120 case ARM::LDRD: 1121 case ARM::LDRD_PRE: 1122 case ARM::LDRD_POST: 1123 case ARM::LDRHTr: 1124 case ARM::LDRSBTr: 1125 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1126 return false; 1127 break; 1128 default: 1129 break; 1130 } 1131 } 1132 1133 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1134 return false; 1135 1136 if (type) { 1137 Inst.addOperand(MCOperand::CreateReg(0)); 1138 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1139 } else { 1140 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1141 return false; 1142 Inst.addOperand(MCOperand::CreateImm(U)); 1143 } 1144 1145 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1146 1147 return true; 1148} 1149 1150static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1151 uint64_t Address, const void *Decoder) { 1152 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1153 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1154 1155 switch (mode) { 1156 case 0: 1157 mode = ARM_AM::da; 1158 break; 1159 case 1: 1160 mode = ARM_AM::ia; 1161 break; 1162 case 2: 1163 mode = ARM_AM::db; 1164 break; 1165 case 3: 1166 mode = ARM_AM::ib; 1167 break; 1168 } 1169 1170 Inst.addOperand(MCOperand::CreateImm(mode)); 1171 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1172 1173 return true; 1174} 1175 1176static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1177 unsigned Insn, 1178 uint64_t Address, const void *Decoder) { 1179 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1180 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1181 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1182 1183 if (pred == 0xF) { 1184 switch (Inst.getOpcode()) { 1185 case ARM::STMDA: 1186 Inst.setOpcode(ARM::RFEDA); 1187 break; 1188 case ARM::STMDA_UPD: 1189 Inst.setOpcode(ARM::RFEDA_UPD); 1190 break; 1191 case ARM::STMDB: 1192 Inst.setOpcode(ARM::RFEDB); 1193 break; 1194 case ARM::STMDB_UPD: 1195 Inst.setOpcode(ARM::RFEDB_UPD); 1196 break; 1197 case ARM::STMIA: 1198 Inst.setOpcode(ARM::RFEIA); 1199 break; 1200 case ARM::STMIA_UPD: 1201 Inst.setOpcode(ARM::RFEIA_UPD); 1202 break; 1203 case ARM::STMIB: 1204 Inst.setOpcode(ARM::RFEIB); 1205 break; 1206 case ARM::STMIB_UPD: 1207 Inst.setOpcode(ARM::RFEIB_UPD); 1208 break; 1209 } 1210 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1211 } 1212 1213 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1214 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1215 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1216 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1217 return false; 1218 1219 return true; 1220} 1221 1222static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1223 uint64_t Address, const void *Decoder) { 1224 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1225 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1226 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1227 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1228 1229 // imod == '01' --> UNPREDICTABLE 1230 if (imod == 1) return false; 1231 1232 if (M && mode && imod && iflags) { 1233 Inst.setOpcode(ARM::CPS3p); 1234 Inst.addOperand(MCOperand::CreateImm(imod)); 1235 Inst.addOperand(MCOperand::CreateImm(iflags)); 1236 Inst.addOperand(MCOperand::CreateImm(mode)); 1237 return true; 1238 } else if (!mode && !M) { 1239 Inst.setOpcode(ARM::CPS2p); 1240 Inst.addOperand(MCOperand::CreateImm(imod)); 1241 Inst.addOperand(MCOperand::CreateImm(iflags)); 1242 return true; 1243 } else if (!imod && !iflags && M) { 1244 Inst.setOpcode(ARM::CPS1p); 1245 Inst.addOperand(MCOperand::CreateImm(mode)); 1246 return true; 1247 } 1248 1249 return false; 1250} 1251 1252static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1253 uint64_t Address, const void *Decoder) { 1254 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1255 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1256 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1257 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1258 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1259 1260 if (pred == 0xF) 1261 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1262 1263 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1264 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1265 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1266 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1267 return false; 1268 1269 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1270 1271 return true; 1272} 1273 1274static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1275 uint64_t Address, const void *Decoder) { 1276 unsigned add = fieldFromInstruction32(Val, 12, 1); 1277 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1278 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1279 1280 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1281 return false; 1282 1283 if (!add) imm *= -1; 1284 if (imm == 0 && !add) imm = INT32_MIN; 1285 Inst.addOperand(MCOperand::CreateImm(imm)); 1286 1287 return true; 1288} 1289 1290static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1291 uint64_t Address, const void *Decoder) { 1292 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1293 unsigned U = fieldFromInstruction32(Val, 8, 1); 1294 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1295 1296 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1297 return false; 1298 1299 if (U) 1300 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1301 else 1302 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1303 1304 return true; 1305} 1306 1307static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1308 uint64_t Address, const void *Decoder) { 1309 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1310} 1311 1312static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1313 uint64_t Address, const void *Decoder) { 1314 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1315 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1316 1317 if (pred == 0xF) { 1318 Inst.setOpcode(ARM::BLXi); 1319 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1320 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1321 return true; 1322 } 1323 1324 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1325 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1326 1327 return true; 1328} 1329 1330 1331static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1332 uint64_t Address, const void *Decoder) { 1333 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1334 return true; 1335} 1336 1337static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1338 uint64_t Address, const void *Decoder) { 1339 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1340 unsigned align = fieldFromInstruction32(Val, 4, 2); 1341 1342 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1343 return false; 1344 if (!align) 1345 Inst.addOperand(MCOperand::CreateImm(0)); 1346 else 1347 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1348 1349 return true; 1350} 1351 1352static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1353 uint64_t Address, const void *Decoder) { 1354 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1355 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1356 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1357 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1358 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1359 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1360 1361 // First output register 1362 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1363 1364 // Second output register 1365 switch (Inst.getOpcode()) { 1366 case ARM::VLD1q8: 1367 case ARM::VLD1q16: 1368 case ARM::VLD1q32: 1369 case ARM::VLD1q64: 1370 case ARM::VLD1q8_UPD: 1371 case ARM::VLD1q16_UPD: 1372 case ARM::VLD1q32_UPD: 1373 case ARM::VLD1q64_UPD: 1374 case ARM::VLD1d8T: 1375 case ARM::VLD1d16T: 1376 case ARM::VLD1d32T: 1377 case ARM::VLD1d64T: 1378 case ARM::VLD1d8T_UPD: 1379 case ARM::VLD1d16T_UPD: 1380 case ARM::VLD1d32T_UPD: 1381 case ARM::VLD1d64T_UPD: 1382 case ARM::VLD1d8Q: 1383 case ARM::VLD1d16Q: 1384 case ARM::VLD1d32Q: 1385 case ARM::VLD1d64Q: 1386 case ARM::VLD1d8Q_UPD: 1387 case ARM::VLD1d16Q_UPD: 1388 case ARM::VLD1d32Q_UPD: 1389 case ARM::VLD1d64Q_UPD: 1390 case ARM::VLD2d8: 1391 case ARM::VLD2d16: 1392 case ARM::VLD2d32: 1393 case ARM::VLD2d8_UPD: 1394 case ARM::VLD2d16_UPD: 1395 case ARM::VLD2d32_UPD: 1396 case ARM::VLD2q8: 1397 case ARM::VLD2q16: 1398 case ARM::VLD2q32: 1399 case ARM::VLD2q8_UPD: 1400 case ARM::VLD2q16_UPD: 1401 case ARM::VLD2q32_UPD: 1402 case ARM::VLD3d8: 1403 case ARM::VLD3d16: 1404 case ARM::VLD3d32: 1405 case ARM::VLD3d8_UPD: 1406 case ARM::VLD3d16_UPD: 1407 case ARM::VLD3d32_UPD: 1408 case ARM::VLD4d8: 1409 case ARM::VLD4d16: 1410 case ARM::VLD4d32: 1411 case ARM::VLD4d8_UPD: 1412 case ARM::VLD4d16_UPD: 1413 case ARM::VLD4d32_UPD: 1414 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1415 break; 1416 case ARM::VLD2b8: 1417 case ARM::VLD2b16: 1418 case ARM::VLD2b32: 1419 case ARM::VLD2b8_UPD: 1420 case ARM::VLD2b16_UPD: 1421 case ARM::VLD2b32_UPD: 1422 case ARM::VLD3q8: 1423 case ARM::VLD3q16: 1424 case ARM::VLD3q32: 1425 case ARM::VLD3q8_UPD: 1426 case ARM::VLD3q16_UPD: 1427 case ARM::VLD3q32_UPD: 1428 case ARM::VLD4q8: 1429 case ARM::VLD4q16: 1430 case ARM::VLD4q32: 1431 case ARM::VLD4q8_UPD: 1432 case ARM::VLD4q16_UPD: 1433 case ARM::VLD4q32_UPD: 1434 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1435 default: 1436 break; 1437 } 1438 1439 // Third output register 1440 switch(Inst.getOpcode()) { 1441 case ARM::VLD1d8T: 1442 case ARM::VLD1d16T: 1443 case ARM::VLD1d32T: 1444 case ARM::VLD1d64T: 1445 case ARM::VLD1d8T_UPD: 1446 case ARM::VLD1d16T_UPD: 1447 case ARM::VLD1d32T_UPD: 1448 case ARM::VLD1d64T_UPD: 1449 case ARM::VLD1d8Q: 1450 case ARM::VLD1d16Q: 1451 case ARM::VLD1d32Q: 1452 case ARM::VLD1d64Q: 1453 case ARM::VLD1d8Q_UPD: 1454 case ARM::VLD1d16Q_UPD: 1455 case ARM::VLD1d32Q_UPD: 1456 case ARM::VLD1d64Q_UPD: 1457 case ARM::VLD2q8: 1458 case ARM::VLD2q16: 1459 case ARM::VLD2q32: 1460 case ARM::VLD2q8_UPD: 1461 case ARM::VLD2q16_UPD: 1462 case ARM::VLD2q32_UPD: 1463 case ARM::VLD3d8: 1464 case ARM::VLD3d16: 1465 case ARM::VLD3d32: 1466 case ARM::VLD3d8_UPD: 1467 case ARM::VLD3d16_UPD: 1468 case ARM::VLD3d32_UPD: 1469 case ARM::VLD4d8: 1470 case ARM::VLD4d16: 1471 case ARM::VLD4d32: 1472 case ARM::VLD4d8_UPD: 1473 case ARM::VLD4d16_UPD: 1474 case ARM::VLD4d32_UPD: 1475 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1476 break; 1477 case ARM::VLD3q8: 1478 case ARM::VLD3q16: 1479 case ARM::VLD3q32: 1480 case ARM::VLD3q8_UPD: 1481 case ARM::VLD3q16_UPD: 1482 case ARM::VLD3q32_UPD: 1483 case ARM::VLD4q8: 1484 case ARM::VLD4q16: 1485 case ARM::VLD4q32: 1486 case ARM::VLD4q8_UPD: 1487 case ARM::VLD4q16_UPD: 1488 case ARM::VLD4q32_UPD: 1489 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1490 break; 1491 default: 1492 break; 1493 } 1494 1495 // Fourth output register 1496 switch (Inst.getOpcode()) { 1497 case ARM::VLD1d8Q: 1498 case ARM::VLD1d16Q: 1499 case ARM::VLD1d32Q: 1500 case ARM::VLD1d64Q: 1501 case ARM::VLD1d8Q_UPD: 1502 case ARM::VLD1d16Q_UPD: 1503 case ARM::VLD1d32Q_UPD: 1504 case ARM::VLD1d64Q_UPD: 1505 case ARM::VLD2q8: 1506 case ARM::VLD2q16: 1507 case ARM::VLD2q32: 1508 case ARM::VLD2q8_UPD: 1509 case ARM::VLD2q16_UPD: 1510 case ARM::VLD2q32_UPD: 1511 case ARM::VLD4d8: 1512 case ARM::VLD4d16: 1513 case ARM::VLD4d32: 1514 case ARM::VLD4d8_UPD: 1515 case ARM::VLD4d16_UPD: 1516 case ARM::VLD4d32_UPD: 1517 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1518 break; 1519 case ARM::VLD4q8: 1520 case ARM::VLD4q16: 1521 case ARM::VLD4q32: 1522 case ARM::VLD4q8_UPD: 1523 case ARM::VLD4q16_UPD: 1524 case ARM::VLD4q32_UPD: 1525 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1526 break; 1527 default: 1528 break; 1529 } 1530 1531 // Writeback operand 1532 switch (Inst.getOpcode()) { 1533 case ARM::VLD1d8_UPD: 1534 case ARM::VLD1d16_UPD: 1535 case ARM::VLD1d32_UPD: 1536 case ARM::VLD1d64_UPD: 1537 case ARM::VLD1q8_UPD: 1538 case ARM::VLD1q16_UPD: 1539 case ARM::VLD1q32_UPD: 1540 case ARM::VLD1q64_UPD: 1541 case ARM::VLD1d8T_UPD: 1542 case ARM::VLD1d16T_UPD: 1543 case ARM::VLD1d32T_UPD: 1544 case ARM::VLD1d64T_UPD: 1545 case ARM::VLD1d8Q_UPD: 1546 case ARM::VLD1d16Q_UPD: 1547 case ARM::VLD1d32Q_UPD: 1548 case ARM::VLD1d64Q_UPD: 1549 case ARM::VLD2d8_UPD: 1550 case ARM::VLD2d16_UPD: 1551 case ARM::VLD2d32_UPD: 1552 case ARM::VLD2q8_UPD: 1553 case ARM::VLD2q16_UPD: 1554 case ARM::VLD2q32_UPD: 1555 case ARM::VLD2b8_UPD: 1556 case ARM::VLD2b16_UPD: 1557 case ARM::VLD2b32_UPD: 1558 case ARM::VLD3d8_UPD: 1559 case ARM::VLD3d16_UPD: 1560 case ARM::VLD3d32_UPD: 1561 case ARM::VLD3q8_UPD: 1562 case ARM::VLD3q16_UPD: 1563 case ARM::VLD3q32_UPD: 1564 case ARM::VLD4d8_UPD: 1565 case ARM::VLD4d16_UPD: 1566 case ARM::VLD4d32_UPD: 1567 case ARM::VLD4q8_UPD: 1568 case ARM::VLD4q16_UPD: 1569 case ARM::VLD4q32_UPD: 1570 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1571 break; 1572 default: 1573 break; 1574 } 1575 1576 // AddrMode6 Base (register+alignment) 1577 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1578 1579 // AddrMode6 Offset (register) 1580 if (Rm == 0xD) 1581 Inst.addOperand(MCOperand::CreateReg(0)); 1582 else if (Rm != 0xF) { 1583 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1584 return false; 1585 } 1586 1587 return true; 1588} 1589 1590static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1591 uint64_t Address, const void *Decoder) { 1592 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1593 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1594 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1595 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1596 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1597 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1598 1599 // Writeback Operand 1600 switch (Inst.getOpcode()) { 1601 case ARM::VST1d8_UPD: 1602 case ARM::VST1d16_UPD: 1603 case ARM::VST1d32_UPD: 1604 case ARM::VST1d64_UPD: 1605 case ARM::VST1q8_UPD: 1606 case ARM::VST1q16_UPD: 1607 case ARM::VST1q32_UPD: 1608 case ARM::VST1q64_UPD: 1609 case ARM::VST1d8T_UPD: 1610 case ARM::VST1d16T_UPD: 1611 case ARM::VST1d32T_UPD: 1612 case ARM::VST1d64T_UPD: 1613 case ARM::VST1d8Q_UPD: 1614 case ARM::VST1d16Q_UPD: 1615 case ARM::VST1d32Q_UPD: 1616 case ARM::VST1d64Q_UPD: 1617 case ARM::VST2d8_UPD: 1618 case ARM::VST2d16_UPD: 1619 case ARM::VST2d32_UPD: 1620 case ARM::VST2q8_UPD: 1621 case ARM::VST2q16_UPD: 1622 case ARM::VST2q32_UPD: 1623 case ARM::VST2b8_UPD: 1624 case ARM::VST2b16_UPD: 1625 case ARM::VST2b32_UPD: 1626 case ARM::VST3d8_UPD: 1627 case ARM::VST3d16_UPD: 1628 case ARM::VST3d32_UPD: 1629 case ARM::VST3q8_UPD: 1630 case ARM::VST3q16_UPD: 1631 case ARM::VST3q32_UPD: 1632 case ARM::VST4d8_UPD: 1633 case ARM::VST4d16_UPD: 1634 case ARM::VST4d32_UPD: 1635 case ARM::VST4q8_UPD: 1636 case ARM::VST4q16_UPD: 1637 case ARM::VST4q32_UPD: 1638 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1639 return false; 1640 break; 1641 default: 1642 break; 1643 } 1644 1645 // AddrMode6 Base (register+alignment) 1646 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1647 1648 // AddrMode6 Offset (register) 1649 if (Rm == 0xD) 1650 Inst.addOperand(MCOperand::CreateReg(0)); 1651 else if (Rm != 0xF) { 1652 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1653 } 1654 1655 // First input register 1656 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1657 1658 // Second input register 1659 switch (Inst.getOpcode()) { 1660 case ARM::VST1q8: 1661 case ARM::VST1q16: 1662 case ARM::VST1q32: 1663 case ARM::VST1q64: 1664 case ARM::VST1q8_UPD: 1665 case ARM::VST1q16_UPD: 1666 case ARM::VST1q32_UPD: 1667 case ARM::VST1q64_UPD: 1668 case ARM::VST1d8T: 1669 case ARM::VST1d16T: 1670 case ARM::VST1d32T: 1671 case ARM::VST1d64T: 1672 case ARM::VST1d8T_UPD: 1673 case ARM::VST1d16T_UPD: 1674 case ARM::VST1d32T_UPD: 1675 case ARM::VST1d64T_UPD: 1676 case ARM::VST1d8Q: 1677 case ARM::VST1d16Q: 1678 case ARM::VST1d32Q: 1679 case ARM::VST1d64Q: 1680 case ARM::VST1d8Q_UPD: 1681 case ARM::VST1d16Q_UPD: 1682 case ARM::VST1d32Q_UPD: 1683 case ARM::VST1d64Q_UPD: 1684 case ARM::VST2d8: 1685 case ARM::VST2d16: 1686 case ARM::VST2d32: 1687 case ARM::VST2d8_UPD: 1688 case ARM::VST2d16_UPD: 1689 case ARM::VST2d32_UPD: 1690 case ARM::VST2q8: 1691 case ARM::VST2q16: 1692 case ARM::VST2q32: 1693 case ARM::VST2q8_UPD: 1694 case ARM::VST2q16_UPD: 1695 case ARM::VST2q32_UPD: 1696 case ARM::VST3d8: 1697 case ARM::VST3d16: 1698 case ARM::VST3d32: 1699 case ARM::VST3d8_UPD: 1700 case ARM::VST3d16_UPD: 1701 case ARM::VST3d32_UPD: 1702 case ARM::VST4d8: 1703 case ARM::VST4d16: 1704 case ARM::VST4d32: 1705 case ARM::VST4d8_UPD: 1706 case ARM::VST4d16_UPD: 1707 case ARM::VST4d32_UPD: 1708 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1709 break; 1710 case ARM::VST2b8: 1711 case ARM::VST2b16: 1712 case ARM::VST2b32: 1713 case ARM::VST2b8_UPD: 1714 case ARM::VST2b16_UPD: 1715 case ARM::VST2b32_UPD: 1716 case ARM::VST3q8: 1717 case ARM::VST3q16: 1718 case ARM::VST3q32: 1719 case ARM::VST3q8_UPD: 1720 case ARM::VST3q16_UPD: 1721 case ARM::VST3q32_UPD: 1722 case ARM::VST4q8: 1723 case ARM::VST4q16: 1724 case ARM::VST4q32: 1725 case ARM::VST4q8_UPD: 1726 case ARM::VST4q16_UPD: 1727 case ARM::VST4q32_UPD: 1728 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1729 break; 1730 default: 1731 break; 1732 } 1733 1734 // Third input register 1735 switch (Inst.getOpcode()) { 1736 case ARM::VST1d8T: 1737 case ARM::VST1d16T: 1738 case ARM::VST1d32T: 1739 case ARM::VST1d64T: 1740 case ARM::VST1d8T_UPD: 1741 case ARM::VST1d16T_UPD: 1742 case ARM::VST1d32T_UPD: 1743 case ARM::VST1d64T_UPD: 1744 case ARM::VST1d8Q: 1745 case ARM::VST1d16Q: 1746 case ARM::VST1d32Q: 1747 case ARM::VST1d64Q: 1748 case ARM::VST1d8Q_UPD: 1749 case ARM::VST1d16Q_UPD: 1750 case ARM::VST1d32Q_UPD: 1751 case ARM::VST1d64Q_UPD: 1752 case ARM::VST2q8: 1753 case ARM::VST2q16: 1754 case ARM::VST2q32: 1755 case ARM::VST2q8_UPD: 1756 case ARM::VST2q16_UPD: 1757 case ARM::VST2q32_UPD: 1758 case ARM::VST3d8: 1759 case ARM::VST3d16: 1760 case ARM::VST3d32: 1761 case ARM::VST3d8_UPD: 1762 case ARM::VST3d16_UPD: 1763 case ARM::VST3d32_UPD: 1764 case ARM::VST4d8: 1765 case ARM::VST4d16: 1766 case ARM::VST4d32: 1767 case ARM::VST4d8_UPD: 1768 case ARM::VST4d16_UPD: 1769 case ARM::VST4d32_UPD: 1770 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1771 break; 1772 case ARM::VST3q8: 1773 case ARM::VST3q16: 1774 case ARM::VST3q32: 1775 case ARM::VST3q8_UPD: 1776 case ARM::VST3q16_UPD: 1777 case ARM::VST3q32_UPD: 1778 case ARM::VST4q8: 1779 case ARM::VST4q16: 1780 case ARM::VST4q32: 1781 case ARM::VST4q8_UPD: 1782 case ARM::VST4q16_UPD: 1783 case ARM::VST4q32_UPD: 1784 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1785 break; 1786 default: 1787 break; 1788 } 1789 1790 // Fourth input register 1791 switch (Inst.getOpcode()) { 1792 case ARM::VST1d8Q: 1793 case ARM::VST1d16Q: 1794 case ARM::VST1d32Q: 1795 case ARM::VST1d64Q: 1796 case ARM::VST1d8Q_UPD: 1797 case ARM::VST1d16Q_UPD: 1798 case ARM::VST1d32Q_UPD: 1799 case ARM::VST1d64Q_UPD: 1800 case ARM::VST2q8: 1801 case ARM::VST2q16: 1802 case ARM::VST2q32: 1803 case ARM::VST2q8_UPD: 1804 case ARM::VST2q16_UPD: 1805 case ARM::VST2q32_UPD: 1806 case ARM::VST4d8: 1807 case ARM::VST4d16: 1808 case ARM::VST4d32: 1809 case ARM::VST4d8_UPD: 1810 case ARM::VST4d16_UPD: 1811 case ARM::VST4d32_UPD: 1812 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1813 break; 1814 case ARM::VST4q8: 1815 case ARM::VST4q16: 1816 case ARM::VST4q32: 1817 case ARM::VST4q8_UPD: 1818 case ARM::VST4q16_UPD: 1819 case ARM::VST4q32_UPD: 1820 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1821 break; 1822 default: 1823 break; 1824 } 1825 1826 return true; 1827} 1828 1829static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1830 uint64_t Address, const void *Decoder) { 1831 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1832 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1833 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1834 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1835 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1836 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1837 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1838 1839 align *= (1 << size); 1840 1841 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1842 if (regs == 2) { 1843 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1844 } 1845 if (Rm == 0xD) { 1846 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1847 } 1848 1849 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1850 Inst.addOperand(MCOperand::CreateImm(align)); 1851 1852 if (Rm == 0xD) 1853 Inst.addOperand(MCOperand::CreateReg(0)); 1854 else if (Rm != 0xF) { 1855 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1856 } 1857 1858 return true; 1859} 1860 1861static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1862 uint64_t Address, const void *Decoder) { 1863 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1864 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1865 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1866 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1867 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1868 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1869 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1870 align *= 2*size; 1871 1872 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1873 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1874 if (Rm == 0xD) { 1875 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1876 } 1877 1878 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1879 Inst.addOperand(MCOperand::CreateImm(align)); 1880 1881 if (Rm == 0xD) 1882 Inst.addOperand(MCOperand::CreateReg(0)); 1883 else if (Rm != 0xF) { 1884 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1885 } 1886 1887 return true; 1888} 1889 1890static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1891 uint64_t Address, const void *Decoder) { 1892 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1893 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1894 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1895 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1896 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1897 1898 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1899 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1900 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1901 return false; 1902 if (Rm == 0xD) { 1903 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1904 } 1905 1906 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1907 Inst.addOperand(MCOperand::CreateImm(0)); 1908 1909 if (Rm == 0xD) 1910 Inst.addOperand(MCOperand::CreateReg(0)); 1911 else if (Rm != 0xF) { 1912 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1913 } 1914 1915 return true; 1916} 1917 1918static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1919 uint64_t Address, const void *Decoder) { 1920 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1921 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1922 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1923 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1924 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1925 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1926 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1927 1928 if (size == 0x3) { 1929 size = 4; 1930 align = 16; 1931 } else { 1932 if (size == 2) { 1933 size = 1 << size; 1934 align *= 8; 1935 } else { 1936 size = 1 << size; 1937 align *= 4*size; 1938 } 1939 } 1940 1941 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1942 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1943 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1944 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 1945 return false; 1946 if (Rm == 0xD) { 1947 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1948 } 1949 1950 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1951 Inst.addOperand(MCOperand::CreateImm(align)); 1952 1953 if (Rm == 0xD) 1954 Inst.addOperand(MCOperand::CreateReg(0)); 1955 else if (Rm != 0xF) { 1956 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1957 } 1958 1959 return true; 1960} 1961 1962static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1963 uint64_t Address, const void *Decoder) { 1964 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1965 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1966 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1967 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1968 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1969 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1970 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1971 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1972 1973 if (Q) { 1974 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1975 } else { 1976 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1977 } 1978 1979 Inst.addOperand(MCOperand::CreateImm(imm)); 1980 1981 switch (Inst.getOpcode()) { 1982 case ARM::VORRiv4i16: 1983 case ARM::VORRiv2i32: 1984 case ARM::VBICiv4i16: 1985 case ARM::VBICiv2i32: 1986 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1987 break; 1988 case ARM::VORRiv8i16: 1989 case ARM::VORRiv4i32: 1990 case ARM::VBICiv8i16: 1991 case ARM::VBICiv4i32: 1992 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1993 break; 1994 default: 1995 break; 1996 } 1997 1998 return true; 1999} 2000 2001static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2002 uint64_t Address, const void *Decoder) { 2003 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2004 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2005 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2006 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2007 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2008 2009 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2010 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2011 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2012 2013 return true; 2014} 2015 2016static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2017 uint64_t Address, const void *Decoder) { 2018 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2019 return true; 2020} 2021 2022static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2023 uint64_t Address, const void *Decoder) { 2024 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2025 return true; 2026} 2027 2028static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2029 uint64_t Address, const void *Decoder) { 2030 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2031 return true; 2032} 2033 2034static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2035 uint64_t Address, const void *Decoder) { 2036 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2037 return true; 2038} 2039 2040static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2041 uint64_t Address, const void *Decoder) { 2042 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2043 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2044 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2045 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2046 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2047 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2048 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2049 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2050 2051 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2052 if (op) { 2053 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2054 } 2055 2056 for (unsigned i = 0; i < length; ++i) { 2057 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2058 } 2059 2060 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2061 2062 return true; 2063} 2064 2065static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2066 uint64_t Address, const void *Decoder) { 2067 // The immediate needs to be a fully instantiated float. However, the 2068 // auto-generated decoder is only able to fill in some of the bits 2069 // necessary. For instance, the 'b' bit is replicated multiple times, 2070 // and is even present in inverted form in one bit. We do a little 2071 // binary parsing here to fill in those missing bits, and then 2072 // reinterpret it all as a float. 2073 union { 2074 uint32_t integer; 2075 float fp; 2076 } fp_conv; 2077 2078 fp_conv.integer = Val; 2079 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2080 fp_conv.integer |= b << 26; 2081 fp_conv.integer |= b << 27; 2082 fp_conv.integer |= b << 28; 2083 fp_conv.integer |= b << 29; 2084 fp_conv.integer |= (~b & 0x1) << 30; 2085 2086 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2087 return true; 2088} 2089 2090static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2091 uint64_t Address, const void *Decoder) { 2092 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2093 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2094 2095 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2096 2097 if (Inst.getOpcode() == ARM::tADR) 2098 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2099 else if (Inst.getOpcode() == ARM::tADDrSPi) 2100 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2101 else 2102 return false; 2103 2104 Inst.addOperand(MCOperand::CreateImm(imm)); 2105 return true; 2106} 2107 2108static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2109 uint64_t Address, const void *Decoder) { 2110 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2111 return true; 2112} 2113 2114static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2115 uint64_t Address, const void *Decoder) { 2116 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2117 return true; 2118} 2119 2120static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2121 uint64_t Address, const void *Decoder) { 2122 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2123 return true; 2124} 2125 2126static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2127 uint64_t Address, const void *Decoder) { 2128 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2129 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2130 2131 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2132 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2133 return false; 2134 2135 return true; 2136} 2137 2138static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2139 uint64_t Address, const void *Decoder) { 2140 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2141 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2142 2143 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2144 Inst.addOperand(MCOperand::CreateImm(imm)); 2145 2146 return true; 2147} 2148 2149static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2150 uint64_t Address, const void *Decoder) { 2151 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2152 2153 return true; 2154} 2155 2156static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2157 uint64_t Address, const void *Decoder) { 2158 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2159 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2160 2161 return true; 2162} 2163 2164static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2165 uint64_t Address, const void *Decoder) { 2166 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2167 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2168 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2169 2170 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2171 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2172 return false; 2173 Inst.addOperand(MCOperand::CreateImm(imm)); 2174 2175 return true; 2176} 2177 2178static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2179 uint64_t Address, const void *Decoder) { 2180 if (Inst.getOpcode() != ARM::t2PLDs) { 2181 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2182 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2183 } 2184 2185 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2186 if (Rn == 0xF) { 2187 switch (Inst.getOpcode()) { 2188 case ARM::t2LDRBs: 2189 Inst.setOpcode(ARM::t2LDRBpci); 2190 break; 2191 case ARM::t2LDRHs: 2192 Inst.setOpcode(ARM::t2LDRHpci); 2193 break; 2194 case ARM::t2LDRSHs: 2195 Inst.setOpcode(ARM::t2LDRSHpci); 2196 break; 2197 case ARM::t2LDRSBs: 2198 Inst.setOpcode(ARM::t2LDRSBpci); 2199 break; 2200 case ARM::t2PLDs: 2201 Inst.setOpcode(ARM::t2PLDi12); 2202 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2203 break; 2204 default: 2205 return false; 2206 } 2207 2208 int imm = fieldFromInstruction32(Insn, 0, 12); 2209 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2210 Inst.addOperand(MCOperand::CreateImm(imm)); 2211 2212 return true; 2213 } 2214 2215 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2216 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2217 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2218 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2219 2220 return true; 2221} 2222 2223static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2224 uint64_t Address, const void *Decoder) { 2225 int imm = Val & 0xFF; 2226 if (!(Val & 0x100)) imm *= -1; 2227 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2228 2229 return true; 2230} 2231 2232static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2233 uint64_t Address, const void *Decoder) { 2234 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2235 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2236 2237 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2238 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2239 return false; 2240 2241 return true; 2242} 2243 2244static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2245 uint64_t Address, const void *Decoder) { 2246 int imm = Val & 0xFF; 2247 if (!(Val & 0x100)) imm *= -1; 2248 Inst.addOperand(MCOperand::CreateImm(imm)); 2249 2250 return true; 2251} 2252 2253 2254static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2255 uint64_t Address, const void *Decoder) { 2256 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2257 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2258 2259 // Some instructions always use an additive offset. 2260 switch (Inst.getOpcode()) { 2261 case ARM::t2LDRT: 2262 case ARM::t2LDRBT: 2263 case ARM::t2LDRHT: 2264 case ARM::t2LDRSBT: 2265 case ARM::t2LDRSHT: 2266 imm |= 0x100; 2267 break; 2268 default: 2269 break; 2270 } 2271 2272 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2273 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2274 return false; 2275 2276 return true; 2277} 2278 2279 2280static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2281 uint64_t Address, const void *Decoder) { 2282 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2283 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2284 2285 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2286 Inst.addOperand(MCOperand::CreateImm(imm)); 2287 2288 return true; 2289} 2290 2291 2292static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2293 uint64_t Address, const void *Decoder) { 2294 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2295 2296 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2297 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2298 Inst.addOperand(MCOperand::CreateImm(imm)); 2299 2300 return true; 2301} 2302 2303static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2304 uint64_t Address, const void *Decoder) { 2305 if (Inst.getOpcode() == ARM::tADDrSP) { 2306 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2307 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2308 2309 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2310 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2311 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2312 } else if (Inst.getOpcode() == ARM::tADDspr) { 2313 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2314 2315 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2316 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2317 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2318 } 2319 2320 return true; 2321} 2322 2323static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2324 uint64_t Address, const void *Decoder) { 2325 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2326 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2327 2328 Inst.addOperand(MCOperand::CreateImm(imod)); 2329 Inst.addOperand(MCOperand::CreateImm(flags)); 2330 2331 return true; 2332} 2333 2334static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2335 uint64_t Address, const void *Decoder) { 2336 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2337 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2338 2339 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2340 Inst.addOperand(MCOperand::CreateImm(add)); 2341 2342 return true; 2343} 2344 2345static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2346 uint64_t Address, const void *Decoder) { 2347 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2348 return true; 2349} 2350 2351static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2352 uint64_t Address, const void *Decoder) { 2353 if (Val == 0xA || Val == 0xB) 2354 return false; 2355 2356 Inst.addOperand(MCOperand::CreateImm(Val)); 2357 return true; 2358} 2359 2360static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2361 uint64_t Address, const void *Decoder) { 2362 if (Val == 0) 2363 Inst.addOperand(MCOperand::CreateImm(32)); 2364 else 2365 Inst.addOperand(MCOperand::CreateImm(Val)); 2366 return true; 2367} 2368 2369static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2370 uint64_t Address, const void *Decoder) { 2371 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2372 if (pred == 0xE || pred == 0xF) { 2373 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2374 switch (opc) { 2375 default: 2376 return false; 2377 case 0: 2378 Inst.setOpcode(ARM::t2DSB); 2379 break; 2380 case 1: 2381 Inst.setOpcode(ARM::t2DMB); 2382 break; 2383 case 2: 2384 Inst.setOpcode(ARM::t2ISB); 2385 return true; 2386 } 2387 2388 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2389 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2390 } 2391 2392 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2393 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2394 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2395 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2396 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2397 2398 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2399 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2400 return false; 2401 2402 return true; 2403} 2404 2405// Decode a shifted immediate operand. These basically consist 2406// of an 8-bit value, and a 4-bit directive that specifies either 2407// a splat operation or a rotation. 2408static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2409 uint64_t Address, const void *Decoder) { 2410 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2411 if (ctrl == 0) { 2412 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2413 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2414 switch (byte) { 2415 case 0: 2416 Inst.addOperand(MCOperand::CreateImm(imm)); 2417 break; 2418 case 1: 2419 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2420 break; 2421 case 2: 2422 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2423 break; 2424 case 3: 2425 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2426 (imm << 8) | imm)); 2427 break; 2428 } 2429 } else { 2430 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2431 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2432 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2433 Inst.addOperand(MCOperand::CreateImm(imm)); 2434 } 2435 2436 return true; 2437} 2438 2439static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2440 uint64_t Address, const void *Decoder){ 2441 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2442 return true; 2443} 2444 2445static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2446 uint64_t Address, const void *Decoder){ 2447 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2448 return true; 2449} 2450 2451static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, 2452 uint64_t Address, const void *Decoder) { 2453 bool isImm = fieldFromInstruction32(Val, 9, 1); 2454 bool isAdd = fieldFromInstruction32(Val, 8, 1); 2455 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2456 2457 if (!isImm) { 2458 if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false; 2459 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); 2460 } else { 2461 Inst.addOperand(MCOperand::CreateReg(0)); 2462 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); 2463 } 2464 2465 return true; 2466} 2467 2468static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2469 uint64_t Address, const void *Decoder) { 2470 switch (Val) { 2471 default: 2472 return false; 2473 case 0xF: // SY 2474 case 0xE: // ST 2475 case 0xB: // ISH 2476 case 0xA: // ISHST 2477 case 0x7: // NSH 2478 case 0x6: // NSHST 2479 case 0x3: // OSH 2480 case 0x2: // OSHST 2481 break; 2482 } 2483 2484 Inst.addOperand(MCOperand::CreateImm(Val)); 2485 return true; 2486} 2487 2488static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2489 uint64_t Address, const void *Decoder) { 2490 if (!Val) return false; 2491 Inst.addOperand(MCOperand::CreateImm(Val)); 2492 return true; 2493} 2494 2495static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2496 uint64_t Address, const void *Decoder) { 2497 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2498 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2499 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2500 2501 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2502 2503 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2504 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2505 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2506 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2507 2508 return true; 2509} 2510 2511 2512static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2513 uint64_t Address, const void *Decoder) { 2514 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2515 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2516 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2517 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2518 2519 if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2520 2521 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2522 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; 2523 2524 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2525 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2526 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2527 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2528 2529 return true; 2530} 2531 2532static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2533 uint64_t Address, const void *Decoder) { 2534 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2535 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2536 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2537 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2538 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2539 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2540 2541 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2542 2543 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2544 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2545 if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false; 2546 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2547 2548 return true; 2549} 2550 2551static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2552 uint64_t Address, const void *Decoder) { 2553 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2554 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2555 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2556 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2557 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2558 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2559 2560 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2561 2562 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2563 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2564 if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false; 2565 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2566 2567 return true; 2568} 2569