ARMDisassembler.cpp revision a4e3c7fc4ba2d55695b0484480685698132eba20
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "ARM.h" 13#include "ARMSubtarget.h" 14#include "MCTargetDesc/ARMAddressingModes.h" 15#include "MCTargetDesc/ARMMCExpr.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "llvm/MC/EDInstInfo.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCInstrDesc.h" 20#include "llvm/MC/MCExpr.h" 21#include "llvm/MC/MCContext.h" 22#include "llvm/MC/MCDisassembler.h" 23#include "llvm/Support/Debug.h" 24#include "llvm/Support/MemoryObject.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Support/TargetRegistry.h" 27#include "llvm/Support/raw_ostream.h" 28 29using namespace llvm; 30 31typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33namespace { 34/// ARMDisassembler - ARM disassembler for all ARM platforms. 35class ARMDisassembler : public MCDisassembler { 36public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 EDInstInfo *getEDInfo() const; 56private: 57}; 58 59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60class ThumbDisassembler : public MCDisassembler { 61public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 EDInstInfo *getEDInfo() const; 81private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85}; 86} 87 88static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 return false; 101} 102 103 104// Forward declare these because the autogenerated code will reference them. 105// Definitions are further down. 106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129 130static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 131 uint64_t Address, const void *Decoder); 132static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 143static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 144 uint64_t Address, const void *Decoder); 145static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 146 uint64_t Address, const void *Decoder); 147static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 152 uint64_t Address, const void *Decoder); 153static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 154 uint64_t Address, const void *Decoder); 155static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 160static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 161 unsigned Insn, 162 uint64_t Adddress, 163 const void *Decoder); 164static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 181 uint64_t Address, const void *Decoder); 182static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 197 uint64_t Address, const void *Decoder); 198static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 209 uint64_t Address, const void *Decoder); 210static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 211 uint64_t Address, const void *Decoder); 212static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 257 258static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 259 uint64_t Address, const void *Decoder); 260static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 281 uint64_t Address, const void *Decoder); 282static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 283 uint64_t Address, const void *Decoder); 284static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 289 uint64_t Address, const void *Decoder); 290static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 291 uint64_t Address, const void *Decoder); 292static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 293 uint64_t Address, const void *Decoder); 294static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 305 uint64_t Address, const void *Decoder); 306static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 311 uint64_t Address, const void *Decoder); 312static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 313 uint64_t Address, const void *Decoder); 314static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 321 322 323#include "ARMGenDisassemblerTables.inc" 324#include "ARMGenInstrInfo.inc" 325#include "ARMGenEDInfo.inc" 326 327static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 328 return new ARMDisassembler(STI); 329} 330 331static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 332 return new ThumbDisassembler(STI); 333} 334 335EDInstInfo *ARMDisassembler::getEDInfo() const { 336 return instInfoARM; 337} 338 339EDInstInfo *ThumbDisassembler::getEDInfo() const { 340 return instInfoARM; 341} 342 343DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 344 const MemoryObject &Region, 345 uint64_t Address, 346 raw_ostream &os, 347 raw_ostream &cs) const { 348 CommentStream = &cs; 349 350 uint8_t bytes[4]; 351 352 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 353 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 354 355 // We want to read exactly 4 bytes of data. 356 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 357 Size = 0; 358 return MCDisassembler::Fail; 359 } 360 361 // Encoded as a small-endian 32-bit word in the stream. 362 uint32_t insn = (bytes[3] << 24) | 363 (bytes[2] << 16) | 364 (bytes[1] << 8) | 365 (bytes[0] << 0); 366 367 // Calling the auto-generated decoder function. 368 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 369 if (result != MCDisassembler::Fail) { 370 Size = 4; 371 return result; 372 } 373 374 // VFP and NEON instructions, similarly, are shared between ARM 375 // and Thumb modes. 376 MI.clear(); 377 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 378 if (result != MCDisassembler::Fail) { 379 Size = 4; 380 return result; 381 } 382 383 MI.clear(); 384 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 385 if (result != MCDisassembler::Fail) { 386 Size = 4; 387 // Add a fake predicate operand, because we share these instruction 388 // definitions with Thumb2 where these instructions are predicable. 389 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 390 return MCDisassembler::Fail; 391 return result; 392 } 393 394 MI.clear(); 395 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 396 if (result != MCDisassembler::Fail) { 397 Size = 4; 398 // Add a fake predicate operand, because we share these instruction 399 // definitions with Thumb2 where these instructions are predicable. 400 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 401 return MCDisassembler::Fail; 402 return result; 403 } 404 405 MI.clear(); 406 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 407 if (result != MCDisassembler::Fail) { 408 Size = 4; 409 // Add a fake predicate operand, because we share these instruction 410 // definitions with Thumb2 where these instructions are predicable. 411 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 412 return MCDisassembler::Fail; 413 return result; 414 } 415 416 MI.clear(); 417 418 Size = 0; 419 return MCDisassembler::Fail; 420} 421 422namespace llvm { 423extern const MCInstrDesc ARMInsts[]; 424} 425 426/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 427/// immediate Value in the MCInst. The immediate Value has had any PC 428/// adjustment made by the caller. If the instruction is a branch instruction 429/// then isBranch is true, else false. If the getOpInfo() function was set as 430/// part of the setupForSymbolicDisassembly() call then that function is called 431/// to get any symbolic information at the Address for this instruction. If 432/// that returns non-zero then the symbolic information it returns is used to 433/// create an MCExpr and that is added as an operand to the MCInst. If 434/// getOpInfo() returns zero and isBranch is true then a symbol look up for 435/// Value is done and if a symbol is found an MCExpr is created with that, else 436/// an MCExpr with Value is created. This function returns true if it adds an 437/// operand to the MCInst and false otherwise. 438static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 439 bool isBranch, uint64_t InstSize, 440 MCInst &MI, const void *Decoder) { 441 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 442 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 443 if (!getOpInfo) 444 return false; 445 446 struct LLVMOpInfo1 SymbolicOp; 447 SymbolicOp.Value = Value; 448 void *DisInfo = Dis->getDisInfoBlock(); 449 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 450 if (isBranch) { 451 LLVMSymbolLookupCallback SymbolLookUp = 452 Dis->getLLVMSymbolLookupCallback(); 453 if (SymbolLookUp) { 454 uint64_t ReferenceType; 455 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 456 const char *ReferenceName; 457 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 458 &ReferenceName); 459 if (Name) { 460 SymbolicOp.AddSymbol.Name = Name; 461 SymbolicOp.AddSymbol.Present = true; 462 SymbolicOp.Value = 0; 463 } 464 else { 465 SymbolicOp.Value = Value; 466 } 467 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 468 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 469 } 470 else { 471 return false; 472 } 473 } 474 else { 475 return false; 476 } 477 } 478 479 MCContext *Ctx = Dis->getMCContext(); 480 const MCExpr *Add = NULL; 481 if (SymbolicOp.AddSymbol.Present) { 482 if (SymbolicOp.AddSymbol.Name) { 483 StringRef Name(SymbolicOp.AddSymbol.Name); 484 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 485 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 486 } else { 487 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 488 } 489 } 490 491 const MCExpr *Sub = NULL; 492 if (SymbolicOp.SubtractSymbol.Present) { 493 if (SymbolicOp.SubtractSymbol.Name) { 494 StringRef Name(SymbolicOp.SubtractSymbol.Name); 495 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 496 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 497 } else { 498 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 499 } 500 } 501 502 const MCExpr *Off = NULL; 503 if (SymbolicOp.Value != 0) 504 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 505 506 const MCExpr *Expr; 507 if (Sub) { 508 const MCExpr *LHS; 509 if (Add) 510 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 511 else 512 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 513 if (Off != 0) 514 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 515 else 516 Expr = LHS; 517 } else if (Add) { 518 if (Off != 0) 519 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 520 else 521 Expr = Add; 522 } else { 523 if (Off != 0) 524 Expr = Off; 525 else 526 Expr = MCConstantExpr::Create(0, *Ctx); 527 } 528 529 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 530 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 531 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 532 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 533 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 534 MI.addOperand(MCOperand::CreateExpr(Expr)); 535 else 536 assert(0 && "bad SymbolicOp.VariantKind"); 537 538 return true; 539} 540 541/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 542/// referenced by a load instruction with the base register that is the Pc. 543/// These can often be values in a literal pool near the Address of the 544/// instruction. The Address of the instruction and its immediate Value are 545/// used as a possible literal pool entry. The SymbolLookUp call back will 546/// return the name of a symbol referenced by the the literal pool's entry if 547/// the referenced address is that of a symbol. Or it will return a pointer to 548/// a literal 'C' string if the referenced address of the literal pool's entry 549/// is an address into a section with 'C' string literals. 550static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 551 const void *Decoder) { 552 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 553 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 554 if (SymbolLookUp) { 555 void *DisInfo = Dis->getDisInfoBlock(); 556 uint64_t ReferenceType; 557 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 558 const char *ReferenceName; 559 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 560 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 561 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 562 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 563 } 564} 565 566// Thumb1 instructions don't have explicit S bits. Rather, they 567// implicitly set CPSR. Since it's not represented in the encoding, the 568// auto-generated decoder won't inject the CPSR operand. We need to fix 569// that as a post-pass. 570static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 571 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 572 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 573 MCInst::iterator I = MI.begin(); 574 for (unsigned i = 0; i < NumOps; ++i, ++I) { 575 if (I == MI.end()) break; 576 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 577 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 579 return; 580 } 581 } 582 583 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 584} 585 586// Most Thumb instructions don't have explicit predicates in the 587// encoding, but rather get their predicates from IT context. We need 588// to fix up the predicate operands using this context information as a 589// post-pass. 590MCDisassembler::DecodeStatus 591ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 592 MCDisassembler::DecodeStatus S = Success; 593 594 // A few instructions actually have predicates encoded in them. Don't 595 // try to overwrite it if we're seeing one of those. 596 switch (MI.getOpcode()) { 597 case ARM::tBcc: 598 case ARM::t2Bcc: 599 case ARM::tCBZ: 600 case ARM::tCBNZ: 601 case ARM::tCPS: 602 case ARM::t2CPS3p: 603 case ARM::t2CPS2p: 604 case ARM::t2CPS1p: 605 case ARM::tMOVSr: 606 case ARM::tSETEND: 607 // Some instructions (mostly conditional branches) are not 608 // allowed in IT blocks. 609 if (!ITBlock.empty()) 610 S = SoftFail; 611 else 612 return Success; 613 break; 614 case ARM::tB: 615 case ARM::t2B: 616 case ARM::t2TBB: 617 case ARM::t2TBH: 618 // Some instructions (mostly unconditional branches) can 619 // only appears at the end of, or outside of, an IT. 620 if (ITBlock.size() > 1) 621 S = SoftFail; 622 break; 623 default: 624 break; 625 } 626 627 // If we're in an IT block, base the predicate on that. Otherwise, 628 // assume a predicate of AL. 629 unsigned CC; 630 if (!ITBlock.empty()) { 631 CC = ITBlock.back(); 632 if (CC == 0xF) 633 CC = ARMCC::AL; 634 ITBlock.pop_back(); 635 } else 636 CC = ARMCC::AL; 637 638 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 639 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 640 MCInst::iterator I = MI.begin(); 641 for (unsigned i = 0; i < NumOps; ++i, ++I) { 642 if (I == MI.end()) break; 643 if (OpInfo[i].isPredicate()) { 644 I = MI.insert(I, MCOperand::CreateImm(CC)); 645 ++I; 646 if (CC == ARMCC::AL) 647 MI.insert(I, MCOperand::CreateReg(0)); 648 else 649 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 650 return S; 651 } 652 } 653 654 I = MI.insert(I, MCOperand::CreateImm(CC)); 655 ++I; 656 if (CC == ARMCC::AL) 657 MI.insert(I, MCOperand::CreateReg(0)); 658 else 659 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 660 661 return S; 662} 663 664// Thumb VFP instructions are a special case. Because we share their 665// encodings between ARM and Thumb modes, and they are predicable in ARM 666// mode, the auto-generated decoder will give them an (incorrect) 667// predicate operand. We need to rewrite these operands based on the IT 668// context as a post-pass. 669void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 670 unsigned CC; 671 if (!ITBlock.empty()) { 672 CC = ITBlock.back(); 673 ITBlock.pop_back(); 674 } else 675 CC = ARMCC::AL; 676 677 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 678 MCInst::iterator I = MI.begin(); 679 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 680 for (unsigned i = 0; i < NumOps; ++i, ++I) { 681 if (OpInfo[i].isPredicate() ) { 682 I->setImm(CC); 683 ++I; 684 if (CC == ARMCC::AL) 685 I->setReg(0); 686 else 687 I->setReg(ARM::CPSR); 688 return; 689 } 690 } 691} 692 693DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 694 const MemoryObject &Region, 695 uint64_t Address, 696 raw_ostream &os, 697 raw_ostream &cs) const { 698 CommentStream = &cs; 699 700 uint8_t bytes[4]; 701 702 assert((STI.getFeatureBits() & ARM::ModeThumb) && 703 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 704 705 // We want to read exactly 2 bytes of data. 706 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 707 Size = 0; 708 return MCDisassembler::Fail; 709 } 710 711 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 712 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 713 if (result != MCDisassembler::Fail) { 714 Size = 2; 715 Check(result, AddThumbPredicate(MI)); 716 return result; 717 } 718 719 MI.clear(); 720 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 721 if (result) { 722 Size = 2; 723 bool InITBlock = !ITBlock.empty(); 724 Check(result, AddThumbPredicate(MI)); 725 AddThumb1SBit(MI, InITBlock); 726 return result; 727 } 728 729 MI.clear(); 730 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 731 if (result != MCDisassembler::Fail) { 732 Size = 2; 733 734 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 735 // the Thumb predicate. 736 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 737 result = MCDisassembler::SoftFail; 738 739 Check(result, AddThumbPredicate(MI)); 740 741 // If we find an IT instruction, we need to parse its condition 742 // code and mask operands so that we can apply them correctly 743 // to the subsequent instructions. 744 if (MI.getOpcode() == ARM::t2IT) { 745 746 // (3 - the number of trailing zeros) is the number of then / else. 747 unsigned firstcond = MI.getOperand(0).getImm(); 748 unsigned Mask = MI.getOperand(1).getImm(); 749 unsigned CondBit0 = Mask >> 4 & 1; 750 unsigned NumTZ = CountTrailingZeros_32(Mask); 751 assert(NumTZ <= 3 && "Invalid IT mask!"); 752 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 753 bool T = ((Mask >> Pos) & 1) == CondBit0; 754 if (T) 755 ITBlock.insert(ITBlock.begin(), firstcond); 756 else 757 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 758 } 759 760 ITBlock.push_back(firstcond); 761 } 762 763 return result; 764 } 765 766 // We want to read exactly 4 bytes of data. 767 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 768 Size = 0; 769 return MCDisassembler::Fail; 770 } 771 772 uint32_t insn32 = (bytes[3] << 8) | 773 (bytes[2] << 0) | 774 (bytes[1] << 24) | 775 (bytes[0] << 16); 776 MI.clear(); 777 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 778 if (result != MCDisassembler::Fail) { 779 Size = 4; 780 bool InITBlock = ITBlock.size(); 781 Check(result, AddThumbPredicate(MI)); 782 AddThumb1SBit(MI, InITBlock); 783 return result; 784 } 785 786 MI.clear(); 787 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 788 if (result != MCDisassembler::Fail) { 789 Size = 4; 790 Check(result, AddThumbPredicate(MI)); 791 return result; 792 } 793 794 MI.clear(); 795 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 796 if (result != MCDisassembler::Fail) { 797 Size = 4; 798 UpdateThumbVFPPredicate(MI); 799 return result; 800 } 801 802 MI.clear(); 803 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 804 if (result != MCDisassembler::Fail) { 805 Size = 4; 806 Check(result, AddThumbPredicate(MI)); 807 return result; 808 } 809 810 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 811 MI.clear(); 812 uint32_t NEONLdStInsn = insn32; 813 NEONLdStInsn &= 0xF0FFFFFF; 814 NEONLdStInsn |= 0x04000000; 815 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 816 if (result != MCDisassembler::Fail) { 817 Size = 4; 818 Check(result, AddThumbPredicate(MI)); 819 return result; 820 } 821 } 822 823 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 824 MI.clear(); 825 uint32_t NEONDataInsn = insn32; 826 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 827 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 828 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 829 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 830 if (result != MCDisassembler::Fail) { 831 Size = 4; 832 Check(result, AddThumbPredicate(MI)); 833 return result; 834 } 835 } 836 837 Size = 0; 838 return MCDisassembler::Fail; 839} 840 841 842extern "C" void LLVMInitializeARMDisassembler() { 843 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 844 createARMDisassembler); 845 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 846 createThumbDisassembler); 847} 848 849static const unsigned GPRDecoderTable[] = { 850 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 851 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 852 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 853 ARM::R12, ARM::SP, ARM::LR, ARM::PC 854}; 855 856static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 857 uint64_t Address, const void *Decoder) { 858 if (RegNo > 15) 859 return MCDisassembler::Fail; 860 861 unsigned Register = GPRDecoderTable[RegNo]; 862 Inst.addOperand(MCOperand::CreateReg(Register)); 863 return MCDisassembler::Success; 864} 865 866static DecodeStatus 867DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 868 uint64_t Address, const void *Decoder) { 869 if (RegNo == 15) return MCDisassembler::Fail; 870 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 871} 872 873static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 874 uint64_t Address, const void *Decoder) { 875 if (RegNo > 7) 876 return MCDisassembler::Fail; 877 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 878} 879 880static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 881 uint64_t Address, const void *Decoder) { 882 unsigned Register = 0; 883 switch (RegNo) { 884 case 0: 885 Register = ARM::R0; 886 break; 887 case 1: 888 Register = ARM::R1; 889 break; 890 case 2: 891 Register = ARM::R2; 892 break; 893 case 3: 894 Register = ARM::R3; 895 break; 896 case 9: 897 Register = ARM::R9; 898 break; 899 case 12: 900 Register = ARM::R12; 901 break; 902 default: 903 return MCDisassembler::Fail; 904 } 905 906 Inst.addOperand(MCOperand::CreateReg(Register)); 907 return MCDisassembler::Success; 908} 909 910static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 911 uint64_t Address, const void *Decoder) { 912 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 913 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 914} 915 916static const unsigned SPRDecoderTable[] = { 917 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 918 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 919 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 920 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 921 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 922 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 923 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 924 ARM::S28, ARM::S29, ARM::S30, ARM::S31 925}; 926 927static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 928 uint64_t Address, const void *Decoder) { 929 if (RegNo > 31) 930 return MCDisassembler::Fail; 931 932 unsigned Register = SPRDecoderTable[RegNo]; 933 Inst.addOperand(MCOperand::CreateReg(Register)); 934 return MCDisassembler::Success; 935} 936 937static const unsigned DPRDecoderTable[] = { 938 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 939 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 940 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 941 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 942 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 943 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 944 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 945 ARM::D28, ARM::D29, ARM::D30, ARM::D31 946}; 947 948static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 949 uint64_t Address, const void *Decoder) { 950 if (RegNo > 31) 951 return MCDisassembler::Fail; 952 953 unsigned Register = DPRDecoderTable[RegNo]; 954 Inst.addOperand(MCOperand::CreateReg(Register)); 955 return MCDisassembler::Success; 956} 957 958static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 959 uint64_t Address, const void *Decoder) { 960 if (RegNo > 7) 961 return MCDisassembler::Fail; 962 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 963} 964 965static DecodeStatus 966DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 967 uint64_t Address, const void *Decoder) { 968 if (RegNo > 15) 969 return MCDisassembler::Fail; 970 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 971} 972 973static const unsigned QPRDecoderTable[] = { 974 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 975 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 976 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 977 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 978}; 979 980 981static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 982 uint64_t Address, const void *Decoder) { 983 if (RegNo > 31) 984 return MCDisassembler::Fail; 985 RegNo >>= 1; 986 987 unsigned Register = QPRDecoderTable[RegNo]; 988 Inst.addOperand(MCOperand::CreateReg(Register)); 989 return MCDisassembler::Success; 990} 991 992static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 993 uint64_t Address, const void *Decoder) { 994 if (Val == 0xF) return MCDisassembler::Fail; 995 // AL predicate is not allowed on Thumb1 branches. 996 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 997 return MCDisassembler::Fail; 998 Inst.addOperand(MCOperand::CreateImm(Val)); 999 if (Val == ARMCC::AL) { 1000 Inst.addOperand(MCOperand::CreateReg(0)); 1001 } else 1002 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1003 return MCDisassembler::Success; 1004} 1005 1006static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1007 uint64_t Address, const void *Decoder) { 1008 if (Val) 1009 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1010 else 1011 Inst.addOperand(MCOperand::CreateReg(0)); 1012 return MCDisassembler::Success; 1013} 1014 1015static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1016 uint64_t Address, const void *Decoder) { 1017 uint32_t imm = Val & 0xFF; 1018 uint32_t rot = (Val & 0xF00) >> 7; 1019 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1020 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1021 return MCDisassembler::Success; 1022} 1023 1024static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1025 uint64_t Address, const void *Decoder) { 1026 DecodeStatus S = MCDisassembler::Success; 1027 1028 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1029 unsigned type = fieldFromInstruction32(Val, 5, 2); 1030 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1031 1032 // Register-immediate 1033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1034 return MCDisassembler::Fail; 1035 1036 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1037 switch (type) { 1038 case 0: 1039 Shift = ARM_AM::lsl; 1040 break; 1041 case 1: 1042 Shift = ARM_AM::lsr; 1043 break; 1044 case 2: 1045 Shift = ARM_AM::asr; 1046 break; 1047 case 3: 1048 Shift = ARM_AM::ror; 1049 break; 1050 } 1051 1052 if (Shift == ARM_AM::ror && imm == 0) 1053 Shift = ARM_AM::rrx; 1054 1055 unsigned Op = Shift | (imm << 3); 1056 Inst.addOperand(MCOperand::CreateImm(Op)); 1057 1058 return S; 1059} 1060 1061static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1062 uint64_t Address, const void *Decoder) { 1063 DecodeStatus S = MCDisassembler::Success; 1064 1065 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1066 unsigned type = fieldFromInstruction32(Val, 5, 2); 1067 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1068 1069 // Register-register 1070 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1071 return MCDisassembler::Fail; 1072 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1073 return MCDisassembler::Fail; 1074 1075 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1076 switch (type) { 1077 case 0: 1078 Shift = ARM_AM::lsl; 1079 break; 1080 case 1: 1081 Shift = ARM_AM::lsr; 1082 break; 1083 case 2: 1084 Shift = ARM_AM::asr; 1085 break; 1086 case 3: 1087 Shift = ARM_AM::ror; 1088 break; 1089 } 1090 1091 Inst.addOperand(MCOperand::CreateImm(Shift)); 1092 1093 return S; 1094} 1095 1096static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1097 uint64_t Address, const void *Decoder) { 1098 DecodeStatus S = MCDisassembler::Success; 1099 1100 bool writebackLoad = false; 1101 unsigned writebackReg = 0; 1102 switch (Inst.getOpcode()) { 1103 default: 1104 break; 1105 case ARM::LDMIA_UPD: 1106 case ARM::LDMDB_UPD: 1107 case ARM::LDMIB_UPD: 1108 case ARM::LDMDA_UPD: 1109 case ARM::t2LDMIA_UPD: 1110 case ARM::t2LDMDB_UPD: 1111 writebackLoad = true; 1112 writebackReg = Inst.getOperand(0).getReg(); 1113 break; 1114 } 1115 1116 // Empty register lists are not allowed. 1117 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1118 for (unsigned i = 0; i < 16; ++i) { 1119 if (Val & (1 << i)) { 1120 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1121 return MCDisassembler::Fail; 1122 // Writeback not allowed if Rn is in the target list. 1123 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1124 Check(S, MCDisassembler::SoftFail); 1125 } 1126 } 1127 1128 return S; 1129} 1130 1131static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1132 uint64_t Address, const void *Decoder) { 1133 DecodeStatus S = MCDisassembler::Success; 1134 1135 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1136 unsigned regs = Val & 0xFF; 1137 1138 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1139 return MCDisassembler::Fail; 1140 for (unsigned i = 0; i < (regs - 1); ++i) { 1141 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1142 return MCDisassembler::Fail; 1143 } 1144 1145 return S; 1146} 1147 1148static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1149 uint64_t Address, const void *Decoder) { 1150 DecodeStatus S = MCDisassembler::Success; 1151 1152 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1153 unsigned regs = (Val & 0xFF) / 2; 1154 1155 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1156 return MCDisassembler::Fail; 1157 for (unsigned i = 0; i < (regs - 1); ++i) { 1158 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1159 return MCDisassembler::Fail; 1160 } 1161 1162 return S; 1163} 1164 1165static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1166 uint64_t Address, const void *Decoder) { 1167 // This operand encodes a mask of contiguous zeros between a specified MSB 1168 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1169 // the mask of all bits LSB-and-lower, and then xor them to create 1170 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1171 // create the final mask. 1172 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1173 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1174 1175 DecodeStatus S = MCDisassembler::Success; 1176 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1177 1178 uint32_t msb_mask = 0xFFFFFFFF; 1179 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1180 uint32_t lsb_mask = (1U << lsb) - 1; 1181 1182 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1183 return S; 1184} 1185 1186static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1187 uint64_t Address, const void *Decoder) { 1188 DecodeStatus S = MCDisassembler::Success; 1189 1190 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1191 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1192 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1193 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1194 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1195 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1196 1197 switch (Inst.getOpcode()) { 1198 case ARM::LDC_OFFSET: 1199 case ARM::LDC_PRE: 1200 case ARM::LDC_POST: 1201 case ARM::LDC_OPTION: 1202 case ARM::LDCL_OFFSET: 1203 case ARM::LDCL_PRE: 1204 case ARM::LDCL_POST: 1205 case ARM::LDCL_OPTION: 1206 case ARM::STC_OFFSET: 1207 case ARM::STC_PRE: 1208 case ARM::STC_POST: 1209 case ARM::STC_OPTION: 1210 case ARM::STCL_OFFSET: 1211 case ARM::STCL_PRE: 1212 case ARM::STCL_POST: 1213 case ARM::STCL_OPTION: 1214 case ARM::t2LDC_OFFSET: 1215 case ARM::t2LDC_PRE: 1216 case ARM::t2LDC_POST: 1217 case ARM::t2LDC_OPTION: 1218 case ARM::t2LDCL_OFFSET: 1219 case ARM::t2LDCL_PRE: 1220 case ARM::t2LDCL_POST: 1221 case ARM::t2LDCL_OPTION: 1222 case ARM::t2STC_OFFSET: 1223 case ARM::t2STC_PRE: 1224 case ARM::t2STC_POST: 1225 case ARM::t2STC_OPTION: 1226 case ARM::t2STCL_OFFSET: 1227 case ARM::t2STCL_PRE: 1228 case ARM::t2STCL_POST: 1229 case ARM::t2STCL_OPTION: 1230 if (coproc == 0xA || coproc == 0xB) 1231 return MCDisassembler::Fail; 1232 break; 1233 default: 1234 break; 1235 } 1236 1237 Inst.addOperand(MCOperand::CreateImm(coproc)); 1238 Inst.addOperand(MCOperand::CreateImm(CRd)); 1239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1240 return MCDisassembler::Fail; 1241 1242 switch (Inst.getOpcode()) { 1243 case ARM::t2LDC2_OFFSET: 1244 case ARM::t2LDC2L_OFFSET: 1245 case ARM::t2LDC2_PRE: 1246 case ARM::t2LDC2L_PRE: 1247 case ARM::t2STC2_OFFSET: 1248 case ARM::t2STC2L_OFFSET: 1249 case ARM::t2STC2_PRE: 1250 case ARM::t2STC2L_PRE: 1251 case ARM::LDC2_OFFSET: 1252 case ARM::LDC2L_OFFSET: 1253 case ARM::LDC2_PRE: 1254 case ARM::LDC2L_PRE: 1255 case ARM::STC2_OFFSET: 1256 case ARM::STC2L_OFFSET: 1257 case ARM::STC2_PRE: 1258 case ARM::STC2L_PRE: 1259 case ARM::t2LDC_OFFSET: 1260 case ARM::t2LDCL_OFFSET: 1261 case ARM::t2LDC_PRE: 1262 case ARM::t2LDCL_PRE: 1263 case ARM::t2STC_OFFSET: 1264 case ARM::t2STCL_OFFSET: 1265 case ARM::t2STC_PRE: 1266 case ARM::t2STCL_PRE: 1267 case ARM::LDC_OFFSET: 1268 case ARM::LDCL_OFFSET: 1269 case ARM::LDC_PRE: 1270 case ARM::LDCL_PRE: 1271 case ARM::STC_OFFSET: 1272 case ARM::STCL_OFFSET: 1273 case ARM::STC_PRE: 1274 case ARM::STCL_PRE: 1275 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1276 Inst.addOperand(MCOperand::CreateImm(imm)); 1277 break; 1278 case ARM::t2LDC2_POST: 1279 case ARM::t2LDC2L_POST: 1280 case ARM::t2STC2_POST: 1281 case ARM::t2STC2L_POST: 1282 case ARM::LDC2_POST: 1283 case ARM::LDC2L_POST: 1284 case ARM::STC2_POST: 1285 case ARM::STC2L_POST: 1286 case ARM::t2LDC_POST: 1287 case ARM::t2LDCL_POST: 1288 case ARM::t2STC_POST: 1289 case ARM::t2STCL_POST: 1290 case ARM::LDC_POST: 1291 case ARM::LDCL_POST: 1292 case ARM::STC_POST: 1293 case ARM::STCL_POST: 1294 imm |= U << 8; 1295 // fall through. 1296 default: 1297 // The 'option' variant doesn't encode 'U' in the immediate since 1298 // the immediate is unsigned [0,255]. 1299 Inst.addOperand(MCOperand::CreateImm(imm)); 1300 break; 1301 } 1302 1303 switch (Inst.getOpcode()) { 1304 case ARM::LDC_OFFSET: 1305 case ARM::LDC_PRE: 1306 case ARM::LDC_POST: 1307 case ARM::LDC_OPTION: 1308 case ARM::LDCL_OFFSET: 1309 case ARM::LDCL_PRE: 1310 case ARM::LDCL_POST: 1311 case ARM::LDCL_OPTION: 1312 case ARM::STC_OFFSET: 1313 case ARM::STC_PRE: 1314 case ARM::STC_POST: 1315 case ARM::STC_OPTION: 1316 case ARM::STCL_OFFSET: 1317 case ARM::STCL_PRE: 1318 case ARM::STCL_POST: 1319 case ARM::STCL_OPTION: 1320 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1321 return MCDisassembler::Fail; 1322 break; 1323 default: 1324 break; 1325 } 1326 1327 return S; 1328} 1329 1330static DecodeStatus 1331DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1332 uint64_t Address, const void *Decoder) { 1333 DecodeStatus S = MCDisassembler::Success; 1334 1335 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1336 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1337 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1338 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1339 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1340 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1341 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1342 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1343 1344 // On stores, the writeback operand precedes Rt. 1345 switch (Inst.getOpcode()) { 1346 case ARM::STR_POST_IMM: 1347 case ARM::STR_POST_REG: 1348 case ARM::STRB_POST_IMM: 1349 case ARM::STRB_POST_REG: 1350 case ARM::STRT_POST_REG: 1351 case ARM::STRT_POST_IMM: 1352 case ARM::STRBT_POST_REG: 1353 case ARM::STRBT_POST_IMM: 1354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1355 return MCDisassembler::Fail; 1356 break; 1357 default: 1358 break; 1359 } 1360 1361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1362 return MCDisassembler::Fail; 1363 1364 // On loads, the writeback operand comes after Rt. 1365 switch (Inst.getOpcode()) { 1366 case ARM::LDR_POST_IMM: 1367 case ARM::LDR_POST_REG: 1368 case ARM::LDRB_POST_IMM: 1369 case ARM::LDRB_POST_REG: 1370 case ARM::LDRBT_POST_REG: 1371 case ARM::LDRBT_POST_IMM: 1372 case ARM::LDRT_POST_REG: 1373 case ARM::LDRT_POST_IMM: 1374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1375 return MCDisassembler::Fail; 1376 break; 1377 default: 1378 break; 1379 } 1380 1381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1382 return MCDisassembler::Fail; 1383 1384 ARM_AM::AddrOpc Op = ARM_AM::add; 1385 if (!fieldFromInstruction32(Insn, 23, 1)) 1386 Op = ARM_AM::sub; 1387 1388 bool writeback = (P == 0) || (W == 1); 1389 unsigned idx_mode = 0; 1390 if (P && writeback) 1391 idx_mode = ARMII::IndexModePre; 1392 else if (!P && writeback) 1393 idx_mode = ARMII::IndexModePost; 1394 1395 if (writeback && (Rn == 15 || Rn == Rt)) 1396 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1397 1398 if (reg) { 1399 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1400 return MCDisassembler::Fail; 1401 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1402 switch( fieldFromInstruction32(Insn, 5, 2)) { 1403 case 0: 1404 Opc = ARM_AM::lsl; 1405 break; 1406 case 1: 1407 Opc = ARM_AM::lsr; 1408 break; 1409 case 2: 1410 Opc = ARM_AM::asr; 1411 break; 1412 case 3: 1413 Opc = ARM_AM::ror; 1414 break; 1415 default: 1416 return MCDisassembler::Fail; 1417 } 1418 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1419 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1420 1421 Inst.addOperand(MCOperand::CreateImm(imm)); 1422 } else { 1423 Inst.addOperand(MCOperand::CreateReg(0)); 1424 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1425 Inst.addOperand(MCOperand::CreateImm(tmp)); 1426 } 1427 1428 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1429 return MCDisassembler::Fail; 1430 1431 return S; 1432} 1433 1434static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1435 uint64_t Address, const void *Decoder) { 1436 DecodeStatus S = MCDisassembler::Success; 1437 1438 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1439 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1440 unsigned type = fieldFromInstruction32(Val, 5, 2); 1441 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1442 unsigned U = fieldFromInstruction32(Val, 12, 1); 1443 1444 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1445 switch (type) { 1446 case 0: 1447 ShOp = ARM_AM::lsl; 1448 break; 1449 case 1: 1450 ShOp = ARM_AM::lsr; 1451 break; 1452 case 2: 1453 ShOp = ARM_AM::asr; 1454 break; 1455 case 3: 1456 ShOp = ARM_AM::ror; 1457 break; 1458 } 1459 1460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1461 return MCDisassembler::Fail; 1462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1463 return MCDisassembler::Fail; 1464 unsigned shift; 1465 if (U) 1466 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1467 else 1468 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1469 Inst.addOperand(MCOperand::CreateImm(shift)); 1470 1471 return S; 1472} 1473 1474static DecodeStatus 1475DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1476 uint64_t Address, const void *Decoder) { 1477 DecodeStatus S = MCDisassembler::Success; 1478 1479 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1480 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1481 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1482 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1483 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1484 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1485 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1486 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1487 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1488 1489 bool writeback = (W == 1) | (P == 0); 1490 1491 // For {LD,ST}RD, Rt must be even, else undefined. 1492 switch (Inst.getOpcode()) { 1493 case ARM::STRD: 1494 case ARM::STRD_PRE: 1495 case ARM::STRD_POST: 1496 case ARM::LDRD: 1497 case ARM::LDRD_PRE: 1498 case ARM::LDRD_POST: 1499 if (Rt & 0x1) return MCDisassembler::Fail; 1500 break; 1501 default: 1502 break; 1503 } 1504 1505 if (writeback) { // Writeback 1506 if (P) 1507 U |= ARMII::IndexModePre << 9; 1508 else 1509 U |= ARMII::IndexModePost << 9; 1510 1511 // On stores, the writeback operand precedes Rt. 1512 switch (Inst.getOpcode()) { 1513 case ARM::STRD: 1514 case ARM::STRD_PRE: 1515 case ARM::STRD_POST: 1516 case ARM::STRH: 1517 case ARM::STRH_PRE: 1518 case ARM::STRH_POST: 1519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1520 return MCDisassembler::Fail; 1521 break; 1522 default: 1523 break; 1524 } 1525 } 1526 1527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1528 return MCDisassembler::Fail; 1529 switch (Inst.getOpcode()) { 1530 case ARM::STRD: 1531 case ARM::STRD_PRE: 1532 case ARM::STRD_POST: 1533 case ARM::LDRD: 1534 case ARM::LDRD_PRE: 1535 case ARM::LDRD_POST: 1536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1537 return MCDisassembler::Fail; 1538 break; 1539 default: 1540 break; 1541 } 1542 1543 if (writeback) { 1544 // On loads, the writeback operand comes after Rt. 1545 switch (Inst.getOpcode()) { 1546 case ARM::LDRD: 1547 case ARM::LDRD_PRE: 1548 case ARM::LDRD_POST: 1549 case ARM::LDRH: 1550 case ARM::LDRH_PRE: 1551 case ARM::LDRH_POST: 1552 case ARM::LDRSH: 1553 case ARM::LDRSH_PRE: 1554 case ARM::LDRSH_POST: 1555 case ARM::LDRSB: 1556 case ARM::LDRSB_PRE: 1557 case ARM::LDRSB_POST: 1558 case ARM::LDRHTr: 1559 case ARM::LDRSBTr: 1560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1561 return MCDisassembler::Fail; 1562 break; 1563 default: 1564 break; 1565 } 1566 } 1567 1568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1569 return MCDisassembler::Fail; 1570 1571 if (type) { 1572 Inst.addOperand(MCOperand::CreateReg(0)); 1573 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1574 } else { 1575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1576 return MCDisassembler::Fail; 1577 Inst.addOperand(MCOperand::CreateImm(U)); 1578 } 1579 1580 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1581 return MCDisassembler::Fail; 1582 1583 return S; 1584} 1585 1586static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1587 uint64_t Address, const void *Decoder) { 1588 DecodeStatus S = MCDisassembler::Success; 1589 1590 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1591 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1592 1593 switch (mode) { 1594 case 0: 1595 mode = ARM_AM::da; 1596 break; 1597 case 1: 1598 mode = ARM_AM::ia; 1599 break; 1600 case 2: 1601 mode = ARM_AM::db; 1602 break; 1603 case 3: 1604 mode = ARM_AM::ib; 1605 break; 1606 } 1607 1608 Inst.addOperand(MCOperand::CreateImm(mode)); 1609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1610 return MCDisassembler::Fail; 1611 1612 return S; 1613} 1614 1615static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1616 unsigned Insn, 1617 uint64_t Address, const void *Decoder) { 1618 DecodeStatus S = MCDisassembler::Success; 1619 1620 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1621 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1622 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1623 1624 if (pred == 0xF) { 1625 switch (Inst.getOpcode()) { 1626 case ARM::LDMDA: 1627 Inst.setOpcode(ARM::RFEDA); 1628 break; 1629 case ARM::LDMDA_UPD: 1630 Inst.setOpcode(ARM::RFEDA_UPD); 1631 break; 1632 case ARM::LDMDB: 1633 Inst.setOpcode(ARM::RFEDB); 1634 break; 1635 case ARM::LDMDB_UPD: 1636 Inst.setOpcode(ARM::RFEDB_UPD); 1637 break; 1638 case ARM::LDMIA: 1639 Inst.setOpcode(ARM::RFEIA); 1640 break; 1641 case ARM::LDMIA_UPD: 1642 Inst.setOpcode(ARM::RFEIA_UPD); 1643 break; 1644 case ARM::LDMIB: 1645 Inst.setOpcode(ARM::RFEIB); 1646 break; 1647 case ARM::LDMIB_UPD: 1648 Inst.setOpcode(ARM::RFEIB_UPD); 1649 break; 1650 case ARM::STMDA: 1651 Inst.setOpcode(ARM::SRSDA); 1652 break; 1653 case ARM::STMDA_UPD: 1654 Inst.setOpcode(ARM::SRSDA_UPD); 1655 break; 1656 case ARM::STMDB: 1657 Inst.setOpcode(ARM::SRSDB); 1658 break; 1659 case ARM::STMDB_UPD: 1660 Inst.setOpcode(ARM::SRSDB_UPD); 1661 break; 1662 case ARM::STMIA: 1663 Inst.setOpcode(ARM::SRSIA); 1664 break; 1665 case ARM::STMIA_UPD: 1666 Inst.setOpcode(ARM::SRSIA_UPD); 1667 break; 1668 case ARM::STMIB: 1669 Inst.setOpcode(ARM::SRSIB); 1670 break; 1671 case ARM::STMIB_UPD: 1672 Inst.setOpcode(ARM::SRSIB_UPD); 1673 break; 1674 default: 1675 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1676 } 1677 1678 // For stores (which become SRS's, the only operand is the mode. 1679 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1680 Inst.addOperand( 1681 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1682 return S; 1683 } 1684 1685 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1686 } 1687 1688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1689 return MCDisassembler::Fail; 1690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1691 return MCDisassembler::Fail; // Tied 1692 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1693 return MCDisassembler::Fail; 1694 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1695 return MCDisassembler::Fail; 1696 1697 return S; 1698} 1699 1700static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1701 uint64_t Address, const void *Decoder) { 1702 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1703 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1704 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1705 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1706 1707 DecodeStatus S = MCDisassembler::Success; 1708 1709 // imod == '01' --> UNPREDICTABLE 1710 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1711 // return failure here. The '01' imod value is unprintable, so there's 1712 // nothing useful we could do even if we returned UNPREDICTABLE. 1713 1714 if (imod == 1) return MCDisassembler::Fail; 1715 1716 if (imod && M) { 1717 Inst.setOpcode(ARM::CPS3p); 1718 Inst.addOperand(MCOperand::CreateImm(imod)); 1719 Inst.addOperand(MCOperand::CreateImm(iflags)); 1720 Inst.addOperand(MCOperand::CreateImm(mode)); 1721 } else if (imod && !M) { 1722 Inst.setOpcode(ARM::CPS2p); 1723 Inst.addOperand(MCOperand::CreateImm(imod)); 1724 Inst.addOperand(MCOperand::CreateImm(iflags)); 1725 if (mode) S = MCDisassembler::SoftFail; 1726 } else if (!imod && M) { 1727 Inst.setOpcode(ARM::CPS1p); 1728 Inst.addOperand(MCOperand::CreateImm(mode)); 1729 if (iflags) S = MCDisassembler::SoftFail; 1730 } else { 1731 // imod == '00' && M == '0' --> UNPREDICTABLE 1732 Inst.setOpcode(ARM::CPS1p); 1733 Inst.addOperand(MCOperand::CreateImm(mode)); 1734 S = MCDisassembler::SoftFail; 1735 } 1736 1737 return S; 1738} 1739 1740static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1741 uint64_t Address, const void *Decoder) { 1742 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1743 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1744 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1745 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1746 1747 DecodeStatus S = MCDisassembler::Success; 1748 1749 // imod == '01' --> UNPREDICTABLE 1750 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1751 // return failure here. The '01' imod value is unprintable, so there's 1752 // nothing useful we could do even if we returned UNPREDICTABLE. 1753 1754 if (imod == 1) return MCDisassembler::Fail; 1755 1756 if (imod && M) { 1757 Inst.setOpcode(ARM::t2CPS3p); 1758 Inst.addOperand(MCOperand::CreateImm(imod)); 1759 Inst.addOperand(MCOperand::CreateImm(iflags)); 1760 Inst.addOperand(MCOperand::CreateImm(mode)); 1761 } else if (imod && !M) { 1762 Inst.setOpcode(ARM::t2CPS2p); 1763 Inst.addOperand(MCOperand::CreateImm(imod)); 1764 Inst.addOperand(MCOperand::CreateImm(iflags)); 1765 if (mode) S = MCDisassembler::SoftFail; 1766 } else if (!imod && M) { 1767 Inst.setOpcode(ARM::t2CPS1p); 1768 Inst.addOperand(MCOperand::CreateImm(mode)); 1769 if (iflags) S = MCDisassembler::SoftFail; 1770 } else { 1771 // imod == '00' && M == '0' --> UNPREDICTABLE 1772 Inst.setOpcode(ARM::t2CPS1p); 1773 Inst.addOperand(MCOperand::CreateImm(mode)); 1774 S = MCDisassembler::SoftFail; 1775 } 1776 1777 return S; 1778} 1779 1780static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1781 uint64_t Address, const void *Decoder) { 1782 DecodeStatus S = MCDisassembler::Success; 1783 1784 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1785 unsigned imm = 0; 1786 1787 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1788 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1789 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1790 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1791 1792 if (Inst.getOpcode() == ARM::t2MOVTi16) 1793 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1796 return MCDisassembler::Fail; 1797 1798 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1799 Inst.addOperand(MCOperand::CreateImm(imm)); 1800 1801 return S; 1802} 1803 1804static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1805 uint64_t Address, const void *Decoder) { 1806 DecodeStatus S = MCDisassembler::Success; 1807 1808 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1809 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1810 unsigned imm = 0; 1811 1812 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1813 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1814 1815 if (Inst.getOpcode() == ARM::MOVTi16) 1816 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1817 return MCDisassembler::Fail; 1818 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1819 return MCDisassembler::Fail; 1820 1821 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1822 Inst.addOperand(MCOperand::CreateImm(imm)); 1823 1824 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1825 return MCDisassembler::Fail; 1826 1827 return S; 1828} 1829 1830static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1831 uint64_t Address, const void *Decoder) { 1832 DecodeStatus S = MCDisassembler::Success; 1833 1834 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1835 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1836 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1837 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1838 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1839 1840 if (pred == 0xF) 1841 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1842 1843 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1844 return MCDisassembler::Fail; 1845 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1846 return MCDisassembler::Fail; 1847 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1848 return MCDisassembler::Fail; 1849 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1850 return MCDisassembler::Fail; 1851 1852 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1853 return MCDisassembler::Fail; 1854 1855 return S; 1856} 1857 1858static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1859 uint64_t Address, const void *Decoder) { 1860 DecodeStatus S = MCDisassembler::Success; 1861 1862 unsigned add = fieldFromInstruction32(Val, 12, 1); 1863 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1864 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1865 1866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1867 return MCDisassembler::Fail; 1868 1869 if (!add) imm *= -1; 1870 if (imm == 0 && !add) imm = INT32_MIN; 1871 Inst.addOperand(MCOperand::CreateImm(imm)); 1872 if (Rn == 15) 1873 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1874 1875 return S; 1876} 1877 1878static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1879 uint64_t Address, const void *Decoder) { 1880 DecodeStatus S = MCDisassembler::Success; 1881 1882 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1883 unsigned U = fieldFromInstruction32(Val, 8, 1); 1884 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1885 1886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1887 return MCDisassembler::Fail; 1888 1889 if (U) 1890 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1891 else 1892 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1893 1894 return S; 1895} 1896 1897static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1898 uint64_t Address, const void *Decoder) { 1899 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1900} 1901 1902static DecodeStatus 1903DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1904 uint64_t Address, const void *Decoder) { 1905 DecodeStatus S = MCDisassembler::Success; 1906 1907 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1908 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1909 1910 if (pred == 0xF) { 1911 Inst.setOpcode(ARM::BLXi); 1912 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1913 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1914 return S; 1915 } 1916 1917 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true, 1918 4, Inst, Decoder)) 1919 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1920 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1921 return MCDisassembler::Fail; 1922 1923 return S; 1924} 1925 1926 1927static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1928 uint64_t Address, const void *Decoder) { 1929 DecodeStatus S = MCDisassembler::Success; 1930 1931 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1932 unsigned align = fieldFromInstruction32(Val, 4, 2); 1933 1934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1935 return MCDisassembler::Fail; 1936 if (!align) 1937 Inst.addOperand(MCOperand::CreateImm(0)); 1938 else 1939 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1940 1941 return S; 1942} 1943 1944static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1945 uint64_t Address, const void *Decoder) { 1946 DecodeStatus S = MCDisassembler::Success; 1947 1948 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1949 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1950 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1951 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1952 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1953 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1954 1955 // First output register 1956 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1957 return MCDisassembler::Fail; 1958 1959 // Second output register 1960 switch (Inst.getOpcode()) { 1961 case ARM::VLD3d8: 1962 case ARM::VLD3d16: 1963 case ARM::VLD3d32: 1964 case ARM::VLD3d8_UPD: 1965 case ARM::VLD3d16_UPD: 1966 case ARM::VLD3d32_UPD: 1967 case ARM::VLD4d8: 1968 case ARM::VLD4d16: 1969 case ARM::VLD4d32: 1970 case ARM::VLD4d8_UPD: 1971 case ARM::VLD4d16_UPD: 1972 case ARM::VLD4d32_UPD: 1973 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 break; 1976 case ARM::VLD3q8: 1977 case ARM::VLD3q16: 1978 case ARM::VLD3q32: 1979 case ARM::VLD3q8_UPD: 1980 case ARM::VLD3q16_UPD: 1981 case ARM::VLD3q32_UPD: 1982 case ARM::VLD4q8: 1983 case ARM::VLD4q16: 1984 case ARM::VLD4q32: 1985 case ARM::VLD4q8_UPD: 1986 case ARM::VLD4q16_UPD: 1987 case ARM::VLD4q32_UPD: 1988 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1989 return MCDisassembler::Fail; 1990 default: 1991 break; 1992 } 1993 1994 // Third output register 1995 switch(Inst.getOpcode()) { 1996 case ARM::VLD3d8: 1997 case ARM::VLD3d16: 1998 case ARM::VLD3d32: 1999 case ARM::VLD3d8_UPD: 2000 case ARM::VLD3d16_UPD: 2001 case ARM::VLD3d32_UPD: 2002 case ARM::VLD4d8: 2003 case ARM::VLD4d16: 2004 case ARM::VLD4d32: 2005 case ARM::VLD4d8_UPD: 2006 case ARM::VLD4d16_UPD: 2007 case ARM::VLD4d32_UPD: 2008 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2009 return MCDisassembler::Fail; 2010 break; 2011 case ARM::VLD3q8: 2012 case ARM::VLD3q16: 2013 case ARM::VLD3q32: 2014 case ARM::VLD3q8_UPD: 2015 case ARM::VLD3q16_UPD: 2016 case ARM::VLD3q32_UPD: 2017 case ARM::VLD4q8: 2018 case ARM::VLD4q16: 2019 case ARM::VLD4q32: 2020 case ARM::VLD4q8_UPD: 2021 case ARM::VLD4q16_UPD: 2022 case ARM::VLD4q32_UPD: 2023 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2024 return MCDisassembler::Fail; 2025 break; 2026 default: 2027 break; 2028 } 2029 2030 // Fourth output register 2031 switch (Inst.getOpcode()) { 2032 case ARM::VLD4d8: 2033 case ARM::VLD4d16: 2034 case ARM::VLD4d32: 2035 case ARM::VLD4d8_UPD: 2036 case ARM::VLD4d16_UPD: 2037 case ARM::VLD4d32_UPD: 2038 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2039 return MCDisassembler::Fail; 2040 break; 2041 case ARM::VLD4q8: 2042 case ARM::VLD4q16: 2043 case ARM::VLD4q32: 2044 case ARM::VLD4q8_UPD: 2045 case ARM::VLD4q16_UPD: 2046 case ARM::VLD4q32_UPD: 2047 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2048 return MCDisassembler::Fail; 2049 break; 2050 default: 2051 break; 2052 } 2053 2054 // Writeback operand 2055 switch (Inst.getOpcode()) { 2056 case ARM::VLD1d8wb_fixed: 2057 case ARM::VLD1d16wb_fixed: 2058 case ARM::VLD1d32wb_fixed: 2059 case ARM::VLD1d64wb_fixed: 2060 case ARM::VLD1d8wb_register: 2061 case ARM::VLD1d16wb_register: 2062 case ARM::VLD1d32wb_register: 2063 case ARM::VLD1d64wb_register: 2064 case ARM::VLD1q8wb_fixed: 2065 case ARM::VLD1q16wb_fixed: 2066 case ARM::VLD1q32wb_fixed: 2067 case ARM::VLD1q64wb_fixed: 2068 case ARM::VLD1q8wb_register: 2069 case ARM::VLD1q16wb_register: 2070 case ARM::VLD1q32wb_register: 2071 case ARM::VLD1q64wb_register: 2072 case ARM::VLD1d8Twb_fixed: 2073 case ARM::VLD1d8Twb_register: 2074 case ARM::VLD1d16Twb_fixed: 2075 case ARM::VLD1d16Twb_register: 2076 case ARM::VLD1d32Twb_fixed: 2077 case ARM::VLD1d32Twb_register: 2078 case ARM::VLD1d64Twb_fixed: 2079 case ARM::VLD1d64Twb_register: 2080 case ARM::VLD1d8Qwb_fixed: 2081 case ARM::VLD1d8Qwb_register: 2082 case ARM::VLD1d16Qwb_fixed: 2083 case ARM::VLD1d16Qwb_register: 2084 case ARM::VLD1d32Qwb_fixed: 2085 case ARM::VLD1d32Qwb_register: 2086 case ARM::VLD1d64Qwb_fixed: 2087 case ARM::VLD1d64Qwb_register: 2088 case ARM::VLD2d8wb_fixed: 2089 case ARM::VLD2d16wb_fixed: 2090 case ARM::VLD2d32wb_fixed: 2091 case ARM::VLD2q8wb_fixed: 2092 case ARM::VLD2q16wb_fixed: 2093 case ARM::VLD2q32wb_fixed: 2094 case ARM::VLD2d8wb_register: 2095 case ARM::VLD2d16wb_register: 2096 case ARM::VLD2d32wb_register: 2097 case ARM::VLD2q8wb_register: 2098 case ARM::VLD2q16wb_register: 2099 case ARM::VLD2q32wb_register: 2100 case ARM::VLD2b8wb_fixed: 2101 case ARM::VLD2b16wb_fixed: 2102 case ARM::VLD2b32wb_fixed: 2103 case ARM::VLD2b8wb_register: 2104 case ARM::VLD2b16wb_register: 2105 case ARM::VLD2b32wb_register: 2106 case ARM::VLD3d8_UPD: 2107 case ARM::VLD3d16_UPD: 2108 case ARM::VLD3d32_UPD: 2109 case ARM::VLD3q8_UPD: 2110 case ARM::VLD3q16_UPD: 2111 case ARM::VLD3q32_UPD: 2112 case ARM::VLD4d8_UPD: 2113 case ARM::VLD4d16_UPD: 2114 case ARM::VLD4d32_UPD: 2115 case ARM::VLD4q8_UPD: 2116 case ARM::VLD4q16_UPD: 2117 case ARM::VLD4q32_UPD: 2118 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2119 return MCDisassembler::Fail; 2120 break; 2121 default: 2122 break; 2123 } 2124 2125 // AddrMode6 Base (register+alignment) 2126 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2127 return MCDisassembler::Fail; 2128 2129 // AddrMode6 Offset (register) 2130 switch (Inst.getOpcode()) { 2131 default: 2132 // The below have been updated to have explicit am6offset split 2133 // between fixed and register offset. For those instructions not 2134 // yet updated, we need to add an additional reg0 operand for the 2135 // fixed variant. 2136 // 2137 // The fixed offset encodes as Rm == 0xd, so we check for that. 2138 if (Rm == 0xd) { 2139 Inst.addOperand(MCOperand::CreateReg(0)); 2140 break; 2141 } 2142 // Fall through to handle the register offset variant. 2143 case ARM::VLD1d8wb_fixed: 2144 case ARM::VLD1d16wb_fixed: 2145 case ARM::VLD1d32wb_fixed: 2146 case ARM::VLD1d64wb_fixed: 2147 case ARM::VLD1d8Twb_fixed: 2148 case ARM::VLD1d16Twb_fixed: 2149 case ARM::VLD1d32Twb_fixed: 2150 case ARM::VLD1d64Twb_fixed: 2151 case ARM::VLD1d8Qwb_fixed: 2152 case ARM::VLD1d16Qwb_fixed: 2153 case ARM::VLD1d32Qwb_fixed: 2154 case ARM::VLD1d64Qwb_fixed: 2155 case ARM::VLD1d8wb_register: 2156 case ARM::VLD1d16wb_register: 2157 case ARM::VLD1d32wb_register: 2158 case ARM::VLD1d64wb_register: 2159 case ARM::VLD1q8wb_fixed: 2160 case ARM::VLD1q16wb_fixed: 2161 case ARM::VLD1q32wb_fixed: 2162 case ARM::VLD1q64wb_fixed: 2163 case ARM::VLD1q8wb_register: 2164 case ARM::VLD1q16wb_register: 2165 case ARM::VLD1q32wb_register: 2166 case ARM::VLD1q64wb_register: 2167 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2168 // variant encodes Rm == 0xf. Anything else is a register offset post- 2169 // increment and we need to add the register operand to the instruction. 2170 if (Rm != 0xD && Rm != 0xF && 2171 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2172 return MCDisassembler::Fail; 2173 break; 2174 } 2175 2176 return S; 2177} 2178 2179static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2180 uint64_t Address, const void *Decoder) { 2181 DecodeStatus S = MCDisassembler::Success; 2182 2183 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2184 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2185 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2186 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2187 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2188 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2189 2190 // Writeback Operand 2191 switch (Inst.getOpcode()) { 2192 case ARM::VST1d8wb_fixed: 2193 case ARM::VST1d16wb_fixed: 2194 case ARM::VST1d32wb_fixed: 2195 case ARM::VST1d64wb_fixed: 2196 case ARM::VST1d8wb_register: 2197 case ARM::VST1d16wb_register: 2198 case ARM::VST1d32wb_register: 2199 case ARM::VST1d64wb_register: 2200 case ARM::VST1q8wb_fixed: 2201 case ARM::VST1q16wb_fixed: 2202 case ARM::VST1q32wb_fixed: 2203 case ARM::VST1q64wb_fixed: 2204 case ARM::VST1q8wb_register: 2205 case ARM::VST1q16wb_register: 2206 case ARM::VST1q32wb_register: 2207 case ARM::VST1q64wb_register: 2208 case ARM::VST1d8Twb_fixed: 2209 case ARM::VST1d16Twb_fixed: 2210 case ARM::VST1d32Twb_fixed: 2211 case ARM::VST1d64Twb_fixed: 2212 case ARM::VST1d8Twb_register: 2213 case ARM::VST1d16Twb_register: 2214 case ARM::VST1d32Twb_register: 2215 case ARM::VST1d64Twb_register: 2216 case ARM::VST1d8Qwb_fixed: 2217 case ARM::VST1d16Qwb_fixed: 2218 case ARM::VST1d32Qwb_fixed: 2219 case ARM::VST1d64Qwb_fixed: 2220 case ARM::VST1d8Qwb_register: 2221 case ARM::VST1d16Qwb_register: 2222 case ARM::VST1d32Qwb_register: 2223 case ARM::VST1d64Qwb_register: 2224 case ARM::VST2d8_UPD: 2225 case ARM::VST2d16_UPD: 2226 case ARM::VST2d32_UPD: 2227 case ARM::VST2q8_UPD: 2228 case ARM::VST2q16_UPD: 2229 case ARM::VST2q32_UPD: 2230 case ARM::VST2b8_UPD: 2231 case ARM::VST2b16_UPD: 2232 case ARM::VST2b32_UPD: 2233 case ARM::VST3d8_UPD: 2234 case ARM::VST3d16_UPD: 2235 case ARM::VST3d32_UPD: 2236 case ARM::VST3q8_UPD: 2237 case ARM::VST3q16_UPD: 2238 case ARM::VST3q32_UPD: 2239 case ARM::VST4d8_UPD: 2240 case ARM::VST4d16_UPD: 2241 case ARM::VST4d32_UPD: 2242 case ARM::VST4q8_UPD: 2243 case ARM::VST4q16_UPD: 2244 case ARM::VST4q32_UPD: 2245 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2246 return MCDisassembler::Fail; 2247 break; 2248 default: 2249 break; 2250 } 2251 2252 // AddrMode6 Base (register+alignment) 2253 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2254 return MCDisassembler::Fail; 2255 2256 // AddrMode6 Offset (register) 2257 switch (Inst.getOpcode()) { 2258 default: 2259 if (Rm == 0xD) 2260 Inst.addOperand(MCOperand::CreateReg(0)); 2261 else if (Rm != 0xF) { 2262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2263 return MCDisassembler::Fail; 2264 } 2265 break; 2266 case ARM::VST1d8wb_fixed: 2267 case ARM::VST1d16wb_fixed: 2268 case ARM::VST1d32wb_fixed: 2269 case ARM::VST1d64wb_fixed: 2270 case ARM::VST1q8wb_fixed: 2271 case ARM::VST1q16wb_fixed: 2272 case ARM::VST1q32wb_fixed: 2273 case ARM::VST1q64wb_fixed: 2274 break; 2275 } 2276 2277 2278 // First input register 2279 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2280 return MCDisassembler::Fail; 2281 2282 // Second input register 2283 switch (Inst.getOpcode()) { 2284 case ARM::VST2d8: 2285 case ARM::VST2d16: 2286 case ARM::VST2d32: 2287 case ARM::VST2d8_UPD: 2288 case ARM::VST2d16_UPD: 2289 case ARM::VST2d32_UPD: 2290 case ARM::VST2q8: 2291 case ARM::VST2q16: 2292 case ARM::VST2q32: 2293 case ARM::VST2q8_UPD: 2294 case ARM::VST2q16_UPD: 2295 case ARM::VST2q32_UPD: 2296 case ARM::VST3d8: 2297 case ARM::VST3d16: 2298 case ARM::VST3d32: 2299 case ARM::VST3d8_UPD: 2300 case ARM::VST3d16_UPD: 2301 case ARM::VST3d32_UPD: 2302 case ARM::VST4d8: 2303 case ARM::VST4d16: 2304 case ARM::VST4d32: 2305 case ARM::VST4d8_UPD: 2306 case ARM::VST4d16_UPD: 2307 case ARM::VST4d32_UPD: 2308 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2309 return MCDisassembler::Fail; 2310 break; 2311 case ARM::VST2b8: 2312 case ARM::VST2b16: 2313 case ARM::VST2b32: 2314 case ARM::VST2b8_UPD: 2315 case ARM::VST2b16_UPD: 2316 case ARM::VST2b32_UPD: 2317 case ARM::VST3q8: 2318 case ARM::VST3q16: 2319 case ARM::VST3q32: 2320 case ARM::VST3q8_UPD: 2321 case ARM::VST3q16_UPD: 2322 case ARM::VST3q32_UPD: 2323 case ARM::VST4q8: 2324 case ARM::VST4q16: 2325 case ARM::VST4q32: 2326 case ARM::VST4q8_UPD: 2327 case ARM::VST4q16_UPD: 2328 case ARM::VST4q32_UPD: 2329 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2330 return MCDisassembler::Fail; 2331 break; 2332 default: 2333 break; 2334 } 2335 2336 // Third input register 2337 switch (Inst.getOpcode()) { 2338 case ARM::VST2q8: 2339 case ARM::VST2q16: 2340 case ARM::VST2q32: 2341 case ARM::VST2q8_UPD: 2342 case ARM::VST2q16_UPD: 2343 case ARM::VST2q32_UPD: 2344 case ARM::VST3d8: 2345 case ARM::VST3d16: 2346 case ARM::VST3d32: 2347 case ARM::VST3d8_UPD: 2348 case ARM::VST3d16_UPD: 2349 case ARM::VST3d32_UPD: 2350 case ARM::VST4d8: 2351 case ARM::VST4d16: 2352 case ARM::VST4d32: 2353 case ARM::VST4d8_UPD: 2354 case ARM::VST4d16_UPD: 2355 case ARM::VST4d32_UPD: 2356 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2357 return MCDisassembler::Fail; 2358 break; 2359 case ARM::VST3q8: 2360 case ARM::VST3q16: 2361 case ARM::VST3q32: 2362 case ARM::VST3q8_UPD: 2363 case ARM::VST3q16_UPD: 2364 case ARM::VST3q32_UPD: 2365 case ARM::VST4q8: 2366 case ARM::VST4q16: 2367 case ARM::VST4q32: 2368 case ARM::VST4q8_UPD: 2369 case ARM::VST4q16_UPD: 2370 case ARM::VST4q32_UPD: 2371 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2372 return MCDisassembler::Fail; 2373 break; 2374 default: 2375 break; 2376 } 2377 2378 // Fourth input register 2379 switch (Inst.getOpcode()) { 2380 case ARM::VST2q8: 2381 case ARM::VST2q16: 2382 case ARM::VST2q32: 2383 case ARM::VST2q8_UPD: 2384 case ARM::VST2q16_UPD: 2385 case ARM::VST2q32_UPD: 2386 case ARM::VST4d8: 2387 case ARM::VST4d16: 2388 case ARM::VST4d32: 2389 case ARM::VST4d8_UPD: 2390 case ARM::VST4d16_UPD: 2391 case ARM::VST4d32_UPD: 2392 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2393 return MCDisassembler::Fail; 2394 break; 2395 case ARM::VST4q8: 2396 case ARM::VST4q16: 2397 case ARM::VST4q32: 2398 case ARM::VST4q8_UPD: 2399 case ARM::VST4q16_UPD: 2400 case ARM::VST4q32_UPD: 2401 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2402 return MCDisassembler::Fail; 2403 break; 2404 default: 2405 break; 2406 } 2407 2408 return S; 2409} 2410 2411static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2412 uint64_t Address, const void *Decoder) { 2413 DecodeStatus S = MCDisassembler::Success; 2414 2415 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2416 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2417 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2418 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2419 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2420 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2421 2422 align *= (1 << size); 2423 2424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2425 return MCDisassembler::Fail; 2426 if (Rm != 0xF) { 2427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2428 return MCDisassembler::Fail; 2429 } 2430 2431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2432 return MCDisassembler::Fail; 2433 Inst.addOperand(MCOperand::CreateImm(align)); 2434 2435 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2436 // variant encodes Rm == 0xf. Anything else is a register offset post- 2437 // increment and we need to add the register operand to the instruction. 2438 if (Rm != 0xD && Rm != 0xF && 2439 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2440 return MCDisassembler::Fail; 2441 2442 return S; 2443} 2444 2445static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2446 uint64_t Address, const void *Decoder) { 2447 DecodeStatus S = MCDisassembler::Success; 2448 2449 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2450 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2451 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2452 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2453 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2454 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2455 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2456 align *= 2*size; 2457 2458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2459 return MCDisassembler::Fail; 2460 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2461 return MCDisassembler::Fail; 2462 if (Rm != 0xF) { 2463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2464 return MCDisassembler::Fail; 2465 } 2466 2467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2468 return MCDisassembler::Fail; 2469 Inst.addOperand(MCOperand::CreateImm(align)); 2470 2471 if (Rm == 0xD) 2472 Inst.addOperand(MCOperand::CreateReg(0)); 2473 else if (Rm != 0xF) { 2474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2475 return MCDisassembler::Fail; 2476 } 2477 2478 return S; 2479} 2480 2481static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2482 uint64_t Address, const void *Decoder) { 2483 DecodeStatus S = MCDisassembler::Success; 2484 2485 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2486 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2487 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2488 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2489 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2490 2491 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2492 return MCDisassembler::Fail; 2493 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2494 return MCDisassembler::Fail; 2495 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2496 return MCDisassembler::Fail; 2497 if (Rm != 0xF) { 2498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2499 return MCDisassembler::Fail; 2500 } 2501 2502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2503 return MCDisassembler::Fail; 2504 Inst.addOperand(MCOperand::CreateImm(0)); 2505 2506 if (Rm == 0xD) 2507 Inst.addOperand(MCOperand::CreateReg(0)); 2508 else if (Rm != 0xF) { 2509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2510 return MCDisassembler::Fail; 2511 } 2512 2513 return S; 2514} 2515 2516static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2517 uint64_t Address, const void *Decoder) { 2518 DecodeStatus S = MCDisassembler::Success; 2519 2520 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2521 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2522 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2523 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2524 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2525 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2526 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2527 2528 if (size == 0x3) { 2529 size = 4; 2530 align = 16; 2531 } else { 2532 if (size == 2) { 2533 size = 1 << size; 2534 align *= 8; 2535 } else { 2536 size = 1 << size; 2537 align *= 4*size; 2538 } 2539 } 2540 2541 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2542 return MCDisassembler::Fail; 2543 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2544 return MCDisassembler::Fail; 2545 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2546 return MCDisassembler::Fail; 2547 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2548 return MCDisassembler::Fail; 2549 if (Rm != 0xF) { 2550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2551 return MCDisassembler::Fail; 2552 } 2553 2554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2555 return MCDisassembler::Fail; 2556 Inst.addOperand(MCOperand::CreateImm(align)); 2557 2558 if (Rm == 0xD) 2559 Inst.addOperand(MCOperand::CreateReg(0)); 2560 else if (Rm != 0xF) { 2561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2562 return MCDisassembler::Fail; 2563 } 2564 2565 return S; 2566} 2567 2568static DecodeStatus 2569DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2570 uint64_t Address, const void *Decoder) { 2571 DecodeStatus S = MCDisassembler::Success; 2572 2573 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2574 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2575 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2576 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2577 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2578 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2579 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2580 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2581 2582 if (Q) { 2583 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2584 return MCDisassembler::Fail; 2585 } else { 2586 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2587 return MCDisassembler::Fail; 2588 } 2589 2590 Inst.addOperand(MCOperand::CreateImm(imm)); 2591 2592 switch (Inst.getOpcode()) { 2593 case ARM::VORRiv4i16: 2594 case ARM::VORRiv2i32: 2595 case ARM::VBICiv4i16: 2596 case ARM::VBICiv2i32: 2597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2598 return MCDisassembler::Fail; 2599 break; 2600 case ARM::VORRiv8i16: 2601 case ARM::VORRiv4i32: 2602 case ARM::VBICiv8i16: 2603 case ARM::VBICiv4i32: 2604 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2605 return MCDisassembler::Fail; 2606 break; 2607 default: 2608 break; 2609 } 2610 2611 return S; 2612} 2613 2614static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2615 uint64_t Address, const void *Decoder) { 2616 DecodeStatus S = MCDisassembler::Success; 2617 2618 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2619 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2620 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2621 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2622 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2623 2624 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2625 return MCDisassembler::Fail; 2626 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2627 return MCDisassembler::Fail; 2628 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2629 2630 return S; 2631} 2632 2633static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2634 uint64_t Address, const void *Decoder) { 2635 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2636 return MCDisassembler::Success; 2637} 2638 2639static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2640 uint64_t Address, const void *Decoder) { 2641 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2642 return MCDisassembler::Success; 2643} 2644 2645static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2646 uint64_t Address, const void *Decoder) { 2647 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2648 return MCDisassembler::Success; 2649} 2650 2651static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2652 uint64_t Address, const void *Decoder) { 2653 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2654 return MCDisassembler::Success; 2655} 2656 2657static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2658 uint64_t Address, const void *Decoder) { 2659 DecodeStatus S = MCDisassembler::Success; 2660 2661 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2662 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2663 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2664 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2665 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2666 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2667 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2668 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2669 2670 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2671 return MCDisassembler::Fail; 2672 if (op) { 2673 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2674 return MCDisassembler::Fail; // Writeback 2675 } 2676 2677 for (unsigned i = 0; i < length; ++i) { 2678 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2679 return MCDisassembler::Fail; 2680 } 2681 2682 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2683 return MCDisassembler::Fail; 2684 2685 return S; 2686} 2687 2688static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2689 uint64_t Address, const void *Decoder) { 2690 DecodeStatus S = MCDisassembler::Success; 2691 2692 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2693 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2694 2695 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2696 return MCDisassembler::Fail; 2697 2698 switch(Inst.getOpcode()) { 2699 default: 2700 return MCDisassembler::Fail; 2701 case ARM::tADR: 2702 break; // tADR does not explicitly represent the PC as an operand. 2703 case ARM::tADDrSPi: 2704 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2705 break; 2706 } 2707 2708 Inst.addOperand(MCOperand::CreateImm(imm)); 2709 return S; 2710} 2711 2712static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2713 uint64_t Address, const void *Decoder) { 2714 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2715 return MCDisassembler::Success; 2716} 2717 2718static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2719 uint64_t Address, const void *Decoder) { 2720 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2721 return MCDisassembler::Success; 2722} 2723 2724static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2725 uint64_t Address, const void *Decoder) { 2726 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2727 return MCDisassembler::Success; 2728} 2729 2730static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2731 uint64_t Address, const void *Decoder) { 2732 DecodeStatus S = MCDisassembler::Success; 2733 2734 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2735 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2736 2737 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2738 return MCDisassembler::Fail; 2739 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2740 return MCDisassembler::Fail; 2741 2742 return S; 2743} 2744 2745static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2746 uint64_t Address, const void *Decoder) { 2747 DecodeStatus S = MCDisassembler::Success; 2748 2749 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2750 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2751 2752 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2753 return MCDisassembler::Fail; 2754 Inst.addOperand(MCOperand::CreateImm(imm)); 2755 2756 return S; 2757} 2758 2759static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2760 uint64_t Address, const void *Decoder) { 2761 unsigned imm = Val << 2; 2762 2763 Inst.addOperand(MCOperand::CreateImm(imm)); 2764 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2765 2766 return MCDisassembler::Success; 2767} 2768 2769static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2770 uint64_t Address, const void *Decoder) { 2771 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2772 Inst.addOperand(MCOperand::CreateImm(Val)); 2773 2774 return MCDisassembler::Success; 2775} 2776 2777static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2778 uint64_t Address, const void *Decoder) { 2779 DecodeStatus S = MCDisassembler::Success; 2780 2781 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2782 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2783 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2784 2785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2786 return MCDisassembler::Fail; 2787 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 Inst.addOperand(MCOperand::CreateImm(imm)); 2790 2791 return S; 2792} 2793 2794static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2795 uint64_t Address, const void *Decoder) { 2796 DecodeStatus S = MCDisassembler::Success; 2797 2798 switch (Inst.getOpcode()) { 2799 case ARM::t2PLDs: 2800 case ARM::t2PLDWs: 2801 case ARM::t2PLIs: 2802 break; 2803 default: { 2804 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2805 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2806 return MCDisassembler::Fail; 2807 } 2808 } 2809 2810 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2811 if (Rn == 0xF) { 2812 switch (Inst.getOpcode()) { 2813 case ARM::t2LDRBs: 2814 Inst.setOpcode(ARM::t2LDRBpci); 2815 break; 2816 case ARM::t2LDRHs: 2817 Inst.setOpcode(ARM::t2LDRHpci); 2818 break; 2819 case ARM::t2LDRSHs: 2820 Inst.setOpcode(ARM::t2LDRSHpci); 2821 break; 2822 case ARM::t2LDRSBs: 2823 Inst.setOpcode(ARM::t2LDRSBpci); 2824 break; 2825 case ARM::t2PLDs: 2826 Inst.setOpcode(ARM::t2PLDi12); 2827 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2828 break; 2829 default: 2830 return MCDisassembler::Fail; 2831 } 2832 2833 int imm = fieldFromInstruction32(Insn, 0, 12); 2834 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2835 Inst.addOperand(MCOperand::CreateImm(imm)); 2836 2837 return S; 2838 } 2839 2840 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2841 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2842 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2843 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2844 return MCDisassembler::Fail; 2845 2846 return S; 2847} 2848 2849static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2850 uint64_t Address, const void *Decoder) { 2851 int imm = Val & 0xFF; 2852 if (!(Val & 0x100)) imm *= -1; 2853 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2854 2855 return MCDisassembler::Success; 2856} 2857 2858static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2859 uint64_t Address, const void *Decoder) { 2860 DecodeStatus S = MCDisassembler::Success; 2861 2862 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2863 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2864 2865 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2866 return MCDisassembler::Fail; 2867 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2868 return MCDisassembler::Fail; 2869 2870 return S; 2871} 2872 2873static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2874 uint64_t Address, const void *Decoder) { 2875 DecodeStatus S = MCDisassembler::Success; 2876 2877 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2878 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2879 2880 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2881 return MCDisassembler::Fail; 2882 2883 Inst.addOperand(MCOperand::CreateImm(imm)); 2884 2885 return S; 2886} 2887 2888static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2889 uint64_t Address, const void *Decoder) { 2890 int imm = Val & 0xFF; 2891 if (Val == 0) 2892 imm = INT32_MIN; 2893 else if (!(Val & 0x100)) 2894 imm *= -1; 2895 Inst.addOperand(MCOperand::CreateImm(imm)); 2896 2897 return MCDisassembler::Success; 2898} 2899 2900 2901static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2902 uint64_t Address, const void *Decoder) { 2903 DecodeStatus S = MCDisassembler::Success; 2904 2905 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2906 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2907 2908 // Some instructions always use an additive offset. 2909 switch (Inst.getOpcode()) { 2910 case ARM::t2LDRT: 2911 case ARM::t2LDRBT: 2912 case ARM::t2LDRHT: 2913 case ARM::t2LDRSBT: 2914 case ARM::t2LDRSHT: 2915 case ARM::t2STRT: 2916 case ARM::t2STRBT: 2917 case ARM::t2STRHT: 2918 imm |= 0x100; 2919 break; 2920 default: 2921 break; 2922 } 2923 2924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2925 return MCDisassembler::Fail; 2926 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2927 return MCDisassembler::Fail; 2928 2929 return S; 2930} 2931 2932static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2933 uint64_t Address, const void *Decoder) { 2934 DecodeStatus S = MCDisassembler::Success; 2935 2936 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2937 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2938 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2939 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2940 addr |= Rn << 9; 2941 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2942 2943 if (!load) { 2944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2945 return MCDisassembler::Fail; 2946 } 2947 2948 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2949 return MCDisassembler::Fail; 2950 2951 if (load) { 2952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2953 return MCDisassembler::Fail; 2954 } 2955 2956 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 2959 return S; 2960} 2961 2962static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2963 uint64_t Address, const void *Decoder) { 2964 DecodeStatus S = MCDisassembler::Success; 2965 2966 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2967 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2968 2969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2970 return MCDisassembler::Fail; 2971 Inst.addOperand(MCOperand::CreateImm(imm)); 2972 2973 return S; 2974} 2975 2976 2977static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2978 uint64_t Address, const void *Decoder) { 2979 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2980 2981 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2982 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2983 Inst.addOperand(MCOperand::CreateImm(imm)); 2984 2985 return MCDisassembler::Success; 2986} 2987 2988static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2989 uint64_t Address, const void *Decoder) { 2990 DecodeStatus S = MCDisassembler::Success; 2991 2992 if (Inst.getOpcode() == ARM::tADDrSP) { 2993 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2994 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2995 2996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2997 return MCDisassembler::Fail; 2998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2999 return MCDisassembler::Fail; 3000 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3001 } else if (Inst.getOpcode() == ARM::tADDspr) { 3002 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3003 3004 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3005 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3006 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3007 return MCDisassembler::Fail; 3008 } 3009 3010 return S; 3011} 3012 3013static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 3014 uint64_t Address, const void *Decoder) { 3015 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3016 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3017 3018 Inst.addOperand(MCOperand::CreateImm(imod)); 3019 Inst.addOperand(MCOperand::CreateImm(flags)); 3020 3021 return MCDisassembler::Success; 3022} 3023 3024static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3025 uint64_t Address, const void *Decoder) { 3026 DecodeStatus S = MCDisassembler::Success; 3027 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3028 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3029 3030 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3031 return MCDisassembler::Fail; 3032 Inst.addOperand(MCOperand::CreateImm(add)); 3033 3034 return S; 3035} 3036 3037static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3038 uint64_t Address, const void *Decoder) { 3039 if (!tryAddingSymbolicOperand(Address, 3040 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3041 true, 4, Inst, Decoder)) 3042 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3043 return MCDisassembler::Success; 3044} 3045 3046static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3047 uint64_t Address, const void *Decoder) { 3048 if (Val == 0xA || Val == 0xB) 3049 return MCDisassembler::Fail; 3050 3051 Inst.addOperand(MCOperand::CreateImm(Val)); 3052 return MCDisassembler::Success; 3053} 3054 3055static DecodeStatus 3056DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3057 uint64_t Address, const void *Decoder) { 3058 DecodeStatus S = MCDisassembler::Success; 3059 3060 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3061 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3062 3063 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3064 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3065 return MCDisassembler::Fail; 3066 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3067 return MCDisassembler::Fail; 3068 return S; 3069} 3070 3071static DecodeStatus 3072DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3073 uint64_t Address, const void *Decoder) { 3074 DecodeStatus S = MCDisassembler::Success; 3075 3076 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3077 if (pred == 0xE || pred == 0xF) { 3078 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3079 switch (opc) { 3080 default: 3081 return MCDisassembler::Fail; 3082 case 0xf3bf8f4: 3083 Inst.setOpcode(ARM::t2DSB); 3084 break; 3085 case 0xf3bf8f5: 3086 Inst.setOpcode(ARM::t2DMB); 3087 break; 3088 case 0xf3bf8f6: 3089 Inst.setOpcode(ARM::t2ISB); 3090 break; 3091 } 3092 3093 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3094 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3095 } 3096 3097 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3098 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3099 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3100 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3101 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3102 3103 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3104 return MCDisassembler::Fail; 3105 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 3108 return S; 3109} 3110 3111// Decode a shifted immediate operand. These basically consist 3112// of an 8-bit value, and a 4-bit directive that specifies either 3113// a splat operation or a rotation. 3114static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3115 uint64_t Address, const void *Decoder) { 3116 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3117 if (ctrl == 0) { 3118 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3119 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3120 switch (byte) { 3121 case 0: 3122 Inst.addOperand(MCOperand::CreateImm(imm)); 3123 break; 3124 case 1: 3125 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3126 break; 3127 case 2: 3128 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3129 break; 3130 case 3: 3131 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3132 (imm << 8) | imm)); 3133 break; 3134 } 3135 } else { 3136 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3137 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3138 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3139 Inst.addOperand(MCOperand::CreateImm(imm)); 3140 } 3141 3142 return MCDisassembler::Success; 3143} 3144 3145static DecodeStatus 3146DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3147 uint64_t Address, const void *Decoder){ 3148 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3149 return MCDisassembler::Success; 3150} 3151 3152static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3153 uint64_t Address, const void *Decoder){ 3154 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3155 return MCDisassembler::Success; 3156} 3157 3158static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3159 uint64_t Address, const void *Decoder) { 3160 switch (Val) { 3161 default: 3162 return MCDisassembler::Fail; 3163 case 0xF: // SY 3164 case 0xE: // ST 3165 case 0xB: // ISH 3166 case 0xA: // ISHST 3167 case 0x7: // NSH 3168 case 0x6: // NSHST 3169 case 0x3: // OSH 3170 case 0x2: // OSHST 3171 break; 3172 } 3173 3174 Inst.addOperand(MCOperand::CreateImm(Val)); 3175 return MCDisassembler::Success; 3176} 3177 3178static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3179 uint64_t Address, const void *Decoder) { 3180 if (!Val) return MCDisassembler::Fail; 3181 Inst.addOperand(MCOperand::CreateImm(Val)); 3182 return MCDisassembler::Success; 3183} 3184 3185static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3186 uint64_t Address, const void *Decoder) { 3187 DecodeStatus S = MCDisassembler::Success; 3188 3189 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3190 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3191 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3192 3193 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3194 3195 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3196 return MCDisassembler::Fail; 3197 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3198 return MCDisassembler::Fail; 3199 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3200 return MCDisassembler::Fail; 3201 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3202 return MCDisassembler::Fail; 3203 3204 return S; 3205} 3206 3207 3208static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3209 uint64_t Address, const void *Decoder){ 3210 DecodeStatus S = MCDisassembler::Success; 3211 3212 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3213 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3214 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3215 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3216 3217 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3218 return MCDisassembler::Fail; 3219 3220 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3221 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3222 3223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3224 return MCDisassembler::Fail; 3225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3226 return MCDisassembler::Fail; 3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 3232 return S; 3233} 3234 3235static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3236 uint64_t Address, const void *Decoder) { 3237 DecodeStatus S = MCDisassembler::Success; 3238 3239 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3240 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3241 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3242 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3243 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3244 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3245 3246 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3247 3248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3249 return MCDisassembler::Fail; 3250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3251 return MCDisassembler::Fail; 3252 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3253 return MCDisassembler::Fail; 3254 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3255 return MCDisassembler::Fail; 3256 3257 return S; 3258} 3259 3260static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3261 uint64_t Address, const void *Decoder) { 3262 DecodeStatus S = MCDisassembler::Success; 3263 3264 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3265 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3266 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3267 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3268 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3269 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3270 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3271 3272 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3273 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3274 3275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3276 return MCDisassembler::Fail; 3277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3278 return MCDisassembler::Fail; 3279 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3280 return MCDisassembler::Fail; 3281 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3282 return MCDisassembler::Fail; 3283 3284 return S; 3285} 3286 3287 3288static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3289 uint64_t Address, const void *Decoder) { 3290 DecodeStatus S = MCDisassembler::Success; 3291 3292 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3293 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3294 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3295 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3296 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3297 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3298 3299 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3300 3301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3302 return MCDisassembler::Fail; 3303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3304 return MCDisassembler::Fail; 3305 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3308 return MCDisassembler::Fail; 3309 3310 return S; 3311} 3312 3313static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3314 uint64_t Address, const void *Decoder) { 3315 DecodeStatus S = MCDisassembler::Success; 3316 3317 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3318 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3319 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3320 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3321 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3322 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3323 3324 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3325 3326 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3327 return MCDisassembler::Fail; 3328 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3329 return MCDisassembler::Fail; 3330 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3331 return MCDisassembler::Fail; 3332 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3333 return MCDisassembler::Fail; 3334 3335 return S; 3336} 3337 3338static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3339 uint64_t Address, const void *Decoder) { 3340 DecodeStatus S = MCDisassembler::Success; 3341 3342 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3343 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3344 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3345 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3346 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3347 3348 unsigned align = 0; 3349 unsigned index = 0; 3350 switch (size) { 3351 default: 3352 return MCDisassembler::Fail; 3353 case 0: 3354 if (fieldFromInstruction32(Insn, 4, 1)) 3355 return MCDisassembler::Fail; // UNDEFINED 3356 index = fieldFromInstruction32(Insn, 5, 3); 3357 break; 3358 case 1: 3359 if (fieldFromInstruction32(Insn, 5, 1)) 3360 return MCDisassembler::Fail; // UNDEFINED 3361 index = fieldFromInstruction32(Insn, 6, 2); 3362 if (fieldFromInstruction32(Insn, 4, 1)) 3363 align = 2; 3364 break; 3365 case 2: 3366 if (fieldFromInstruction32(Insn, 6, 1)) 3367 return MCDisassembler::Fail; // UNDEFINED 3368 index = fieldFromInstruction32(Insn, 7, 1); 3369 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3370 align = 4; 3371 } 3372 3373 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3374 return MCDisassembler::Fail; 3375 if (Rm != 0xF) { // Writeback 3376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3377 return MCDisassembler::Fail; 3378 } 3379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3380 return MCDisassembler::Fail; 3381 Inst.addOperand(MCOperand::CreateImm(align)); 3382 if (Rm != 0xF) { 3383 if (Rm != 0xD) { 3384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3385 return MCDisassembler::Fail; 3386 } else 3387 Inst.addOperand(MCOperand::CreateReg(0)); 3388 } 3389 3390 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3391 return MCDisassembler::Fail; 3392 Inst.addOperand(MCOperand::CreateImm(index)); 3393 3394 return S; 3395} 3396 3397static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3398 uint64_t Address, const void *Decoder) { 3399 DecodeStatus S = MCDisassembler::Success; 3400 3401 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3402 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3403 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3404 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3405 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3406 3407 unsigned align = 0; 3408 unsigned index = 0; 3409 switch (size) { 3410 default: 3411 return MCDisassembler::Fail; 3412 case 0: 3413 if (fieldFromInstruction32(Insn, 4, 1)) 3414 return MCDisassembler::Fail; // UNDEFINED 3415 index = fieldFromInstruction32(Insn, 5, 3); 3416 break; 3417 case 1: 3418 if (fieldFromInstruction32(Insn, 5, 1)) 3419 return MCDisassembler::Fail; // UNDEFINED 3420 index = fieldFromInstruction32(Insn, 6, 2); 3421 if (fieldFromInstruction32(Insn, 4, 1)) 3422 align = 2; 3423 break; 3424 case 2: 3425 if (fieldFromInstruction32(Insn, 6, 1)) 3426 return MCDisassembler::Fail; // UNDEFINED 3427 index = fieldFromInstruction32(Insn, 7, 1); 3428 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3429 align = 4; 3430 } 3431 3432 if (Rm != 0xF) { // Writeback 3433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 } 3436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3437 return MCDisassembler::Fail; 3438 Inst.addOperand(MCOperand::CreateImm(align)); 3439 if (Rm != 0xF) { 3440 if (Rm != 0xD) { 3441 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 } else 3444 Inst.addOperand(MCOperand::CreateReg(0)); 3445 } 3446 3447 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3448 return MCDisassembler::Fail; 3449 Inst.addOperand(MCOperand::CreateImm(index)); 3450 3451 return S; 3452} 3453 3454 3455static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3456 uint64_t Address, const void *Decoder) { 3457 DecodeStatus S = MCDisassembler::Success; 3458 3459 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3460 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3461 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3462 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3463 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3464 3465 unsigned align = 0; 3466 unsigned index = 0; 3467 unsigned inc = 1; 3468 switch (size) { 3469 default: 3470 return MCDisassembler::Fail; 3471 case 0: 3472 index = fieldFromInstruction32(Insn, 5, 3); 3473 if (fieldFromInstruction32(Insn, 4, 1)) 3474 align = 2; 3475 break; 3476 case 1: 3477 index = fieldFromInstruction32(Insn, 6, 2); 3478 if (fieldFromInstruction32(Insn, 4, 1)) 3479 align = 4; 3480 if (fieldFromInstruction32(Insn, 5, 1)) 3481 inc = 2; 3482 break; 3483 case 2: 3484 if (fieldFromInstruction32(Insn, 5, 1)) 3485 return MCDisassembler::Fail; // UNDEFINED 3486 index = fieldFromInstruction32(Insn, 7, 1); 3487 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3488 align = 8; 3489 if (fieldFromInstruction32(Insn, 6, 1)) 3490 inc = 2; 3491 break; 3492 } 3493 3494 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3495 return MCDisassembler::Fail; 3496 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3497 return MCDisassembler::Fail; 3498 if (Rm != 0xF) { // Writeback 3499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 } 3502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3503 return MCDisassembler::Fail; 3504 Inst.addOperand(MCOperand::CreateImm(align)); 3505 if (Rm != 0xF) { 3506 if (Rm != 0xD) { 3507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3508 return MCDisassembler::Fail; 3509 } else 3510 Inst.addOperand(MCOperand::CreateReg(0)); 3511 } 3512 3513 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3514 return MCDisassembler::Fail; 3515 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3516 return MCDisassembler::Fail; 3517 Inst.addOperand(MCOperand::CreateImm(index)); 3518 3519 return S; 3520} 3521 3522static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3523 uint64_t Address, const void *Decoder) { 3524 DecodeStatus S = MCDisassembler::Success; 3525 3526 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3527 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3528 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3529 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3530 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3531 3532 unsigned align = 0; 3533 unsigned index = 0; 3534 unsigned inc = 1; 3535 switch (size) { 3536 default: 3537 return MCDisassembler::Fail; 3538 case 0: 3539 index = fieldFromInstruction32(Insn, 5, 3); 3540 if (fieldFromInstruction32(Insn, 4, 1)) 3541 align = 2; 3542 break; 3543 case 1: 3544 index = fieldFromInstruction32(Insn, 6, 2); 3545 if (fieldFromInstruction32(Insn, 4, 1)) 3546 align = 4; 3547 if (fieldFromInstruction32(Insn, 5, 1)) 3548 inc = 2; 3549 break; 3550 case 2: 3551 if (fieldFromInstruction32(Insn, 5, 1)) 3552 return MCDisassembler::Fail; // UNDEFINED 3553 index = fieldFromInstruction32(Insn, 7, 1); 3554 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3555 align = 8; 3556 if (fieldFromInstruction32(Insn, 6, 1)) 3557 inc = 2; 3558 break; 3559 } 3560 3561 if (Rm != 0xF) { // Writeback 3562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 } 3565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3566 return MCDisassembler::Fail; 3567 Inst.addOperand(MCOperand::CreateImm(align)); 3568 if (Rm != 0xF) { 3569 if (Rm != 0xD) { 3570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3571 return MCDisassembler::Fail; 3572 } else 3573 Inst.addOperand(MCOperand::CreateReg(0)); 3574 } 3575 3576 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3577 return MCDisassembler::Fail; 3578 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3579 return MCDisassembler::Fail; 3580 Inst.addOperand(MCOperand::CreateImm(index)); 3581 3582 return S; 3583} 3584 3585 3586static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3587 uint64_t Address, const void *Decoder) { 3588 DecodeStatus S = MCDisassembler::Success; 3589 3590 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3591 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3592 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3593 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3594 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3595 3596 unsigned align = 0; 3597 unsigned index = 0; 3598 unsigned inc = 1; 3599 switch (size) { 3600 default: 3601 return MCDisassembler::Fail; 3602 case 0: 3603 if (fieldFromInstruction32(Insn, 4, 1)) 3604 return MCDisassembler::Fail; // UNDEFINED 3605 index = fieldFromInstruction32(Insn, 5, 3); 3606 break; 3607 case 1: 3608 if (fieldFromInstruction32(Insn, 4, 1)) 3609 return MCDisassembler::Fail; // UNDEFINED 3610 index = fieldFromInstruction32(Insn, 6, 2); 3611 if (fieldFromInstruction32(Insn, 5, 1)) 3612 inc = 2; 3613 break; 3614 case 2: 3615 if (fieldFromInstruction32(Insn, 4, 2)) 3616 return MCDisassembler::Fail; // UNDEFINED 3617 index = fieldFromInstruction32(Insn, 7, 1); 3618 if (fieldFromInstruction32(Insn, 6, 1)) 3619 inc = 2; 3620 break; 3621 } 3622 3623 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3624 return MCDisassembler::Fail; 3625 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3626 return MCDisassembler::Fail; 3627 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3628 return MCDisassembler::Fail; 3629 3630 if (Rm != 0xF) { // Writeback 3631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3632 return MCDisassembler::Fail; 3633 } 3634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 Inst.addOperand(MCOperand::CreateImm(align)); 3637 if (Rm != 0xF) { 3638 if (Rm != 0xD) { 3639 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3640 return MCDisassembler::Fail; 3641 } else 3642 Inst.addOperand(MCOperand::CreateReg(0)); 3643 } 3644 3645 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3646 return MCDisassembler::Fail; 3647 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3648 return MCDisassembler::Fail; 3649 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3650 return MCDisassembler::Fail; 3651 Inst.addOperand(MCOperand::CreateImm(index)); 3652 3653 return S; 3654} 3655 3656static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3657 uint64_t Address, const void *Decoder) { 3658 DecodeStatus S = MCDisassembler::Success; 3659 3660 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3661 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3662 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3663 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3664 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3665 3666 unsigned align = 0; 3667 unsigned index = 0; 3668 unsigned inc = 1; 3669 switch (size) { 3670 default: 3671 return MCDisassembler::Fail; 3672 case 0: 3673 if (fieldFromInstruction32(Insn, 4, 1)) 3674 return MCDisassembler::Fail; // UNDEFINED 3675 index = fieldFromInstruction32(Insn, 5, 3); 3676 break; 3677 case 1: 3678 if (fieldFromInstruction32(Insn, 4, 1)) 3679 return MCDisassembler::Fail; // UNDEFINED 3680 index = fieldFromInstruction32(Insn, 6, 2); 3681 if (fieldFromInstruction32(Insn, 5, 1)) 3682 inc = 2; 3683 break; 3684 case 2: 3685 if (fieldFromInstruction32(Insn, 4, 2)) 3686 return MCDisassembler::Fail; // UNDEFINED 3687 index = fieldFromInstruction32(Insn, 7, 1); 3688 if (fieldFromInstruction32(Insn, 6, 1)) 3689 inc = 2; 3690 break; 3691 } 3692 3693 if (Rm != 0xF) { // Writeback 3694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3695 return MCDisassembler::Fail; 3696 } 3697 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3698 return MCDisassembler::Fail; 3699 Inst.addOperand(MCOperand::CreateImm(align)); 3700 if (Rm != 0xF) { 3701 if (Rm != 0xD) { 3702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3703 return MCDisassembler::Fail; 3704 } else 3705 Inst.addOperand(MCOperand::CreateReg(0)); 3706 } 3707 3708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3709 return MCDisassembler::Fail; 3710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3711 return MCDisassembler::Fail; 3712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3713 return MCDisassembler::Fail; 3714 Inst.addOperand(MCOperand::CreateImm(index)); 3715 3716 return S; 3717} 3718 3719 3720static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3721 uint64_t Address, const void *Decoder) { 3722 DecodeStatus S = MCDisassembler::Success; 3723 3724 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3725 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3726 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3727 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3728 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3729 3730 unsigned align = 0; 3731 unsigned index = 0; 3732 unsigned inc = 1; 3733 switch (size) { 3734 default: 3735 return MCDisassembler::Fail; 3736 case 0: 3737 if (fieldFromInstruction32(Insn, 4, 1)) 3738 align = 4; 3739 index = fieldFromInstruction32(Insn, 5, 3); 3740 break; 3741 case 1: 3742 if (fieldFromInstruction32(Insn, 4, 1)) 3743 align = 8; 3744 index = fieldFromInstruction32(Insn, 6, 2); 3745 if (fieldFromInstruction32(Insn, 5, 1)) 3746 inc = 2; 3747 break; 3748 case 2: 3749 if (fieldFromInstruction32(Insn, 4, 2)) 3750 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3751 index = fieldFromInstruction32(Insn, 7, 1); 3752 if (fieldFromInstruction32(Insn, 6, 1)) 3753 inc = 2; 3754 break; 3755 } 3756 3757 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3758 return MCDisassembler::Fail; 3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3762 return MCDisassembler::Fail; 3763 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3764 return MCDisassembler::Fail; 3765 3766 if (Rm != 0xF) { // Writeback 3767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3768 return MCDisassembler::Fail; 3769 } 3770 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3771 return MCDisassembler::Fail; 3772 Inst.addOperand(MCOperand::CreateImm(align)); 3773 if (Rm != 0xF) { 3774 if (Rm != 0xD) { 3775 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3776 return MCDisassembler::Fail; 3777 } else 3778 Inst.addOperand(MCOperand::CreateReg(0)); 3779 } 3780 3781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3782 return MCDisassembler::Fail; 3783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3784 return MCDisassembler::Fail; 3785 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3786 return MCDisassembler::Fail; 3787 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3788 return MCDisassembler::Fail; 3789 Inst.addOperand(MCOperand::CreateImm(index)); 3790 3791 return S; 3792} 3793 3794static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3795 uint64_t Address, const void *Decoder) { 3796 DecodeStatus S = MCDisassembler::Success; 3797 3798 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3799 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3800 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3801 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3802 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3803 3804 unsigned align = 0; 3805 unsigned index = 0; 3806 unsigned inc = 1; 3807 switch (size) { 3808 default: 3809 return MCDisassembler::Fail; 3810 case 0: 3811 if (fieldFromInstruction32(Insn, 4, 1)) 3812 align = 4; 3813 index = fieldFromInstruction32(Insn, 5, 3); 3814 break; 3815 case 1: 3816 if (fieldFromInstruction32(Insn, 4, 1)) 3817 align = 8; 3818 index = fieldFromInstruction32(Insn, 6, 2); 3819 if (fieldFromInstruction32(Insn, 5, 1)) 3820 inc = 2; 3821 break; 3822 case 2: 3823 if (fieldFromInstruction32(Insn, 4, 2)) 3824 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3825 index = fieldFromInstruction32(Insn, 7, 1); 3826 if (fieldFromInstruction32(Insn, 6, 1)) 3827 inc = 2; 3828 break; 3829 } 3830 3831 if (Rm != 0xF) { // Writeback 3832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3833 return MCDisassembler::Fail; 3834 } 3835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3836 return MCDisassembler::Fail; 3837 Inst.addOperand(MCOperand::CreateImm(align)); 3838 if (Rm != 0xF) { 3839 if (Rm != 0xD) { 3840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3841 return MCDisassembler::Fail; 3842 } else 3843 Inst.addOperand(MCOperand::CreateReg(0)); 3844 } 3845 3846 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3847 return MCDisassembler::Fail; 3848 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3849 return MCDisassembler::Fail; 3850 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3851 return MCDisassembler::Fail; 3852 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3853 return MCDisassembler::Fail; 3854 Inst.addOperand(MCOperand::CreateImm(index)); 3855 3856 return S; 3857} 3858 3859static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3860 uint64_t Address, const void *Decoder) { 3861 DecodeStatus S = MCDisassembler::Success; 3862 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3863 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3864 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3865 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3866 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3867 3868 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3869 S = MCDisassembler::SoftFail; 3870 3871 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3874 return MCDisassembler::Fail; 3875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3876 return MCDisassembler::Fail; 3877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3878 return MCDisassembler::Fail; 3879 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3880 return MCDisassembler::Fail; 3881 3882 return S; 3883} 3884 3885static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3886 uint64_t Address, const void *Decoder) { 3887 DecodeStatus S = MCDisassembler::Success; 3888 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3889 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3890 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3891 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3892 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3893 3894 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3895 S = MCDisassembler::SoftFail; 3896 3897 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3898 return MCDisassembler::Fail; 3899 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3900 return MCDisassembler::Fail; 3901 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3902 return MCDisassembler::Fail; 3903 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3904 return MCDisassembler::Fail; 3905 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3906 return MCDisassembler::Fail; 3907 3908 return S; 3909} 3910 3911static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3912 uint64_t Address, const void *Decoder) { 3913 DecodeStatus S = MCDisassembler::Success; 3914 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3915 // The InstPrinter needs to have the low bit of the predicate in 3916 // the mask operand to be able to print it properly. 3917 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3918 3919 if (pred == 0xF) { 3920 pred = 0xE; 3921 S = MCDisassembler::SoftFail; 3922 } 3923 3924 if ((mask & 0xF) == 0) { 3925 // Preserve the high bit of the mask, which is the low bit of 3926 // the predicate. 3927 mask &= 0x10; 3928 mask |= 0x8; 3929 S = MCDisassembler::SoftFail; 3930 } 3931 3932 Inst.addOperand(MCOperand::CreateImm(pred)); 3933 Inst.addOperand(MCOperand::CreateImm(mask)); 3934 return S; 3935} 3936 3937static DecodeStatus 3938DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3939 uint64_t Address, const void *Decoder) { 3940 DecodeStatus S = MCDisassembler::Success; 3941 3942 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3943 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3944 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3945 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3946 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3947 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3948 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3949 bool writeback = (W == 1) | (P == 0); 3950 3951 addr |= (U << 8) | (Rn << 9); 3952 3953 if (writeback && (Rn == Rt || Rn == Rt2)) 3954 Check(S, MCDisassembler::SoftFail); 3955 if (Rt == Rt2) 3956 Check(S, MCDisassembler::SoftFail); 3957 3958 // Rt 3959 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3960 return MCDisassembler::Fail; 3961 // Rt2 3962 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3963 return MCDisassembler::Fail; 3964 // Writeback operand 3965 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3966 return MCDisassembler::Fail; 3967 // addr 3968 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3969 return MCDisassembler::Fail; 3970 3971 return S; 3972} 3973 3974static DecodeStatus 3975DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3976 uint64_t Address, const void *Decoder) { 3977 DecodeStatus S = MCDisassembler::Success; 3978 3979 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3980 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3981 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3982 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3983 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3984 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3985 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3986 bool writeback = (W == 1) | (P == 0); 3987 3988 addr |= (U << 8) | (Rn << 9); 3989 3990 if (writeback && (Rn == Rt || Rn == Rt2)) 3991 Check(S, MCDisassembler::SoftFail); 3992 3993 // Writeback operand 3994 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3995 return MCDisassembler::Fail; 3996 // Rt 3997 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3998 return MCDisassembler::Fail; 3999 // Rt2 4000 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4001 return MCDisassembler::Fail; 4002 // addr 4003 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4004 return MCDisassembler::Fail; 4005 4006 return S; 4007} 4008 4009static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 4010 uint64_t Address, const void *Decoder) { 4011 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4012 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4013 if (sign1 != sign2) return MCDisassembler::Fail; 4014 4015 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4016 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4017 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4018 Val |= sign1 << 12; 4019 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4020 4021 return MCDisassembler::Success; 4022} 4023 4024static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4025 uint64_t Address, 4026 const void *Decoder) { 4027 DecodeStatus S = MCDisassembler::Success; 4028 4029 // Shift of "asr #32" is not allowed in Thumb2 mode. 4030 if (Val == 0x20) S = MCDisassembler::SoftFail; 4031 Inst.addOperand(MCOperand::CreateImm(Val)); 4032 return S; 4033} 4034 4035static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 4036 uint64_t Address, const void *Decoder) { 4037 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4038 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4039 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4040 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4041 4042 if (pred == 0xF) 4043 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4044 4045 DecodeStatus S = MCDisassembler::Success; 4046 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4047 return MCDisassembler::Fail; 4048 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4049 return MCDisassembler::Fail; 4050 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4051 return MCDisassembler::Fail; 4052 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4053 return MCDisassembler::Fail; 4054 4055 return S; 4056} 4057 4058static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 4059 uint64_t Address, const void *Decoder) { 4060 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4061 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4062 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4063 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4064 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4065 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4066 4067 DecodeStatus S = MCDisassembler::Success; 4068 4069 // VMOVv2f32 is ambiguous with these decodings. 4070 if (!(imm & 0x38) && cmode == 0xF) { 4071 Inst.setOpcode(ARM::VMOVv2f32); 4072 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4073 } 4074 4075 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4076 4077 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4078 return MCDisassembler::Fail; 4079 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4080 return MCDisassembler::Fail; 4081 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4082 4083 return S; 4084} 4085 4086static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 4087 uint64_t Address, const void *Decoder) { 4088 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4089 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4090 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4091 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4092 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4093 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4094 4095 DecodeStatus S = MCDisassembler::Success; 4096 4097 // VMOVv4f32 is ambiguous with these decodings. 4098 if (!(imm & 0x38) && cmode == 0xF) { 4099 Inst.setOpcode(ARM::VMOVv4f32); 4100 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4101 } 4102 4103 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4104 4105 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4106 return MCDisassembler::Fail; 4107 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4108 return MCDisassembler::Fail; 4109 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4110 4111 return S; 4112} 4113