ARMDisassembler.cpp revision a69da35c127dd7e35ae6216d965670643dc55bb6
1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "MCTargetDesc/ARMAddressingModes.h" 13#include "MCTargetDesc/ARMMCExpr.h" 14#include "MCTargetDesc/ARMBaseInfo.h" 15#include "llvm/MC/EDInstInfo.h" 16#include "llvm/MC/MCInst.h" 17#include "llvm/MC/MCInstrDesc.h" 18#include "llvm/MC/MCExpr.h" 19#include "llvm/MC/MCContext.h" 20#include "llvm/MC/MCDisassembler.h" 21#include "llvm/MC/MCSubtargetInfo.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/MemoryObject.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/TargetRegistry.h" 26#include "llvm/Support/raw_ostream.h" 27 28using namespace llvm; 29 30typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32namespace { 33/// ARMDisassembler - ARM disassembler for all ARM platforms. 34class ARMDisassembler : public MCDisassembler { 35public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream, 51 raw_ostream &cStream) const; 52 53 /// getEDInfo - See MCDisassembler. 54 const EDInstInfo *getEDInfo() const; 55private: 56}; 57 58/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 59class ThumbDisassembler : public MCDisassembler { 60public: 61 /// Constructor - Initializes the disassembler. 62 /// 63 ThumbDisassembler(const MCSubtargetInfo &STI) : 64 MCDisassembler(STI) { 65 } 66 67 ~ThumbDisassembler() { 68 } 69 70 /// getInstruction - See MCDisassembler. 71 DecodeStatus getInstruction(MCInst &instr, 72 uint64_t &size, 73 const MemoryObject ®ion, 74 uint64_t address, 75 raw_ostream &vStream, 76 raw_ostream &cStream) const; 77 78 /// getEDInfo - See MCDisassembler. 79 const EDInstInfo *getEDInfo() const; 80private: 81 mutable std::vector<unsigned> ITBlock; 82 DecodeStatus AddThumbPredicate(MCInst&) const; 83 void UpdateThumbVFPPredicate(MCInst&) const; 84}; 85} 86 87static bool Check(DecodeStatus &Out, DecodeStatus In) { 88 switch (In) { 89 case MCDisassembler::Success: 90 // Out stays the same. 91 return true; 92 case MCDisassembler::SoftFail: 93 Out = In; 94 return true; 95 case MCDisassembler::Fail: 96 Out = In; 97 return false; 98 } 99 llvm_unreachable("Invalid DecodeStatus!"); 100} 101 102 103// Forward declare these because the autogenerated code will reference them. 104// Definitions are further down. 105static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 106 uint64_t Address, const void *Decoder); 107static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 108 unsigned RegNo, uint64_t Address, 109 const void *Decoder); 110static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 121 uint64_t Address, const void *Decoder); 122static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 123 unsigned RegNo, 124 uint64_t Address, 125 const void *Decoder); 126static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 127 uint64_t Address, const void *Decoder); 128static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, const void *Decoder); 130static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 131 unsigned RegNo, uint64_t Address, 132 const void *Decoder); 133 134static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 147static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 148 uint64_t Address, const void *Decoder); 149static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 150 uint64_t Address, const void *Decoder); 151static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 152 unsigned Insn, 153 uint64_t Address, 154 const void *Decoder); 155static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 158 uint64_t Address, const void *Decoder); 159static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 160 uint64_t Address, const void *Decoder); 161static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 164static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 165 unsigned Insn, 166 uint64_t Adddress, 167 const void *Decoder); 168static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 185 uint64_t Address, const void *Decoder); 186static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 201 uint64_t Address, const void *Decoder); 202static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 211 uint64_t Address, const void *Decoder); 212static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 257 uint64_t Address, const void *Decoder); 258static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 261 262static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 263 uint64_t Address, const void *Decoder); 264static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 281 uint64_t Address, const void *Decoder); 282static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 283 uint64_t Address, const void *Decoder); 284static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 287 uint64_t Address, const void *Decoder); 288static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 293 uint64_t Address, const void *Decoder); 294static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 295 uint64_t Address, const void *Decoder); 296static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 297 uint64_t Address, const void *Decoder); 298static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 309 uint64_t Address, const void *Decoder); 310static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 315 uint64_t Address, const void *Decoder); 316static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 317 uint64_t Address, const void *Decoder); 318static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 325static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327#include "ARMGenDisassemblerTables.inc" 328#include "ARMGenInstrInfo.inc" 329#include "ARMGenEDInfo.inc" 330 331static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 332 return new ARMDisassembler(STI); 333} 334 335static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 336 return new ThumbDisassembler(STI); 337} 338 339const EDInstInfo *ARMDisassembler::getEDInfo() const { 340 return instInfoARM; 341} 342 343const EDInstInfo *ThumbDisassembler::getEDInfo() const { 344 return instInfoARM; 345} 346 347DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 348 const MemoryObject &Region, 349 uint64_t Address, 350 raw_ostream &os, 351 raw_ostream &cs) const { 352 CommentStream = &cs; 353 354 uint8_t bytes[4]; 355 356 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 357 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 358 359 // We want to read exactly 4 bytes of data. 360 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 361 Size = 0; 362 return MCDisassembler::Fail; 363 } 364 365 // Encoded as a small-endian 32-bit word in the stream. 366 uint32_t insn = (bytes[3] << 24) | 367 (bytes[2] << 16) | 368 (bytes[1] << 8) | 369 (bytes[0] << 0); 370 371 // Calling the auto-generated decoder function. 372 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 373 if (result != MCDisassembler::Fail) { 374 Size = 4; 375 return result; 376 } 377 378 // VFP and NEON instructions, similarly, are shared between ARM 379 // and Thumb modes. 380 MI.clear(); 381 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 382 if (result != MCDisassembler::Fail) { 383 Size = 4; 384 return result; 385 } 386 387 MI.clear(); 388 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 389 if (result != MCDisassembler::Fail) { 390 Size = 4; 391 // Add a fake predicate operand, because we share these instruction 392 // definitions with Thumb2 where these instructions are predicable. 393 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 394 return MCDisassembler::Fail; 395 return result; 396 } 397 398 MI.clear(); 399 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 400 if (result != MCDisassembler::Fail) { 401 Size = 4; 402 // Add a fake predicate operand, because we share these instruction 403 // definitions with Thumb2 where these instructions are predicable. 404 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 405 return MCDisassembler::Fail; 406 return result; 407 } 408 409 MI.clear(); 410 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 411 if (result != MCDisassembler::Fail) { 412 Size = 4; 413 // Add a fake predicate operand, because we share these instruction 414 // definitions with Thumb2 where these instructions are predicable. 415 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 416 return MCDisassembler::Fail; 417 return result; 418 } 419 420 MI.clear(); 421 422 Size = 0; 423 return MCDisassembler::Fail; 424} 425 426namespace llvm { 427extern const MCInstrDesc ARMInsts[]; 428} 429 430/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 431/// immediate Value in the MCInst. The immediate Value has had any PC 432/// adjustment made by the caller. If the instruction is a branch instruction 433/// then isBranch is true, else false. If the getOpInfo() function was set as 434/// part of the setupForSymbolicDisassembly() call then that function is called 435/// to get any symbolic information at the Address for this instruction. If 436/// that returns non-zero then the symbolic information it returns is used to 437/// create an MCExpr and that is added as an operand to the MCInst. If 438/// getOpInfo() returns zero and isBranch is true then a symbol look up for 439/// Value is done and if a symbol is found an MCExpr is created with that, else 440/// an MCExpr with Value is created. This function returns true if it adds an 441/// operand to the MCInst and false otherwise. 442static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 443 bool isBranch, uint64_t InstSize, 444 MCInst &MI, const void *Decoder) { 445 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 446 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 447 struct LLVMOpInfo1 SymbolicOp; 448 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 449 SymbolicOp.Value = Value; 450 void *DisInfo = Dis->getDisInfoBlock(); 451 452 if (!getOpInfo || 453 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 454 // Clear SymbolicOp.Value from above and also all other fields. 455 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 456 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 457 if (!SymbolLookUp) 458 return false; 459 uint64_t ReferenceType; 460 if (isBranch) 461 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 462 else 463 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 464 const char *ReferenceName; 465 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 466 &ReferenceName); 467 if (Name) { 468 SymbolicOp.AddSymbol.Name = Name; 469 SymbolicOp.AddSymbol.Present = true; 470 } 471 // For branches always create an MCExpr so it gets printed as hex address. 472 else if (isBranch) { 473 SymbolicOp.Value = Value; 474 } 475 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 476 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 477 if (!Name && !isBranch) 478 return false; 479 } 480 481 MCContext *Ctx = Dis->getMCContext(); 482 const MCExpr *Add = NULL; 483 if (SymbolicOp.AddSymbol.Present) { 484 if (SymbolicOp.AddSymbol.Name) { 485 StringRef Name(SymbolicOp.AddSymbol.Name); 486 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 487 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 488 } else { 489 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 490 } 491 } 492 493 const MCExpr *Sub = NULL; 494 if (SymbolicOp.SubtractSymbol.Present) { 495 if (SymbolicOp.SubtractSymbol.Name) { 496 StringRef Name(SymbolicOp.SubtractSymbol.Name); 497 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 498 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 499 } else { 500 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 501 } 502 } 503 504 const MCExpr *Off = NULL; 505 if (SymbolicOp.Value != 0) 506 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 507 508 const MCExpr *Expr; 509 if (Sub) { 510 const MCExpr *LHS; 511 if (Add) 512 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 513 else 514 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 515 if (Off != 0) 516 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 517 else 518 Expr = LHS; 519 } else if (Add) { 520 if (Off != 0) 521 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 522 else 523 Expr = Add; 524 } else { 525 if (Off != 0) 526 Expr = Off; 527 else 528 Expr = MCConstantExpr::Create(0, *Ctx); 529 } 530 531 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 532 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 533 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 534 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 535 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 536 MI.addOperand(MCOperand::CreateExpr(Expr)); 537 else 538 llvm_unreachable("bad SymbolicOp.VariantKind"); 539 540 return true; 541} 542 543/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 544/// referenced by a load instruction with the base register that is the Pc. 545/// These can often be values in a literal pool near the Address of the 546/// instruction. The Address of the instruction and its immediate Value are 547/// used as a possible literal pool entry. The SymbolLookUp call back will 548/// return the name of a symbol referenced by the the literal pool's entry if 549/// the referenced address is that of a symbol. Or it will return a pointer to 550/// a literal 'C' string if the referenced address of the literal pool's entry 551/// is an address into a section with 'C' string literals. 552static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 553 const void *Decoder) { 554 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 555 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 556 if (SymbolLookUp) { 557 void *DisInfo = Dis->getDisInfoBlock(); 558 uint64_t ReferenceType; 559 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 560 const char *ReferenceName; 561 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 562 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 563 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 564 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 565 } 566} 567 568// Thumb1 instructions don't have explicit S bits. Rather, they 569// implicitly set CPSR. Since it's not represented in the encoding, the 570// auto-generated decoder won't inject the CPSR operand. We need to fix 571// that as a post-pass. 572static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 573 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 574 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 575 MCInst::iterator I = MI.begin(); 576 for (unsigned i = 0; i < NumOps; ++i, ++I) { 577 if (I == MI.end()) break; 578 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 579 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 580 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 581 return; 582 } 583 } 584 585 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 586} 587 588// Most Thumb instructions don't have explicit predicates in the 589// encoding, but rather get their predicates from IT context. We need 590// to fix up the predicate operands using this context information as a 591// post-pass. 592MCDisassembler::DecodeStatus 593ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 594 MCDisassembler::DecodeStatus S = Success; 595 596 // A few instructions actually have predicates encoded in them. Don't 597 // try to overwrite it if we're seeing one of those. 598 switch (MI.getOpcode()) { 599 case ARM::tBcc: 600 case ARM::t2Bcc: 601 case ARM::tCBZ: 602 case ARM::tCBNZ: 603 case ARM::tCPS: 604 case ARM::t2CPS3p: 605 case ARM::t2CPS2p: 606 case ARM::t2CPS1p: 607 case ARM::tMOVSr: 608 case ARM::tSETEND: 609 // Some instructions (mostly conditional branches) are not 610 // allowed in IT blocks. 611 if (!ITBlock.empty()) 612 S = SoftFail; 613 else 614 return Success; 615 break; 616 case ARM::tB: 617 case ARM::t2B: 618 case ARM::t2TBB: 619 case ARM::t2TBH: 620 // Some instructions (mostly unconditional branches) can 621 // only appears at the end of, or outside of, an IT. 622 if (ITBlock.size() > 1) 623 S = SoftFail; 624 break; 625 default: 626 break; 627 } 628 629 // If we're in an IT block, base the predicate on that. Otherwise, 630 // assume a predicate of AL. 631 unsigned CC; 632 if (!ITBlock.empty()) { 633 CC = ITBlock.back(); 634 if (CC == 0xF) 635 CC = ARMCC::AL; 636 ITBlock.pop_back(); 637 } else 638 CC = ARMCC::AL; 639 640 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 641 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 642 MCInst::iterator I = MI.begin(); 643 for (unsigned i = 0; i < NumOps; ++i, ++I) { 644 if (I == MI.end()) break; 645 if (OpInfo[i].isPredicate()) { 646 I = MI.insert(I, MCOperand::CreateImm(CC)); 647 ++I; 648 if (CC == ARMCC::AL) 649 MI.insert(I, MCOperand::CreateReg(0)); 650 else 651 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 652 return S; 653 } 654 } 655 656 I = MI.insert(I, MCOperand::CreateImm(CC)); 657 ++I; 658 if (CC == ARMCC::AL) 659 MI.insert(I, MCOperand::CreateReg(0)); 660 else 661 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 662 663 return S; 664} 665 666// Thumb VFP instructions are a special case. Because we share their 667// encodings between ARM and Thumb modes, and they are predicable in ARM 668// mode, the auto-generated decoder will give them an (incorrect) 669// predicate operand. We need to rewrite these operands based on the IT 670// context as a post-pass. 671void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 672 unsigned CC; 673 if (!ITBlock.empty()) { 674 CC = ITBlock.back(); 675 ITBlock.pop_back(); 676 } else 677 CC = ARMCC::AL; 678 679 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 680 MCInst::iterator I = MI.begin(); 681 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 682 for (unsigned i = 0; i < NumOps; ++i, ++I) { 683 if (OpInfo[i].isPredicate() ) { 684 I->setImm(CC); 685 ++I; 686 if (CC == ARMCC::AL) 687 I->setReg(0); 688 else 689 I->setReg(ARM::CPSR); 690 return; 691 } 692 } 693} 694 695DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 696 const MemoryObject &Region, 697 uint64_t Address, 698 raw_ostream &os, 699 raw_ostream &cs) const { 700 CommentStream = &cs; 701 702 uint8_t bytes[4]; 703 704 assert((STI.getFeatureBits() & ARM::ModeThumb) && 705 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 706 707 // We want to read exactly 2 bytes of data. 708 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 709 Size = 0; 710 return MCDisassembler::Fail; 711 } 712 713 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 714 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 715 if (result != MCDisassembler::Fail) { 716 Size = 2; 717 Check(result, AddThumbPredicate(MI)); 718 return result; 719 } 720 721 MI.clear(); 722 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 723 if (result) { 724 Size = 2; 725 bool InITBlock = !ITBlock.empty(); 726 Check(result, AddThumbPredicate(MI)); 727 AddThumb1SBit(MI, InITBlock); 728 return result; 729 } 730 731 MI.clear(); 732 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 733 if (result != MCDisassembler::Fail) { 734 Size = 2; 735 736 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 737 // the Thumb predicate. 738 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 739 result = MCDisassembler::SoftFail; 740 741 Check(result, AddThumbPredicate(MI)); 742 743 // If we find an IT instruction, we need to parse its condition 744 // code and mask operands so that we can apply them correctly 745 // to the subsequent instructions. 746 if (MI.getOpcode() == ARM::t2IT) { 747 748 // (3 - the number of trailing zeros) is the number of then / else. 749 unsigned firstcond = MI.getOperand(0).getImm(); 750 unsigned Mask = MI.getOperand(1).getImm(); 751 unsigned CondBit0 = Mask >> 4 & 1; 752 unsigned NumTZ = CountTrailingZeros_32(Mask); 753 assert(NumTZ <= 3 && "Invalid IT mask!"); 754 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 755 bool T = ((Mask >> Pos) & 1) == CondBit0; 756 if (T) 757 ITBlock.insert(ITBlock.begin(), firstcond); 758 else 759 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 760 } 761 762 ITBlock.push_back(firstcond); 763 } 764 765 return result; 766 } 767 768 // We want to read exactly 4 bytes of data. 769 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 770 Size = 0; 771 return MCDisassembler::Fail; 772 } 773 774 uint32_t insn32 = (bytes[3] << 8) | 775 (bytes[2] << 0) | 776 (bytes[1] << 24) | 777 (bytes[0] << 16); 778 MI.clear(); 779 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 780 if (result != MCDisassembler::Fail) { 781 Size = 4; 782 bool InITBlock = ITBlock.size(); 783 Check(result, AddThumbPredicate(MI)); 784 AddThumb1SBit(MI, InITBlock); 785 return result; 786 } 787 788 MI.clear(); 789 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 790 if (result != MCDisassembler::Fail) { 791 Size = 4; 792 Check(result, AddThumbPredicate(MI)); 793 return result; 794 } 795 796 MI.clear(); 797 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 798 if (result != MCDisassembler::Fail) { 799 Size = 4; 800 UpdateThumbVFPPredicate(MI); 801 return result; 802 } 803 804 MI.clear(); 805 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 806 if (result != MCDisassembler::Fail) { 807 Size = 4; 808 Check(result, AddThumbPredicate(MI)); 809 return result; 810 } 811 812 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 813 MI.clear(); 814 uint32_t NEONLdStInsn = insn32; 815 NEONLdStInsn &= 0xF0FFFFFF; 816 NEONLdStInsn |= 0x04000000; 817 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 818 if (result != MCDisassembler::Fail) { 819 Size = 4; 820 Check(result, AddThumbPredicate(MI)); 821 return result; 822 } 823 } 824 825 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 826 MI.clear(); 827 uint32_t NEONDataInsn = insn32; 828 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 829 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 830 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 831 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 832 if (result != MCDisassembler::Fail) { 833 Size = 4; 834 Check(result, AddThumbPredicate(MI)); 835 return result; 836 } 837 } 838 839 Size = 0; 840 return MCDisassembler::Fail; 841} 842 843 844extern "C" void LLVMInitializeARMDisassembler() { 845 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 846 createARMDisassembler); 847 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 848 createThumbDisassembler); 849} 850 851static const uint16_t GPRDecoderTable[] = { 852 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 853 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 854 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 855 ARM::R12, ARM::SP, ARM::LR, ARM::PC 856}; 857 858static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 859 uint64_t Address, const void *Decoder) { 860 if (RegNo > 15) 861 return MCDisassembler::Fail; 862 863 unsigned Register = GPRDecoderTable[RegNo]; 864 Inst.addOperand(MCOperand::CreateReg(Register)); 865 return MCDisassembler::Success; 866} 867 868static DecodeStatus 869DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 870 uint64_t Address, const void *Decoder) { 871 DecodeStatus S = MCDisassembler::Success; 872 873 if (RegNo == 15) 874 S = MCDisassembler::SoftFail; 875 876 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 877 878 return S; 879} 880 881static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 882 uint64_t Address, const void *Decoder) { 883 if (RegNo > 7) 884 return MCDisassembler::Fail; 885 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 886} 887 888static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 889 uint64_t Address, const void *Decoder) { 890 unsigned Register = 0; 891 switch (RegNo) { 892 case 0: 893 Register = ARM::R0; 894 break; 895 case 1: 896 Register = ARM::R1; 897 break; 898 case 2: 899 Register = ARM::R2; 900 break; 901 case 3: 902 Register = ARM::R3; 903 break; 904 case 9: 905 Register = ARM::R9; 906 break; 907 case 12: 908 Register = ARM::R12; 909 break; 910 default: 911 return MCDisassembler::Fail; 912 } 913 914 Inst.addOperand(MCOperand::CreateReg(Register)); 915 return MCDisassembler::Success; 916} 917 918static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 919 uint64_t Address, const void *Decoder) { 920 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 921 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 922} 923 924static const uint16_t SPRDecoderTable[] = { 925 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 926 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 927 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 928 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 929 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 930 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 931 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 932 ARM::S28, ARM::S29, ARM::S30, ARM::S31 933}; 934 935static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 936 uint64_t Address, const void *Decoder) { 937 if (RegNo > 31) 938 return MCDisassembler::Fail; 939 940 unsigned Register = SPRDecoderTable[RegNo]; 941 Inst.addOperand(MCOperand::CreateReg(Register)); 942 return MCDisassembler::Success; 943} 944 945static const uint16_t DPRDecoderTable[] = { 946 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 947 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 948 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 949 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 950 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 951 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 952 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 953 ARM::D28, ARM::D29, ARM::D30, ARM::D31 954}; 955 956static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 957 uint64_t Address, const void *Decoder) { 958 if (RegNo > 31) 959 return MCDisassembler::Fail; 960 961 unsigned Register = DPRDecoderTable[RegNo]; 962 Inst.addOperand(MCOperand::CreateReg(Register)); 963 return MCDisassembler::Success; 964} 965 966static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 967 uint64_t Address, const void *Decoder) { 968 if (RegNo > 7) 969 return MCDisassembler::Fail; 970 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 971} 972 973static DecodeStatus 974DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 975 uint64_t Address, const void *Decoder) { 976 if (RegNo > 15) 977 return MCDisassembler::Fail; 978 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 979} 980 981static const uint16_t QPRDecoderTable[] = { 982 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 983 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 984 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 985 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 986}; 987 988 989static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 990 uint64_t Address, const void *Decoder) { 991 if (RegNo > 31) 992 return MCDisassembler::Fail; 993 RegNo >>= 1; 994 995 unsigned Register = QPRDecoderTable[RegNo]; 996 Inst.addOperand(MCOperand::CreateReg(Register)); 997 return MCDisassembler::Success; 998} 999 1000static const uint16_t DPairDecoderTable[] = { 1001 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1002 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1003 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1004 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1005 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1006 ARM::Q15 1007}; 1008 1009static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1010 uint64_t Address, const void *Decoder) { 1011 if (RegNo > 30) 1012 return MCDisassembler::Fail; 1013 1014 unsigned Register = DPairDecoderTable[RegNo]; 1015 Inst.addOperand(MCOperand::CreateReg(Register)); 1016 return MCDisassembler::Success; 1017} 1018 1019static const uint16_t DPairSpacedDecoderTable[] = { 1020 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1021 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1022 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1023 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1024 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1025 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1026 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1027 ARM::D28_D30, ARM::D29_D31 1028}; 1029 1030static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1031 unsigned RegNo, 1032 uint64_t Address, 1033 const void *Decoder) { 1034 if (RegNo > 29) 1035 return MCDisassembler::Fail; 1036 1037 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1038 Inst.addOperand(MCOperand::CreateReg(Register)); 1039 return MCDisassembler::Success; 1040} 1041 1042static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1043 uint64_t Address, const void *Decoder) { 1044 if (Val == 0xF) return MCDisassembler::Fail; 1045 // AL predicate is not allowed on Thumb1 branches. 1046 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1047 return MCDisassembler::Fail; 1048 Inst.addOperand(MCOperand::CreateImm(Val)); 1049 if (Val == ARMCC::AL) { 1050 Inst.addOperand(MCOperand::CreateReg(0)); 1051 } else 1052 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1053 return MCDisassembler::Success; 1054} 1055 1056static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1057 uint64_t Address, const void *Decoder) { 1058 if (Val) 1059 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1060 else 1061 Inst.addOperand(MCOperand::CreateReg(0)); 1062 return MCDisassembler::Success; 1063} 1064 1065static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1066 uint64_t Address, const void *Decoder) { 1067 uint32_t imm = Val & 0xFF; 1068 uint32_t rot = (Val & 0xF00) >> 7; 1069 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1070 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1071 return MCDisassembler::Success; 1072} 1073 1074static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1075 uint64_t Address, const void *Decoder) { 1076 DecodeStatus S = MCDisassembler::Success; 1077 1078 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1079 unsigned type = fieldFromInstruction32(Val, 5, 2); 1080 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1081 1082 // Register-immediate 1083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1084 return MCDisassembler::Fail; 1085 1086 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1087 switch (type) { 1088 case 0: 1089 Shift = ARM_AM::lsl; 1090 break; 1091 case 1: 1092 Shift = ARM_AM::lsr; 1093 break; 1094 case 2: 1095 Shift = ARM_AM::asr; 1096 break; 1097 case 3: 1098 Shift = ARM_AM::ror; 1099 break; 1100 } 1101 1102 if (Shift == ARM_AM::ror && imm == 0) 1103 Shift = ARM_AM::rrx; 1104 1105 unsigned Op = Shift | (imm << 3); 1106 Inst.addOperand(MCOperand::CreateImm(Op)); 1107 1108 return S; 1109} 1110 1111static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1112 uint64_t Address, const void *Decoder) { 1113 DecodeStatus S = MCDisassembler::Success; 1114 1115 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1116 unsigned type = fieldFromInstruction32(Val, 5, 2); 1117 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1118 1119 // Register-register 1120 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1121 return MCDisassembler::Fail; 1122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1123 return MCDisassembler::Fail; 1124 1125 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1126 switch (type) { 1127 case 0: 1128 Shift = ARM_AM::lsl; 1129 break; 1130 case 1: 1131 Shift = ARM_AM::lsr; 1132 break; 1133 case 2: 1134 Shift = ARM_AM::asr; 1135 break; 1136 case 3: 1137 Shift = ARM_AM::ror; 1138 break; 1139 } 1140 1141 Inst.addOperand(MCOperand::CreateImm(Shift)); 1142 1143 return S; 1144} 1145 1146static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1147 uint64_t Address, const void *Decoder) { 1148 DecodeStatus S = MCDisassembler::Success; 1149 1150 bool writebackLoad = false; 1151 unsigned writebackReg = 0; 1152 switch (Inst.getOpcode()) { 1153 default: 1154 break; 1155 case ARM::LDMIA_UPD: 1156 case ARM::LDMDB_UPD: 1157 case ARM::LDMIB_UPD: 1158 case ARM::LDMDA_UPD: 1159 case ARM::t2LDMIA_UPD: 1160 case ARM::t2LDMDB_UPD: 1161 writebackLoad = true; 1162 writebackReg = Inst.getOperand(0).getReg(); 1163 break; 1164 } 1165 1166 // Empty register lists are not allowed. 1167 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1168 for (unsigned i = 0; i < 16; ++i) { 1169 if (Val & (1 << i)) { 1170 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1171 return MCDisassembler::Fail; 1172 // Writeback not allowed if Rn is in the target list. 1173 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1174 Check(S, MCDisassembler::SoftFail); 1175 } 1176 } 1177 1178 return S; 1179} 1180 1181static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1182 uint64_t Address, const void *Decoder) { 1183 DecodeStatus S = MCDisassembler::Success; 1184 1185 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1186 unsigned regs = Val & 0xFF; 1187 1188 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1189 return MCDisassembler::Fail; 1190 for (unsigned i = 0; i < (regs - 1); ++i) { 1191 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1192 return MCDisassembler::Fail; 1193 } 1194 1195 return S; 1196} 1197 1198static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1199 uint64_t Address, const void *Decoder) { 1200 DecodeStatus S = MCDisassembler::Success; 1201 1202 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1203 unsigned regs = (Val & 0xFF) / 2; 1204 1205 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1206 return MCDisassembler::Fail; 1207 for (unsigned i = 0; i < (regs - 1); ++i) { 1208 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1209 return MCDisassembler::Fail; 1210 } 1211 1212 return S; 1213} 1214 1215static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1216 uint64_t Address, const void *Decoder) { 1217 // This operand encodes a mask of contiguous zeros between a specified MSB 1218 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1219 // the mask of all bits LSB-and-lower, and then xor them to create 1220 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1221 // create the final mask. 1222 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1223 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1224 1225 DecodeStatus S = MCDisassembler::Success; 1226 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1227 1228 uint32_t msb_mask = 0xFFFFFFFF; 1229 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1230 uint32_t lsb_mask = (1U << lsb) - 1; 1231 1232 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1233 return S; 1234} 1235 1236static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1237 uint64_t Address, const void *Decoder) { 1238 DecodeStatus S = MCDisassembler::Success; 1239 1240 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1241 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1242 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1243 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1244 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1245 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1246 1247 switch (Inst.getOpcode()) { 1248 case ARM::LDC_OFFSET: 1249 case ARM::LDC_PRE: 1250 case ARM::LDC_POST: 1251 case ARM::LDC_OPTION: 1252 case ARM::LDCL_OFFSET: 1253 case ARM::LDCL_PRE: 1254 case ARM::LDCL_POST: 1255 case ARM::LDCL_OPTION: 1256 case ARM::STC_OFFSET: 1257 case ARM::STC_PRE: 1258 case ARM::STC_POST: 1259 case ARM::STC_OPTION: 1260 case ARM::STCL_OFFSET: 1261 case ARM::STCL_PRE: 1262 case ARM::STCL_POST: 1263 case ARM::STCL_OPTION: 1264 case ARM::t2LDC_OFFSET: 1265 case ARM::t2LDC_PRE: 1266 case ARM::t2LDC_POST: 1267 case ARM::t2LDC_OPTION: 1268 case ARM::t2LDCL_OFFSET: 1269 case ARM::t2LDCL_PRE: 1270 case ARM::t2LDCL_POST: 1271 case ARM::t2LDCL_OPTION: 1272 case ARM::t2STC_OFFSET: 1273 case ARM::t2STC_PRE: 1274 case ARM::t2STC_POST: 1275 case ARM::t2STC_OPTION: 1276 case ARM::t2STCL_OFFSET: 1277 case ARM::t2STCL_PRE: 1278 case ARM::t2STCL_POST: 1279 case ARM::t2STCL_OPTION: 1280 if (coproc == 0xA || coproc == 0xB) 1281 return MCDisassembler::Fail; 1282 break; 1283 default: 1284 break; 1285 } 1286 1287 Inst.addOperand(MCOperand::CreateImm(coproc)); 1288 Inst.addOperand(MCOperand::CreateImm(CRd)); 1289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1290 return MCDisassembler::Fail; 1291 1292 switch (Inst.getOpcode()) { 1293 case ARM::t2LDC2_OFFSET: 1294 case ARM::t2LDC2L_OFFSET: 1295 case ARM::t2LDC2_PRE: 1296 case ARM::t2LDC2L_PRE: 1297 case ARM::t2STC2_OFFSET: 1298 case ARM::t2STC2L_OFFSET: 1299 case ARM::t2STC2_PRE: 1300 case ARM::t2STC2L_PRE: 1301 case ARM::LDC2_OFFSET: 1302 case ARM::LDC2L_OFFSET: 1303 case ARM::LDC2_PRE: 1304 case ARM::LDC2L_PRE: 1305 case ARM::STC2_OFFSET: 1306 case ARM::STC2L_OFFSET: 1307 case ARM::STC2_PRE: 1308 case ARM::STC2L_PRE: 1309 case ARM::t2LDC_OFFSET: 1310 case ARM::t2LDCL_OFFSET: 1311 case ARM::t2LDC_PRE: 1312 case ARM::t2LDCL_PRE: 1313 case ARM::t2STC_OFFSET: 1314 case ARM::t2STCL_OFFSET: 1315 case ARM::t2STC_PRE: 1316 case ARM::t2STCL_PRE: 1317 case ARM::LDC_OFFSET: 1318 case ARM::LDCL_OFFSET: 1319 case ARM::LDC_PRE: 1320 case ARM::LDCL_PRE: 1321 case ARM::STC_OFFSET: 1322 case ARM::STCL_OFFSET: 1323 case ARM::STC_PRE: 1324 case ARM::STCL_PRE: 1325 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1326 Inst.addOperand(MCOperand::CreateImm(imm)); 1327 break; 1328 case ARM::t2LDC2_POST: 1329 case ARM::t2LDC2L_POST: 1330 case ARM::t2STC2_POST: 1331 case ARM::t2STC2L_POST: 1332 case ARM::LDC2_POST: 1333 case ARM::LDC2L_POST: 1334 case ARM::STC2_POST: 1335 case ARM::STC2L_POST: 1336 case ARM::t2LDC_POST: 1337 case ARM::t2LDCL_POST: 1338 case ARM::t2STC_POST: 1339 case ARM::t2STCL_POST: 1340 case ARM::LDC_POST: 1341 case ARM::LDCL_POST: 1342 case ARM::STC_POST: 1343 case ARM::STCL_POST: 1344 imm |= U << 8; 1345 // fall through. 1346 default: 1347 // The 'option' variant doesn't encode 'U' in the immediate since 1348 // the immediate is unsigned [0,255]. 1349 Inst.addOperand(MCOperand::CreateImm(imm)); 1350 break; 1351 } 1352 1353 switch (Inst.getOpcode()) { 1354 case ARM::LDC_OFFSET: 1355 case ARM::LDC_PRE: 1356 case ARM::LDC_POST: 1357 case ARM::LDC_OPTION: 1358 case ARM::LDCL_OFFSET: 1359 case ARM::LDCL_PRE: 1360 case ARM::LDCL_POST: 1361 case ARM::LDCL_OPTION: 1362 case ARM::STC_OFFSET: 1363 case ARM::STC_PRE: 1364 case ARM::STC_POST: 1365 case ARM::STC_OPTION: 1366 case ARM::STCL_OFFSET: 1367 case ARM::STCL_PRE: 1368 case ARM::STCL_POST: 1369 case ARM::STCL_OPTION: 1370 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1371 return MCDisassembler::Fail; 1372 break; 1373 default: 1374 break; 1375 } 1376 1377 return S; 1378} 1379 1380static DecodeStatus 1381DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1382 uint64_t Address, const void *Decoder) { 1383 DecodeStatus S = MCDisassembler::Success; 1384 1385 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1386 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1387 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1388 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1389 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1390 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1391 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1392 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1393 1394 // On stores, the writeback operand precedes Rt. 1395 switch (Inst.getOpcode()) { 1396 case ARM::STR_POST_IMM: 1397 case ARM::STR_POST_REG: 1398 case ARM::STRB_POST_IMM: 1399 case ARM::STRB_POST_REG: 1400 case ARM::STRT_POST_REG: 1401 case ARM::STRT_POST_IMM: 1402 case ARM::STRBT_POST_REG: 1403 case ARM::STRBT_POST_IMM: 1404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1405 return MCDisassembler::Fail; 1406 break; 1407 default: 1408 break; 1409 } 1410 1411 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1412 return MCDisassembler::Fail; 1413 1414 // On loads, the writeback operand comes after Rt. 1415 switch (Inst.getOpcode()) { 1416 case ARM::LDR_POST_IMM: 1417 case ARM::LDR_POST_REG: 1418 case ARM::LDRB_POST_IMM: 1419 case ARM::LDRB_POST_REG: 1420 case ARM::LDRBT_POST_REG: 1421 case ARM::LDRBT_POST_IMM: 1422 case ARM::LDRT_POST_REG: 1423 case ARM::LDRT_POST_IMM: 1424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1425 return MCDisassembler::Fail; 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1432 return MCDisassembler::Fail; 1433 1434 ARM_AM::AddrOpc Op = ARM_AM::add; 1435 if (!fieldFromInstruction32(Insn, 23, 1)) 1436 Op = ARM_AM::sub; 1437 1438 bool writeback = (P == 0) || (W == 1); 1439 unsigned idx_mode = 0; 1440 if (P && writeback) 1441 idx_mode = ARMII::IndexModePre; 1442 else if (!P && writeback) 1443 idx_mode = ARMII::IndexModePost; 1444 1445 if (writeback && (Rn == 15 || Rn == Rt)) 1446 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1447 1448 if (reg) { 1449 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1450 return MCDisassembler::Fail; 1451 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1452 switch( fieldFromInstruction32(Insn, 5, 2)) { 1453 case 0: 1454 Opc = ARM_AM::lsl; 1455 break; 1456 case 1: 1457 Opc = ARM_AM::lsr; 1458 break; 1459 case 2: 1460 Opc = ARM_AM::asr; 1461 break; 1462 case 3: 1463 Opc = ARM_AM::ror; 1464 break; 1465 default: 1466 return MCDisassembler::Fail; 1467 } 1468 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1469 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1470 1471 Inst.addOperand(MCOperand::CreateImm(imm)); 1472 } else { 1473 Inst.addOperand(MCOperand::CreateReg(0)); 1474 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1475 Inst.addOperand(MCOperand::CreateImm(tmp)); 1476 } 1477 1478 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1479 return MCDisassembler::Fail; 1480 1481 return S; 1482} 1483 1484static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1485 uint64_t Address, const void *Decoder) { 1486 DecodeStatus S = MCDisassembler::Success; 1487 1488 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1489 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1490 unsigned type = fieldFromInstruction32(Val, 5, 2); 1491 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1492 unsigned U = fieldFromInstruction32(Val, 12, 1); 1493 1494 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1495 switch (type) { 1496 case 0: 1497 ShOp = ARM_AM::lsl; 1498 break; 1499 case 1: 1500 ShOp = ARM_AM::lsr; 1501 break; 1502 case 2: 1503 ShOp = ARM_AM::asr; 1504 break; 1505 case 3: 1506 ShOp = ARM_AM::ror; 1507 break; 1508 } 1509 1510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1511 return MCDisassembler::Fail; 1512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1513 return MCDisassembler::Fail; 1514 unsigned shift; 1515 if (U) 1516 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1517 else 1518 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1519 Inst.addOperand(MCOperand::CreateImm(shift)); 1520 1521 return S; 1522} 1523 1524static DecodeStatus 1525DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1526 uint64_t Address, const void *Decoder) { 1527 DecodeStatus S = MCDisassembler::Success; 1528 1529 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1530 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1531 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1532 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1533 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1534 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1535 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1536 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1537 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1538 unsigned Rt2 = Rt + 1; 1539 1540 bool writeback = (W == 1) | (P == 0); 1541 1542 // For {LD,ST}RD, Rt must be even, else undefined. 1543 switch (Inst.getOpcode()) { 1544 case ARM::STRD: 1545 case ARM::STRD_PRE: 1546 case ARM::STRD_POST: 1547 case ARM::LDRD: 1548 case ARM::LDRD_PRE: 1549 case ARM::LDRD_POST: 1550 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1551 break; 1552 default: 1553 break; 1554 } 1555 switch (Inst.getOpcode()) { 1556 case ARM::STRD: 1557 case ARM::STRD_PRE: 1558 case ARM::STRD_POST: 1559 if (P == 0 && W == 1) 1560 S = MCDisassembler::SoftFail; 1561 1562 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1563 S = MCDisassembler::SoftFail; 1564 if (type && Rm == 15) 1565 S = MCDisassembler::SoftFail; 1566 if (Rt2 == 15) 1567 S = MCDisassembler::SoftFail; 1568 if (!type && fieldFromInstruction32(Insn, 8, 4)) 1569 S = MCDisassembler::SoftFail; 1570 break; 1571 case ARM::STRH: 1572 case ARM::STRH_PRE: 1573 case ARM::STRH_POST: 1574 if (Rt == 15) 1575 S = MCDisassembler::SoftFail; 1576 if (writeback && (Rn == 15 || Rn == Rt)) 1577 S = MCDisassembler::SoftFail; 1578 if (!type && Rm == 15) 1579 S = MCDisassembler::SoftFail; 1580 break; 1581 case ARM::LDRD: 1582 case ARM::LDRD_PRE: 1583 case ARM::LDRD_POST: 1584 if (type && Rn == 15){ 1585 if (Rt2 == 15) 1586 S = MCDisassembler::SoftFail; 1587 break; 1588 } 1589 if (P == 0 && W == 1) 1590 S = MCDisassembler::SoftFail; 1591 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1592 S = MCDisassembler::SoftFail; 1593 if (!type && writeback && Rn == 15) 1594 S = MCDisassembler::SoftFail; 1595 if (writeback && (Rn == Rt || Rn == Rt2)) 1596 S = MCDisassembler::SoftFail; 1597 break; 1598 case ARM::LDRH: 1599 case ARM::LDRH_PRE: 1600 case ARM::LDRH_POST: 1601 if (type && Rn == 15){ 1602 if (Rt == 15) 1603 S = MCDisassembler::SoftFail; 1604 break; 1605 } 1606 if (Rt == 15) 1607 S = MCDisassembler::SoftFail; 1608 if (!type && Rm == 15) 1609 S = MCDisassembler::SoftFail; 1610 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1611 S = MCDisassembler::SoftFail; 1612 break; 1613 case ARM::LDRSH: 1614 case ARM::LDRSH_PRE: 1615 case ARM::LDRSH_POST: 1616 case ARM::LDRSB: 1617 case ARM::LDRSB_PRE: 1618 case ARM::LDRSB_POST: 1619 if (type && Rn == 15){ 1620 if (Rt == 15) 1621 S = MCDisassembler::SoftFail; 1622 break; 1623 } 1624 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1625 S = MCDisassembler::SoftFail; 1626 if (!type && (Rt == 15 || Rm == 15)) 1627 S = MCDisassembler::SoftFail; 1628 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1629 S = MCDisassembler::SoftFail; 1630 break; 1631 default: 1632 break; 1633 } 1634 1635 if (writeback) { // Writeback 1636 if (P) 1637 U |= ARMII::IndexModePre << 9; 1638 else 1639 U |= ARMII::IndexModePost << 9; 1640 1641 // On stores, the writeback operand precedes Rt. 1642 switch (Inst.getOpcode()) { 1643 case ARM::STRD: 1644 case ARM::STRD_PRE: 1645 case ARM::STRD_POST: 1646 case ARM::STRH: 1647 case ARM::STRH_PRE: 1648 case ARM::STRH_POST: 1649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1650 return MCDisassembler::Fail; 1651 break; 1652 default: 1653 break; 1654 } 1655 } 1656 1657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1658 return MCDisassembler::Fail; 1659 switch (Inst.getOpcode()) { 1660 case ARM::STRD: 1661 case ARM::STRD_PRE: 1662 case ARM::STRD_POST: 1663 case ARM::LDRD: 1664 case ARM::LDRD_PRE: 1665 case ARM::LDRD_POST: 1666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1667 return MCDisassembler::Fail; 1668 break; 1669 default: 1670 break; 1671 } 1672 1673 if (writeback) { 1674 // On loads, the writeback operand comes after Rt. 1675 switch (Inst.getOpcode()) { 1676 case ARM::LDRD: 1677 case ARM::LDRD_PRE: 1678 case ARM::LDRD_POST: 1679 case ARM::LDRH: 1680 case ARM::LDRH_PRE: 1681 case ARM::LDRH_POST: 1682 case ARM::LDRSH: 1683 case ARM::LDRSH_PRE: 1684 case ARM::LDRSH_POST: 1685 case ARM::LDRSB: 1686 case ARM::LDRSB_PRE: 1687 case ARM::LDRSB_POST: 1688 case ARM::LDRHTr: 1689 case ARM::LDRSBTr: 1690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1691 return MCDisassembler::Fail; 1692 break; 1693 default: 1694 break; 1695 } 1696 } 1697 1698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1699 return MCDisassembler::Fail; 1700 1701 if (type) { 1702 Inst.addOperand(MCOperand::CreateReg(0)); 1703 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1704 } else { 1705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1706 return MCDisassembler::Fail; 1707 Inst.addOperand(MCOperand::CreateImm(U)); 1708 } 1709 1710 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1711 return MCDisassembler::Fail; 1712 1713 return S; 1714} 1715 1716static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1717 uint64_t Address, const void *Decoder) { 1718 DecodeStatus S = MCDisassembler::Success; 1719 1720 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1721 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1722 1723 switch (mode) { 1724 case 0: 1725 mode = ARM_AM::da; 1726 break; 1727 case 1: 1728 mode = ARM_AM::ia; 1729 break; 1730 case 2: 1731 mode = ARM_AM::db; 1732 break; 1733 case 3: 1734 mode = ARM_AM::ib; 1735 break; 1736 } 1737 1738 Inst.addOperand(MCOperand::CreateImm(mode)); 1739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1740 return MCDisassembler::Fail; 1741 1742 return S; 1743} 1744 1745static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1746 unsigned Insn, 1747 uint64_t Address, const void *Decoder) { 1748 DecodeStatus S = MCDisassembler::Success; 1749 1750 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1751 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1752 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1753 1754 if (pred == 0xF) { 1755 switch (Inst.getOpcode()) { 1756 case ARM::LDMDA: 1757 Inst.setOpcode(ARM::RFEDA); 1758 break; 1759 case ARM::LDMDA_UPD: 1760 Inst.setOpcode(ARM::RFEDA_UPD); 1761 break; 1762 case ARM::LDMDB: 1763 Inst.setOpcode(ARM::RFEDB); 1764 break; 1765 case ARM::LDMDB_UPD: 1766 Inst.setOpcode(ARM::RFEDB_UPD); 1767 break; 1768 case ARM::LDMIA: 1769 Inst.setOpcode(ARM::RFEIA); 1770 break; 1771 case ARM::LDMIA_UPD: 1772 Inst.setOpcode(ARM::RFEIA_UPD); 1773 break; 1774 case ARM::LDMIB: 1775 Inst.setOpcode(ARM::RFEIB); 1776 break; 1777 case ARM::LDMIB_UPD: 1778 Inst.setOpcode(ARM::RFEIB_UPD); 1779 break; 1780 case ARM::STMDA: 1781 Inst.setOpcode(ARM::SRSDA); 1782 break; 1783 case ARM::STMDA_UPD: 1784 Inst.setOpcode(ARM::SRSDA_UPD); 1785 break; 1786 case ARM::STMDB: 1787 Inst.setOpcode(ARM::SRSDB); 1788 break; 1789 case ARM::STMDB_UPD: 1790 Inst.setOpcode(ARM::SRSDB_UPD); 1791 break; 1792 case ARM::STMIA: 1793 Inst.setOpcode(ARM::SRSIA); 1794 break; 1795 case ARM::STMIA_UPD: 1796 Inst.setOpcode(ARM::SRSIA_UPD); 1797 break; 1798 case ARM::STMIB: 1799 Inst.setOpcode(ARM::SRSIB); 1800 break; 1801 case ARM::STMIB_UPD: 1802 Inst.setOpcode(ARM::SRSIB_UPD); 1803 break; 1804 default: 1805 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1806 } 1807 1808 // For stores (which become SRS's, the only operand is the mode. 1809 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1810 Inst.addOperand( 1811 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1812 return S; 1813 } 1814 1815 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1816 } 1817 1818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1819 return MCDisassembler::Fail; 1820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1821 return MCDisassembler::Fail; // Tied 1822 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1823 return MCDisassembler::Fail; 1824 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1825 return MCDisassembler::Fail; 1826 1827 return S; 1828} 1829 1830static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1831 uint64_t Address, const void *Decoder) { 1832 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1833 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1834 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1835 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1836 1837 DecodeStatus S = MCDisassembler::Success; 1838 1839 // imod == '01' --> UNPREDICTABLE 1840 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1841 // return failure here. The '01' imod value is unprintable, so there's 1842 // nothing useful we could do even if we returned UNPREDICTABLE. 1843 1844 if (imod == 1) return MCDisassembler::Fail; 1845 1846 if (imod && M) { 1847 Inst.setOpcode(ARM::CPS3p); 1848 Inst.addOperand(MCOperand::CreateImm(imod)); 1849 Inst.addOperand(MCOperand::CreateImm(iflags)); 1850 Inst.addOperand(MCOperand::CreateImm(mode)); 1851 } else if (imod && !M) { 1852 Inst.setOpcode(ARM::CPS2p); 1853 Inst.addOperand(MCOperand::CreateImm(imod)); 1854 Inst.addOperand(MCOperand::CreateImm(iflags)); 1855 if (mode) S = MCDisassembler::SoftFail; 1856 } else if (!imod && M) { 1857 Inst.setOpcode(ARM::CPS1p); 1858 Inst.addOperand(MCOperand::CreateImm(mode)); 1859 if (iflags) S = MCDisassembler::SoftFail; 1860 } else { 1861 // imod == '00' && M == '0' --> UNPREDICTABLE 1862 Inst.setOpcode(ARM::CPS1p); 1863 Inst.addOperand(MCOperand::CreateImm(mode)); 1864 S = MCDisassembler::SoftFail; 1865 } 1866 1867 return S; 1868} 1869 1870static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1871 uint64_t Address, const void *Decoder) { 1872 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1873 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1874 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1875 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1876 1877 DecodeStatus S = MCDisassembler::Success; 1878 1879 // imod == '01' --> UNPREDICTABLE 1880 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1881 // return failure here. The '01' imod value is unprintable, so there's 1882 // nothing useful we could do even if we returned UNPREDICTABLE. 1883 1884 if (imod == 1) return MCDisassembler::Fail; 1885 1886 if (imod && M) { 1887 Inst.setOpcode(ARM::t2CPS3p); 1888 Inst.addOperand(MCOperand::CreateImm(imod)); 1889 Inst.addOperand(MCOperand::CreateImm(iflags)); 1890 Inst.addOperand(MCOperand::CreateImm(mode)); 1891 } else if (imod && !M) { 1892 Inst.setOpcode(ARM::t2CPS2p); 1893 Inst.addOperand(MCOperand::CreateImm(imod)); 1894 Inst.addOperand(MCOperand::CreateImm(iflags)); 1895 if (mode) S = MCDisassembler::SoftFail; 1896 } else if (!imod && M) { 1897 Inst.setOpcode(ARM::t2CPS1p); 1898 Inst.addOperand(MCOperand::CreateImm(mode)); 1899 if (iflags) S = MCDisassembler::SoftFail; 1900 } else { 1901 // imod == '00' && M == '0' --> UNPREDICTABLE 1902 Inst.setOpcode(ARM::t2CPS1p); 1903 Inst.addOperand(MCOperand::CreateImm(mode)); 1904 S = MCDisassembler::SoftFail; 1905 } 1906 1907 return S; 1908} 1909 1910static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1911 uint64_t Address, const void *Decoder) { 1912 DecodeStatus S = MCDisassembler::Success; 1913 1914 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1915 unsigned imm = 0; 1916 1917 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1918 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1919 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1920 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1921 1922 if (Inst.getOpcode() == ARM::t2MOVTi16) 1923 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1924 return MCDisassembler::Fail; 1925 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1926 return MCDisassembler::Fail; 1927 1928 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1929 Inst.addOperand(MCOperand::CreateImm(imm)); 1930 1931 return S; 1932} 1933 1934static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 1935 uint64_t Address, const void *Decoder) { 1936 DecodeStatus S = MCDisassembler::Success; 1937 1938 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1939 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1940 unsigned imm = 0; 1941 1942 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1943 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1944 1945 if (Inst.getOpcode() == ARM::MOVTi16) 1946 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1947 return MCDisassembler::Fail; 1948 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 1951 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1952 Inst.addOperand(MCOperand::CreateImm(imm)); 1953 1954 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1955 return MCDisassembler::Fail; 1956 1957 return S; 1958} 1959 1960static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 1961 uint64_t Address, const void *Decoder) { 1962 DecodeStatus S = MCDisassembler::Success; 1963 1964 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1965 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1966 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1967 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1968 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1969 1970 if (pred == 0xF) 1971 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1972 1973 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1976 return MCDisassembler::Fail; 1977 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1978 return MCDisassembler::Fail; 1979 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1980 return MCDisassembler::Fail; 1981 1982 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1983 return MCDisassembler::Fail; 1984 1985 return S; 1986} 1987 1988static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 1989 uint64_t Address, const void *Decoder) { 1990 DecodeStatus S = MCDisassembler::Success; 1991 1992 unsigned add = fieldFromInstruction32(Val, 12, 1); 1993 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1994 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1995 1996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1997 return MCDisassembler::Fail; 1998 1999 if (!add) imm *= -1; 2000 if (imm == 0 && !add) imm = INT32_MIN; 2001 Inst.addOperand(MCOperand::CreateImm(imm)); 2002 if (Rn == 15) 2003 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2004 2005 return S; 2006} 2007 2008static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2009 uint64_t Address, const void *Decoder) { 2010 DecodeStatus S = MCDisassembler::Success; 2011 2012 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2013 unsigned U = fieldFromInstruction32(Val, 8, 1); 2014 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2015 2016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2017 return MCDisassembler::Fail; 2018 2019 if (U) 2020 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2021 else 2022 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2023 2024 return S; 2025} 2026 2027static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2028 uint64_t Address, const void *Decoder) { 2029 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2030} 2031 2032static DecodeStatus 2033DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2034 uint64_t Address, const void *Decoder) { 2035 DecodeStatus S = MCDisassembler::Success; 2036 2037 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2038 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 2039 2040 if (pred == 0xF) { 2041 Inst.setOpcode(ARM::BLXi); 2042 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 2043 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2044 true, 4, Inst, Decoder)) 2045 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2046 return S; 2047 } 2048 2049 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2050 true, 4, Inst, Decoder)) 2051 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2052 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2053 return MCDisassembler::Fail; 2054 2055 return S; 2056} 2057 2058 2059static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2060 uint64_t Address, const void *Decoder) { 2061 DecodeStatus S = MCDisassembler::Success; 2062 2063 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 2064 unsigned align = fieldFromInstruction32(Val, 4, 2); 2065 2066 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2067 return MCDisassembler::Fail; 2068 if (!align) 2069 Inst.addOperand(MCOperand::CreateImm(0)); 2070 else 2071 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2072 2073 return S; 2074} 2075 2076static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2077 uint64_t Address, const void *Decoder) { 2078 DecodeStatus S = MCDisassembler::Success; 2079 2080 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2081 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2082 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2083 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2084 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2085 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2086 2087 // First output register 2088 switch (Inst.getOpcode()) { 2089 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2090 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2091 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2092 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2093 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2094 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2095 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2096 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2097 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2098 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2099 return MCDisassembler::Fail; 2100 break; 2101 case ARM::VLD2b16: 2102 case ARM::VLD2b32: 2103 case ARM::VLD2b8: 2104 case ARM::VLD2b16wb_fixed: 2105 case ARM::VLD2b16wb_register: 2106 case ARM::VLD2b32wb_fixed: 2107 case ARM::VLD2b32wb_register: 2108 case ARM::VLD2b8wb_fixed: 2109 case ARM::VLD2b8wb_register: 2110 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2111 return MCDisassembler::Fail; 2112 break; 2113 default: 2114 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2115 return MCDisassembler::Fail; 2116 } 2117 2118 // Second output register 2119 switch (Inst.getOpcode()) { 2120 case ARM::VLD3d8: 2121 case ARM::VLD3d16: 2122 case ARM::VLD3d32: 2123 case ARM::VLD3d8_UPD: 2124 case ARM::VLD3d16_UPD: 2125 case ARM::VLD3d32_UPD: 2126 case ARM::VLD4d8: 2127 case ARM::VLD4d16: 2128 case ARM::VLD4d32: 2129 case ARM::VLD4d8_UPD: 2130 case ARM::VLD4d16_UPD: 2131 case ARM::VLD4d32_UPD: 2132 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2133 return MCDisassembler::Fail; 2134 break; 2135 case ARM::VLD3q8: 2136 case ARM::VLD3q16: 2137 case ARM::VLD3q32: 2138 case ARM::VLD3q8_UPD: 2139 case ARM::VLD3q16_UPD: 2140 case ARM::VLD3q32_UPD: 2141 case ARM::VLD4q8: 2142 case ARM::VLD4q16: 2143 case ARM::VLD4q32: 2144 case ARM::VLD4q8_UPD: 2145 case ARM::VLD4q16_UPD: 2146 case ARM::VLD4q32_UPD: 2147 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2148 return MCDisassembler::Fail; 2149 default: 2150 break; 2151 } 2152 2153 // Third output register 2154 switch(Inst.getOpcode()) { 2155 case ARM::VLD3d8: 2156 case ARM::VLD3d16: 2157 case ARM::VLD3d32: 2158 case ARM::VLD3d8_UPD: 2159 case ARM::VLD3d16_UPD: 2160 case ARM::VLD3d32_UPD: 2161 case ARM::VLD4d8: 2162 case ARM::VLD4d16: 2163 case ARM::VLD4d32: 2164 case ARM::VLD4d8_UPD: 2165 case ARM::VLD4d16_UPD: 2166 case ARM::VLD4d32_UPD: 2167 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2168 return MCDisassembler::Fail; 2169 break; 2170 case ARM::VLD3q8: 2171 case ARM::VLD3q16: 2172 case ARM::VLD3q32: 2173 case ARM::VLD3q8_UPD: 2174 case ARM::VLD3q16_UPD: 2175 case ARM::VLD3q32_UPD: 2176 case ARM::VLD4q8: 2177 case ARM::VLD4q16: 2178 case ARM::VLD4q32: 2179 case ARM::VLD4q8_UPD: 2180 case ARM::VLD4q16_UPD: 2181 case ARM::VLD4q32_UPD: 2182 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2183 return MCDisassembler::Fail; 2184 break; 2185 default: 2186 break; 2187 } 2188 2189 // Fourth output register 2190 switch (Inst.getOpcode()) { 2191 case ARM::VLD4d8: 2192 case ARM::VLD4d16: 2193 case ARM::VLD4d32: 2194 case ARM::VLD4d8_UPD: 2195 case ARM::VLD4d16_UPD: 2196 case ARM::VLD4d32_UPD: 2197 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2198 return MCDisassembler::Fail; 2199 break; 2200 case ARM::VLD4q8: 2201 case ARM::VLD4q16: 2202 case ARM::VLD4q32: 2203 case ARM::VLD4q8_UPD: 2204 case ARM::VLD4q16_UPD: 2205 case ARM::VLD4q32_UPD: 2206 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2207 return MCDisassembler::Fail; 2208 break; 2209 default: 2210 break; 2211 } 2212 2213 // Writeback operand 2214 switch (Inst.getOpcode()) { 2215 case ARM::VLD1d8wb_fixed: 2216 case ARM::VLD1d16wb_fixed: 2217 case ARM::VLD1d32wb_fixed: 2218 case ARM::VLD1d64wb_fixed: 2219 case ARM::VLD1d8wb_register: 2220 case ARM::VLD1d16wb_register: 2221 case ARM::VLD1d32wb_register: 2222 case ARM::VLD1d64wb_register: 2223 case ARM::VLD1q8wb_fixed: 2224 case ARM::VLD1q16wb_fixed: 2225 case ARM::VLD1q32wb_fixed: 2226 case ARM::VLD1q64wb_fixed: 2227 case ARM::VLD1q8wb_register: 2228 case ARM::VLD1q16wb_register: 2229 case ARM::VLD1q32wb_register: 2230 case ARM::VLD1q64wb_register: 2231 case ARM::VLD1d8Twb_fixed: 2232 case ARM::VLD1d8Twb_register: 2233 case ARM::VLD1d16Twb_fixed: 2234 case ARM::VLD1d16Twb_register: 2235 case ARM::VLD1d32Twb_fixed: 2236 case ARM::VLD1d32Twb_register: 2237 case ARM::VLD1d64Twb_fixed: 2238 case ARM::VLD1d64Twb_register: 2239 case ARM::VLD1d8Qwb_fixed: 2240 case ARM::VLD1d8Qwb_register: 2241 case ARM::VLD1d16Qwb_fixed: 2242 case ARM::VLD1d16Qwb_register: 2243 case ARM::VLD1d32Qwb_fixed: 2244 case ARM::VLD1d32Qwb_register: 2245 case ARM::VLD1d64Qwb_fixed: 2246 case ARM::VLD1d64Qwb_register: 2247 case ARM::VLD2d8wb_fixed: 2248 case ARM::VLD2d16wb_fixed: 2249 case ARM::VLD2d32wb_fixed: 2250 case ARM::VLD2q8wb_fixed: 2251 case ARM::VLD2q16wb_fixed: 2252 case ARM::VLD2q32wb_fixed: 2253 case ARM::VLD2d8wb_register: 2254 case ARM::VLD2d16wb_register: 2255 case ARM::VLD2d32wb_register: 2256 case ARM::VLD2q8wb_register: 2257 case ARM::VLD2q16wb_register: 2258 case ARM::VLD2q32wb_register: 2259 case ARM::VLD2b8wb_fixed: 2260 case ARM::VLD2b16wb_fixed: 2261 case ARM::VLD2b32wb_fixed: 2262 case ARM::VLD2b8wb_register: 2263 case ARM::VLD2b16wb_register: 2264 case ARM::VLD2b32wb_register: 2265 Inst.addOperand(MCOperand::CreateImm(0)); 2266 break; 2267 case ARM::VLD3d8_UPD: 2268 case ARM::VLD3d16_UPD: 2269 case ARM::VLD3d32_UPD: 2270 case ARM::VLD3q8_UPD: 2271 case ARM::VLD3q16_UPD: 2272 case ARM::VLD3q32_UPD: 2273 case ARM::VLD4d8_UPD: 2274 case ARM::VLD4d16_UPD: 2275 case ARM::VLD4d32_UPD: 2276 case ARM::VLD4q8_UPD: 2277 case ARM::VLD4q16_UPD: 2278 case ARM::VLD4q32_UPD: 2279 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2280 return MCDisassembler::Fail; 2281 break; 2282 default: 2283 break; 2284 } 2285 2286 // AddrMode6 Base (register+alignment) 2287 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2288 return MCDisassembler::Fail; 2289 2290 // AddrMode6 Offset (register) 2291 switch (Inst.getOpcode()) { 2292 default: 2293 // The below have been updated to have explicit am6offset split 2294 // between fixed and register offset. For those instructions not 2295 // yet updated, we need to add an additional reg0 operand for the 2296 // fixed variant. 2297 // 2298 // The fixed offset encodes as Rm == 0xd, so we check for that. 2299 if (Rm == 0xd) { 2300 Inst.addOperand(MCOperand::CreateReg(0)); 2301 break; 2302 } 2303 // Fall through to handle the register offset variant. 2304 case ARM::VLD1d8wb_fixed: 2305 case ARM::VLD1d16wb_fixed: 2306 case ARM::VLD1d32wb_fixed: 2307 case ARM::VLD1d64wb_fixed: 2308 case ARM::VLD1d8Twb_fixed: 2309 case ARM::VLD1d16Twb_fixed: 2310 case ARM::VLD1d32Twb_fixed: 2311 case ARM::VLD1d64Twb_fixed: 2312 case ARM::VLD1d8Qwb_fixed: 2313 case ARM::VLD1d16Qwb_fixed: 2314 case ARM::VLD1d32Qwb_fixed: 2315 case ARM::VLD1d64Qwb_fixed: 2316 case ARM::VLD1d8wb_register: 2317 case ARM::VLD1d16wb_register: 2318 case ARM::VLD1d32wb_register: 2319 case ARM::VLD1d64wb_register: 2320 case ARM::VLD1q8wb_fixed: 2321 case ARM::VLD1q16wb_fixed: 2322 case ARM::VLD1q32wb_fixed: 2323 case ARM::VLD1q64wb_fixed: 2324 case ARM::VLD1q8wb_register: 2325 case ARM::VLD1q16wb_register: 2326 case ARM::VLD1q32wb_register: 2327 case ARM::VLD1q64wb_register: 2328 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2329 // variant encodes Rm == 0xf. Anything else is a register offset post- 2330 // increment and we need to add the register operand to the instruction. 2331 if (Rm != 0xD && Rm != 0xF && 2332 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2333 return MCDisassembler::Fail; 2334 break; 2335 case ARM::VLD2d8wb_fixed: 2336 case ARM::VLD2d16wb_fixed: 2337 case ARM::VLD2d32wb_fixed: 2338 case ARM::VLD2b8wb_fixed: 2339 case ARM::VLD2b16wb_fixed: 2340 case ARM::VLD2b32wb_fixed: 2341 case ARM::VLD2q8wb_fixed: 2342 case ARM::VLD2q16wb_fixed: 2343 case ARM::VLD2q32wb_fixed: 2344 break; 2345 } 2346 2347 return S; 2348} 2349 2350static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2351 uint64_t Address, const void *Decoder) { 2352 DecodeStatus S = MCDisassembler::Success; 2353 2354 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2355 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2356 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2357 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2358 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2359 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2360 2361 // Writeback Operand 2362 switch (Inst.getOpcode()) { 2363 case ARM::VST1d8wb_fixed: 2364 case ARM::VST1d16wb_fixed: 2365 case ARM::VST1d32wb_fixed: 2366 case ARM::VST1d64wb_fixed: 2367 case ARM::VST1d8wb_register: 2368 case ARM::VST1d16wb_register: 2369 case ARM::VST1d32wb_register: 2370 case ARM::VST1d64wb_register: 2371 case ARM::VST1q8wb_fixed: 2372 case ARM::VST1q16wb_fixed: 2373 case ARM::VST1q32wb_fixed: 2374 case ARM::VST1q64wb_fixed: 2375 case ARM::VST1q8wb_register: 2376 case ARM::VST1q16wb_register: 2377 case ARM::VST1q32wb_register: 2378 case ARM::VST1q64wb_register: 2379 case ARM::VST1d8Twb_fixed: 2380 case ARM::VST1d16Twb_fixed: 2381 case ARM::VST1d32Twb_fixed: 2382 case ARM::VST1d64Twb_fixed: 2383 case ARM::VST1d8Twb_register: 2384 case ARM::VST1d16Twb_register: 2385 case ARM::VST1d32Twb_register: 2386 case ARM::VST1d64Twb_register: 2387 case ARM::VST1d8Qwb_fixed: 2388 case ARM::VST1d16Qwb_fixed: 2389 case ARM::VST1d32Qwb_fixed: 2390 case ARM::VST1d64Qwb_fixed: 2391 case ARM::VST1d8Qwb_register: 2392 case ARM::VST1d16Qwb_register: 2393 case ARM::VST1d32Qwb_register: 2394 case ARM::VST1d64Qwb_register: 2395 case ARM::VST2d8wb_fixed: 2396 case ARM::VST2d16wb_fixed: 2397 case ARM::VST2d32wb_fixed: 2398 case ARM::VST2d8wb_register: 2399 case ARM::VST2d16wb_register: 2400 case ARM::VST2d32wb_register: 2401 case ARM::VST2q8wb_fixed: 2402 case ARM::VST2q16wb_fixed: 2403 case ARM::VST2q32wb_fixed: 2404 case ARM::VST2q8wb_register: 2405 case ARM::VST2q16wb_register: 2406 case ARM::VST2q32wb_register: 2407 case ARM::VST2b8wb_fixed: 2408 case ARM::VST2b16wb_fixed: 2409 case ARM::VST2b32wb_fixed: 2410 case ARM::VST2b8wb_register: 2411 case ARM::VST2b16wb_register: 2412 case ARM::VST2b32wb_register: 2413 Inst.addOperand(MCOperand::CreateImm(0)); 2414 break; 2415 case ARM::VST3d8_UPD: 2416 case ARM::VST3d16_UPD: 2417 case ARM::VST3d32_UPD: 2418 case ARM::VST3q8_UPD: 2419 case ARM::VST3q16_UPD: 2420 case ARM::VST3q32_UPD: 2421 case ARM::VST4d8_UPD: 2422 case ARM::VST4d16_UPD: 2423 case ARM::VST4d32_UPD: 2424 case ARM::VST4q8_UPD: 2425 case ARM::VST4q16_UPD: 2426 case ARM::VST4q32_UPD: 2427 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2428 return MCDisassembler::Fail; 2429 break; 2430 default: 2431 break; 2432 } 2433 2434 // AddrMode6 Base (register+alignment) 2435 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2436 return MCDisassembler::Fail; 2437 2438 // AddrMode6 Offset (register) 2439 switch (Inst.getOpcode()) { 2440 default: 2441 if (Rm == 0xD) 2442 Inst.addOperand(MCOperand::CreateReg(0)); 2443 else if (Rm != 0xF) { 2444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2445 return MCDisassembler::Fail; 2446 } 2447 break; 2448 case ARM::VST1d8wb_fixed: 2449 case ARM::VST1d16wb_fixed: 2450 case ARM::VST1d32wb_fixed: 2451 case ARM::VST1d64wb_fixed: 2452 case ARM::VST1q8wb_fixed: 2453 case ARM::VST1q16wb_fixed: 2454 case ARM::VST1q32wb_fixed: 2455 case ARM::VST1q64wb_fixed: 2456 case ARM::VST1d8Twb_fixed: 2457 case ARM::VST1d16Twb_fixed: 2458 case ARM::VST1d32Twb_fixed: 2459 case ARM::VST1d64Twb_fixed: 2460 case ARM::VST1d8Qwb_fixed: 2461 case ARM::VST1d16Qwb_fixed: 2462 case ARM::VST1d32Qwb_fixed: 2463 case ARM::VST1d64Qwb_fixed: 2464 case ARM::VST2d8wb_fixed: 2465 case ARM::VST2d16wb_fixed: 2466 case ARM::VST2d32wb_fixed: 2467 case ARM::VST2q8wb_fixed: 2468 case ARM::VST2q16wb_fixed: 2469 case ARM::VST2q32wb_fixed: 2470 case ARM::VST2b8wb_fixed: 2471 case ARM::VST2b16wb_fixed: 2472 case ARM::VST2b32wb_fixed: 2473 break; 2474 } 2475 2476 2477 // First input register 2478 switch (Inst.getOpcode()) { 2479 case ARM::VST1q16: 2480 case ARM::VST1q32: 2481 case ARM::VST1q64: 2482 case ARM::VST1q8: 2483 case ARM::VST1q16wb_fixed: 2484 case ARM::VST1q16wb_register: 2485 case ARM::VST1q32wb_fixed: 2486 case ARM::VST1q32wb_register: 2487 case ARM::VST1q64wb_fixed: 2488 case ARM::VST1q64wb_register: 2489 case ARM::VST1q8wb_fixed: 2490 case ARM::VST1q8wb_register: 2491 case ARM::VST2d16: 2492 case ARM::VST2d32: 2493 case ARM::VST2d8: 2494 case ARM::VST2d16wb_fixed: 2495 case ARM::VST2d16wb_register: 2496 case ARM::VST2d32wb_fixed: 2497 case ARM::VST2d32wb_register: 2498 case ARM::VST2d8wb_fixed: 2499 case ARM::VST2d8wb_register: 2500 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2501 return MCDisassembler::Fail; 2502 break; 2503 case ARM::VST2b16: 2504 case ARM::VST2b32: 2505 case ARM::VST2b8: 2506 case ARM::VST2b16wb_fixed: 2507 case ARM::VST2b16wb_register: 2508 case ARM::VST2b32wb_fixed: 2509 case ARM::VST2b32wb_register: 2510 case ARM::VST2b8wb_fixed: 2511 case ARM::VST2b8wb_register: 2512 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2513 return MCDisassembler::Fail; 2514 break; 2515 default: 2516 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2517 return MCDisassembler::Fail; 2518 } 2519 2520 // Second input register 2521 switch (Inst.getOpcode()) { 2522 case ARM::VST3d8: 2523 case ARM::VST3d16: 2524 case ARM::VST3d32: 2525 case ARM::VST3d8_UPD: 2526 case ARM::VST3d16_UPD: 2527 case ARM::VST3d32_UPD: 2528 case ARM::VST4d8: 2529 case ARM::VST4d16: 2530 case ARM::VST4d32: 2531 case ARM::VST4d8_UPD: 2532 case ARM::VST4d16_UPD: 2533 case ARM::VST4d32_UPD: 2534 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2535 return MCDisassembler::Fail; 2536 break; 2537 case ARM::VST3q8: 2538 case ARM::VST3q16: 2539 case ARM::VST3q32: 2540 case ARM::VST3q8_UPD: 2541 case ARM::VST3q16_UPD: 2542 case ARM::VST3q32_UPD: 2543 case ARM::VST4q8: 2544 case ARM::VST4q16: 2545 case ARM::VST4q32: 2546 case ARM::VST4q8_UPD: 2547 case ARM::VST4q16_UPD: 2548 case ARM::VST4q32_UPD: 2549 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2550 return MCDisassembler::Fail; 2551 break; 2552 default: 2553 break; 2554 } 2555 2556 // Third input register 2557 switch (Inst.getOpcode()) { 2558 case ARM::VST3d8: 2559 case ARM::VST3d16: 2560 case ARM::VST3d32: 2561 case ARM::VST3d8_UPD: 2562 case ARM::VST3d16_UPD: 2563 case ARM::VST3d32_UPD: 2564 case ARM::VST4d8: 2565 case ARM::VST4d16: 2566 case ARM::VST4d32: 2567 case ARM::VST4d8_UPD: 2568 case ARM::VST4d16_UPD: 2569 case ARM::VST4d32_UPD: 2570 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2571 return MCDisassembler::Fail; 2572 break; 2573 case ARM::VST3q8: 2574 case ARM::VST3q16: 2575 case ARM::VST3q32: 2576 case ARM::VST3q8_UPD: 2577 case ARM::VST3q16_UPD: 2578 case ARM::VST3q32_UPD: 2579 case ARM::VST4q8: 2580 case ARM::VST4q16: 2581 case ARM::VST4q32: 2582 case ARM::VST4q8_UPD: 2583 case ARM::VST4q16_UPD: 2584 case ARM::VST4q32_UPD: 2585 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2586 return MCDisassembler::Fail; 2587 break; 2588 default: 2589 break; 2590 } 2591 2592 // Fourth input register 2593 switch (Inst.getOpcode()) { 2594 case ARM::VST4d8: 2595 case ARM::VST4d16: 2596 case ARM::VST4d32: 2597 case ARM::VST4d8_UPD: 2598 case ARM::VST4d16_UPD: 2599 case ARM::VST4d32_UPD: 2600 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2601 return MCDisassembler::Fail; 2602 break; 2603 case ARM::VST4q8: 2604 case ARM::VST4q16: 2605 case ARM::VST4q32: 2606 case ARM::VST4q8_UPD: 2607 case ARM::VST4q16_UPD: 2608 case ARM::VST4q32_UPD: 2609 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2610 return MCDisassembler::Fail; 2611 break; 2612 default: 2613 break; 2614 } 2615 2616 return S; 2617} 2618 2619static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2620 uint64_t Address, const void *Decoder) { 2621 DecodeStatus S = MCDisassembler::Success; 2622 2623 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2624 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2625 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2626 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2627 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2628 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2629 2630 align *= (1 << size); 2631 2632 switch (Inst.getOpcode()) { 2633 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2634 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2635 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2636 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2637 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2638 return MCDisassembler::Fail; 2639 break; 2640 default: 2641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2642 return MCDisassembler::Fail; 2643 break; 2644 } 2645 if (Rm != 0xF) { 2646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2647 return MCDisassembler::Fail; 2648 } 2649 2650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2651 return MCDisassembler::Fail; 2652 Inst.addOperand(MCOperand::CreateImm(align)); 2653 2654 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2655 // variant encodes Rm == 0xf. Anything else is a register offset post- 2656 // increment and we need to add the register operand to the instruction. 2657 if (Rm != 0xD && Rm != 0xF && 2658 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2659 return MCDisassembler::Fail; 2660 2661 return S; 2662} 2663 2664static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2665 uint64_t Address, const void *Decoder) { 2666 DecodeStatus S = MCDisassembler::Success; 2667 2668 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2669 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2670 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2671 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2672 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2673 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2674 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2675 align *= 2*size; 2676 2677 switch (Inst.getOpcode()) { 2678 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2679 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2680 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2681 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2682 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2683 return MCDisassembler::Fail; 2684 break; 2685 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2686 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2687 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2688 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2689 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2690 return MCDisassembler::Fail; 2691 break; 2692 default: 2693 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2694 return MCDisassembler::Fail; 2695 break; 2696 } 2697 2698 if (Rm != 0xF) 2699 Inst.addOperand(MCOperand::CreateImm(0)); 2700 2701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2702 return MCDisassembler::Fail; 2703 Inst.addOperand(MCOperand::CreateImm(align)); 2704 2705 if (Rm == 0xD) 2706 Inst.addOperand(MCOperand::CreateReg(0)); 2707 else if (Rm != 0xF) { 2708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2709 return MCDisassembler::Fail; 2710 } 2711 2712 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2713 return MCDisassembler::Fail; 2714 2715 return S; 2716} 2717 2718static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2719 uint64_t Address, const void *Decoder) { 2720 DecodeStatus S = MCDisassembler::Success; 2721 2722 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2723 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2724 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2725 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2726 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2727 2728 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2729 return MCDisassembler::Fail; 2730 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2731 return MCDisassembler::Fail; 2732 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2733 return MCDisassembler::Fail; 2734 if (Rm != 0xF) { 2735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 } 2738 2739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2740 return MCDisassembler::Fail; 2741 Inst.addOperand(MCOperand::CreateImm(0)); 2742 2743 if (Rm == 0xD) 2744 Inst.addOperand(MCOperand::CreateReg(0)); 2745 else if (Rm != 0xF) { 2746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2747 return MCDisassembler::Fail; 2748 } 2749 2750 return S; 2751} 2752 2753static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2754 uint64_t Address, const void *Decoder) { 2755 DecodeStatus S = MCDisassembler::Success; 2756 2757 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2758 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2759 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2760 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2761 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2762 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2763 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2764 2765 if (size == 0x3) { 2766 size = 4; 2767 align = 16; 2768 } else { 2769 if (size == 2) { 2770 size = 1 << size; 2771 align *= 8; 2772 } else { 2773 size = 1 << size; 2774 align *= 4*size; 2775 } 2776 } 2777 2778 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2779 return MCDisassembler::Fail; 2780 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2781 return MCDisassembler::Fail; 2782 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2783 return MCDisassembler::Fail; 2784 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2785 return MCDisassembler::Fail; 2786 if (Rm != 0xF) { 2787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 } 2790 2791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2792 return MCDisassembler::Fail; 2793 Inst.addOperand(MCOperand::CreateImm(align)); 2794 2795 if (Rm == 0xD) 2796 Inst.addOperand(MCOperand::CreateReg(0)); 2797 else if (Rm != 0xF) { 2798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2799 return MCDisassembler::Fail; 2800 } 2801 2802 return S; 2803} 2804 2805static DecodeStatus 2806DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2807 uint64_t Address, const void *Decoder) { 2808 DecodeStatus S = MCDisassembler::Success; 2809 2810 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2811 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2812 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2813 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2814 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2815 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2816 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2817 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2818 2819 if (Q) { 2820 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2821 return MCDisassembler::Fail; 2822 } else { 2823 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2824 return MCDisassembler::Fail; 2825 } 2826 2827 Inst.addOperand(MCOperand::CreateImm(imm)); 2828 2829 switch (Inst.getOpcode()) { 2830 case ARM::VORRiv4i16: 2831 case ARM::VORRiv2i32: 2832 case ARM::VBICiv4i16: 2833 case ARM::VBICiv2i32: 2834 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2835 return MCDisassembler::Fail; 2836 break; 2837 case ARM::VORRiv8i16: 2838 case ARM::VORRiv4i32: 2839 case ARM::VBICiv8i16: 2840 case ARM::VBICiv4i32: 2841 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2842 return MCDisassembler::Fail; 2843 break; 2844 default: 2845 break; 2846 } 2847 2848 return S; 2849} 2850 2851static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2852 uint64_t Address, const void *Decoder) { 2853 DecodeStatus S = MCDisassembler::Success; 2854 2855 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2856 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2857 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2858 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2859 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2860 2861 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2862 return MCDisassembler::Fail; 2863 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2864 return MCDisassembler::Fail; 2865 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2866 2867 return S; 2868} 2869 2870static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2871 uint64_t Address, const void *Decoder) { 2872 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2873 return MCDisassembler::Success; 2874} 2875 2876static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2877 uint64_t Address, const void *Decoder) { 2878 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2879 return MCDisassembler::Success; 2880} 2881 2882static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2883 uint64_t Address, const void *Decoder) { 2884 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2885 return MCDisassembler::Success; 2886} 2887 2888static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2889 uint64_t Address, const void *Decoder) { 2890 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2891 return MCDisassembler::Success; 2892} 2893 2894static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2895 uint64_t Address, const void *Decoder) { 2896 DecodeStatus S = MCDisassembler::Success; 2897 2898 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2899 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2900 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2901 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2902 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2903 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2904 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2905 2906 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2907 return MCDisassembler::Fail; 2908 if (op) { 2909 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2910 return MCDisassembler::Fail; // Writeback 2911 } 2912 2913 switch (Inst.getOpcode()) { 2914 case ARM::VTBL2: 2915 case ARM::VTBX2: 2916 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2917 return MCDisassembler::Fail; 2918 break; 2919 default: 2920 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2921 return MCDisassembler::Fail; 2922 } 2923 2924 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2925 return MCDisassembler::Fail; 2926 2927 return S; 2928} 2929 2930static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 2931 uint64_t Address, const void *Decoder) { 2932 DecodeStatus S = MCDisassembler::Success; 2933 2934 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2935 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2936 2937 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2938 return MCDisassembler::Fail; 2939 2940 switch(Inst.getOpcode()) { 2941 default: 2942 return MCDisassembler::Fail; 2943 case ARM::tADR: 2944 break; // tADR does not explicitly represent the PC as an operand. 2945 case ARM::tADDrSPi: 2946 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2947 break; 2948 } 2949 2950 Inst.addOperand(MCOperand::CreateImm(imm)); 2951 return S; 2952} 2953 2954static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 2955 uint64_t Address, const void *Decoder) { 2956 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2957 return MCDisassembler::Success; 2958} 2959 2960static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 2961 uint64_t Address, const void *Decoder) { 2962 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2963 return MCDisassembler::Success; 2964} 2965 2966static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 2967 uint64_t Address, const void *Decoder) { 2968 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2969 return MCDisassembler::Success; 2970} 2971 2972static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 2973 uint64_t Address, const void *Decoder) { 2974 DecodeStatus S = MCDisassembler::Success; 2975 2976 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2977 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2978 2979 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2980 return MCDisassembler::Fail; 2981 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2982 return MCDisassembler::Fail; 2983 2984 return S; 2985} 2986 2987static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 2988 uint64_t Address, const void *Decoder) { 2989 DecodeStatus S = MCDisassembler::Success; 2990 2991 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2992 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2993 2994 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2995 return MCDisassembler::Fail; 2996 Inst.addOperand(MCOperand::CreateImm(imm)); 2997 2998 return S; 2999} 3000 3001static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3002 uint64_t Address, const void *Decoder) { 3003 unsigned imm = Val << 2; 3004 3005 Inst.addOperand(MCOperand::CreateImm(imm)); 3006 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3007 3008 return MCDisassembler::Success; 3009} 3010 3011static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3012 uint64_t Address, const void *Decoder) { 3013 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3014 Inst.addOperand(MCOperand::CreateImm(Val)); 3015 3016 return MCDisassembler::Success; 3017} 3018 3019static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3020 uint64_t Address, const void *Decoder) { 3021 DecodeStatus S = MCDisassembler::Success; 3022 3023 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 3024 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 3025 unsigned imm = fieldFromInstruction32(Val, 0, 2); 3026 3027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3028 return MCDisassembler::Fail; 3029 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3030 return MCDisassembler::Fail; 3031 Inst.addOperand(MCOperand::CreateImm(imm)); 3032 3033 return S; 3034} 3035 3036static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3037 uint64_t Address, const void *Decoder) { 3038 DecodeStatus S = MCDisassembler::Success; 3039 3040 switch (Inst.getOpcode()) { 3041 case ARM::t2PLDs: 3042 case ARM::t2PLDWs: 3043 case ARM::t2PLIs: 3044 break; 3045 default: { 3046 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3047 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3048 return MCDisassembler::Fail; 3049 } 3050 } 3051 3052 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3053 if (Rn == 0xF) { 3054 switch (Inst.getOpcode()) { 3055 case ARM::t2LDRBs: 3056 Inst.setOpcode(ARM::t2LDRBpci); 3057 break; 3058 case ARM::t2LDRHs: 3059 Inst.setOpcode(ARM::t2LDRHpci); 3060 break; 3061 case ARM::t2LDRSHs: 3062 Inst.setOpcode(ARM::t2LDRSHpci); 3063 break; 3064 case ARM::t2LDRSBs: 3065 Inst.setOpcode(ARM::t2LDRSBpci); 3066 break; 3067 case ARM::t2PLDs: 3068 Inst.setOpcode(ARM::t2PLDi12); 3069 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3070 break; 3071 default: 3072 return MCDisassembler::Fail; 3073 } 3074 3075 int imm = fieldFromInstruction32(Insn, 0, 12); 3076 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 3077 Inst.addOperand(MCOperand::CreateImm(imm)); 3078 3079 return S; 3080 } 3081 3082 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 3083 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 3084 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 3085 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3086 return MCDisassembler::Fail; 3087 3088 return S; 3089} 3090 3091static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3092 uint64_t Address, const void *Decoder) { 3093 int imm = Val & 0xFF; 3094 if (!(Val & 0x100)) imm *= -1; 3095 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 3096 3097 return MCDisassembler::Success; 3098} 3099 3100static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3101 uint64_t Address, const void *Decoder) { 3102 DecodeStatus S = MCDisassembler::Success; 3103 3104 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3105 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3106 3107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3108 return MCDisassembler::Fail; 3109 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3110 return MCDisassembler::Fail; 3111 3112 return S; 3113} 3114 3115static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3116 uint64_t Address, const void *Decoder) { 3117 DecodeStatus S = MCDisassembler::Success; 3118 3119 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 3120 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3121 3122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3123 return MCDisassembler::Fail; 3124 3125 Inst.addOperand(MCOperand::CreateImm(imm)); 3126 3127 return S; 3128} 3129 3130static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3131 uint64_t Address, const void *Decoder) { 3132 int imm = Val & 0xFF; 3133 if (Val == 0) 3134 imm = INT32_MIN; 3135 else if (!(Val & 0x100)) 3136 imm *= -1; 3137 Inst.addOperand(MCOperand::CreateImm(imm)); 3138 3139 return MCDisassembler::Success; 3140} 3141 3142 3143static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3144 uint64_t Address, const void *Decoder) { 3145 DecodeStatus S = MCDisassembler::Success; 3146 3147 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3148 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3149 3150 // Some instructions always use an additive offset. 3151 switch (Inst.getOpcode()) { 3152 case ARM::t2LDRT: 3153 case ARM::t2LDRBT: 3154 case ARM::t2LDRHT: 3155 case ARM::t2LDRSBT: 3156 case ARM::t2LDRSHT: 3157 case ARM::t2STRT: 3158 case ARM::t2STRBT: 3159 case ARM::t2STRHT: 3160 imm |= 0x100; 3161 break; 3162 default: 3163 break; 3164 } 3165 3166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3167 return MCDisassembler::Fail; 3168 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3169 return MCDisassembler::Fail; 3170 3171 return S; 3172} 3173 3174static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3175 uint64_t Address, const void *Decoder) { 3176 DecodeStatus S = MCDisassembler::Success; 3177 3178 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3179 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3180 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3181 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 3182 addr |= Rn << 9; 3183 unsigned load = fieldFromInstruction32(Insn, 20, 1); 3184 3185 if (!load) { 3186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 } 3189 3190 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3191 return MCDisassembler::Fail; 3192 3193 if (load) { 3194 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3195 return MCDisassembler::Fail; 3196 } 3197 3198 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3199 return MCDisassembler::Fail; 3200 3201 return S; 3202} 3203 3204static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3205 uint64_t Address, const void *Decoder) { 3206 DecodeStatus S = MCDisassembler::Success; 3207 3208 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 3209 unsigned imm = fieldFromInstruction32(Val, 0, 12); 3210 3211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3212 return MCDisassembler::Fail; 3213 Inst.addOperand(MCOperand::CreateImm(imm)); 3214 3215 return S; 3216} 3217 3218 3219static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3220 uint64_t Address, const void *Decoder) { 3221 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3222 3223 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3224 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3225 Inst.addOperand(MCOperand::CreateImm(imm)); 3226 3227 return MCDisassembler::Success; 3228} 3229 3230static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3231 uint64_t Address, const void *Decoder) { 3232 DecodeStatus S = MCDisassembler::Success; 3233 3234 if (Inst.getOpcode() == ARM::tADDrSP) { 3235 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3236 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3237 3238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3239 return MCDisassembler::Fail; 3240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3241 return MCDisassembler::Fail; 3242 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3243 } else if (Inst.getOpcode() == ARM::tADDspr) { 3244 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3245 3246 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3247 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3249 return MCDisassembler::Fail; 3250 } 3251 3252 return S; 3253} 3254 3255static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3256 uint64_t Address, const void *Decoder) { 3257 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3258 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3259 3260 Inst.addOperand(MCOperand::CreateImm(imod)); 3261 Inst.addOperand(MCOperand::CreateImm(flags)); 3262 3263 return MCDisassembler::Success; 3264} 3265 3266static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3267 uint64_t Address, const void *Decoder) { 3268 DecodeStatus S = MCDisassembler::Success; 3269 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3270 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3271 3272 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3273 return MCDisassembler::Fail; 3274 Inst.addOperand(MCOperand::CreateImm(add)); 3275 3276 return S; 3277} 3278 3279static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3280 uint64_t Address, const void *Decoder) { 3281 if (!tryAddingSymbolicOperand(Address, 3282 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3283 true, 4, Inst, Decoder)) 3284 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3285 return MCDisassembler::Success; 3286} 3287 3288static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3289 uint64_t Address, const void *Decoder) { 3290 if (Val == 0xA || Val == 0xB) 3291 return MCDisassembler::Fail; 3292 3293 Inst.addOperand(MCOperand::CreateImm(Val)); 3294 return MCDisassembler::Success; 3295} 3296 3297static DecodeStatus 3298DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3299 uint64_t Address, const void *Decoder) { 3300 DecodeStatus S = MCDisassembler::Success; 3301 3302 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3303 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3304 3305 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3307 return MCDisassembler::Fail; 3308 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3309 return MCDisassembler::Fail; 3310 return S; 3311} 3312 3313static DecodeStatus 3314DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3315 uint64_t Address, const void *Decoder) { 3316 DecodeStatus S = MCDisassembler::Success; 3317 3318 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3319 if (pred == 0xE || pred == 0xF) { 3320 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3321 switch (opc) { 3322 default: 3323 return MCDisassembler::Fail; 3324 case 0xf3bf8f4: 3325 Inst.setOpcode(ARM::t2DSB); 3326 break; 3327 case 0xf3bf8f5: 3328 Inst.setOpcode(ARM::t2DMB); 3329 break; 3330 case 0xf3bf8f6: 3331 Inst.setOpcode(ARM::t2ISB); 3332 break; 3333 } 3334 3335 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3336 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3337 } 3338 3339 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3340 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3341 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3342 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3343 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3344 3345 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3346 return MCDisassembler::Fail; 3347 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3348 return MCDisassembler::Fail; 3349 3350 return S; 3351} 3352 3353// Decode a shifted immediate operand. These basically consist 3354// of an 8-bit value, and a 4-bit directive that specifies either 3355// a splat operation or a rotation. 3356static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3357 uint64_t Address, const void *Decoder) { 3358 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3359 if (ctrl == 0) { 3360 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3361 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3362 switch (byte) { 3363 case 0: 3364 Inst.addOperand(MCOperand::CreateImm(imm)); 3365 break; 3366 case 1: 3367 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3368 break; 3369 case 2: 3370 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3371 break; 3372 case 3: 3373 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3374 (imm << 8) | imm)); 3375 break; 3376 } 3377 } else { 3378 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3379 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3380 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3381 Inst.addOperand(MCOperand::CreateImm(imm)); 3382 } 3383 3384 return MCDisassembler::Success; 3385} 3386 3387static DecodeStatus 3388DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3389 uint64_t Address, const void *Decoder){ 3390 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3391 return MCDisassembler::Success; 3392} 3393 3394static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3395 uint64_t Address, const void *Decoder){ 3396 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3397 true, 4, Inst, Decoder)) 3398 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3399 return MCDisassembler::Success; 3400} 3401 3402static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3403 uint64_t Address, const void *Decoder) { 3404 switch (Val) { 3405 default: 3406 return MCDisassembler::Fail; 3407 case 0xF: // SY 3408 case 0xE: // ST 3409 case 0xB: // ISH 3410 case 0xA: // ISHST 3411 case 0x7: // NSH 3412 case 0x6: // NSHST 3413 case 0x3: // OSH 3414 case 0x2: // OSHST 3415 break; 3416 } 3417 3418 Inst.addOperand(MCOperand::CreateImm(Val)); 3419 return MCDisassembler::Success; 3420} 3421 3422static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3423 uint64_t Address, const void *Decoder) { 3424 if (!Val) return MCDisassembler::Fail; 3425 Inst.addOperand(MCOperand::CreateImm(Val)); 3426 return MCDisassembler::Success; 3427} 3428 3429static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3430 uint64_t Address, const void *Decoder) { 3431 DecodeStatus S = MCDisassembler::Success; 3432 3433 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3434 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3435 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3436 3437 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3438 3439 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3440 return MCDisassembler::Fail; 3441 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3444 return MCDisassembler::Fail; 3445 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3446 return MCDisassembler::Fail; 3447 3448 return S; 3449} 3450 3451 3452static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3453 uint64_t Address, const void *Decoder){ 3454 DecodeStatus S = MCDisassembler::Success; 3455 3456 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3457 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3458 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3459 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3460 3461 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3462 return MCDisassembler::Fail; 3463 3464 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3465 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3466 3467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3468 return MCDisassembler::Fail; 3469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3470 return MCDisassembler::Fail; 3471 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3472 return MCDisassembler::Fail; 3473 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3474 return MCDisassembler::Fail; 3475 3476 return S; 3477} 3478 3479static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3480 uint64_t Address, const void *Decoder) { 3481 DecodeStatus S = MCDisassembler::Success; 3482 3483 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3484 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3485 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3486 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3487 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3488 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3489 3490 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3491 3492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3493 return MCDisassembler::Fail; 3494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3495 return MCDisassembler::Fail; 3496 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3497 return MCDisassembler::Fail; 3498 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3499 return MCDisassembler::Fail; 3500 3501 return S; 3502} 3503 3504static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3505 uint64_t Address, const void *Decoder) { 3506 DecodeStatus S = MCDisassembler::Success; 3507 3508 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3509 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3510 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3511 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3512 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3513 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3514 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3515 3516 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3517 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3518 3519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3520 return MCDisassembler::Fail; 3521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3522 return MCDisassembler::Fail; 3523 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3524 return MCDisassembler::Fail; 3525 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3526 return MCDisassembler::Fail; 3527 3528 return S; 3529} 3530 3531 3532static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3533 uint64_t Address, const void *Decoder) { 3534 DecodeStatus S = MCDisassembler::Success; 3535 3536 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3537 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3538 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3539 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3540 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3541 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3542 3543 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3544 3545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3546 return MCDisassembler::Fail; 3547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3548 return MCDisassembler::Fail; 3549 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3550 return MCDisassembler::Fail; 3551 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3552 return MCDisassembler::Fail; 3553 3554 return S; 3555} 3556 3557static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3558 uint64_t Address, const void *Decoder) { 3559 DecodeStatus S = MCDisassembler::Success; 3560 3561 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3562 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3563 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3564 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3565 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3566 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3567 3568 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3569 3570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3571 return MCDisassembler::Fail; 3572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3575 return MCDisassembler::Fail; 3576 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3577 return MCDisassembler::Fail; 3578 3579 return S; 3580} 3581 3582static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3583 uint64_t Address, const void *Decoder) { 3584 DecodeStatus S = MCDisassembler::Success; 3585 3586 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3587 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3588 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3589 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3590 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3591 3592 unsigned align = 0; 3593 unsigned index = 0; 3594 switch (size) { 3595 default: 3596 return MCDisassembler::Fail; 3597 case 0: 3598 if (fieldFromInstruction32(Insn, 4, 1)) 3599 return MCDisassembler::Fail; // UNDEFINED 3600 index = fieldFromInstruction32(Insn, 5, 3); 3601 break; 3602 case 1: 3603 if (fieldFromInstruction32(Insn, 5, 1)) 3604 return MCDisassembler::Fail; // UNDEFINED 3605 index = fieldFromInstruction32(Insn, 6, 2); 3606 if (fieldFromInstruction32(Insn, 4, 1)) 3607 align = 2; 3608 break; 3609 case 2: 3610 if (fieldFromInstruction32(Insn, 6, 1)) 3611 return MCDisassembler::Fail; // UNDEFINED 3612 index = fieldFromInstruction32(Insn, 7, 1); 3613 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3614 align = 4; 3615 } 3616 3617 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3618 return MCDisassembler::Fail; 3619 if (Rm != 0xF) { // Writeback 3620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3621 return MCDisassembler::Fail; 3622 } 3623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3624 return MCDisassembler::Fail; 3625 Inst.addOperand(MCOperand::CreateImm(align)); 3626 if (Rm != 0xF) { 3627 if (Rm != 0xD) { 3628 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3629 return MCDisassembler::Fail; 3630 } else 3631 Inst.addOperand(MCOperand::CreateReg(0)); 3632 } 3633 3634 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 Inst.addOperand(MCOperand::CreateImm(index)); 3637 3638 return S; 3639} 3640 3641static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3642 uint64_t Address, const void *Decoder) { 3643 DecodeStatus S = MCDisassembler::Success; 3644 3645 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3646 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3647 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3648 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3649 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3650 3651 unsigned align = 0; 3652 unsigned index = 0; 3653 switch (size) { 3654 default: 3655 return MCDisassembler::Fail; 3656 case 0: 3657 if (fieldFromInstruction32(Insn, 4, 1)) 3658 return MCDisassembler::Fail; // UNDEFINED 3659 index = fieldFromInstruction32(Insn, 5, 3); 3660 break; 3661 case 1: 3662 if (fieldFromInstruction32(Insn, 5, 1)) 3663 return MCDisassembler::Fail; // UNDEFINED 3664 index = fieldFromInstruction32(Insn, 6, 2); 3665 if (fieldFromInstruction32(Insn, 4, 1)) 3666 align = 2; 3667 break; 3668 case 2: 3669 if (fieldFromInstruction32(Insn, 6, 1)) 3670 return MCDisassembler::Fail; // UNDEFINED 3671 index = fieldFromInstruction32(Insn, 7, 1); 3672 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3673 align = 4; 3674 } 3675 3676 if (Rm != 0xF) { // Writeback 3677 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3678 return MCDisassembler::Fail; 3679 } 3680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3681 return MCDisassembler::Fail; 3682 Inst.addOperand(MCOperand::CreateImm(align)); 3683 if (Rm != 0xF) { 3684 if (Rm != 0xD) { 3685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3686 return MCDisassembler::Fail; 3687 } else 3688 Inst.addOperand(MCOperand::CreateReg(0)); 3689 } 3690 3691 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3692 return MCDisassembler::Fail; 3693 Inst.addOperand(MCOperand::CreateImm(index)); 3694 3695 return S; 3696} 3697 3698 3699static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3700 uint64_t Address, const void *Decoder) { 3701 DecodeStatus S = MCDisassembler::Success; 3702 3703 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3704 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3705 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3706 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3707 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3708 3709 unsigned align = 0; 3710 unsigned index = 0; 3711 unsigned inc = 1; 3712 switch (size) { 3713 default: 3714 return MCDisassembler::Fail; 3715 case 0: 3716 index = fieldFromInstruction32(Insn, 5, 3); 3717 if (fieldFromInstruction32(Insn, 4, 1)) 3718 align = 2; 3719 break; 3720 case 1: 3721 index = fieldFromInstruction32(Insn, 6, 2); 3722 if (fieldFromInstruction32(Insn, 4, 1)) 3723 align = 4; 3724 if (fieldFromInstruction32(Insn, 5, 1)) 3725 inc = 2; 3726 break; 3727 case 2: 3728 if (fieldFromInstruction32(Insn, 5, 1)) 3729 return MCDisassembler::Fail; // UNDEFINED 3730 index = fieldFromInstruction32(Insn, 7, 1); 3731 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3732 align = 8; 3733 if (fieldFromInstruction32(Insn, 6, 1)) 3734 inc = 2; 3735 break; 3736 } 3737 3738 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3739 return MCDisassembler::Fail; 3740 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3741 return MCDisassembler::Fail; 3742 if (Rm != 0xF) { // Writeback 3743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3744 return MCDisassembler::Fail; 3745 } 3746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3747 return MCDisassembler::Fail; 3748 Inst.addOperand(MCOperand::CreateImm(align)); 3749 if (Rm != 0xF) { 3750 if (Rm != 0xD) { 3751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3752 return MCDisassembler::Fail; 3753 } else 3754 Inst.addOperand(MCOperand::CreateReg(0)); 3755 } 3756 3757 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3758 return MCDisassembler::Fail; 3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 Inst.addOperand(MCOperand::CreateImm(index)); 3762 3763 return S; 3764} 3765 3766static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3767 uint64_t Address, const void *Decoder) { 3768 DecodeStatus S = MCDisassembler::Success; 3769 3770 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3771 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3772 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3773 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3774 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3775 3776 unsigned align = 0; 3777 unsigned index = 0; 3778 unsigned inc = 1; 3779 switch (size) { 3780 default: 3781 return MCDisassembler::Fail; 3782 case 0: 3783 index = fieldFromInstruction32(Insn, 5, 3); 3784 if (fieldFromInstruction32(Insn, 4, 1)) 3785 align = 2; 3786 break; 3787 case 1: 3788 index = fieldFromInstruction32(Insn, 6, 2); 3789 if (fieldFromInstruction32(Insn, 4, 1)) 3790 align = 4; 3791 if (fieldFromInstruction32(Insn, 5, 1)) 3792 inc = 2; 3793 break; 3794 case 2: 3795 if (fieldFromInstruction32(Insn, 5, 1)) 3796 return MCDisassembler::Fail; // UNDEFINED 3797 index = fieldFromInstruction32(Insn, 7, 1); 3798 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3799 align = 8; 3800 if (fieldFromInstruction32(Insn, 6, 1)) 3801 inc = 2; 3802 break; 3803 } 3804 3805 if (Rm != 0xF) { // Writeback 3806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3807 return MCDisassembler::Fail; 3808 } 3809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3810 return MCDisassembler::Fail; 3811 Inst.addOperand(MCOperand::CreateImm(align)); 3812 if (Rm != 0xF) { 3813 if (Rm != 0xD) { 3814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3815 return MCDisassembler::Fail; 3816 } else 3817 Inst.addOperand(MCOperand::CreateReg(0)); 3818 } 3819 3820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3821 return MCDisassembler::Fail; 3822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3823 return MCDisassembler::Fail; 3824 Inst.addOperand(MCOperand::CreateImm(index)); 3825 3826 return S; 3827} 3828 3829 3830static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3831 uint64_t Address, const void *Decoder) { 3832 DecodeStatus S = MCDisassembler::Success; 3833 3834 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3835 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3836 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3837 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3838 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3839 3840 unsigned align = 0; 3841 unsigned index = 0; 3842 unsigned inc = 1; 3843 switch (size) { 3844 default: 3845 return MCDisassembler::Fail; 3846 case 0: 3847 if (fieldFromInstruction32(Insn, 4, 1)) 3848 return MCDisassembler::Fail; // UNDEFINED 3849 index = fieldFromInstruction32(Insn, 5, 3); 3850 break; 3851 case 1: 3852 if (fieldFromInstruction32(Insn, 4, 1)) 3853 return MCDisassembler::Fail; // UNDEFINED 3854 index = fieldFromInstruction32(Insn, 6, 2); 3855 if (fieldFromInstruction32(Insn, 5, 1)) 3856 inc = 2; 3857 break; 3858 case 2: 3859 if (fieldFromInstruction32(Insn, 4, 2)) 3860 return MCDisassembler::Fail; // UNDEFINED 3861 index = fieldFromInstruction32(Insn, 7, 1); 3862 if (fieldFromInstruction32(Insn, 6, 1)) 3863 inc = 2; 3864 break; 3865 } 3866 3867 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3868 return MCDisassembler::Fail; 3869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3870 return MCDisassembler::Fail; 3871 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 3874 if (Rm != 0xF) { // Writeback 3875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3876 return MCDisassembler::Fail; 3877 } 3878 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3879 return MCDisassembler::Fail; 3880 Inst.addOperand(MCOperand::CreateImm(align)); 3881 if (Rm != 0xF) { 3882 if (Rm != 0xD) { 3883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3884 return MCDisassembler::Fail; 3885 } else 3886 Inst.addOperand(MCOperand::CreateReg(0)); 3887 } 3888 3889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3890 return MCDisassembler::Fail; 3891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3892 return MCDisassembler::Fail; 3893 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3894 return MCDisassembler::Fail; 3895 Inst.addOperand(MCOperand::CreateImm(index)); 3896 3897 return S; 3898} 3899 3900static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 3901 uint64_t Address, const void *Decoder) { 3902 DecodeStatus S = MCDisassembler::Success; 3903 3904 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3905 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3906 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3907 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3908 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3909 3910 unsigned align = 0; 3911 unsigned index = 0; 3912 unsigned inc = 1; 3913 switch (size) { 3914 default: 3915 return MCDisassembler::Fail; 3916 case 0: 3917 if (fieldFromInstruction32(Insn, 4, 1)) 3918 return MCDisassembler::Fail; // UNDEFINED 3919 index = fieldFromInstruction32(Insn, 5, 3); 3920 break; 3921 case 1: 3922 if (fieldFromInstruction32(Insn, 4, 1)) 3923 return MCDisassembler::Fail; // UNDEFINED 3924 index = fieldFromInstruction32(Insn, 6, 2); 3925 if (fieldFromInstruction32(Insn, 5, 1)) 3926 inc = 2; 3927 break; 3928 case 2: 3929 if (fieldFromInstruction32(Insn, 4, 2)) 3930 return MCDisassembler::Fail; // UNDEFINED 3931 index = fieldFromInstruction32(Insn, 7, 1); 3932 if (fieldFromInstruction32(Insn, 6, 1)) 3933 inc = 2; 3934 break; 3935 } 3936 3937 if (Rm != 0xF) { // Writeback 3938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3939 return MCDisassembler::Fail; 3940 } 3941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3942 return MCDisassembler::Fail; 3943 Inst.addOperand(MCOperand::CreateImm(align)); 3944 if (Rm != 0xF) { 3945 if (Rm != 0xD) { 3946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3947 return MCDisassembler::Fail; 3948 } else 3949 Inst.addOperand(MCOperand::CreateReg(0)); 3950 } 3951 3952 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3953 return MCDisassembler::Fail; 3954 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3955 return MCDisassembler::Fail; 3956 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3957 return MCDisassembler::Fail; 3958 Inst.addOperand(MCOperand::CreateImm(index)); 3959 3960 return S; 3961} 3962 3963 3964static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 3965 uint64_t Address, const void *Decoder) { 3966 DecodeStatus S = MCDisassembler::Success; 3967 3968 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3969 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3970 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3971 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3972 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3973 3974 unsigned align = 0; 3975 unsigned index = 0; 3976 unsigned inc = 1; 3977 switch (size) { 3978 default: 3979 return MCDisassembler::Fail; 3980 case 0: 3981 if (fieldFromInstruction32(Insn, 4, 1)) 3982 align = 4; 3983 index = fieldFromInstruction32(Insn, 5, 3); 3984 break; 3985 case 1: 3986 if (fieldFromInstruction32(Insn, 4, 1)) 3987 align = 8; 3988 index = fieldFromInstruction32(Insn, 6, 2); 3989 if (fieldFromInstruction32(Insn, 5, 1)) 3990 inc = 2; 3991 break; 3992 case 2: 3993 if (fieldFromInstruction32(Insn, 4, 2)) 3994 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3995 index = fieldFromInstruction32(Insn, 7, 1); 3996 if (fieldFromInstruction32(Insn, 6, 1)) 3997 inc = 2; 3998 break; 3999 } 4000 4001 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4002 return MCDisassembler::Fail; 4003 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4004 return MCDisassembler::Fail; 4005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4006 return MCDisassembler::Fail; 4007 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4008 return MCDisassembler::Fail; 4009 4010 if (Rm != 0xF) { // Writeback 4011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 } 4014 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4015 return MCDisassembler::Fail; 4016 Inst.addOperand(MCOperand::CreateImm(align)); 4017 if (Rm != 0xF) { 4018 if (Rm != 0xD) { 4019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 } else 4022 Inst.addOperand(MCOperand::CreateReg(0)); 4023 } 4024 4025 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4026 return MCDisassembler::Fail; 4027 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4028 return MCDisassembler::Fail; 4029 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4030 return MCDisassembler::Fail; 4031 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 Inst.addOperand(MCOperand::CreateImm(index)); 4034 4035 return S; 4036} 4037 4038static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4039 uint64_t Address, const void *Decoder) { 4040 DecodeStatus S = MCDisassembler::Success; 4041 4042 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4043 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4044 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 4045 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 4046 unsigned size = fieldFromInstruction32(Insn, 10, 2); 4047 4048 unsigned align = 0; 4049 unsigned index = 0; 4050 unsigned inc = 1; 4051 switch (size) { 4052 default: 4053 return MCDisassembler::Fail; 4054 case 0: 4055 if (fieldFromInstruction32(Insn, 4, 1)) 4056 align = 4; 4057 index = fieldFromInstruction32(Insn, 5, 3); 4058 break; 4059 case 1: 4060 if (fieldFromInstruction32(Insn, 4, 1)) 4061 align = 8; 4062 index = fieldFromInstruction32(Insn, 6, 2); 4063 if (fieldFromInstruction32(Insn, 5, 1)) 4064 inc = 2; 4065 break; 4066 case 2: 4067 if (fieldFromInstruction32(Insn, 4, 2)) 4068 align = 4 << fieldFromInstruction32(Insn, 4, 2); 4069 index = fieldFromInstruction32(Insn, 7, 1); 4070 if (fieldFromInstruction32(Insn, 6, 1)) 4071 inc = 2; 4072 break; 4073 } 4074 4075 if (Rm != 0xF) { // Writeback 4076 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4077 return MCDisassembler::Fail; 4078 } 4079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4080 return MCDisassembler::Fail; 4081 Inst.addOperand(MCOperand::CreateImm(align)); 4082 if (Rm != 0xF) { 4083 if (Rm != 0xD) { 4084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4085 return MCDisassembler::Fail; 4086 } else 4087 Inst.addOperand(MCOperand::CreateReg(0)); 4088 } 4089 4090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4091 return MCDisassembler::Fail; 4092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4093 return MCDisassembler::Fail; 4094 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4095 return MCDisassembler::Fail; 4096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4097 return MCDisassembler::Fail; 4098 Inst.addOperand(MCOperand::CreateImm(index)); 4099 4100 return S; 4101} 4102 4103static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4104 uint64_t Address, const void *Decoder) { 4105 DecodeStatus S = MCDisassembler::Success; 4106 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4107 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4108 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4109 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4110 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4111 4112 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4113 S = MCDisassembler::SoftFail; 4114 4115 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4116 return MCDisassembler::Fail; 4117 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4118 return MCDisassembler::Fail; 4119 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4120 return MCDisassembler::Fail; 4121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4122 return MCDisassembler::Fail; 4123 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4124 return MCDisassembler::Fail; 4125 4126 return S; 4127} 4128 4129static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4130 uint64_t Address, const void *Decoder) { 4131 DecodeStatus S = MCDisassembler::Success; 4132 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4133 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4134 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4135 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4136 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4137 4138 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4139 S = MCDisassembler::SoftFail; 4140 4141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4142 return MCDisassembler::Fail; 4143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4144 return MCDisassembler::Fail; 4145 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4146 return MCDisassembler::Fail; 4147 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4148 return MCDisassembler::Fail; 4149 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4150 return MCDisassembler::Fail; 4151 4152 return S; 4153} 4154 4155static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4156 uint64_t Address, const void *Decoder) { 4157 DecodeStatus S = MCDisassembler::Success; 4158 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 4159 // The InstPrinter needs to have the low bit of the predicate in 4160 // the mask operand to be able to print it properly. 4161 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 4162 4163 if (pred == 0xF) { 4164 pred = 0xE; 4165 S = MCDisassembler::SoftFail; 4166 } 4167 4168 if ((mask & 0xF) == 0) { 4169 // Preserve the high bit of the mask, which is the low bit of 4170 // the predicate. 4171 mask &= 0x10; 4172 mask |= 0x8; 4173 S = MCDisassembler::SoftFail; 4174 } 4175 4176 Inst.addOperand(MCOperand::CreateImm(pred)); 4177 Inst.addOperand(MCOperand::CreateImm(mask)); 4178 return S; 4179} 4180 4181static DecodeStatus 4182DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4183 uint64_t Address, const void *Decoder) { 4184 DecodeStatus S = MCDisassembler::Success; 4185 4186 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4187 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4188 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4189 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4190 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4191 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4192 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4193 bool writeback = (W == 1) | (P == 0); 4194 4195 addr |= (U << 8) | (Rn << 9); 4196 4197 if (writeback && (Rn == Rt || Rn == Rt2)) 4198 Check(S, MCDisassembler::SoftFail); 4199 if (Rt == Rt2) 4200 Check(S, MCDisassembler::SoftFail); 4201 4202 // Rt 4203 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4204 return MCDisassembler::Fail; 4205 // Rt2 4206 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4207 return MCDisassembler::Fail; 4208 // Writeback operand 4209 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4210 return MCDisassembler::Fail; 4211 // addr 4212 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4213 return MCDisassembler::Fail; 4214 4215 return S; 4216} 4217 4218static DecodeStatus 4219DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4220 uint64_t Address, const void *Decoder) { 4221 DecodeStatus S = MCDisassembler::Success; 4222 4223 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4224 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4225 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4226 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4227 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4228 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4229 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4230 bool writeback = (W == 1) | (P == 0); 4231 4232 addr |= (U << 8) | (Rn << 9); 4233 4234 if (writeback && (Rn == Rt || Rn == Rt2)) 4235 Check(S, MCDisassembler::SoftFail); 4236 4237 // Writeback operand 4238 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4239 return MCDisassembler::Fail; 4240 // Rt 4241 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 // Rt2 4244 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4245 return MCDisassembler::Fail; 4246 // addr 4247 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4248 return MCDisassembler::Fail; 4249 4250 return S; 4251} 4252 4253static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4254 uint64_t Address, const void *Decoder) { 4255 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4256 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4257 if (sign1 != sign2) return MCDisassembler::Fail; 4258 4259 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4260 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4261 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4262 Val |= sign1 << 12; 4263 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4264 4265 return MCDisassembler::Success; 4266} 4267 4268static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4269 uint64_t Address, 4270 const void *Decoder) { 4271 DecodeStatus S = MCDisassembler::Success; 4272 4273 // Shift of "asr #32" is not allowed in Thumb2 mode. 4274 if (Val == 0x20) S = MCDisassembler::SoftFail; 4275 Inst.addOperand(MCOperand::CreateImm(Val)); 4276 return S; 4277} 4278 4279static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4280 uint64_t Address, const void *Decoder) { 4281 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4282 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4283 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4284 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4285 4286 if (pred == 0xF) 4287 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4288 4289 DecodeStatus S = MCDisassembler::Success; 4290 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4291 return MCDisassembler::Fail; 4292 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4293 return MCDisassembler::Fail; 4294 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4295 return MCDisassembler::Fail; 4296 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4297 return MCDisassembler::Fail; 4298 4299 return S; 4300} 4301 4302static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4303 uint64_t Address, const void *Decoder) { 4304 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4305 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4306 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4307 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4308 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4309 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4310 4311 DecodeStatus S = MCDisassembler::Success; 4312 4313 // VMOVv2f32 is ambiguous with these decodings. 4314 if (!(imm & 0x38) && cmode == 0xF) { 4315 Inst.setOpcode(ARM::VMOVv2f32); 4316 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4317 } 4318 4319 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4320 4321 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4322 return MCDisassembler::Fail; 4323 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4324 return MCDisassembler::Fail; 4325 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4326 4327 return S; 4328} 4329 4330static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4331 uint64_t Address, const void *Decoder) { 4332 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4333 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4334 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4335 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4336 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4337 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4338 4339 DecodeStatus S = MCDisassembler::Success; 4340 4341 // VMOVv4f32 is ambiguous with these decodings. 4342 if (!(imm & 0x38) && cmode == 0xF) { 4343 Inst.setOpcode(ARM::VMOVv4f32); 4344 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4345 } 4346 4347 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4348 4349 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4350 return MCDisassembler::Fail; 4351 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4352 return MCDisassembler::Fail; 4353 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4354 4355 return S; 4356} 4357 4358static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4359 uint64_t Address, const void *Decoder) { 4360 DecodeStatus S = MCDisassembler::Success; 4361 4362 unsigned Rn = fieldFromInstruction32(Val, 16, 4); 4363 unsigned Rt = fieldFromInstruction32(Val, 12, 4); 4364 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 4365 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4); 4366 unsigned Cond = fieldFromInstruction32(Val, 28, 4); 4367 4368 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt) 4369 S = MCDisassembler::SoftFail; 4370 4371 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4372 return MCDisassembler::Fail; 4373 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4374 return MCDisassembler::Fail; 4375 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4376 return MCDisassembler::Fail; 4377 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4378 return MCDisassembler::Fail; 4379 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4380 return MCDisassembler::Fail; 4381 4382 return S; 4383} 4384 4385