ARMDisassembler.cpp revision bc2198133a1836598b54b943420748e75d5dea94 
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE "arm-disassembler"
11
12#include "ARM.h"
13#include "ARMSubtarget.h"
14#include "MCTargetDesc/ARMAddressingModes.h"
15#include "MCTargetDesc/ARMMCExpr.h"
16#include "MCTargetDesc/ARMBaseInfo.h"
17#include "llvm/MC/EDInstInfo.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstrDesc.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCDisassembler.h"
23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/TargetRegistry.h"
27#include "llvm/Support/raw_ostream.h"
28
29using namespace llvm;
30
31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
33namespace {
34/// ARMDisassembler - ARM disassembler for all ARM platforms.
35class ARMDisassembler : public MCDisassembler {
36public:
37  /// Constructor     - Initializes the disassembler.
38  ///
39  ARMDisassembler(const MCSubtargetInfo &STI) :
40    MCDisassembler(STI) {
41  }
42
43  ~ARMDisassembler() {
44  }
45
46  /// getInstruction - See MCDisassembler.
47  DecodeStatus getInstruction(MCInst &instr,
48                              uint64_t &size,
49                              MemoryObject &region,
50                              uint64_t address,
51                              raw_ostream &vStream,
52                              raw_ostream &cStream) const;
53
54  /// getEDInfo - See MCDisassembler.
55  EDInstInfo *getEDInfo() const;
56private:
57};
58
59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60class ThumbDisassembler : public MCDisassembler {
61public:
62  /// Constructor     - Initializes the disassembler.
63  ///
64  ThumbDisassembler(const MCSubtargetInfo &STI) :
65    MCDisassembler(STI) {
66  }
67
68  ~ThumbDisassembler() {
69  }
70
71  /// getInstruction - See MCDisassembler.
72  DecodeStatus getInstruction(MCInst &instr,
73                              uint64_t &size,
74                              MemoryObject &region,
75                              uint64_t address,
76                              raw_ostream &vStream,
77                              raw_ostream &cStream) const;
78
79  /// getEDInfo - See MCDisassembler.
80  EDInstInfo *getEDInfo() const;
81private:
82  mutable std::vector<unsigned> ITBlock;
83  DecodeStatus AddThumbPredicate(MCInst&) const;
84  void UpdateThumbVFPPredicate(MCInst&) const;
85};
86}
87
88static bool Check(DecodeStatus &Out, DecodeStatus In) {
89  switch (In) {
90    case MCDisassembler::Success:
91      // Out stays the same.
92      return true;
93    case MCDisassembler::SoftFail:
94      Out = In;
95      return true;
96    case MCDisassembler::Fail:
97      Out = In;
98      return false;
99  }
100  llvm_unreachable("Invalid DecodeStatus!");
101}
102
103
104// Forward declare these because the autogenerated code will reference them.
105// Definitions are further down.
106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
107                                   uint64_t Address, const void *Decoder);
108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
109                                               unsigned RegNo, uint64_t Address,
110                                               const void *Decoder);
111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
112                                   uint64_t Address, const void *Decoder);
113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
114                                   uint64_t Address, const void *Decoder);
115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
116                                   uint64_t Address, const void *Decoder);
117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
118                                   uint64_t Address, const void *Decoder);
119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
120                                   uint64_t Address, const void *Decoder);
121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
122                                   uint64_t Address, const void *Decoder);
123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
124                                                unsigned RegNo,
125                                                uint64_t Address,
126                                                const void *Decoder);
127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
128                                   uint64_t Address, const void *Decoder);
129
130static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
131                               uint64_t Address, const void *Decoder);
132static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
133                               uint64_t Address, const void *Decoder);
134static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
135                               uint64_t Address, const void *Decoder);
136static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
137                               uint64_t Address, const void *Decoder);
138static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
139                               uint64_t Address, const void *Decoder);
140static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
141                               uint64_t Address, const void *Decoder);
142
143static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
144                               uint64_t Address, const void *Decoder);
145static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
146                               uint64_t Address, const void *Decoder);
147static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
148                                                  unsigned Insn,
149                                                  uint64_t Address,
150                                                  const void *Decoder);
151static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
152                               uint64_t Address, const void *Decoder);
153static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
154                               uint64_t Address, const void *Decoder);
155static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
156                               uint64_t Address, const void *Decoder);
157static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
158                               uint64_t Address, const void *Decoder);
159
160static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
161                                                  unsigned Insn,
162                                                  uint64_t Adddress,
163                                                  const void *Decoder);
164static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165                               uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167                               uint64_t Address, const void *Decoder);
168static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
169                               uint64_t Address, const void *Decoder);
170static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
171                               uint64_t Address, const void *Decoder);
172static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
173                               uint64_t Address, const void *Decoder);
174static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
175                               uint64_t Address, const void *Decoder);
176static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
177                               uint64_t Address, const void *Decoder);
178static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
179                               uint64_t Address, const void *Decoder);
180static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
181                               uint64_t Address, const void *Decoder);
182static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
183                               uint64_t Address, const void *Decoder);
184static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
185                               uint64_t Address, const void *Decoder);
186static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
187                               uint64_t Address, const void *Decoder);
188static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
189                               uint64_t Address, const void *Decoder);
190static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
191                               uint64_t Address, const void *Decoder);
192static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
193                               uint64_t Address, const void *Decoder);
194static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
195                               uint64_t Address, const void *Decoder);
196static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
197                               uint64_t Address, const void *Decoder);
198static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
199                               uint64_t Address, const void *Decoder);
200static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
201                               uint64_t Address, const void *Decoder);
202static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
203                               uint64_t Address, const void *Decoder);
204static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
205                               uint64_t Address, const void *Decoder);
206static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
207                               uint64_t Address, const void *Decoder);
208static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
209                               uint64_t Address, const void *Decoder);
210static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
211                               uint64_t Address, const void *Decoder);
212static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
213                               uint64_t Address, const void *Decoder);
214static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
215                               uint64_t Address, const void *Decoder);
216static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
217                               uint64_t Address, const void *Decoder);
218static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
219                               uint64_t Address, const void *Decoder);
220static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
221                               uint64_t Address, const void *Decoder);
222static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
223                               uint64_t Address, const void *Decoder);
224static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
225                               uint64_t Address, const void *Decoder);
226static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
227                               uint64_t Address, const void *Decoder);
228static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
229                               uint64_t Address, const void *Decoder);
230static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
231                               uint64_t Address, const void *Decoder);
232static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
233                               uint64_t Address, const void *Decoder);
234static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
235                               uint64_t Address, const void *Decoder);
236static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
237                               uint64_t Address, const void *Decoder);
238static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
239                               uint64_t Address, const void *Decoder);
240static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
241                               uint64_t Address, const void *Decoder);
242static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
243                               uint64_t Address, const void *Decoder);
244static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
245                               uint64_t Address, const void *Decoder);
246static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
247                               uint64_t Address, const void *Decoder);
248static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
249                               uint64_t Address, const void *Decoder);
250static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
251                               uint64_t Address, const void *Decoder);
252static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
253                                uint64_t Address, const void *Decoder);
254static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
255                                uint64_t Address, const void *Decoder);
256
257
258static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
259                               uint64_t Address, const void *Decoder);
260static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
261                               uint64_t Address, const void *Decoder);
262static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
263                               uint64_t Address, const void *Decoder);
264static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
265                               uint64_t Address, const void *Decoder);
266static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
267                               uint64_t Address, const void *Decoder);
268static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
269                               uint64_t Address, const void *Decoder);
270static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
271                               uint64_t Address, const void *Decoder);
272static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
273                               uint64_t Address, const void *Decoder);
274static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
275                               uint64_t Address, const void *Decoder);
276static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
277                               uint64_t Address, const void *Decoder);
278static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
279                               uint64_t Address, const void *Decoder);
280static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
281                               uint64_t Address, const void *Decoder);
282static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
283                               uint64_t Address, const void *Decoder);
284static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
285                               uint64_t Address, const void *Decoder);
286static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
287                               uint64_t Address, const void *Decoder);
288static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
289                               uint64_t Address, const void *Decoder);
290static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
291                                uint64_t Address, const void *Decoder);
292static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
293                                uint64_t Address, const void *Decoder);
294static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
295                                uint64_t Address, const void *Decoder);
296static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
297                                uint64_t Address, const void *Decoder);
298static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
299                                uint64_t Address, const void *Decoder);
300static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
301                                uint64_t Address, const void *Decoder);
302static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
303                                uint64_t Address, const void *Decoder);
304static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
305                                uint64_t Address, const void *Decoder);
306static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
307                                uint64_t Address, const void *Decoder);
308static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
309                                uint64_t Address, const void *Decoder);
310static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
311                               uint64_t Address, const void *Decoder);
312static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
313                               uint64_t Address, const void *Decoder);
314static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
315                                uint64_t Address, const void *Decoder);
316static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
317                                uint64_t Address, const void *Decoder);
318static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
319                                uint64_t Address, const void *Decoder);
320
321
322
323#include "ARMGenDisassemblerTables.inc"
324#include "ARMGenInstrInfo.inc"
325#include "ARMGenEDInfo.inc"
326
327static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
328  return new ARMDisassembler(STI);
329}
330
331static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
332  return new ThumbDisassembler(STI);
333}
334
335EDInstInfo *ARMDisassembler::getEDInfo() const {
336  return instInfoARM;
337}
338
339EDInstInfo *ThumbDisassembler::getEDInfo() const {
340  return instInfoARM;
341}
342
343DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
344                                             MemoryObject &Region,
345                                             uint64_t Address,
346                                             raw_ostream &os,
347                                             raw_ostream &cs) const {
348  CommentStream = &cs;
349
350  uint8_t bytes[4];
351
352  assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
353         "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
354
355  // We want to read exactly 4 bytes of data.
356  if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
357    Size = 0;
358    return MCDisassembler::Fail;
359  }
360
361  // Encoded as a small-endian 32-bit word in the stream.
362  uint32_t insn = (bytes[3] << 24) |
363                  (bytes[2] << 16) |
364                  (bytes[1] <<  8) |
365                  (bytes[0] <<  0);
366
367  // Calling the auto-generated decoder function.
368  DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
369  if (result != MCDisassembler::Fail) {
370    Size = 4;
371    return result;
372  }
373
374  // VFP and NEON instructions, similarly, are shared between ARM
375  // and Thumb modes.
376  MI.clear();
377  result = decodeVFPInstruction32(MI, insn, Address, this, STI);
378  if (result != MCDisassembler::Fail) {
379    Size = 4;
380    return result;
381  }
382
383  MI.clear();
384  result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
385  if (result != MCDisassembler::Fail) {
386    Size = 4;
387    // Add a fake predicate operand, because we share these instruction
388    // definitions with Thumb2 where these instructions are predicable.
389    if (!DecodePredicateOperand(MI, 0xE, Address, this))
390      return MCDisassembler::Fail;
391    return result;
392  }
393
394  MI.clear();
395  result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
396  if (result != MCDisassembler::Fail) {
397    Size = 4;
398    // Add a fake predicate operand, because we share these instruction
399    // definitions with Thumb2 where these instructions are predicable.
400    if (!DecodePredicateOperand(MI, 0xE, Address, this))
401      return MCDisassembler::Fail;
402    return result;
403  }
404
405  MI.clear();
406  result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
407  if (result != MCDisassembler::Fail) {
408    Size = 4;
409    // Add a fake predicate operand, because we share these instruction
410    // definitions with Thumb2 where these instructions are predicable.
411    if (!DecodePredicateOperand(MI, 0xE, Address, this))
412      return MCDisassembler::Fail;
413    return result;
414  }
415
416  MI.clear();
417
418  Size = 0;
419  return MCDisassembler::Fail;
420}
421
422namespace llvm {
423extern const MCInstrDesc ARMInsts[];
424}
425
426/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
427/// immediate Value in the MCInst.  The immediate Value has had any PC
428/// adjustment made by the caller.  If the instruction is a branch instruction
429/// then isBranch is true, else false.  If the getOpInfo() function was set as
430/// part of the setupForSymbolicDisassembly() call then that function is called
431/// to get any symbolic information at the Address for this instruction.  If
432/// that returns non-zero then the symbolic information it returns is used to
433/// create an MCExpr and that is added as an operand to the MCInst.  If
434/// getOpInfo() returns zero and isBranch is true then a symbol look up for
435/// Value is done and if a symbol is found an MCExpr is created with that, else
436/// an MCExpr with Value is created.  This function returns true if it adds an
437/// operand to the MCInst and false otherwise.
438static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
439                                     bool isBranch, uint64_t InstSize,
440                                     MCInst &MI, const void *Decoder) {
441  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
442  LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
443  if (!getOpInfo)
444    return false;
445
446  struct LLVMOpInfo1 SymbolicOp;
447  SymbolicOp.Value = Value;
448  void *DisInfo = Dis->getDisInfoBlock();
449  if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
450    if (isBranch) {
451      LLVMSymbolLookupCallback SymbolLookUp =
452                                            Dis->getLLVMSymbolLookupCallback();
453      if (SymbolLookUp) {
454        uint64_t ReferenceType;
455        ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
456        const char *ReferenceName;
457        const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
458                                        &ReferenceName);
459        if (Name) {
460          SymbolicOp.AddSymbol.Name = Name;
461          SymbolicOp.AddSymbol.Present = true;
462          SymbolicOp.Value = 0;
463        }
464        else {
465          SymbolicOp.Value = Value;
466        }
467        if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
468          (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
469      }
470      else {
471        return false;
472      }
473    }
474    else {
475      return false;
476    }
477  }
478
479  MCContext *Ctx = Dis->getMCContext();
480  const MCExpr *Add = NULL;
481  if (SymbolicOp.AddSymbol.Present) {
482    if (SymbolicOp.AddSymbol.Name) {
483      StringRef Name(SymbolicOp.AddSymbol.Name);
484      MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
485      Add = MCSymbolRefExpr::Create(Sym, *Ctx);
486    } else {
487      Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
488    }
489  }
490
491  const MCExpr *Sub = NULL;
492  if (SymbolicOp.SubtractSymbol.Present) {
493    if (SymbolicOp.SubtractSymbol.Name) {
494      StringRef Name(SymbolicOp.SubtractSymbol.Name);
495      MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
496      Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
497    } else {
498      Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
499    }
500  }
501
502  const MCExpr *Off = NULL;
503  if (SymbolicOp.Value != 0)
504    Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
505
506  const MCExpr *Expr;
507  if (Sub) {
508    const MCExpr *LHS;
509    if (Add)
510      LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
511    else
512      LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
513    if (Off != 0)
514      Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
515    else
516      Expr = LHS;
517  } else if (Add) {
518    if (Off != 0)
519      Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
520    else
521      Expr = Add;
522  } else {
523    if (Off != 0)
524      Expr = Off;
525    else
526      Expr = MCConstantExpr::Create(0, *Ctx);
527  }
528
529  if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
530    MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
531  else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
532    MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
533  else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
534    MI.addOperand(MCOperand::CreateExpr(Expr));
535  else
536    llvm_unreachable("bad SymbolicOp.VariantKind");
537
538  return true;
539}
540
541/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
542/// referenced by a load instruction with the base register that is the Pc.
543/// These can often be values in a literal pool near the Address of the
544/// instruction.  The Address of the instruction and its immediate Value are
545/// used as a possible literal pool entry.  The SymbolLookUp call back will
546/// return the name of a symbol referenced by the the literal pool's entry if
547/// the referenced address is that of a symbol.  Or it will return a pointer to
548/// a literal 'C' string if the referenced address of the literal pool's entry
549/// is an address into a section with 'C' string literals.
550static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
551					    const void *Decoder) {
552  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
553  LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
554  if (SymbolLookUp) {
555    void *DisInfo = Dis->getDisInfoBlock();
556    uint64_t ReferenceType;
557    ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
558    const char *ReferenceName;
559    (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
560    if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
561       ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
562      (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
563  }
564}
565
566// Thumb1 instructions don't have explicit S bits.  Rather, they
567// implicitly set CPSR.  Since it's not represented in the encoding, the
568// auto-generated decoder won't inject the CPSR operand.  We need to fix
569// that as a post-pass.
570static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
571  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
572  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
573  MCInst::iterator I = MI.begin();
574  for (unsigned i = 0; i < NumOps; ++i, ++I) {
575    if (I == MI.end()) break;
576    if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
577      if (i > 0 && OpInfo[i-1].isPredicate()) continue;
578      MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
579      return;
580    }
581  }
582
583  MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
584}
585
586// Most Thumb instructions don't have explicit predicates in the
587// encoding, but rather get their predicates from IT context.  We need
588// to fix up the predicate operands using this context information as a
589// post-pass.
590MCDisassembler::DecodeStatus
591ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
592  MCDisassembler::DecodeStatus S = Success;
593
594  // A few instructions actually have predicates encoded in them.  Don't
595  // try to overwrite it if we're seeing one of those.
596  switch (MI.getOpcode()) {
597    case ARM::tBcc:
598    case ARM::t2Bcc:
599    case ARM::tCBZ:
600    case ARM::tCBNZ:
601    case ARM::tCPS:
602    case ARM::t2CPS3p:
603    case ARM::t2CPS2p:
604    case ARM::t2CPS1p:
605    case ARM::tMOVSr:
606    case ARM::tSETEND:
607      // Some instructions (mostly conditional branches) are not
608      // allowed in IT blocks.
609      if (!ITBlock.empty())
610        S = SoftFail;
611      else
612        return Success;
613      break;
614    case ARM::tB:
615    case ARM::t2B:
616    case ARM::t2TBB:
617    case ARM::t2TBH:
618      // Some instructions (mostly unconditional branches) can
619      // only appears at the end of, or outside of, an IT.
620      if (ITBlock.size() > 1)
621        S = SoftFail;
622      break;
623    default:
624      break;
625  }
626
627  // If we're in an IT block, base the predicate on that.  Otherwise,
628  // assume a predicate of AL.
629  unsigned CC;
630  if (!ITBlock.empty()) {
631    CC = ITBlock.back();
632    if (CC == 0xF)
633      CC = ARMCC::AL;
634    ITBlock.pop_back();
635  } else
636    CC = ARMCC::AL;
637
638  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
639  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
640  MCInst::iterator I = MI.begin();
641  for (unsigned i = 0; i < NumOps; ++i, ++I) {
642    if (I == MI.end()) break;
643    if (OpInfo[i].isPredicate()) {
644      I = MI.insert(I, MCOperand::CreateImm(CC));
645      ++I;
646      if (CC == ARMCC::AL)
647        MI.insert(I, MCOperand::CreateReg(0));
648      else
649        MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
650      return S;
651    }
652  }
653
654  I = MI.insert(I, MCOperand::CreateImm(CC));
655  ++I;
656  if (CC == ARMCC::AL)
657    MI.insert(I, MCOperand::CreateReg(0));
658  else
659    MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
660
661  return S;
662}
663
664// Thumb VFP instructions are a special case.  Because we share their
665// encodings between ARM and Thumb modes, and they are predicable in ARM
666// mode, the auto-generated decoder will give them an (incorrect)
667// predicate operand.  We need to rewrite these operands based on the IT
668// context as a post-pass.
669void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
670  unsigned CC;
671  if (!ITBlock.empty()) {
672    CC = ITBlock.back();
673    ITBlock.pop_back();
674  } else
675    CC = ARMCC::AL;
676
677  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
678  MCInst::iterator I = MI.begin();
679  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
680  for (unsigned i = 0; i < NumOps; ++i, ++I) {
681    if (OpInfo[i].isPredicate() ) {
682      I->setImm(CC);
683      ++I;
684      if (CC == ARMCC::AL)
685        I->setReg(0);
686      else
687        I->setReg(ARM::CPSR);
688      return;
689    }
690  }
691}
692
693DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
694                                               MemoryObject &Region,
695                                               uint64_t Address,
696                                               raw_ostream &os,
697                                               raw_ostream &cs) const {
698  CommentStream = &cs;
699
700  uint8_t bytes[4];
701
702  assert((STI.getFeatureBits() & ARM::ModeThumb) &&
703         "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
704
705  // We want to read exactly 2 bytes of data.
706  if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
707    Size = 0;
708    return MCDisassembler::Fail;
709  }
710
711  uint16_t insn16 = (bytes[1] << 8) | bytes[0];
712  DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
713  if (result != MCDisassembler::Fail) {
714    Size = 2;
715    Check(result, AddThumbPredicate(MI));
716    return result;
717  }
718
719  MI.clear();
720  result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
721  if (result) {
722    Size = 2;
723    bool InITBlock = !ITBlock.empty();
724    Check(result, AddThumbPredicate(MI));
725    AddThumb1SBit(MI, InITBlock);
726    return result;
727  }
728
729  MI.clear();
730  result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
731  if (result != MCDisassembler::Fail) {
732    Size = 2;
733
734    // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
735    // the Thumb predicate.
736    if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
737      result = MCDisassembler::SoftFail;
738
739    Check(result, AddThumbPredicate(MI));
740
741    // If we find an IT instruction, we need to parse its condition
742    // code and mask operands so that we can apply them correctly
743    // to the subsequent instructions.
744    if (MI.getOpcode() == ARM::t2IT) {
745
746      // (3 - the number of trailing zeros) is the number of then / else.
747      unsigned firstcond = MI.getOperand(0).getImm();
748      unsigned Mask = MI.getOperand(1).getImm();
749      unsigned CondBit0 = Mask >> 4 & 1;
750      unsigned NumTZ = CountTrailingZeros_32(Mask);
751      assert(NumTZ <= 3 && "Invalid IT mask!");
752      for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
753        bool T = ((Mask >> Pos) & 1) == CondBit0;
754        if (T)
755          ITBlock.insert(ITBlock.begin(), firstcond);
756        else
757          ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
758      }
759
760      ITBlock.push_back(firstcond);
761    }
762
763    return result;
764  }
765
766  // We want to read exactly 4 bytes of data.
767  if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
768    Size = 0;
769    return MCDisassembler::Fail;
770  }
771
772  uint32_t insn32 = (bytes[3] <<  8) |
773                    (bytes[2] <<  0) |
774                    (bytes[1] << 24) |
775                    (bytes[0] << 16);
776  MI.clear();
777  result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
778  if (result != MCDisassembler::Fail) {
779    Size = 4;
780    bool InITBlock = ITBlock.size();
781    Check(result, AddThumbPredicate(MI));
782    AddThumb1SBit(MI, InITBlock);
783    return result;
784  }
785
786  MI.clear();
787  result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
788  if (result != MCDisassembler::Fail) {
789    Size = 4;
790    Check(result, AddThumbPredicate(MI));
791    return result;
792  }
793
794  MI.clear();
795  result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
796  if (result != MCDisassembler::Fail) {
797    Size = 4;
798    UpdateThumbVFPPredicate(MI);
799    return result;
800  }
801
802  MI.clear();
803  result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
804  if (result != MCDisassembler::Fail) {
805    Size = 4;
806    Check(result, AddThumbPredicate(MI));
807    return result;
808  }
809
810  if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
811    MI.clear();
812    uint32_t NEONLdStInsn = insn32;
813    NEONLdStInsn &= 0xF0FFFFFF;
814    NEONLdStInsn |= 0x04000000;
815    result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
816    if (result != MCDisassembler::Fail) {
817      Size = 4;
818      Check(result, AddThumbPredicate(MI));
819      return result;
820    }
821  }
822
823  if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
824    MI.clear();
825    uint32_t NEONDataInsn = insn32;
826    NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
827    NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
828    NEONDataInsn |= 0x12000000; // Set bits 28 and 25
829    result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
830    if (result != MCDisassembler::Fail) {
831      Size = 4;
832      Check(result, AddThumbPredicate(MI));
833      return result;
834    }
835  }
836
837  Size = 0;
838  return MCDisassembler::Fail;
839}
840
841
842extern "C" void LLVMInitializeARMDisassembler() {
843  TargetRegistry::RegisterMCDisassembler(TheARMTarget,
844                                         createARMDisassembler);
845  TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
846                                         createThumbDisassembler);
847}
848
849static const unsigned GPRDecoderTable[] = {
850  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
851  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
852  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
853  ARM::R12, ARM::SP, ARM::LR, ARM::PC
854};
855
856static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
857                                   uint64_t Address, const void *Decoder) {
858  if (RegNo > 15)
859    return MCDisassembler::Fail;
860
861  unsigned Register = GPRDecoderTable[RegNo];
862  Inst.addOperand(MCOperand::CreateReg(Register));
863  return MCDisassembler::Success;
864}
865
866static DecodeStatus
867DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
868                           uint64_t Address, const void *Decoder) {
869  if (RegNo == 15) return MCDisassembler::Fail;
870  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
871}
872
873static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
874                                   uint64_t Address, const void *Decoder) {
875  if (RegNo > 7)
876    return MCDisassembler::Fail;
877  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
878}
879
880static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
881                                   uint64_t Address, const void *Decoder) {
882  unsigned Register = 0;
883  switch (RegNo) {
884    case 0:
885      Register = ARM::R0;
886      break;
887    case 1:
888      Register = ARM::R1;
889      break;
890    case 2:
891      Register = ARM::R2;
892      break;
893    case 3:
894      Register = ARM::R3;
895      break;
896    case 9:
897      Register = ARM::R9;
898      break;
899    case 12:
900      Register = ARM::R12;
901      break;
902    default:
903      return MCDisassembler::Fail;
904    }
905
906  Inst.addOperand(MCOperand::CreateReg(Register));
907  return MCDisassembler::Success;
908}
909
910static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
911                                   uint64_t Address, const void *Decoder) {
912  if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
913  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
914}
915
916static const unsigned SPRDecoderTable[] = {
917     ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
918     ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
919     ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
920    ARM::S12, ARM::S13, ARM::S14, ARM::S15,
921    ARM::S16, ARM::S17, ARM::S18, ARM::S19,
922    ARM::S20, ARM::S21, ARM::S22, ARM::S23,
923    ARM::S24, ARM::S25, ARM::S26, ARM::S27,
924    ARM::S28, ARM::S29, ARM::S30, ARM::S31
925};
926
927static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
928                                   uint64_t Address, const void *Decoder) {
929  if (RegNo > 31)
930    return MCDisassembler::Fail;
931
932  unsigned Register = SPRDecoderTable[RegNo];
933  Inst.addOperand(MCOperand::CreateReg(Register));
934  return MCDisassembler::Success;
935}
936
937static const unsigned DPRDecoderTable[] = {
938     ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
939     ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
940     ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
941    ARM::D12, ARM::D13, ARM::D14, ARM::D15,
942    ARM::D16, ARM::D17, ARM::D18, ARM::D19,
943    ARM::D20, ARM::D21, ARM::D22, ARM::D23,
944    ARM::D24, ARM::D25, ARM::D26, ARM::D27,
945    ARM::D28, ARM::D29, ARM::D30, ARM::D31
946};
947
948static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
949                                   uint64_t Address, const void *Decoder) {
950  if (RegNo > 31)
951    return MCDisassembler::Fail;
952
953  unsigned Register = DPRDecoderTable[RegNo];
954  Inst.addOperand(MCOperand::CreateReg(Register));
955  return MCDisassembler::Success;
956}
957
958static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
959                                   uint64_t Address, const void *Decoder) {
960  if (RegNo > 7)
961    return MCDisassembler::Fail;
962  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
963}
964
965static DecodeStatus
966DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
967                            uint64_t Address, const void *Decoder) {
968  if (RegNo > 15)
969    return MCDisassembler::Fail;
970  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
971}
972
973static const unsigned QPRDecoderTable[] = {
974     ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
975     ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
976     ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
977    ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
978};
979
980
981static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
982                                   uint64_t Address, const void *Decoder) {
983  if (RegNo > 31)
984    return MCDisassembler::Fail;
985  RegNo >>= 1;
986
987  unsigned Register = QPRDecoderTable[RegNo];
988  Inst.addOperand(MCOperand::CreateReg(Register));
989  return MCDisassembler::Success;
990}
991
992static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
993                               uint64_t Address, const void *Decoder) {
994  if (Val == 0xF) return MCDisassembler::Fail;
995  // AL predicate is not allowed on Thumb1 branches.
996  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
997    return MCDisassembler::Fail;
998  Inst.addOperand(MCOperand::CreateImm(Val));
999  if (Val == ARMCC::AL) {
1000    Inst.addOperand(MCOperand::CreateReg(0));
1001  } else
1002    Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1003  return MCDisassembler::Success;
1004}
1005
1006static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
1007                               uint64_t Address, const void *Decoder) {
1008  if (Val)
1009    Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1010  else
1011    Inst.addOperand(MCOperand::CreateReg(0));
1012  return MCDisassembler::Success;
1013}
1014
1015static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
1016                               uint64_t Address, const void *Decoder) {
1017  uint32_t imm = Val & 0xFF;
1018  uint32_t rot = (Val & 0xF00) >> 7;
1019  uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1020  Inst.addOperand(MCOperand::CreateImm(rot_imm));
1021  return MCDisassembler::Success;
1022}
1023
1024static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
1025                               uint64_t Address, const void *Decoder) {
1026  DecodeStatus S = MCDisassembler::Success;
1027
1028  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1029  unsigned type = fieldFromInstruction32(Val, 5, 2);
1030  unsigned imm = fieldFromInstruction32(Val, 7, 5);
1031
1032  // Register-immediate
1033  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1034    return MCDisassembler::Fail;
1035
1036  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1037  switch (type) {
1038    case 0:
1039      Shift = ARM_AM::lsl;
1040      break;
1041    case 1:
1042      Shift = ARM_AM::lsr;
1043      break;
1044    case 2:
1045      Shift = ARM_AM::asr;
1046      break;
1047    case 3:
1048      Shift = ARM_AM::ror;
1049      break;
1050  }
1051
1052  if (Shift == ARM_AM::ror && imm == 0)
1053    Shift = ARM_AM::rrx;
1054
1055  unsigned Op = Shift | (imm << 3);
1056  Inst.addOperand(MCOperand::CreateImm(Op));
1057
1058  return S;
1059}
1060
1061static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
1062                               uint64_t Address, const void *Decoder) {
1063  DecodeStatus S = MCDisassembler::Success;
1064
1065  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1066  unsigned type = fieldFromInstruction32(Val, 5, 2);
1067  unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1068
1069  // Register-register
1070  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1071    return MCDisassembler::Fail;
1072  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1073    return MCDisassembler::Fail;
1074
1075  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1076  switch (type) {
1077    case 0:
1078      Shift = ARM_AM::lsl;
1079      break;
1080    case 1:
1081      Shift = ARM_AM::lsr;
1082      break;
1083    case 2:
1084      Shift = ARM_AM::asr;
1085      break;
1086    case 3:
1087      Shift = ARM_AM::ror;
1088      break;
1089  }
1090
1091  Inst.addOperand(MCOperand::CreateImm(Shift));
1092
1093  return S;
1094}
1095
1096static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
1097                                 uint64_t Address, const void *Decoder) {
1098  DecodeStatus S = MCDisassembler::Success;
1099
1100  bool writebackLoad = false;
1101  unsigned writebackReg = 0;
1102  switch (Inst.getOpcode()) {
1103    default:
1104      break;
1105    case ARM::LDMIA_UPD:
1106    case ARM::LDMDB_UPD:
1107    case ARM::LDMIB_UPD:
1108    case ARM::LDMDA_UPD:
1109    case ARM::t2LDMIA_UPD:
1110    case ARM::t2LDMDB_UPD:
1111      writebackLoad = true;
1112      writebackReg = Inst.getOperand(0).getReg();
1113      break;
1114  }
1115
1116  // Empty register lists are not allowed.
1117  if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1118  for (unsigned i = 0; i < 16; ++i) {
1119    if (Val & (1 << i)) {
1120      if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1121        return MCDisassembler::Fail;
1122      // Writeback not allowed if Rn is in the target list.
1123      if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1124        Check(S, MCDisassembler::SoftFail);
1125    }
1126  }
1127
1128  return S;
1129}
1130
1131static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1132                                 uint64_t Address, const void *Decoder) {
1133  DecodeStatus S = MCDisassembler::Success;
1134
1135  unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1136  unsigned regs = Val & 0xFF;
1137
1138  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1139    return MCDisassembler::Fail;
1140  for (unsigned i = 0; i < (regs - 1); ++i) {
1141    if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1142      return MCDisassembler::Fail;
1143  }
1144
1145  return S;
1146}
1147
1148static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1149                                 uint64_t Address, const void *Decoder) {
1150  DecodeStatus S = MCDisassembler::Success;
1151
1152  unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1153  unsigned regs = (Val & 0xFF) / 2;
1154
1155  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1156      return MCDisassembler::Fail;
1157  for (unsigned i = 0; i < (regs - 1); ++i) {
1158    if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1159      return MCDisassembler::Fail;
1160  }
1161
1162  return S;
1163}
1164
1165static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
1166                                      uint64_t Address, const void *Decoder) {
1167  // This operand encodes a mask of contiguous zeros between a specified MSB
1168  // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
1169  // the mask of all bits LSB-and-lower, and then xor them to create
1170  // the mask of that's all ones on [msb, lsb].  Finally we not it to
1171  // create the final mask.
1172  unsigned msb = fieldFromInstruction32(Val, 5, 5);
1173  unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1174
1175  DecodeStatus S = MCDisassembler::Success;
1176  if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1177
1178  uint32_t msb_mask = 0xFFFFFFFF;
1179  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1180  uint32_t lsb_mask = (1U << lsb) - 1;
1181
1182  Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1183  return S;
1184}
1185
1186static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
1187                                  uint64_t Address, const void *Decoder) {
1188  DecodeStatus S = MCDisassembler::Success;
1189
1190  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1191  unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1192  unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1193  unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1194  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1195  unsigned U = fieldFromInstruction32(Insn, 23, 1);
1196
1197  switch (Inst.getOpcode()) {
1198    case ARM::LDC_OFFSET:
1199    case ARM::LDC_PRE:
1200    case ARM::LDC_POST:
1201    case ARM::LDC_OPTION:
1202    case ARM::LDCL_OFFSET:
1203    case ARM::LDCL_PRE:
1204    case ARM::LDCL_POST:
1205    case ARM::LDCL_OPTION:
1206    case ARM::STC_OFFSET:
1207    case ARM::STC_PRE:
1208    case ARM::STC_POST:
1209    case ARM::STC_OPTION:
1210    case ARM::STCL_OFFSET:
1211    case ARM::STCL_PRE:
1212    case ARM::STCL_POST:
1213    case ARM::STCL_OPTION:
1214    case ARM::t2LDC_OFFSET:
1215    case ARM::t2LDC_PRE:
1216    case ARM::t2LDC_POST:
1217    case ARM::t2LDC_OPTION:
1218    case ARM::t2LDCL_OFFSET:
1219    case ARM::t2LDCL_PRE:
1220    case ARM::t2LDCL_POST:
1221    case ARM::t2LDCL_OPTION:
1222    case ARM::t2STC_OFFSET:
1223    case ARM::t2STC_PRE:
1224    case ARM::t2STC_POST:
1225    case ARM::t2STC_OPTION:
1226    case ARM::t2STCL_OFFSET:
1227    case ARM::t2STCL_PRE:
1228    case ARM::t2STCL_POST:
1229    case ARM::t2STCL_OPTION:
1230      if (coproc == 0xA || coproc == 0xB)
1231        return MCDisassembler::Fail;
1232      break;
1233    default:
1234      break;
1235  }
1236
1237  Inst.addOperand(MCOperand::CreateImm(coproc));
1238  Inst.addOperand(MCOperand::CreateImm(CRd));
1239  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1240    return MCDisassembler::Fail;
1241
1242  switch (Inst.getOpcode()) {
1243    case ARM::t2LDC2_OFFSET:
1244    case ARM::t2LDC2L_OFFSET:
1245    case ARM::t2LDC2_PRE:
1246    case ARM::t2LDC2L_PRE:
1247    case ARM::t2STC2_OFFSET:
1248    case ARM::t2STC2L_OFFSET:
1249    case ARM::t2STC2_PRE:
1250    case ARM::t2STC2L_PRE:
1251    case ARM::LDC2_OFFSET:
1252    case ARM::LDC2L_OFFSET:
1253    case ARM::LDC2_PRE:
1254    case ARM::LDC2L_PRE:
1255    case ARM::STC2_OFFSET:
1256    case ARM::STC2L_OFFSET:
1257    case ARM::STC2_PRE:
1258    case ARM::STC2L_PRE:
1259    case ARM::t2LDC_OFFSET:
1260    case ARM::t2LDCL_OFFSET:
1261    case ARM::t2LDC_PRE:
1262    case ARM::t2LDCL_PRE:
1263    case ARM::t2STC_OFFSET:
1264    case ARM::t2STCL_OFFSET:
1265    case ARM::t2STC_PRE:
1266    case ARM::t2STCL_PRE:
1267    case ARM::LDC_OFFSET:
1268    case ARM::LDCL_OFFSET:
1269    case ARM::LDC_PRE:
1270    case ARM::LDCL_PRE:
1271    case ARM::STC_OFFSET:
1272    case ARM::STCL_OFFSET:
1273    case ARM::STC_PRE:
1274    case ARM::STCL_PRE:
1275      imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1276      Inst.addOperand(MCOperand::CreateImm(imm));
1277      break;
1278    case ARM::t2LDC2_POST:
1279    case ARM::t2LDC2L_POST:
1280    case ARM::t2STC2_POST:
1281    case ARM::t2STC2L_POST:
1282    case ARM::LDC2_POST:
1283    case ARM::LDC2L_POST:
1284    case ARM::STC2_POST:
1285    case ARM::STC2L_POST:
1286    case ARM::t2LDC_POST:
1287    case ARM::t2LDCL_POST:
1288    case ARM::t2STC_POST:
1289    case ARM::t2STCL_POST:
1290    case ARM::LDC_POST:
1291    case ARM::LDCL_POST:
1292    case ARM::STC_POST:
1293    case ARM::STCL_POST:
1294      imm |= U << 8;
1295      // fall through.
1296    default:
1297      // The 'option' variant doesn't encode 'U' in the immediate since
1298      // the immediate is unsigned [0,255].
1299      Inst.addOperand(MCOperand::CreateImm(imm));
1300      break;
1301  }
1302
1303  switch (Inst.getOpcode()) {
1304    case ARM::LDC_OFFSET:
1305    case ARM::LDC_PRE:
1306    case ARM::LDC_POST:
1307    case ARM::LDC_OPTION:
1308    case ARM::LDCL_OFFSET:
1309    case ARM::LDCL_PRE:
1310    case ARM::LDCL_POST:
1311    case ARM::LDCL_OPTION:
1312    case ARM::STC_OFFSET:
1313    case ARM::STC_PRE:
1314    case ARM::STC_POST:
1315    case ARM::STC_OPTION:
1316    case ARM::STCL_OFFSET:
1317    case ARM::STCL_PRE:
1318    case ARM::STCL_POST:
1319    case ARM::STCL_OPTION:
1320      if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1321        return MCDisassembler::Fail;
1322      break;
1323    default:
1324      break;
1325  }
1326
1327  return S;
1328}
1329
1330static DecodeStatus
1331DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1332                              uint64_t Address, const void *Decoder) {
1333  DecodeStatus S = MCDisassembler::Success;
1334
1335  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1336  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1337  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1338  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1339  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1340  unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1341  unsigned P = fieldFromInstruction32(Insn, 24, 1);
1342  unsigned W = fieldFromInstruction32(Insn, 21, 1);
1343
1344  // On stores, the writeback operand precedes Rt.
1345  switch (Inst.getOpcode()) {
1346    case ARM::STR_POST_IMM:
1347    case ARM::STR_POST_REG:
1348    case ARM::STRB_POST_IMM:
1349    case ARM::STRB_POST_REG:
1350    case ARM::STRT_POST_REG:
1351    case ARM::STRT_POST_IMM:
1352    case ARM::STRBT_POST_REG:
1353    case ARM::STRBT_POST_IMM:
1354      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1355        return MCDisassembler::Fail;
1356      break;
1357    default:
1358      break;
1359  }
1360
1361  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1362    return MCDisassembler::Fail;
1363
1364  // On loads, the writeback operand comes after Rt.
1365  switch (Inst.getOpcode()) {
1366    case ARM::LDR_POST_IMM:
1367    case ARM::LDR_POST_REG:
1368    case ARM::LDRB_POST_IMM:
1369    case ARM::LDRB_POST_REG:
1370    case ARM::LDRBT_POST_REG:
1371    case ARM::LDRBT_POST_IMM:
1372    case ARM::LDRT_POST_REG:
1373    case ARM::LDRT_POST_IMM:
1374      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1375        return MCDisassembler::Fail;
1376      break;
1377    default:
1378      break;
1379  }
1380
1381  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1382    return MCDisassembler::Fail;
1383
1384  ARM_AM::AddrOpc Op = ARM_AM::add;
1385  if (!fieldFromInstruction32(Insn, 23, 1))
1386    Op = ARM_AM::sub;
1387
1388  bool writeback = (P == 0) || (W == 1);
1389  unsigned idx_mode = 0;
1390  if (P && writeback)
1391    idx_mode = ARMII::IndexModePre;
1392  else if (!P && writeback)
1393    idx_mode = ARMII::IndexModePost;
1394
1395  if (writeback && (Rn == 15 || Rn == Rt))
1396    S = MCDisassembler::SoftFail; // UNPREDICTABLE
1397
1398  if (reg) {
1399    if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1400      return MCDisassembler::Fail;
1401    ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1402    switch( fieldFromInstruction32(Insn, 5, 2)) {
1403      case 0:
1404        Opc = ARM_AM::lsl;
1405        break;
1406      case 1:
1407        Opc = ARM_AM::lsr;
1408        break;
1409      case 2:
1410        Opc = ARM_AM::asr;
1411        break;
1412      case 3:
1413        Opc = ARM_AM::ror;
1414        break;
1415      default:
1416        return MCDisassembler::Fail;
1417    }
1418    unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1419    unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1420
1421    Inst.addOperand(MCOperand::CreateImm(imm));
1422  } else {
1423    Inst.addOperand(MCOperand::CreateReg(0));
1424    unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1425    Inst.addOperand(MCOperand::CreateImm(tmp));
1426  }
1427
1428  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1429    return MCDisassembler::Fail;
1430
1431  return S;
1432}
1433
1434static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1435                                  uint64_t Address, const void *Decoder) {
1436  DecodeStatus S = MCDisassembler::Success;
1437
1438  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1439  unsigned Rm = fieldFromInstruction32(Val,  0, 4);
1440  unsigned type = fieldFromInstruction32(Val, 5, 2);
1441  unsigned imm = fieldFromInstruction32(Val, 7, 5);
1442  unsigned U = fieldFromInstruction32(Val, 12, 1);
1443
1444  ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1445  switch (type) {
1446    case 0:
1447      ShOp = ARM_AM::lsl;
1448      break;
1449    case 1:
1450      ShOp = ARM_AM::lsr;
1451      break;
1452    case 2:
1453      ShOp = ARM_AM::asr;
1454      break;
1455    case 3:
1456      ShOp = ARM_AM::ror;
1457      break;
1458  }
1459
1460  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1461    return MCDisassembler::Fail;
1462  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1463    return MCDisassembler::Fail;
1464  unsigned shift;
1465  if (U)
1466    shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1467  else
1468    shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1469  Inst.addOperand(MCOperand::CreateImm(shift));
1470
1471  return S;
1472}
1473
1474static DecodeStatus
1475DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1476                           uint64_t Address, const void *Decoder) {
1477  DecodeStatus S = MCDisassembler::Success;
1478
1479  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1480  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1481  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1482  unsigned type = fieldFromInstruction32(Insn, 22, 1);
1483  unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1484  unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1485  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1486  unsigned W = fieldFromInstruction32(Insn, 21, 1);
1487  unsigned P = fieldFromInstruction32(Insn, 24, 1);
1488
1489  bool writeback = (W == 1) | (P == 0);
1490
1491  // For {LD,ST}RD, Rt must be even, else undefined.
1492  switch (Inst.getOpcode()) {
1493    case ARM::STRD:
1494    case ARM::STRD_PRE:
1495    case ARM::STRD_POST:
1496    case ARM::LDRD:
1497    case ARM::LDRD_PRE:
1498    case ARM::LDRD_POST:
1499      if (Rt & 0x1) return MCDisassembler::Fail;
1500      break;
1501    default:
1502      break;
1503  }
1504
1505  if (writeback) { // Writeback
1506    if (P)
1507      U |= ARMII::IndexModePre << 9;
1508    else
1509      U |= ARMII::IndexModePost << 9;
1510
1511    // On stores, the writeback operand precedes Rt.
1512    switch (Inst.getOpcode()) {
1513    case ARM::STRD:
1514    case ARM::STRD_PRE:
1515    case ARM::STRD_POST:
1516    case ARM::STRH:
1517    case ARM::STRH_PRE:
1518    case ARM::STRH_POST:
1519      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1520        return MCDisassembler::Fail;
1521      break;
1522    default:
1523      break;
1524    }
1525  }
1526
1527  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1528    return MCDisassembler::Fail;
1529  switch (Inst.getOpcode()) {
1530    case ARM::STRD:
1531    case ARM::STRD_PRE:
1532    case ARM::STRD_POST:
1533    case ARM::LDRD:
1534    case ARM::LDRD_PRE:
1535    case ARM::LDRD_POST:
1536      if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1537        return MCDisassembler::Fail;
1538      break;
1539    default:
1540      break;
1541  }
1542
1543  if (writeback) {
1544    // On loads, the writeback operand comes after Rt.
1545    switch (Inst.getOpcode()) {
1546    case ARM::LDRD:
1547    case ARM::LDRD_PRE:
1548    case ARM::LDRD_POST:
1549    case ARM::LDRH:
1550    case ARM::LDRH_PRE:
1551    case ARM::LDRH_POST:
1552    case ARM::LDRSH:
1553    case ARM::LDRSH_PRE:
1554    case ARM::LDRSH_POST:
1555    case ARM::LDRSB:
1556    case ARM::LDRSB_PRE:
1557    case ARM::LDRSB_POST:
1558    case ARM::LDRHTr:
1559    case ARM::LDRSBTr:
1560      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1561        return MCDisassembler::Fail;
1562      break;
1563    default:
1564      break;
1565    }
1566  }
1567
1568  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1569    return MCDisassembler::Fail;
1570
1571  if (type) {
1572    Inst.addOperand(MCOperand::CreateReg(0));
1573    Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1574  } else {
1575    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1576    return MCDisassembler::Fail;
1577    Inst.addOperand(MCOperand::CreateImm(U));
1578  }
1579
1580  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1581    return MCDisassembler::Fail;
1582
1583  return S;
1584}
1585
1586static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1587                                 uint64_t Address, const void *Decoder) {
1588  DecodeStatus S = MCDisassembler::Success;
1589
1590  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1591  unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1592
1593  switch (mode) {
1594    case 0:
1595      mode = ARM_AM::da;
1596      break;
1597    case 1:
1598      mode = ARM_AM::ia;
1599      break;
1600    case 2:
1601      mode = ARM_AM::db;
1602      break;
1603    case 3:
1604      mode = ARM_AM::ib;
1605      break;
1606  }
1607
1608  Inst.addOperand(MCOperand::CreateImm(mode));
1609  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1610    return MCDisassembler::Fail;
1611
1612  return S;
1613}
1614
1615static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1616                                  unsigned Insn,
1617                                  uint64_t Address, const void *Decoder) {
1618  DecodeStatus S = MCDisassembler::Success;
1619
1620  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1621  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1622  unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1623
1624  if (pred == 0xF) {
1625    switch (Inst.getOpcode()) {
1626      case ARM::LDMDA:
1627        Inst.setOpcode(ARM::RFEDA);
1628        break;
1629      case ARM::LDMDA_UPD:
1630        Inst.setOpcode(ARM::RFEDA_UPD);
1631        break;
1632      case ARM::LDMDB:
1633        Inst.setOpcode(ARM::RFEDB);
1634        break;
1635      case ARM::LDMDB_UPD:
1636        Inst.setOpcode(ARM::RFEDB_UPD);
1637        break;
1638      case ARM::LDMIA:
1639        Inst.setOpcode(ARM::RFEIA);
1640        break;
1641      case ARM::LDMIA_UPD:
1642        Inst.setOpcode(ARM::RFEIA_UPD);
1643        break;
1644      case ARM::LDMIB:
1645        Inst.setOpcode(ARM::RFEIB);
1646        break;
1647      case ARM::LDMIB_UPD:
1648        Inst.setOpcode(ARM::RFEIB_UPD);
1649        break;
1650      case ARM::STMDA:
1651        Inst.setOpcode(ARM::SRSDA);
1652        break;
1653      case ARM::STMDA_UPD:
1654        Inst.setOpcode(ARM::SRSDA_UPD);
1655        break;
1656      case ARM::STMDB:
1657        Inst.setOpcode(ARM::SRSDB);
1658        break;
1659      case ARM::STMDB_UPD:
1660        Inst.setOpcode(ARM::SRSDB_UPD);
1661        break;
1662      case ARM::STMIA:
1663        Inst.setOpcode(ARM::SRSIA);
1664        break;
1665      case ARM::STMIA_UPD:
1666        Inst.setOpcode(ARM::SRSIA_UPD);
1667        break;
1668      case ARM::STMIB:
1669        Inst.setOpcode(ARM::SRSIB);
1670        break;
1671      case ARM::STMIB_UPD:
1672        Inst.setOpcode(ARM::SRSIB_UPD);
1673        break;
1674      default:
1675        if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1676    }
1677
1678    // For stores (which become SRS's, the only operand is the mode.
1679    if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1680      Inst.addOperand(
1681          MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1682      return S;
1683    }
1684
1685    return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1686  }
1687
1688  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1689    return MCDisassembler::Fail;
1690  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1691    return MCDisassembler::Fail; // Tied
1692  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1693    return MCDisassembler::Fail;
1694  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1695    return MCDisassembler::Fail;
1696
1697  return S;
1698}
1699
1700static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1701                                 uint64_t Address, const void *Decoder) {
1702  unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1703  unsigned M = fieldFromInstruction32(Insn, 17, 1);
1704  unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1705  unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1706
1707  DecodeStatus S = MCDisassembler::Success;
1708
1709  // imod == '01' --> UNPREDICTABLE
1710  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1711  // return failure here.  The '01' imod value is unprintable, so there's
1712  // nothing useful we could do even if we returned UNPREDICTABLE.
1713
1714  if (imod == 1) return MCDisassembler::Fail;
1715
1716  if (imod && M) {
1717    Inst.setOpcode(ARM::CPS3p);
1718    Inst.addOperand(MCOperand::CreateImm(imod));
1719    Inst.addOperand(MCOperand::CreateImm(iflags));
1720    Inst.addOperand(MCOperand::CreateImm(mode));
1721  } else if (imod && !M) {
1722    Inst.setOpcode(ARM::CPS2p);
1723    Inst.addOperand(MCOperand::CreateImm(imod));
1724    Inst.addOperand(MCOperand::CreateImm(iflags));
1725    if (mode) S = MCDisassembler::SoftFail;
1726  } else if (!imod && M) {
1727    Inst.setOpcode(ARM::CPS1p);
1728    Inst.addOperand(MCOperand::CreateImm(mode));
1729    if (iflags) S = MCDisassembler::SoftFail;
1730  } else {
1731    // imod == '00' && M == '0' --> UNPREDICTABLE
1732    Inst.setOpcode(ARM::CPS1p);
1733    Inst.addOperand(MCOperand::CreateImm(mode));
1734    S = MCDisassembler::SoftFail;
1735  }
1736
1737  return S;
1738}
1739
1740static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1741                                 uint64_t Address, const void *Decoder) {
1742  unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1743  unsigned M = fieldFromInstruction32(Insn, 8, 1);
1744  unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1745  unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1746
1747  DecodeStatus S = MCDisassembler::Success;
1748
1749  // imod == '01' --> UNPREDICTABLE
1750  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1751  // return failure here.  The '01' imod value is unprintable, so there's
1752  // nothing useful we could do even if we returned UNPREDICTABLE.
1753
1754  if (imod == 1) return MCDisassembler::Fail;
1755
1756  if (imod && M) {
1757    Inst.setOpcode(ARM::t2CPS3p);
1758    Inst.addOperand(MCOperand::CreateImm(imod));
1759    Inst.addOperand(MCOperand::CreateImm(iflags));
1760    Inst.addOperand(MCOperand::CreateImm(mode));
1761  } else if (imod && !M) {
1762    Inst.setOpcode(ARM::t2CPS2p);
1763    Inst.addOperand(MCOperand::CreateImm(imod));
1764    Inst.addOperand(MCOperand::CreateImm(iflags));
1765    if (mode) S = MCDisassembler::SoftFail;
1766  } else if (!imod && M) {
1767    Inst.setOpcode(ARM::t2CPS1p);
1768    Inst.addOperand(MCOperand::CreateImm(mode));
1769    if (iflags) S = MCDisassembler::SoftFail;
1770  } else {
1771    // imod == '00' && M == '0' --> UNPREDICTABLE
1772    Inst.setOpcode(ARM::t2CPS1p);
1773    Inst.addOperand(MCOperand::CreateImm(mode));
1774    S = MCDisassembler::SoftFail;
1775  }
1776
1777  return S;
1778}
1779
1780static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1781                                 uint64_t Address, const void *Decoder) {
1782  DecodeStatus S = MCDisassembler::Success;
1783
1784  unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1785  unsigned imm = 0;
1786
1787  imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1788  imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1789  imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1790  imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1791
1792  if (Inst.getOpcode() == ARM::t2MOVTi16)
1793    if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1794      return MCDisassembler::Fail;
1795  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1796    return MCDisassembler::Fail;
1797
1798  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1799    Inst.addOperand(MCOperand::CreateImm(imm));
1800
1801  return S;
1802}
1803
1804static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1805                                 uint64_t Address, const void *Decoder) {
1806  DecodeStatus S = MCDisassembler::Success;
1807
1808  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1809  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1810  unsigned imm = 0;
1811
1812  imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1813  imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1814
1815  if (Inst.getOpcode() == ARM::MOVTi16)
1816    if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1817      return MCDisassembler::Fail;
1818  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1819    return MCDisassembler::Fail;
1820
1821  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1822    Inst.addOperand(MCOperand::CreateImm(imm));
1823
1824  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1825    return MCDisassembler::Fail;
1826
1827  return S;
1828}
1829
1830static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1831                                 uint64_t Address, const void *Decoder) {
1832  DecodeStatus S = MCDisassembler::Success;
1833
1834  unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1835  unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1836  unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1837  unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1838  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1839
1840  if (pred == 0xF)
1841    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1842
1843  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1844    return MCDisassembler::Fail;
1845  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1846    return MCDisassembler::Fail;
1847  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1848    return MCDisassembler::Fail;
1849  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1850    return MCDisassembler::Fail;
1851
1852  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1853    return MCDisassembler::Fail;
1854
1855  return S;
1856}
1857
1858static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1859                           uint64_t Address, const void *Decoder) {
1860  DecodeStatus S = MCDisassembler::Success;
1861
1862  unsigned add = fieldFromInstruction32(Val, 12, 1);
1863  unsigned imm = fieldFromInstruction32(Val, 0, 12);
1864  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1865
1866  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1867    return MCDisassembler::Fail;
1868
1869  if (!add) imm *= -1;
1870  if (imm == 0 && !add) imm = INT32_MIN;
1871  Inst.addOperand(MCOperand::CreateImm(imm));
1872  if (Rn == 15)
1873    tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
1874
1875  return S;
1876}
1877
1878static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1879                                   uint64_t Address, const void *Decoder) {
1880  DecodeStatus S = MCDisassembler::Success;
1881
1882  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1883  unsigned U = fieldFromInstruction32(Val, 8, 1);
1884  unsigned imm = fieldFromInstruction32(Val, 0, 8);
1885
1886  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1887    return MCDisassembler::Fail;
1888
1889  if (U)
1890    Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1891  else
1892    Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1893
1894  return S;
1895}
1896
1897static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1898                                   uint64_t Address, const void *Decoder) {
1899  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1900}
1901
1902static DecodeStatus
1903DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1904                           uint64_t Address, const void *Decoder) {
1905  DecodeStatus S = MCDisassembler::Success;
1906
1907  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1908  unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1909
1910  if (pred == 0xF) {
1911    Inst.setOpcode(ARM::BLXi);
1912    imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1913    Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1914    return S;
1915  }
1916
1917  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1918                                4, Inst, Decoder))
1919    Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1920  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1921    return MCDisassembler::Fail;
1922
1923  return S;
1924}
1925
1926
1927static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1928                                   uint64_t Address, const void *Decoder) {
1929  DecodeStatus S = MCDisassembler::Success;
1930
1931  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1932  unsigned align = fieldFromInstruction32(Val, 4, 2);
1933
1934  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1935    return MCDisassembler::Fail;
1936  if (!align)
1937    Inst.addOperand(MCOperand::CreateImm(0));
1938  else
1939    Inst.addOperand(MCOperand::CreateImm(4 << align));
1940
1941  return S;
1942}
1943
1944static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1945                                   uint64_t Address, const void *Decoder) {
1946  DecodeStatus S = MCDisassembler::Success;
1947
1948  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1949  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1950  unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1951  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1952  Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1953  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1954
1955  // First output register
1956  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1957    return MCDisassembler::Fail;
1958
1959  // Second output register
1960  switch (Inst.getOpcode()) {
1961    case ARM::VLD3d8:
1962    case ARM::VLD3d16:
1963    case ARM::VLD3d32:
1964    case ARM::VLD3d8_UPD:
1965    case ARM::VLD3d16_UPD:
1966    case ARM::VLD3d32_UPD:
1967    case ARM::VLD4d8:
1968    case ARM::VLD4d16:
1969    case ARM::VLD4d32:
1970    case ARM::VLD4d8_UPD:
1971    case ARM::VLD4d16_UPD:
1972    case ARM::VLD4d32_UPD:
1973      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1974        return MCDisassembler::Fail;
1975      break;
1976    case ARM::VLD3q8:
1977    case ARM::VLD3q16:
1978    case ARM::VLD3q32:
1979    case ARM::VLD3q8_UPD:
1980    case ARM::VLD3q16_UPD:
1981    case ARM::VLD3q32_UPD:
1982    case ARM::VLD4q8:
1983    case ARM::VLD4q16:
1984    case ARM::VLD4q32:
1985    case ARM::VLD4q8_UPD:
1986    case ARM::VLD4q16_UPD:
1987    case ARM::VLD4q32_UPD:
1988      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1989        return MCDisassembler::Fail;
1990    default:
1991      break;
1992  }
1993
1994  // Third output register
1995  switch(Inst.getOpcode()) {
1996    case ARM::VLD3d8:
1997    case ARM::VLD3d16:
1998    case ARM::VLD3d32:
1999    case ARM::VLD3d8_UPD:
2000    case ARM::VLD3d16_UPD:
2001    case ARM::VLD3d32_UPD:
2002    case ARM::VLD4d8:
2003    case ARM::VLD4d16:
2004    case ARM::VLD4d32:
2005    case ARM::VLD4d8_UPD:
2006    case ARM::VLD4d16_UPD:
2007    case ARM::VLD4d32_UPD:
2008      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2009        return MCDisassembler::Fail;
2010      break;
2011    case ARM::VLD3q8:
2012    case ARM::VLD3q16:
2013    case ARM::VLD3q32:
2014    case ARM::VLD3q8_UPD:
2015    case ARM::VLD3q16_UPD:
2016    case ARM::VLD3q32_UPD:
2017    case ARM::VLD4q8:
2018    case ARM::VLD4q16:
2019    case ARM::VLD4q32:
2020    case ARM::VLD4q8_UPD:
2021    case ARM::VLD4q16_UPD:
2022    case ARM::VLD4q32_UPD:
2023      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2024        return MCDisassembler::Fail;
2025      break;
2026    default:
2027      break;
2028  }
2029
2030  // Fourth output register
2031  switch (Inst.getOpcode()) {
2032    case ARM::VLD4d8:
2033    case ARM::VLD4d16:
2034    case ARM::VLD4d32:
2035    case ARM::VLD4d8_UPD:
2036    case ARM::VLD4d16_UPD:
2037    case ARM::VLD4d32_UPD:
2038      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2039        return MCDisassembler::Fail;
2040      break;
2041    case ARM::VLD4q8:
2042    case ARM::VLD4q16:
2043    case ARM::VLD4q32:
2044    case ARM::VLD4q8_UPD:
2045    case ARM::VLD4q16_UPD:
2046    case ARM::VLD4q32_UPD:
2047      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2048        return MCDisassembler::Fail;
2049      break;
2050    default:
2051      break;
2052  }
2053
2054  // Writeback operand
2055  switch (Inst.getOpcode()) {
2056    case ARM::VLD1d8wb_fixed:
2057    case ARM::VLD1d16wb_fixed:
2058    case ARM::VLD1d32wb_fixed:
2059    case ARM::VLD1d64wb_fixed:
2060    case ARM::VLD1d8wb_register:
2061    case ARM::VLD1d16wb_register:
2062    case ARM::VLD1d32wb_register:
2063    case ARM::VLD1d64wb_register:
2064    case ARM::VLD1q8wb_fixed:
2065    case ARM::VLD1q16wb_fixed:
2066    case ARM::VLD1q32wb_fixed:
2067    case ARM::VLD1q64wb_fixed:
2068    case ARM::VLD1q8wb_register:
2069    case ARM::VLD1q16wb_register:
2070    case ARM::VLD1q32wb_register:
2071    case ARM::VLD1q64wb_register:
2072    case ARM::VLD1d8Twb_fixed:
2073    case ARM::VLD1d8Twb_register:
2074    case ARM::VLD1d16Twb_fixed:
2075    case ARM::VLD1d16Twb_register:
2076    case ARM::VLD1d32Twb_fixed:
2077    case ARM::VLD1d32Twb_register:
2078    case ARM::VLD1d64Twb_fixed:
2079    case ARM::VLD1d64Twb_register:
2080    case ARM::VLD1d8Qwb_fixed:
2081    case ARM::VLD1d8Qwb_register:
2082    case ARM::VLD1d16Qwb_fixed:
2083    case ARM::VLD1d16Qwb_register:
2084    case ARM::VLD1d32Qwb_fixed:
2085    case ARM::VLD1d32Qwb_register:
2086    case ARM::VLD1d64Qwb_fixed:
2087    case ARM::VLD1d64Qwb_register:
2088    case ARM::VLD2d8wb_fixed:
2089    case ARM::VLD2d16wb_fixed:
2090    case ARM::VLD2d32wb_fixed:
2091    case ARM::VLD2q8wb_fixed:
2092    case ARM::VLD2q16wb_fixed:
2093    case ARM::VLD2q32wb_fixed:
2094    case ARM::VLD2d8wb_register:
2095    case ARM::VLD2d16wb_register:
2096    case ARM::VLD2d32wb_register:
2097    case ARM::VLD2q8wb_register:
2098    case ARM::VLD2q16wb_register:
2099    case ARM::VLD2q32wb_register:
2100    case ARM::VLD2b8wb_fixed:
2101    case ARM::VLD2b16wb_fixed:
2102    case ARM::VLD2b32wb_fixed:
2103    case ARM::VLD2b8wb_register:
2104    case ARM::VLD2b16wb_register:
2105    case ARM::VLD2b32wb_register:
2106    case ARM::VLD3d8_UPD:
2107    case ARM::VLD3d16_UPD:
2108    case ARM::VLD3d32_UPD:
2109    case ARM::VLD3q8_UPD:
2110    case ARM::VLD3q16_UPD:
2111    case ARM::VLD3q32_UPD:
2112    case ARM::VLD4d8_UPD:
2113    case ARM::VLD4d16_UPD:
2114    case ARM::VLD4d32_UPD:
2115    case ARM::VLD4q8_UPD:
2116    case ARM::VLD4q16_UPD:
2117    case ARM::VLD4q32_UPD:
2118      if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2119        return MCDisassembler::Fail;
2120      break;
2121    default:
2122      break;
2123  }
2124
2125  // AddrMode6 Base (register+alignment)
2126  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2127    return MCDisassembler::Fail;
2128
2129  // AddrMode6 Offset (register)
2130  switch (Inst.getOpcode()) {
2131  default:
2132    // The below have been updated to have explicit am6offset split
2133    // between fixed and register offset. For those instructions not
2134    // yet updated, we need to add an additional reg0 operand for the
2135    // fixed variant.
2136    //
2137    // The fixed offset encodes as Rm == 0xd, so we check for that.
2138    if (Rm == 0xd) {
2139      Inst.addOperand(MCOperand::CreateReg(0));
2140      break;
2141    }
2142    // Fall through to handle the register offset variant.
2143  case ARM::VLD1d8wb_fixed:
2144  case ARM::VLD1d16wb_fixed:
2145  case ARM::VLD1d32wb_fixed:
2146  case ARM::VLD1d64wb_fixed:
2147  case ARM::VLD1d8Twb_fixed:
2148  case ARM::VLD1d16Twb_fixed:
2149  case ARM::VLD1d32Twb_fixed:
2150  case ARM::VLD1d64Twb_fixed:
2151  case ARM::VLD1d8Qwb_fixed:
2152  case ARM::VLD1d16Qwb_fixed:
2153  case ARM::VLD1d32Qwb_fixed:
2154  case ARM::VLD1d64Qwb_fixed:
2155  case ARM::VLD1d8wb_register:
2156  case ARM::VLD1d16wb_register:
2157  case ARM::VLD1d32wb_register:
2158  case ARM::VLD1d64wb_register:
2159  case ARM::VLD1q8wb_fixed:
2160  case ARM::VLD1q16wb_fixed:
2161  case ARM::VLD1q32wb_fixed:
2162  case ARM::VLD1q64wb_fixed:
2163  case ARM::VLD1q8wb_register:
2164  case ARM::VLD1q16wb_register:
2165  case ARM::VLD1q32wb_register:
2166  case ARM::VLD1q64wb_register:
2167    // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2168    // variant encodes Rm == 0xf. Anything else is a register offset post-
2169    // increment and we need to add the register operand to the instruction.
2170    if (Rm != 0xD && Rm != 0xF &&
2171        !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2172      return MCDisassembler::Fail;
2173    break;
2174  }
2175
2176  return S;
2177}
2178
2179static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
2180                                 uint64_t Address, const void *Decoder) {
2181  DecodeStatus S = MCDisassembler::Success;
2182
2183  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2184  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2185  unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2186  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2187  Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2188  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2189
2190  // Writeback Operand
2191  switch (Inst.getOpcode()) {
2192    case ARM::VST1d8wb_fixed:
2193    case ARM::VST1d16wb_fixed:
2194    case ARM::VST1d32wb_fixed:
2195    case ARM::VST1d64wb_fixed:
2196    case ARM::VST1d8wb_register:
2197    case ARM::VST1d16wb_register:
2198    case ARM::VST1d32wb_register:
2199    case ARM::VST1d64wb_register:
2200    case ARM::VST1q8wb_fixed:
2201    case ARM::VST1q16wb_fixed:
2202    case ARM::VST1q32wb_fixed:
2203    case ARM::VST1q64wb_fixed:
2204    case ARM::VST1q8wb_register:
2205    case ARM::VST1q16wb_register:
2206    case ARM::VST1q32wb_register:
2207    case ARM::VST1q64wb_register:
2208    case ARM::VST1d8Twb_fixed:
2209    case ARM::VST1d16Twb_fixed:
2210    case ARM::VST1d32Twb_fixed:
2211    case ARM::VST1d64Twb_fixed:
2212    case ARM::VST1d8Twb_register:
2213    case ARM::VST1d16Twb_register:
2214    case ARM::VST1d32Twb_register:
2215    case ARM::VST1d64Twb_register:
2216    case ARM::VST1d8Qwb_fixed:
2217    case ARM::VST1d16Qwb_fixed:
2218    case ARM::VST1d32Qwb_fixed:
2219    case ARM::VST1d64Qwb_fixed:
2220    case ARM::VST1d8Qwb_register:
2221    case ARM::VST1d16Qwb_register:
2222    case ARM::VST1d32Qwb_register:
2223    case ARM::VST1d64Qwb_register:
2224    case ARM::VST2d8wb_fixed:
2225    case ARM::VST2d16wb_fixed:
2226    case ARM::VST2d32wb_fixed:
2227    case ARM::VST2d8wb_register:
2228    case ARM::VST2d16wb_register:
2229    case ARM::VST2d32wb_register:
2230    case ARM::VST2q8wb_fixed:
2231    case ARM::VST2q16wb_fixed:
2232    case ARM::VST2q32wb_fixed:
2233    case ARM::VST2q8wb_register:
2234    case ARM::VST2q16wb_register:
2235    case ARM::VST2q32wb_register:
2236    case ARM::VST2b8wb_fixed:
2237    case ARM::VST2b16wb_fixed:
2238    case ARM::VST2b32wb_fixed:
2239    case ARM::VST2b8wb_register:
2240    case ARM::VST2b16wb_register:
2241    case ARM::VST2b32wb_register:
2242    case ARM::VST3d8_UPD:
2243    case ARM::VST3d16_UPD:
2244    case ARM::VST3d32_UPD:
2245    case ARM::VST3q8_UPD:
2246    case ARM::VST3q16_UPD:
2247    case ARM::VST3q32_UPD:
2248    case ARM::VST4d8_UPD:
2249    case ARM::VST4d16_UPD:
2250    case ARM::VST4d32_UPD:
2251    case ARM::VST4q8_UPD:
2252    case ARM::VST4q16_UPD:
2253    case ARM::VST4q32_UPD:
2254      if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2255        return MCDisassembler::Fail;
2256      break;
2257    default:
2258      break;
2259  }
2260
2261  // AddrMode6 Base (register+alignment)
2262  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2263    return MCDisassembler::Fail;
2264
2265  // AddrMode6 Offset (register)
2266  switch (Inst.getOpcode()) {
2267    default:
2268      if (Rm == 0xD)
2269        Inst.addOperand(MCOperand::CreateReg(0));
2270      else if (Rm != 0xF) {
2271        if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2272          return MCDisassembler::Fail;
2273      }
2274      break;
2275    case ARM::VST1d8wb_fixed:
2276    case ARM::VST1d16wb_fixed:
2277    case ARM::VST1d32wb_fixed:
2278    case ARM::VST1d64wb_fixed:
2279    case ARM::VST1q8wb_fixed:
2280    case ARM::VST1q16wb_fixed:
2281    case ARM::VST1q32wb_fixed:
2282    case ARM::VST1q64wb_fixed:
2283      break;
2284  }
2285
2286
2287  // First input register
2288  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2289    return MCDisassembler::Fail;
2290
2291  // Second input register
2292  switch (Inst.getOpcode()) {
2293    case ARM::VST3d8:
2294    case ARM::VST3d16:
2295    case ARM::VST3d32:
2296    case ARM::VST3d8_UPD:
2297    case ARM::VST3d16_UPD:
2298    case ARM::VST3d32_UPD:
2299    case ARM::VST4d8:
2300    case ARM::VST4d16:
2301    case ARM::VST4d32:
2302    case ARM::VST4d8_UPD:
2303    case ARM::VST4d16_UPD:
2304    case ARM::VST4d32_UPD:
2305      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2306        return MCDisassembler::Fail;
2307      break;
2308    case ARM::VST3q8:
2309    case ARM::VST3q16:
2310    case ARM::VST3q32:
2311    case ARM::VST3q8_UPD:
2312    case ARM::VST3q16_UPD:
2313    case ARM::VST3q32_UPD:
2314    case ARM::VST4q8:
2315    case ARM::VST4q16:
2316    case ARM::VST4q32:
2317    case ARM::VST4q8_UPD:
2318    case ARM::VST4q16_UPD:
2319    case ARM::VST4q32_UPD:
2320      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2321        return MCDisassembler::Fail;
2322      break;
2323    default:
2324      break;
2325  }
2326
2327  // Third input register
2328  switch (Inst.getOpcode()) {
2329    case ARM::VST3d8:
2330    case ARM::VST3d16:
2331    case ARM::VST3d32:
2332    case ARM::VST3d8_UPD:
2333    case ARM::VST3d16_UPD:
2334    case ARM::VST3d32_UPD:
2335    case ARM::VST4d8:
2336    case ARM::VST4d16:
2337    case ARM::VST4d32:
2338    case ARM::VST4d8_UPD:
2339    case ARM::VST4d16_UPD:
2340    case ARM::VST4d32_UPD:
2341      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2342        return MCDisassembler::Fail;
2343      break;
2344    case ARM::VST3q8:
2345    case ARM::VST3q16:
2346    case ARM::VST3q32:
2347    case ARM::VST3q8_UPD:
2348    case ARM::VST3q16_UPD:
2349    case ARM::VST3q32_UPD:
2350    case ARM::VST4q8:
2351    case ARM::VST4q16:
2352    case ARM::VST4q32:
2353    case ARM::VST4q8_UPD:
2354    case ARM::VST4q16_UPD:
2355    case ARM::VST4q32_UPD:
2356      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2357        return MCDisassembler::Fail;
2358      break;
2359    default:
2360      break;
2361  }
2362
2363  // Fourth input register
2364  switch (Inst.getOpcode()) {
2365    case ARM::VST4d8:
2366    case ARM::VST4d16:
2367    case ARM::VST4d32:
2368    case ARM::VST4d8_UPD:
2369    case ARM::VST4d16_UPD:
2370    case ARM::VST4d32_UPD:
2371      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2372        return MCDisassembler::Fail;
2373      break;
2374    case ARM::VST4q8:
2375    case ARM::VST4q16:
2376    case ARM::VST4q32:
2377    case ARM::VST4q8_UPD:
2378    case ARM::VST4q16_UPD:
2379    case ARM::VST4q32_UPD:
2380      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2381        return MCDisassembler::Fail;
2382      break;
2383    default:
2384      break;
2385  }
2386
2387  return S;
2388}
2389
2390static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2391                                    uint64_t Address, const void *Decoder) {
2392  DecodeStatus S = MCDisassembler::Success;
2393
2394  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2395  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2396  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2397  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2398  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2399  unsigned size = fieldFromInstruction32(Insn, 6, 2);
2400
2401  align *= (1 << size);
2402
2403  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2404    return MCDisassembler::Fail;
2405  if (Rm != 0xF) {
2406    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2407      return MCDisassembler::Fail;
2408  }
2409
2410  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2411    return MCDisassembler::Fail;
2412  Inst.addOperand(MCOperand::CreateImm(align));
2413
2414  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2415  // variant encodes Rm == 0xf. Anything else is a register offset post-
2416  // increment and we need to add the register operand to the instruction.
2417  if (Rm != 0xD && Rm != 0xF &&
2418      !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2419    return MCDisassembler::Fail;
2420
2421  return S;
2422}
2423
2424static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2425                                    uint64_t Address, const void *Decoder) {
2426  DecodeStatus S = MCDisassembler::Success;
2427
2428  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2429  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2430  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2431  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2432  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2433  unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2434  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2435  align *= 2*size;
2436
2437  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2438    return MCDisassembler::Fail;
2439  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2440    return MCDisassembler::Fail;
2441  if (Rm != 0xF) {
2442    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2443      return MCDisassembler::Fail;
2444  }
2445
2446  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2447    return MCDisassembler::Fail;
2448  Inst.addOperand(MCOperand::CreateImm(align));
2449
2450  if (Rm == 0xD)
2451    Inst.addOperand(MCOperand::CreateReg(0));
2452  else if (Rm != 0xF) {
2453    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2454      return MCDisassembler::Fail;
2455  }
2456
2457  return S;
2458}
2459
2460static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2461                                    uint64_t Address, const void *Decoder) {
2462  DecodeStatus S = MCDisassembler::Success;
2463
2464  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2465  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2466  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2467  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2468  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2469
2470  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2471    return MCDisassembler::Fail;
2472  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2473    return MCDisassembler::Fail;
2474  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2475    return MCDisassembler::Fail;
2476  if (Rm != 0xF) {
2477    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2478      return MCDisassembler::Fail;
2479  }
2480
2481  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2482    return MCDisassembler::Fail;
2483  Inst.addOperand(MCOperand::CreateImm(0));
2484
2485  if (Rm == 0xD)
2486    Inst.addOperand(MCOperand::CreateReg(0));
2487  else if (Rm != 0xF) {
2488    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2489      return MCDisassembler::Fail;
2490  }
2491
2492  return S;
2493}
2494
2495static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2496                                    uint64_t Address, const void *Decoder) {
2497  DecodeStatus S = MCDisassembler::Success;
2498
2499  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2500  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2501  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2502  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2503  unsigned size = fieldFromInstruction32(Insn, 6, 2);
2504  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2505  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2506
2507  if (size == 0x3) {
2508    size = 4;
2509    align = 16;
2510  } else {
2511    if (size == 2) {
2512      size = 1 << size;
2513      align *= 8;
2514    } else {
2515      size = 1 << size;
2516      align *= 4*size;
2517    }
2518  }
2519
2520  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2521    return MCDisassembler::Fail;
2522  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2523    return MCDisassembler::Fail;
2524  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2525    return MCDisassembler::Fail;
2526  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2527    return MCDisassembler::Fail;
2528  if (Rm != 0xF) {
2529    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2530      return MCDisassembler::Fail;
2531  }
2532
2533  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2534    return MCDisassembler::Fail;
2535  Inst.addOperand(MCOperand::CreateImm(align));
2536
2537  if (Rm == 0xD)
2538    Inst.addOperand(MCOperand::CreateReg(0));
2539  else if (Rm != 0xF) {
2540    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2541      return MCDisassembler::Fail;
2542  }
2543
2544  return S;
2545}
2546
2547static DecodeStatus
2548DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2549                            uint64_t Address, const void *Decoder) {
2550  DecodeStatus S = MCDisassembler::Success;
2551
2552  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2553  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2554  unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2555  imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2556  imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2557  imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2558  imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2559  unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2560
2561  if (Q) {
2562    if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2563    return MCDisassembler::Fail;
2564  } else {
2565    if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2566    return MCDisassembler::Fail;
2567  }
2568
2569  Inst.addOperand(MCOperand::CreateImm(imm));
2570
2571  switch (Inst.getOpcode()) {
2572    case ARM::VORRiv4i16:
2573    case ARM::VORRiv2i32:
2574    case ARM::VBICiv4i16:
2575    case ARM::VBICiv2i32:
2576      if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2577        return MCDisassembler::Fail;
2578      break;
2579    case ARM::VORRiv8i16:
2580    case ARM::VORRiv4i32:
2581    case ARM::VBICiv8i16:
2582    case ARM::VBICiv4i32:
2583      if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2584        return MCDisassembler::Fail;
2585      break;
2586    default:
2587      break;
2588  }
2589
2590  return S;
2591}
2592
2593static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2594                                        uint64_t Address, const void *Decoder) {
2595  DecodeStatus S = MCDisassembler::Success;
2596
2597  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2598  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2599  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2600  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2601  unsigned size = fieldFromInstruction32(Insn, 18, 2);
2602
2603  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2604    return MCDisassembler::Fail;
2605  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2606    return MCDisassembler::Fail;
2607  Inst.addOperand(MCOperand::CreateImm(8 << size));
2608
2609  return S;
2610}
2611
2612static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2613                               uint64_t Address, const void *Decoder) {
2614  Inst.addOperand(MCOperand::CreateImm(8 - Val));
2615  return MCDisassembler::Success;
2616}
2617
2618static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2619                               uint64_t Address, const void *Decoder) {
2620  Inst.addOperand(MCOperand::CreateImm(16 - Val));
2621  return MCDisassembler::Success;
2622}
2623
2624static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2625                               uint64_t Address, const void *Decoder) {
2626  Inst.addOperand(MCOperand::CreateImm(32 - Val));
2627  return MCDisassembler::Success;
2628}
2629
2630static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2631                               uint64_t Address, const void *Decoder) {
2632  Inst.addOperand(MCOperand::CreateImm(64 - Val));
2633  return MCDisassembler::Success;
2634}
2635
2636static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2637                               uint64_t Address, const void *Decoder) {
2638  DecodeStatus S = MCDisassembler::Success;
2639
2640  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2641  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2642  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2643  Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2644  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2645  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2646  unsigned op = fieldFromInstruction32(Insn, 6, 1);
2647
2648  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2649    return MCDisassembler::Fail;
2650  if (op) {
2651    if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2652    return MCDisassembler::Fail; // Writeback
2653  }
2654
2655  if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2656    return MCDisassembler::Fail;
2657
2658  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2659    return MCDisassembler::Fail;
2660
2661  return S;
2662}
2663
2664static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2665                                     uint64_t Address, const void *Decoder) {
2666  DecodeStatus S = MCDisassembler::Success;
2667
2668  unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2669  unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2670
2671  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2672    return MCDisassembler::Fail;
2673
2674  switch(Inst.getOpcode()) {
2675    default:
2676      return MCDisassembler::Fail;
2677    case ARM::tADR:
2678      break; // tADR does not explicitly represent the PC as an operand.
2679    case ARM::tADDrSPi:
2680      Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2681      break;
2682  }
2683
2684  Inst.addOperand(MCOperand::CreateImm(imm));
2685  return S;
2686}
2687
2688static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2689                                 uint64_t Address, const void *Decoder) {
2690  Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2691  return MCDisassembler::Success;
2692}
2693
2694static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2695                                 uint64_t Address, const void *Decoder) {
2696  Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2697  return MCDisassembler::Success;
2698}
2699
2700static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2701                                 uint64_t Address, const void *Decoder) {
2702  Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2703  return MCDisassembler::Success;
2704}
2705
2706static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2707                                 uint64_t Address, const void *Decoder) {
2708  DecodeStatus S = MCDisassembler::Success;
2709
2710  unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2711  unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2712
2713  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2714    return MCDisassembler::Fail;
2715  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2716    return MCDisassembler::Fail;
2717
2718  return S;
2719}
2720
2721static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2722                                  uint64_t Address, const void *Decoder) {
2723  DecodeStatus S = MCDisassembler::Success;
2724
2725  unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2726  unsigned imm = fieldFromInstruction32(Val, 3, 5);
2727
2728  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2729    return MCDisassembler::Fail;
2730  Inst.addOperand(MCOperand::CreateImm(imm));
2731
2732  return S;
2733}
2734
2735static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2736                                  uint64_t Address, const void *Decoder) {
2737  unsigned imm = Val << 2;
2738
2739  Inst.addOperand(MCOperand::CreateImm(imm));
2740  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
2741
2742  return MCDisassembler::Success;
2743}
2744
2745static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2746                                  uint64_t Address, const void *Decoder) {
2747  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2748  Inst.addOperand(MCOperand::CreateImm(Val));
2749
2750  return MCDisassembler::Success;
2751}
2752
2753static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2754                                  uint64_t Address, const void *Decoder) {
2755  DecodeStatus S = MCDisassembler::Success;
2756
2757  unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2758  unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2759  unsigned imm = fieldFromInstruction32(Val, 0, 2);
2760
2761  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2762    return MCDisassembler::Fail;
2763  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2764    return MCDisassembler::Fail;
2765  Inst.addOperand(MCOperand::CreateImm(imm));
2766
2767  return S;
2768}
2769
2770static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2771                              uint64_t Address, const void *Decoder) {
2772  DecodeStatus S = MCDisassembler::Success;
2773
2774  switch (Inst.getOpcode()) {
2775    case ARM::t2PLDs:
2776    case ARM::t2PLDWs:
2777    case ARM::t2PLIs:
2778      break;
2779    default: {
2780      unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2781      if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
2782    return MCDisassembler::Fail;
2783    }
2784  }
2785
2786  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2787  if (Rn == 0xF) {
2788    switch (Inst.getOpcode()) {
2789      case ARM::t2LDRBs:
2790        Inst.setOpcode(ARM::t2LDRBpci);
2791        break;
2792      case ARM::t2LDRHs:
2793        Inst.setOpcode(ARM::t2LDRHpci);
2794        break;
2795      case ARM::t2LDRSHs:
2796        Inst.setOpcode(ARM::t2LDRSHpci);
2797        break;
2798      case ARM::t2LDRSBs:
2799        Inst.setOpcode(ARM::t2LDRSBpci);
2800        break;
2801      case ARM::t2PLDs:
2802        Inst.setOpcode(ARM::t2PLDi12);
2803        Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2804        break;
2805      default:
2806        return MCDisassembler::Fail;
2807    }
2808
2809    int imm = fieldFromInstruction32(Insn, 0, 12);
2810    if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2811    Inst.addOperand(MCOperand::CreateImm(imm));
2812
2813    return S;
2814  }
2815
2816  unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2817  addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2818  addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2819  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2820    return MCDisassembler::Fail;
2821
2822  return S;
2823}
2824
2825static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2826                           uint64_t Address, const void *Decoder) {
2827  int imm = Val & 0xFF;
2828  if (!(Val & 0x100)) imm *= -1;
2829  Inst.addOperand(MCOperand::CreateImm(imm << 2));
2830
2831  return MCDisassembler::Success;
2832}
2833
2834static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2835                                   uint64_t Address, const void *Decoder) {
2836  DecodeStatus S = MCDisassembler::Success;
2837
2838  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2839  unsigned imm = fieldFromInstruction32(Val, 0, 9);
2840
2841  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2842    return MCDisassembler::Fail;
2843  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2844    return MCDisassembler::Fail;
2845
2846  return S;
2847}
2848
2849static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2850                                   uint64_t Address, const void *Decoder) {
2851  DecodeStatus S = MCDisassembler::Success;
2852
2853  unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2854  unsigned imm = fieldFromInstruction32(Val, 0, 8);
2855
2856  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2857    return MCDisassembler::Fail;
2858
2859  Inst.addOperand(MCOperand::CreateImm(imm));
2860
2861  return S;
2862}
2863
2864static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2865                         uint64_t Address, const void *Decoder) {
2866  int imm = Val & 0xFF;
2867  if (Val == 0)
2868    imm = INT32_MIN;
2869  else if (!(Val & 0x100))
2870    imm *= -1;
2871  Inst.addOperand(MCOperand::CreateImm(imm));
2872
2873  return MCDisassembler::Success;
2874}
2875
2876
2877static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2878                                 uint64_t Address, const void *Decoder) {
2879  DecodeStatus S = MCDisassembler::Success;
2880
2881  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2882  unsigned imm = fieldFromInstruction32(Val, 0, 9);
2883
2884  // Some instructions always use an additive offset.
2885  switch (Inst.getOpcode()) {
2886    case ARM::t2LDRT:
2887    case ARM::t2LDRBT:
2888    case ARM::t2LDRHT:
2889    case ARM::t2LDRSBT:
2890    case ARM::t2LDRSHT:
2891    case ARM::t2STRT:
2892    case ARM::t2STRBT:
2893    case ARM::t2STRHT:
2894      imm |= 0x100;
2895      break;
2896    default:
2897      break;
2898  }
2899
2900  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2901    return MCDisassembler::Fail;
2902  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2903    return MCDisassembler::Fail;
2904
2905  return S;
2906}
2907
2908static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2909                                    uint64_t Address, const void *Decoder) {
2910  DecodeStatus S = MCDisassembler::Success;
2911
2912  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2913  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2914  unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2915  addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2916  addr |= Rn << 9;
2917  unsigned load = fieldFromInstruction32(Insn, 20, 1);
2918
2919  if (!load) {
2920    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2921      return MCDisassembler::Fail;
2922  }
2923
2924  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
2925    return MCDisassembler::Fail;
2926
2927  if (load) {
2928    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2929      return MCDisassembler::Fail;
2930  }
2931
2932  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2933    return MCDisassembler::Fail;
2934
2935  return S;
2936}
2937
2938static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2939                                  uint64_t Address, const void *Decoder) {
2940  DecodeStatus S = MCDisassembler::Success;
2941
2942  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2943  unsigned imm = fieldFromInstruction32(Val, 0, 12);
2944
2945  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2946    return MCDisassembler::Fail;
2947  Inst.addOperand(MCOperand::CreateImm(imm));
2948
2949  return S;
2950}
2951
2952
2953static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2954                                uint64_t Address, const void *Decoder) {
2955  unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2956
2957  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2958  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2959  Inst.addOperand(MCOperand::CreateImm(imm));
2960
2961  return MCDisassembler::Success;
2962}
2963
2964static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
2965                                uint64_t Address, const void *Decoder) {
2966  DecodeStatus S = MCDisassembler::Success;
2967
2968  if (Inst.getOpcode() == ARM::tADDrSP) {
2969    unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2970    Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2971
2972    if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2973    return MCDisassembler::Fail;
2974    if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2975    return MCDisassembler::Fail;
2976    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2977  } else if (Inst.getOpcode() == ARM::tADDspr) {
2978    unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2979
2980    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2981    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2982    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2983    return MCDisassembler::Fail;
2984  }
2985
2986  return S;
2987}
2988
2989static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
2990                           uint64_t Address, const void *Decoder) {
2991  unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2992  unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2993
2994  Inst.addOperand(MCOperand::CreateImm(imod));
2995  Inst.addOperand(MCOperand::CreateImm(flags));
2996
2997  return MCDisassembler::Success;
2998}
2999
3000static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
3001                             uint64_t Address, const void *Decoder) {
3002  DecodeStatus S = MCDisassembler::Success;
3003  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3004  unsigned add = fieldFromInstruction32(Insn, 4, 1);
3005
3006  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3007    return MCDisassembler::Fail;
3008  Inst.addOperand(MCOperand::CreateImm(add));
3009
3010  return S;
3011}
3012
3013static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
3014                                 uint64_t Address, const void *Decoder) {
3015  if (!tryAddingSymbolicOperand(Address,
3016                                (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3017                                true, 4, Inst, Decoder))
3018    Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3019  return MCDisassembler::Success;
3020}
3021
3022static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
3023                              uint64_t Address, const void *Decoder) {
3024  if (Val == 0xA || Val == 0xB)
3025    return MCDisassembler::Fail;
3026
3027  Inst.addOperand(MCOperand::CreateImm(Val));
3028  return MCDisassembler::Success;
3029}
3030
3031static DecodeStatus
3032DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3033                       uint64_t Address, const void *Decoder) {
3034  DecodeStatus S = MCDisassembler::Success;
3035
3036  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3037  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3038
3039  if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3040  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3041    return MCDisassembler::Fail;
3042  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3043    return MCDisassembler::Fail;
3044  return S;
3045}
3046
3047static DecodeStatus
3048DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3049                           uint64_t Address, const void *Decoder) {
3050  DecodeStatus S = MCDisassembler::Success;
3051
3052  unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3053  if (pred == 0xE || pred == 0xF) {
3054    unsigned opc = fieldFromInstruction32(Insn, 4, 28);
3055    switch (opc) {
3056      default:
3057        return MCDisassembler::Fail;
3058      case 0xf3bf8f4:
3059        Inst.setOpcode(ARM::t2DSB);
3060        break;
3061      case 0xf3bf8f5:
3062        Inst.setOpcode(ARM::t2DMB);
3063        break;
3064      case 0xf3bf8f6:
3065        Inst.setOpcode(ARM::t2ISB);
3066        break;
3067    }
3068
3069    unsigned imm = fieldFromInstruction32(Insn, 0, 4);
3070    return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3071  }
3072
3073  unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3074  brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3075  brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3076  brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3077  brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3078
3079  if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3080    return MCDisassembler::Fail;
3081  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3082    return MCDisassembler::Fail;
3083
3084  return S;
3085}
3086
3087// Decode a shifted immediate operand.  These basically consist
3088// of an 8-bit value, and a 4-bit directive that specifies either
3089// a splat operation or a rotation.
3090static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
3091                          uint64_t Address, const void *Decoder) {
3092  unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3093  if (ctrl == 0) {
3094    unsigned byte = fieldFromInstruction32(Val, 8, 2);
3095    unsigned imm = fieldFromInstruction32(Val, 0, 8);
3096    switch (byte) {
3097      case 0:
3098        Inst.addOperand(MCOperand::CreateImm(imm));
3099        break;
3100      case 1:
3101        Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3102        break;
3103      case 2:
3104        Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3105        break;
3106      case 3:
3107        Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3108                                             (imm << 8)  |  imm));
3109        break;
3110    }
3111  } else {
3112    unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3113    unsigned rot = fieldFromInstruction32(Val, 7, 5);
3114    unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3115    Inst.addOperand(MCOperand::CreateImm(imm));
3116  }
3117
3118  return MCDisassembler::Success;
3119}
3120
3121static DecodeStatus
3122DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3123                            uint64_t Address, const void *Decoder){
3124  Inst.addOperand(MCOperand::CreateImm(Val << 1));
3125  return MCDisassembler::Success;
3126}
3127
3128static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
3129                                       uint64_t Address, const void *Decoder){
3130  Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3131  return MCDisassembler::Success;
3132}
3133
3134static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
3135                                   uint64_t Address, const void *Decoder) {
3136  switch (Val) {
3137  default:
3138    return MCDisassembler::Fail;
3139  case 0xF: // SY
3140  case 0xE: // ST
3141  case 0xB: // ISH
3142  case 0xA: // ISHST
3143  case 0x7: // NSH
3144  case 0x6: // NSHST
3145  case 0x3: // OSH
3146  case 0x2: // OSHST
3147    break;
3148  }
3149
3150  Inst.addOperand(MCOperand::CreateImm(Val));
3151  return MCDisassembler::Success;
3152}
3153
3154static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
3155                          uint64_t Address, const void *Decoder) {
3156  if (!Val) return MCDisassembler::Fail;
3157  Inst.addOperand(MCOperand::CreateImm(Val));
3158  return MCDisassembler::Success;
3159}
3160
3161static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
3162                                        uint64_t Address, const void *Decoder) {
3163  DecodeStatus S = MCDisassembler::Success;
3164
3165  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3166  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3167  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3168
3169  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3170
3171  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3172    return MCDisassembler::Fail;
3173  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3174    return MCDisassembler::Fail;
3175  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3176    return MCDisassembler::Fail;
3177  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3178    return MCDisassembler::Fail;
3179
3180  return S;
3181}
3182
3183
3184static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
3185                                         uint64_t Address, const void *Decoder){
3186  DecodeStatus S = MCDisassembler::Success;
3187
3188  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3189  unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3190  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3191  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3192
3193  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3194    return MCDisassembler::Fail;
3195
3196  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3197  if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3198
3199  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3200    return MCDisassembler::Fail;
3201  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3202    return MCDisassembler::Fail;
3203  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3204    return MCDisassembler::Fail;
3205  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3206    return MCDisassembler::Fail;
3207
3208  return S;
3209}
3210
3211static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
3212                            uint64_t Address, const void *Decoder) {
3213  DecodeStatus S = MCDisassembler::Success;
3214
3215  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3216  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3217  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3218  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3219  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3220  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3221
3222  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3223
3224  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3225    return MCDisassembler::Fail;
3226  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3227    return MCDisassembler::Fail;
3228  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3229    return MCDisassembler::Fail;
3230  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3231    return MCDisassembler::Fail;
3232
3233  return S;
3234}
3235
3236static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
3237                            uint64_t Address, const void *Decoder) {
3238  DecodeStatus S = MCDisassembler::Success;
3239
3240  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3241  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3242  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3243  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3244  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3245  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3246  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3247
3248  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3249  if (Rm == 0xF) S = MCDisassembler::SoftFail;
3250
3251  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3252    return MCDisassembler::Fail;
3253  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3254    return MCDisassembler::Fail;
3255  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3256    return MCDisassembler::Fail;
3257  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3258    return MCDisassembler::Fail;
3259
3260  return S;
3261}
3262
3263
3264static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
3265                            uint64_t Address, const void *Decoder) {
3266  DecodeStatus S = MCDisassembler::Success;
3267
3268  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3269  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3270  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3271  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3272  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3273  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3274
3275  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3276
3277  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3278    return MCDisassembler::Fail;
3279  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3280    return MCDisassembler::Fail;
3281  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3282    return MCDisassembler::Fail;
3283  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3284    return MCDisassembler::Fail;
3285
3286  return S;
3287}
3288
3289static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
3290                            uint64_t Address, const void *Decoder) {
3291  DecodeStatus S = MCDisassembler::Success;
3292
3293  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3294  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3295  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3296  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3297  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3298  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3299
3300  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3301
3302  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3303    return MCDisassembler::Fail;
3304  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3305    return MCDisassembler::Fail;
3306  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3307    return MCDisassembler::Fail;
3308  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3309    return MCDisassembler::Fail;
3310
3311  return S;
3312}
3313
3314static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
3315                         uint64_t Address, const void *Decoder) {
3316  DecodeStatus S = MCDisassembler::Success;
3317
3318  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3319  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3320  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3321  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3322  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3323
3324  unsigned align = 0;
3325  unsigned index = 0;
3326  switch (size) {
3327    default:
3328      return MCDisassembler::Fail;
3329    case 0:
3330      if (fieldFromInstruction32(Insn, 4, 1))
3331        return MCDisassembler::Fail; // UNDEFINED
3332      index = fieldFromInstruction32(Insn, 5, 3);
3333      break;
3334    case 1:
3335      if (fieldFromInstruction32(Insn, 5, 1))
3336        return MCDisassembler::Fail; // UNDEFINED
3337      index = fieldFromInstruction32(Insn, 6, 2);
3338      if (fieldFromInstruction32(Insn, 4, 1))
3339        align = 2;
3340      break;
3341    case 2:
3342      if (fieldFromInstruction32(Insn, 6, 1))
3343        return MCDisassembler::Fail; // UNDEFINED
3344      index = fieldFromInstruction32(Insn, 7, 1);
3345      if (fieldFromInstruction32(Insn, 4, 2) != 0)
3346        align = 4;
3347  }
3348
3349  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3350    return MCDisassembler::Fail;
3351  if (Rm != 0xF) { // Writeback
3352    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3353      return MCDisassembler::Fail;
3354  }
3355  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3356    return MCDisassembler::Fail;
3357  Inst.addOperand(MCOperand::CreateImm(align));
3358  if (Rm != 0xF) {
3359    if (Rm != 0xD) {
3360      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3361        return MCDisassembler::Fail;
3362    } else
3363      Inst.addOperand(MCOperand::CreateReg(0));
3364  }
3365
3366  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3367    return MCDisassembler::Fail;
3368  Inst.addOperand(MCOperand::CreateImm(index));
3369
3370  return S;
3371}
3372
3373static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
3374                         uint64_t Address, const void *Decoder) {
3375  DecodeStatus S = MCDisassembler::Success;
3376
3377  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3378  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3379  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3380  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3381  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3382
3383  unsigned align = 0;
3384  unsigned index = 0;
3385  switch (size) {
3386    default:
3387      return MCDisassembler::Fail;
3388    case 0:
3389      if (fieldFromInstruction32(Insn, 4, 1))
3390        return MCDisassembler::Fail; // UNDEFINED
3391      index = fieldFromInstruction32(Insn, 5, 3);
3392      break;
3393    case 1:
3394      if (fieldFromInstruction32(Insn, 5, 1))
3395        return MCDisassembler::Fail; // UNDEFINED
3396      index = fieldFromInstruction32(Insn, 6, 2);
3397      if (fieldFromInstruction32(Insn, 4, 1))
3398        align = 2;
3399      break;
3400    case 2:
3401      if (fieldFromInstruction32(Insn, 6, 1))
3402        return MCDisassembler::Fail; // UNDEFINED
3403      index = fieldFromInstruction32(Insn, 7, 1);
3404      if (fieldFromInstruction32(Insn, 4, 2) != 0)
3405        align = 4;
3406  }
3407
3408  if (Rm != 0xF) { // Writeback
3409    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3410    return MCDisassembler::Fail;
3411  }
3412  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3413    return MCDisassembler::Fail;
3414  Inst.addOperand(MCOperand::CreateImm(align));
3415  if (Rm != 0xF) {
3416    if (Rm != 0xD) {
3417      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3418    return MCDisassembler::Fail;
3419    } else
3420      Inst.addOperand(MCOperand::CreateReg(0));
3421  }
3422
3423  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3424    return MCDisassembler::Fail;
3425  Inst.addOperand(MCOperand::CreateImm(index));
3426
3427  return S;
3428}
3429
3430
3431static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
3432                         uint64_t Address, const void *Decoder) {
3433  DecodeStatus S = MCDisassembler::Success;
3434
3435  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3436  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3437  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3438  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3439  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3440
3441  unsigned align = 0;
3442  unsigned index = 0;
3443  unsigned inc = 1;
3444  switch (size) {
3445    default:
3446      return MCDisassembler::Fail;
3447    case 0:
3448      index = fieldFromInstruction32(Insn, 5, 3);
3449      if (fieldFromInstruction32(Insn, 4, 1))
3450        align = 2;
3451      break;
3452    case 1:
3453      index = fieldFromInstruction32(Insn, 6, 2);
3454      if (fieldFromInstruction32(Insn, 4, 1))
3455        align = 4;
3456      if (fieldFromInstruction32(Insn, 5, 1))
3457        inc = 2;
3458      break;
3459    case 2:
3460      if (fieldFromInstruction32(Insn, 5, 1))
3461        return MCDisassembler::Fail; // UNDEFINED
3462      index = fieldFromInstruction32(Insn, 7, 1);
3463      if (fieldFromInstruction32(Insn, 4, 1) != 0)
3464        align = 8;
3465      if (fieldFromInstruction32(Insn, 6, 1))
3466        inc = 2;
3467      break;
3468  }
3469
3470  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3471    return MCDisassembler::Fail;
3472  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3473    return MCDisassembler::Fail;
3474  if (Rm != 0xF) { // Writeback
3475    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3476      return MCDisassembler::Fail;
3477  }
3478  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3479    return MCDisassembler::Fail;
3480  Inst.addOperand(MCOperand::CreateImm(align));
3481  if (Rm != 0xF) {
3482    if (Rm != 0xD) {
3483      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3484        return MCDisassembler::Fail;
3485    } else
3486      Inst.addOperand(MCOperand::CreateReg(0));
3487  }
3488
3489  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3490    return MCDisassembler::Fail;
3491  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3492    return MCDisassembler::Fail;
3493  Inst.addOperand(MCOperand::CreateImm(index));
3494
3495  return S;
3496}
3497
3498static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
3499                         uint64_t Address, const void *Decoder) {
3500  DecodeStatus S = MCDisassembler::Success;
3501
3502  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3503  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3504  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3505  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3506  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3507
3508  unsigned align = 0;
3509  unsigned index = 0;
3510  unsigned inc = 1;
3511  switch (size) {
3512    default:
3513      return MCDisassembler::Fail;
3514    case 0:
3515      index = fieldFromInstruction32(Insn, 5, 3);
3516      if (fieldFromInstruction32(Insn, 4, 1))
3517        align = 2;
3518      break;
3519    case 1:
3520      index = fieldFromInstruction32(Insn, 6, 2);
3521      if (fieldFromInstruction32(Insn, 4, 1))
3522        align = 4;
3523      if (fieldFromInstruction32(Insn, 5, 1))
3524        inc = 2;
3525      break;
3526    case 2:
3527      if (fieldFromInstruction32(Insn, 5, 1))
3528        return MCDisassembler::Fail; // UNDEFINED
3529      index = fieldFromInstruction32(Insn, 7, 1);
3530      if (fieldFromInstruction32(Insn, 4, 1) != 0)
3531        align = 8;
3532      if (fieldFromInstruction32(Insn, 6, 1))
3533        inc = 2;
3534      break;
3535  }
3536
3537  if (Rm != 0xF) { // Writeback
3538    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3539      return MCDisassembler::Fail;
3540  }
3541  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3542    return MCDisassembler::Fail;
3543  Inst.addOperand(MCOperand::CreateImm(align));
3544  if (Rm != 0xF) {
3545    if (Rm != 0xD) {
3546      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3547        return MCDisassembler::Fail;
3548    } else
3549      Inst.addOperand(MCOperand::CreateReg(0));
3550  }
3551
3552  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3553    return MCDisassembler::Fail;
3554  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3555    return MCDisassembler::Fail;
3556  Inst.addOperand(MCOperand::CreateImm(index));
3557
3558  return S;
3559}
3560
3561
3562static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3563                         uint64_t Address, const void *Decoder) {
3564  DecodeStatus S = MCDisassembler::Success;
3565
3566  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3567  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3568  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3569  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3570  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3571
3572  unsigned align = 0;
3573  unsigned index = 0;
3574  unsigned inc = 1;
3575  switch (size) {
3576    default:
3577      return MCDisassembler::Fail;
3578    case 0:
3579      if (fieldFromInstruction32(Insn, 4, 1))
3580        return MCDisassembler::Fail; // UNDEFINED
3581      index = fieldFromInstruction32(Insn, 5, 3);
3582      break;
3583    case 1:
3584      if (fieldFromInstruction32(Insn, 4, 1))
3585        return MCDisassembler::Fail; // UNDEFINED
3586      index = fieldFromInstruction32(Insn, 6, 2);
3587      if (fieldFromInstruction32(Insn, 5, 1))
3588        inc = 2;
3589      break;
3590    case 2:
3591      if (fieldFromInstruction32(Insn, 4, 2))
3592        return MCDisassembler::Fail; // UNDEFINED
3593      index = fieldFromInstruction32(Insn, 7, 1);
3594      if (fieldFromInstruction32(Insn, 6, 1))
3595        inc = 2;
3596      break;
3597  }
3598
3599  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3600    return MCDisassembler::Fail;
3601  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3602    return MCDisassembler::Fail;
3603  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3604    return MCDisassembler::Fail;
3605
3606  if (Rm != 0xF) { // Writeback
3607    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3608    return MCDisassembler::Fail;
3609  }
3610  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3611    return MCDisassembler::Fail;
3612  Inst.addOperand(MCOperand::CreateImm(align));
3613  if (Rm != 0xF) {
3614    if (Rm != 0xD) {
3615      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3616    return MCDisassembler::Fail;
3617    } else
3618      Inst.addOperand(MCOperand::CreateReg(0));
3619  }
3620
3621  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3622    return MCDisassembler::Fail;
3623  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3624    return MCDisassembler::Fail;
3625  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3626    return MCDisassembler::Fail;
3627  Inst.addOperand(MCOperand::CreateImm(index));
3628
3629  return S;
3630}
3631
3632static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3633                         uint64_t Address, const void *Decoder) {
3634  DecodeStatus S = MCDisassembler::Success;
3635
3636  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3637  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3638  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3639  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3640  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3641
3642  unsigned align = 0;
3643  unsigned index = 0;
3644  unsigned inc = 1;
3645  switch (size) {
3646    default:
3647      return MCDisassembler::Fail;
3648    case 0:
3649      if (fieldFromInstruction32(Insn, 4, 1))
3650        return MCDisassembler::Fail; // UNDEFINED
3651      index = fieldFromInstruction32(Insn, 5, 3);
3652      break;
3653    case 1:
3654      if (fieldFromInstruction32(Insn, 4, 1))
3655        return MCDisassembler::Fail; // UNDEFINED
3656      index = fieldFromInstruction32(Insn, 6, 2);
3657      if (fieldFromInstruction32(Insn, 5, 1))
3658        inc = 2;
3659      break;
3660    case 2:
3661      if (fieldFromInstruction32(Insn, 4, 2))
3662        return MCDisassembler::Fail; // UNDEFINED
3663      index = fieldFromInstruction32(Insn, 7, 1);
3664      if (fieldFromInstruction32(Insn, 6, 1))
3665        inc = 2;
3666      break;
3667  }
3668
3669  if (Rm != 0xF) { // Writeback
3670    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3671    return MCDisassembler::Fail;
3672  }
3673  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3674    return MCDisassembler::Fail;
3675  Inst.addOperand(MCOperand::CreateImm(align));
3676  if (Rm != 0xF) {
3677    if (Rm != 0xD) {
3678      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3679    return MCDisassembler::Fail;
3680    } else
3681      Inst.addOperand(MCOperand::CreateReg(0));
3682  }
3683
3684  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3685    return MCDisassembler::Fail;
3686  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3687    return MCDisassembler::Fail;
3688  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3689    return MCDisassembler::Fail;
3690  Inst.addOperand(MCOperand::CreateImm(index));
3691
3692  return S;
3693}
3694
3695
3696static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3697                         uint64_t Address, const void *Decoder) {
3698  DecodeStatus S = MCDisassembler::Success;
3699
3700  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3701  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3702  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3703  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3704  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3705
3706  unsigned align = 0;
3707  unsigned index = 0;
3708  unsigned inc = 1;
3709  switch (size) {
3710    default:
3711      return MCDisassembler::Fail;
3712    case 0:
3713      if (fieldFromInstruction32(Insn, 4, 1))
3714        align = 4;
3715      index = fieldFromInstruction32(Insn, 5, 3);
3716      break;
3717    case 1:
3718      if (fieldFromInstruction32(Insn, 4, 1))
3719        align = 8;
3720      index = fieldFromInstruction32(Insn, 6, 2);
3721      if (fieldFromInstruction32(Insn, 5, 1))
3722        inc = 2;
3723      break;
3724    case 2:
3725      if (fieldFromInstruction32(Insn, 4, 2))
3726        align = 4 << fieldFromInstruction32(Insn, 4, 2);
3727      index = fieldFromInstruction32(Insn, 7, 1);
3728      if (fieldFromInstruction32(Insn, 6, 1))
3729        inc = 2;
3730      break;
3731  }
3732
3733  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3734    return MCDisassembler::Fail;
3735  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3736    return MCDisassembler::Fail;
3737  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3738    return MCDisassembler::Fail;
3739  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3740    return MCDisassembler::Fail;
3741
3742  if (Rm != 0xF) { // Writeback
3743    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3744      return MCDisassembler::Fail;
3745  }
3746  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3747    return MCDisassembler::Fail;
3748  Inst.addOperand(MCOperand::CreateImm(align));
3749  if (Rm != 0xF) {
3750    if (Rm != 0xD) {
3751      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3752        return MCDisassembler::Fail;
3753    } else
3754      Inst.addOperand(MCOperand::CreateReg(0));
3755  }
3756
3757  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3758    return MCDisassembler::Fail;
3759  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3760    return MCDisassembler::Fail;
3761  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3762    return MCDisassembler::Fail;
3763  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3764    return MCDisassembler::Fail;
3765  Inst.addOperand(MCOperand::CreateImm(index));
3766
3767  return S;
3768}
3769
3770static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3771                         uint64_t Address, const void *Decoder) {
3772  DecodeStatus S = MCDisassembler::Success;
3773
3774  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3775  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3776  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3777  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3778  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3779
3780  unsigned align = 0;
3781  unsigned index = 0;
3782  unsigned inc = 1;
3783  switch (size) {
3784    default:
3785      return MCDisassembler::Fail;
3786    case 0:
3787      if (fieldFromInstruction32(Insn, 4, 1))
3788        align = 4;
3789      index = fieldFromInstruction32(Insn, 5, 3);
3790      break;
3791    case 1:
3792      if (fieldFromInstruction32(Insn, 4, 1))
3793        align = 8;
3794      index = fieldFromInstruction32(Insn, 6, 2);
3795      if (fieldFromInstruction32(Insn, 5, 1))
3796        inc = 2;
3797      break;
3798    case 2:
3799      if (fieldFromInstruction32(Insn, 4, 2))
3800        align = 4 << fieldFromInstruction32(Insn, 4, 2);
3801      index = fieldFromInstruction32(Insn, 7, 1);
3802      if (fieldFromInstruction32(Insn, 6, 1))
3803        inc = 2;
3804      break;
3805  }
3806
3807  if (Rm != 0xF) { // Writeback
3808    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3809    return MCDisassembler::Fail;
3810  }
3811  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3812    return MCDisassembler::Fail;
3813  Inst.addOperand(MCOperand::CreateImm(align));
3814  if (Rm != 0xF) {
3815    if (Rm != 0xD) {
3816      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3817    return MCDisassembler::Fail;
3818    } else
3819      Inst.addOperand(MCOperand::CreateReg(0));
3820  }
3821
3822  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3823    return MCDisassembler::Fail;
3824  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3825    return MCDisassembler::Fail;
3826  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3827    return MCDisassembler::Fail;
3828  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3829    return MCDisassembler::Fail;
3830  Inst.addOperand(MCOperand::CreateImm(index));
3831
3832  return S;
3833}
3834
3835static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3836                                  uint64_t Address, const void *Decoder) {
3837  DecodeStatus S = MCDisassembler::Success;
3838  unsigned Rt  = fieldFromInstruction32(Insn, 12, 4);
3839  unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3840  unsigned Rm  = fieldFromInstruction32(Insn,  0, 4);
3841  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3842  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3843
3844  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3845    S = MCDisassembler::SoftFail;
3846
3847  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
3848    return MCDisassembler::Fail;
3849  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3850    return MCDisassembler::Fail;
3851  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
3852    return MCDisassembler::Fail;
3853  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3854    return MCDisassembler::Fail;
3855  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3856    return MCDisassembler::Fail;
3857
3858  return S;
3859}
3860
3861static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
3862                                  uint64_t Address, const void *Decoder) {
3863  DecodeStatus S = MCDisassembler::Success;
3864  unsigned Rt  = fieldFromInstruction32(Insn, 12, 4);
3865  unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3866  unsigned Rm  = fieldFromInstruction32(Insn,  0, 4);
3867  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3868  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3869
3870  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3871    S = MCDisassembler::SoftFail;
3872
3873  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
3874    return MCDisassembler::Fail;
3875  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3876    return MCDisassembler::Fail;
3877  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
3878    return MCDisassembler::Fail;
3879  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3880    return MCDisassembler::Fail;
3881  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3882    return MCDisassembler::Fail;
3883
3884  return S;
3885}
3886
3887static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
3888                             uint64_t Address, const void *Decoder) {
3889  DecodeStatus S = MCDisassembler::Success;
3890  unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3891  // The InstPrinter needs to have the low bit of the predicate in
3892  // the mask operand to be able to print it properly.
3893  unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3894
3895  if (pred == 0xF) {
3896    pred = 0xE;
3897    S = MCDisassembler::SoftFail;
3898  }
3899
3900  if ((mask & 0xF) == 0) {
3901    // Preserve the high bit of the mask, which is the low bit of
3902    // the predicate.
3903    mask &= 0x10;
3904    mask |= 0x8;
3905    S = MCDisassembler::SoftFail;
3906  }
3907
3908  Inst.addOperand(MCOperand::CreateImm(pred));
3909  Inst.addOperand(MCOperand::CreateImm(mask));
3910  return S;
3911}
3912
3913static DecodeStatus
3914DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3915                           uint64_t Address, const void *Decoder) {
3916  DecodeStatus S = MCDisassembler::Success;
3917
3918  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3919  unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3920  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3921  unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3922  unsigned W = fieldFromInstruction32(Insn, 21, 1);
3923  unsigned U = fieldFromInstruction32(Insn, 23, 1);
3924  unsigned P = fieldFromInstruction32(Insn, 24, 1);
3925  bool writeback = (W == 1) | (P == 0);
3926
3927  addr |= (U << 8) | (Rn << 9);
3928
3929  if (writeback && (Rn == Rt || Rn == Rt2))
3930    Check(S, MCDisassembler::SoftFail);
3931  if (Rt == Rt2)
3932    Check(S, MCDisassembler::SoftFail);
3933
3934  // Rt
3935  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3936    return MCDisassembler::Fail;
3937  // Rt2
3938  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3939    return MCDisassembler::Fail;
3940  // Writeback operand
3941  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3942    return MCDisassembler::Fail;
3943  // addr
3944  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3945    return MCDisassembler::Fail;
3946
3947  return S;
3948}
3949
3950static DecodeStatus
3951DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3952                           uint64_t Address, const void *Decoder) {
3953  DecodeStatus S = MCDisassembler::Success;
3954
3955  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3956  unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3957  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3958  unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3959  unsigned W = fieldFromInstruction32(Insn, 21, 1);
3960  unsigned U = fieldFromInstruction32(Insn, 23, 1);
3961  unsigned P = fieldFromInstruction32(Insn, 24, 1);
3962  bool writeback = (W == 1) | (P == 0);
3963
3964  addr |= (U << 8) | (Rn << 9);
3965
3966  if (writeback && (Rn == Rt || Rn == Rt2))
3967    Check(S, MCDisassembler::SoftFail);
3968
3969  // Writeback operand
3970  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3971    return MCDisassembler::Fail;
3972  // Rt
3973  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3974    return MCDisassembler::Fail;
3975  // Rt2
3976  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3977    return MCDisassembler::Fail;
3978  // addr
3979  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3980    return MCDisassembler::Fail;
3981
3982  return S;
3983}
3984
3985static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
3986                                uint64_t Address, const void *Decoder) {
3987  unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
3988  unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
3989  if (sign1 != sign2) return MCDisassembler::Fail;
3990
3991  unsigned Val = fieldFromInstruction32(Insn, 0, 8);
3992  Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
3993  Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
3994  Val |= sign1 << 12;
3995  Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
3996
3997  return MCDisassembler::Success;
3998}
3999
4000static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4001                                              uint64_t Address,
4002                                              const void *Decoder) {
4003  DecodeStatus S = MCDisassembler::Success;
4004
4005  // Shift of "asr #32" is not allowed in Thumb2 mode.
4006  if (Val == 0x20) S = MCDisassembler::SoftFail;
4007  Inst.addOperand(MCOperand::CreateImm(Val));
4008  return S;
4009}
4010
4011static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
4012                               uint64_t Address, const void *Decoder) {
4013  unsigned Rt   = fieldFromInstruction32(Insn, 12, 4);
4014  unsigned Rt2  = fieldFromInstruction32(Insn, 0,  4);
4015  unsigned Rn   = fieldFromInstruction32(Insn, 16, 4);
4016  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4017
4018  if (pred == 0xF)
4019    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4020
4021  DecodeStatus S = MCDisassembler::Success;
4022  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4023    return MCDisassembler::Fail;
4024  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4025    return MCDisassembler::Fail;
4026  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4027    return MCDisassembler::Fail;
4028  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4029    return MCDisassembler::Fail;
4030
4031  return S;
4032}
4033
4034static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
4035                                uint64_t Address, const void *Decoder) {
4036  unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4037  Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4038  unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4039  Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4040  unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4041  unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4042
4043  DecodeStatus S = MCDisassembler::Success;
4044
4045  // VMOVv2f32 is ambiguous with these decodings.
4046  if (!(imm & 0x38) && cmode == 0xF) {
4047    Inst.setOpcode(ARM::VMOVv2f32);
4048    return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4049  }
4050
4051  if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4052
4053  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4054    return MCDisassembler::Fail;
4055  if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4056    return MCDisassembler::Fail;
4057  Inst.addOperand(MCOperand::CreateImm(64 - imm));
4058
4059  return S;
4060}
4061
4062static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
4063                                uint64_t Address, const void *Decoder) {
4064  unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4065  Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4066  unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4067  Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4068  unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4069  unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4070
4071  DecodeStatus S = MCDisassembler::Success;
4072
4073  // VMOVv4f32 is ambiguous with these decodings.
4074  if (!(imm & 0x38) && cmode == 0xF) {
4075    Inst.setOpcode(ARM::VMOVv4f32);
4076    return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4077  }
4078
4079  if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4080
4081  if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4082    return MCDisassembler::Fail;
4083  if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4084    return MCDisassembler::Fail;
4085  Inst.addOperand(MCOperand::CreateImm(64 - imm));
4086
4087  return S;
4088}
4089