ARMDisassembler.cpp revision c3384c93c0e4c50da4ad093f08997507f9281c75
1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "ARM.h" 13#include "ARMSubtarget.h" 14#include "MCTargetDesc/ARMAddressingModes.h" 15#include "MCTargetDesc/ARMMCExpr.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "llvm/MC/EDInstInfo.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCInstrDesc.h" 20#include "llvm/MC/MCExpr.h" 21#include "llvm/MC/MCContext.h" 22#include "llvm/MC/MCDisassembler.h" 23#include "llvm/Support/Debug.h" 24#include "llvm/Support/MemoryObject.h" 25#include "llvm/Support/ErrorHandling.h" 26#include "llvm/Support/TargetRegistry.h" 27#include "llvm/Support/raw_ostream.h" 28 29using namespace llvm; 30 31typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33namespace { 34/// ARMDisassembler - ARM disassembler for all ARM platforms. 35class ARMDisassembler : public MCDisassembler { 36public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 const EDInstInfo *getEDInfo() const; 56private: 57}; 58 59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60class ThumbDisassembler : public MCDisassembler { 61public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 const EDInstInfo *getEDInfo() const; 81private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85}; 86} 87 88static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 llvm_unreachable("Invalid DecodeStatus!"); 101} 102 103 104// Forward declare these because the autogenerated code will reference them. 105// Definitions are further down. 106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 130 uint64_t Address, const void *Decoder); 131static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst, 132 unsigned RegNo, uint64_t Address, 133 const void *Decoder); 134 135static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 142 uint64_t Address, const void *Decoder); 143static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 144 uint64_t Address, const void *Decoder); 145static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 146 uint64_t Address, const void *Decoder); 147 148static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 153 unsigned Insn, 154 uint64_t Address, 155 const void *Decoder); 156static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 159 uint64_t Address, const void *Decoder); 160static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164 165static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 166 unsigned Insn, 167 uint64_t Adddress, 168 const void *Decoder); 169static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 170 uint64_t Address, const void *Decoder); 171static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 172 uint64_t Address, const void *Decoder); 173static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 174 uint64_t Address, const void *Decoder); 175static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 176 uint64_t Address, const void *Decoder); 177static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 178 uint64_t Address, const void *Decoder); 179static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 186 uint64_t Address, const void *Decoder); 187static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 202 uint64_t Address, const void *Decoder); 203static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 204 uint64_t Address, const void *Decoder); 205static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 208 uint64_t Address, const void *Decoder); 209static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 210 uint64_t Address, const void *Decoder); 211static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 212 uint64_t Address, const void *Decoder); 213static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 248 uint64_t Address, const void *Decoder); 249static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 250 uint64_t Address, const void *Decoder); 251static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 252 uint64_t Address, const void *Decoder); 253static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 256 uint64_t Address, const void *Decoder); 257static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 258 uint64_t Address, const void *Decoder); 259static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 260 uint64_t Address, const void *Decoder); 261 262 263static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 264 uint64_t Address, const void *Decoder); 265static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 272 uint64_t Address, const void *Decoder); 273static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 274 uint64_t Address, const void *Decoder); 275static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 276 uint64_t Address, const void *Decoder); 277static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 278 uint64_t Address, const void *Decoder); 279static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 286 uint64_t Address, const void *Decoder); 287static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 288 uint64_t Address, const void *Decoder); 289static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 292 uint64_t Address, const void *Decoder); 293static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 294 uint64_t Address, const void *Decoder); 295static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 296 uint64_t Address, const void *Decoder); 297static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 298 uint64_t Address, const void *Decoder); 299static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 310 uint64_t Address, const void *Decoder); 311static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 316 uint64_t Address, const void *Decoder); 317static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 318 uint64_t Address, const void *Decoder); 319static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 326 327 328#include "ARMGenDisassemblerTables.inc" 329#include "ARMGenInstrInfo.inc" 330#include "ARMGenEDInfo.inc" 331 332static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 333 return new ARMDisassembler(STI); 334} 335 336static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 337 return new ThumbDisassembler(STI); 338} 339 340const EDInstInfo *ARMDisassembler::getEDInfo() const { 341 return instInfoARM; 342} 343 344const EDInstInfo *ThumbDisassembler::getEDInfo() const { 345 return instInfoARM; 346} 347 348DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 349 const MemoryObject &Region, 350 uint64_t Address, 351 raw_ostream &os, 352 raw_ostream &cs) const { 353 CommentStream = &cs; 354 355 uint8_t bytes[4]; 356 357 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 358 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 359 360 // We want to read exactly 4 bytes of data. 361 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 362 Size = 0; 363 return MCDisassembler::Fail; 364 } 365 366 // Encoded as a small-endian 32-bit word in the stream. 367 uint32_t insn = (bytes[3] << 24) | 368 (bytes[2] << 16) | 369 (bytes[1] << 8) | 370 (bytes[0] << 0); 371 372 // Calling the auto-generated decoder function. 373 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 374 if (result != MCDisassembler::Fail) { 375 Size = 4; 376 return result; 377 } 378 379 // VFP and NEON instructions, similarly, are shared between ARM 380 // and Thumb modes. 381 MI.clear(); 382 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 383 if (result != MCDisassembler::Fail) { 384 Size = 4; 385 return result; 386 } 387 388 MI.clear(); 389 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 390 if (result != MCDisassembler::Fail) { 391 Size = 4; 392 // Add a fake predicate operand, because we share these instruction 393 // definitions with Thumb2 where these instructions are predicable. 394 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 395 return MCDisassembler::Fail; 396 return result; 397 } 398 399 MI.clear(); 400 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 401 if (result != MCDisassembler::Fail) { 402 Size = 4; 403 // Add a fake predicate operand, because we share these instruction 404 // definitions with Thumb2 where these instructions are predicable. 405 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 406 return MCDisassembler::Fail; 407 return result; 408 } 409 410 MI.clear(); 411 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 412 if (result != MCDisassembler::Fail) { 413 Size = 4; 414 // Add a fake predicate operand, because we share these instruction 415 // definitions with Thumb2 where these instructions are predicable. 416 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 417 return MCDisassembler::Fail; 418 return result; 419 } 420 421 MI.clear(); 422 423 Size = 0; 424 return MCDisassembler::Fail; 425} 426 427namespace llvm { 428extern const MCInstrDesc ARMInsts[]; 429} 430 431/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 432/// immediate Value in the MCInst. The immediate Value has had any PC 433/// adjustment made by the caller. If the instruction is a branch instruction 434/// then isBranch is true, else false. If the getOpInfo() function was set as 435/// part of the setupForSymbolicDisassembly() call then that function is called 436/// to get any symbolic information at the Address for this instruction. If 437/// that returns non-zero then the symbolic information it returns is used to 438/// create an MCExpr and that is added as an operand to the MCInst. If 439/// getOpInfo() returns zero and isBranch is true then a symbol look up for 440/// Value is done and if a symbol is found an MCExpr is created with that, else 441/// an MCExpr with Value is created. This function returns true if it adds an 442/// operand to the MCInst and false otherwise. 443static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 444 bool isBranch, uint64_t InstSize, 445 MCInst &MI, const void *Decoder) { 446 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 447 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 448 struct LLVMOpInfo1 SymbolicOp; 449 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 450 SymbolicOp.Value = Value; 451 void *DisInfo = Dis->getDisInfoBlock(); 452 453 if (!getOpInfo || 454 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 455 // Clear SymbolicOp.Value from above and also all other fields. 456 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 457 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 458 if (!SymbolLookUp) 459 return false; 460 uint64_t ReferenceType; 461 if (isBranch) 462 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 463 else 464 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 465 const char *ReferenceName; 466 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 467 &ReferenceName); 468 if (Name) { 469 SymbolicOp.AddSymbol.Name = Name; 470 SymbolicOp.AddSymbol.Present = true; 471 } 472 // For branches always create an MCExpr so it gets printed as hex address. 473 else if (isBranch) { 474 SymbolicOp.Value = Value; 475 } 476 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 477 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 478 if (!Name && !isBranch) 479 return false; 480 } 481 482 MCContext *Ctx = Dis->getMCContext(); 483 const MCExpr *Add = NULL; 484 if (SymbolicOp.AddSymbol.Present) { 485 if (SymbolicOp.AddSymbol.Name) { 486 StringRef Name(SymbolicOp.AddSymbol.Name); 487 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 488 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 489 } else { 490 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 491 } 492 } 493 494 const MCExpr *Sub = NULL; 495 if (SymbolicOp.SubtractSymbol.Present) { 496 if (SymbolicOp.SubtractSymbol.Name) { 497 StringRef Name(SymbolicOp.SubtractSymbol.Name); 498 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 499 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 500 } else { 501 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 502 } 503 } 504 505 const MCExpr *Off = NULL; 506 if (SymbolicOp.Value != 0) 507 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 508 509 const MCExpr *Expr; 510 if (Sub) { 511 const MCExpr *LHS; 512 if (Add) 513 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 514 else 515 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 516 if (Off != 0) 517 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 518 else 519 Expr = LHS; 520 } else if (Add) { 521 if (Off != 0) 522 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 523 else 524 Expr = Add; 525 } else { 526 if (Off != 0) 527 Expr = Off; 528 else 529 Expr = MCConstantExpr::Create(0, *Ctx); 530 } 531 532 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 533 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 534 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 535 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 536 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 537 MI.addOperand(MCOperand::CreateExpr(Expr)); 538 else 539 llvm_unreachable("bad SymbolicOp.VariantKind"); 540 541 return true; 542} 543 544/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 545/// referenced by a load instruction with the base register that is the Pc. 546/// These can often be values in a literal pool near the Address of the 547/// instruction. The Address of the instruction and its immediate Value are 548/// used as a possible literal pool entry. The SymbolLookUp call back will 549/// return the name of a symbol referenced by the the literal pool's entry if 550/// the referenced address is that of a symbol. Or it will return a pointer to 551/// a literal 'C' string if the referenced address of the literal pool's entry 552/// is an address into a section with 'C' string literals. 553static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 554 const void *Decoder) { 555 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 556 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 557 if (SymbolLookUp) { 558 void *DisInfo = Dis->getDisInfoBlock(); 559 uint64_t ReferenceType; 560 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 561 const char *ReferenceName; 562 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 563 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 564 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 565 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 566 } 567} 568 569// Thumb1 instructions don't have explicit S bits. Rather, they 570// implicitly set CPSR. Since it's not represented in the encoding, the 571// auto-generated decoder won't inject the CPSR operand. We need to fix 572// that as a post-pass. 573static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 576 MCInst::iterator I = MI.begin(); 577 for (unsigned i = 0; i < NumOps; ++i, ++I) { 578 if (I == MI.end()) break; 579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 580 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 581 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 582 return; 583 } 584 } 585 586 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 587} 588 589// Most Thumb instructions don't have explicit predicates in the 590// encoding, but rather get their predicates from IT context. We need 591// to fix up the predicate operands using this context information as a 592// post-pass. 593MCDisassembler::DecodeStatus 594ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 595 MCDisassembler::DecodeStatus S = Success; 596 597 // A few instructions actually have predicates encoded in them. Don't 598 // try to overwrite it if we're seeing one of those. 599 switch (MI.getOpcode()) { 600 case ARM::tBcc: 601 case ARM::t2Bcc: 602 case ARM::tCBZ: 603 case ARM::tCBNZ: 604 case ARM::tCPS: 605 case ARM::t2CPS3p: 606 case ARM::t2CPS2p: 607 case ARM::t2CPS1p: 608 case ARM::tMOVSr: 609 case ARM::tSETEND: 610 // Some instructions (mostly conditional branches) are not 611 // allowed in IT blocks. 612 if (!ITBlock.empty()) 613 S = SoftFail; 614 else 615 return Success; 616 break; 617 case ARM::tB: 618 case ARM::t2B: 619 case ARM::t2TBB: 620 case ARM::t2TBH: 621 // Some instructions (mostly unconditional branches) can 622 // only appears at the end of, or outside of, an IT. 623 if (ITBlock.size() > 1) 624 S = SoftFail; 625 break; 626 default: 627 break; 628 } 629 630 // If we're in an IT block, base the predicate on that. Otherwise, 631 // assume a predicate of AL. 632 unsigned CC; 633 if (!ITBlock.empty()) { 634 CC = ITBlock.back(); 635 if (CC == 0xF) 636 CC = ARMCC::AL; 637 ITBlock.pop_back(); 638 } else 639 CC = ARMCC::AL; 640 641 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 642 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 643 MCInst::iterator I = MI.begin(); 644 for (unsigned i = 0; i < NumOps; ++i, ++I) { 645 if (I == MI.end()) break; 646 if (OpInfo[i].isPredicate()) { 647 I = MI.insert(I, MCOperand::CreateImm(CC)); 648 ++I; 649 if (CC == ARMCC::AL) 650 MI.insert(I, MCOperand::CreateReg(0)); 651 else 652 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 653 return S; 654 } 655 } 656 657 I = MI.insert(I, MCOperand::CreateImm(CC)); 658 ++I; 659 if (CC == ARMCC::AL) 660 MI.insert(I, MCOperand::CreateReg(0)); 661 else 662 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 663 664 return S; 665} 666 667// Thumb VFP instructions are a special case. Because we share their 668// encodings between ARM and Thumb modes, and they are predicable in ARM 669// mode, the auto-generated decoder will give them an (incorrect) 670// predicate operand. We need to rewrite these operands based on the IT 671// context as a post-pass. 672void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 673 unsigned CC; 674 if (!ITBlock.empty()) { 675 CC = ITBlock.back(); 676 ITBlock.pop_back(); 677 } else 678 CC = ARMCC::AL; 679 680 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 681 MCInst::iterator I = MI.begin(); 682 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 683 for (unsigned i = 0; i < NumOps; ++i, ++I) { 684 if (OpInfo[i].isPredicate() ) { 685 I->setImm(CC); 686 ++I; 687 if (CC == ARMCC::AL) 688 I->setReg(0); 689 else 690 I->setReg(ARM::CPSR); 691 return; 692 } 693 } 694} 695 696DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 697 const MemoryObject &Region, 698 uint64_t Address, 699 raw_ostream &os, 700 raw_ostream &cs) const { 701 CommentStream = &cs; 702 703 uint8_t bytes[4]; 704 705 assert((STI.getFeatureBits() & ARM::ModeThumb) && 706 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 707 708 // We want to read exactly 2 bytes of data. 709 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 710 Size = 0; 711 return MCDisassembler::Fail; 712 } 713 714 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 715 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 716 if (result != MCDisassembler::Fail) { 717 Size = 2; 718 Check(result, AddThumbPredicate(MI)); 719 return result; 720 } 721 722 MI.clear(); 723 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 724 if (result) { 725 Size = 2; 726 bool InITBlock = !ITBlock.empty(); 727 Check(result, AddThumbPredicate(MI)); 728 AddThumb1SBit(MI, InITBlock); 729 return result; 730 } 731 732 MI.clear(); 733 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 734 if (result != MCDisassembler::Fail) { 735 Size = 2; 736 737 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 738 // the Thumb predicate. 739 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 740 result = MCDisassembler::SoftFail; 741 742 Check(result, AddThumbPredicate(MI)); 743 744 // If we find an IT instruction, we need to parse its condition 745 // code and mask operands so that we can apply them correctly 746 // to the subsequent instructions. 747 if (MI.getOpcode() == ARM::t2IT) { 748 749 // (3 - the number of trailing zeros) is the number of then / else. 750 unsigned firstcond = MI.getOperand(0).getImm(); 751 unsigned Mask = MI.getOperand(1).getImm(); 752 unsigned CondBit0 = Mask >> 4 & 1; 753 unsigned NumTZ = CountTrailingZeros_32(Mask); 754 assert(NumTZ <= 3 && "Invalid IT mask!"); 755 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 756 bool T = ((Mask >> Pos) & 1) == CondBit0; 757 if (T) 758 ITBlock.insert(ITBlock.begin(), firstcond); 759 else 760 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 761 } 762 763 ITBlock.push_back(firstcond); 764 } 765 766 return result; 767 } 768 769 // We want to read exactly 4 bytes of data. 770 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 771 Size = 0; 772 return MCDisassembler::Fail; 773 } 774 775 uint32_t insn32 = (bytes[3] << 8) | 776 (bytes[2] << 0) | 777 (bytes[1] << 24) | 778 (bytes[0] << 16); 779 MI.clear(); 780 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 781 if (result != MCDisassembler::Fail) { 782 Size = 4; 783 bool InITBlock = ITBlock.size(); 784 Check(result, AddThumbPredicate(MI)); 785 AddThumb1SBit(MI, InITBlock); 786 return result; 787 } 788 789 MI.clear(); 790 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 791 if (result != MCDisassembler::Fail) { 792 Size = 4; 793 Check(result, AddThumbPredicate(MI)); 794 return result; 795 } 796 797 MI.clear(); 798 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 799 if (result != MCDisassembler::Fail) { 800 Size = 4; 801 UpdateThumbVFPPredicate(MI); 802 return result; 803 } 804 805 MI.clear(); 806 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 807 if (result != MCDisassembler::Fail) { 808 Size = 4; 809 Check(result, AddThumbPredicate(MI)); 810 return result; 811 } 812 813 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 814 MI.clear(); 815 uint32_t NEONLdStInsn = insn32; 816 NEONLdStInsn &= 0xF0FFFFFF; 817 NEONLdStInsn |= 0x04000000; 818 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 819 if (result != MCDisassembler::Fail) { 820 Size = 4; 821 Check(result, AddThumbPredicate(MI)); 822 return result; 823 } 824 } 825 826 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 827 MI.clear(); 828 uint32_t NEONDataInsn = insn32; 829 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 830 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 831 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 832 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 833 if (result != MCDisassembler::Fail) { 834 Size = 4; 835 Check(result, AddThumbPredicate(MI)); 836 return result; 837 } 838 } 839 840 Size = 0; 841 return MCDisassembler::Fail; 842} 843 844 845extern "C" void LLVMInitializeARMDisassembler() { 846 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 847 createARMDisassembler); 848 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 849 createThumbDisassembler); 850} 851 852static const unsigned GPRDecoderTable[] = { 853 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 854 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 855 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 856 ARM::R12, ARM::SP, ARM::LR, ARM::PC 857}; 858 859static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 860 uint64_t Address, const void *Decoder) { 861 if (RegNo > 15) 862 return MCDisassembler::Fail; 863 864 unsigned Register = GPRDecoderTable[RegNo]; 865 Inst.addOperand(MCOperand::CreateReg(Register)); 866 return MCDisassembler::Success; 867} 868 869static DecodeStatus 870DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 871 uint64_t Address, const void *Decoder) { 872 if (RegNo == 15) return MCDisassembler::Fail; 873 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 874} 875 876static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 877 uint64_t Address, const void *Decoder) { 878 if (RegNo > 7) 879 return MCDisassembler::Fail; 880 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 881} 882 883static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 884 uint64_t Address, const void *Decoder) { 885 unsigned Register = 0; 886 switch (RegNo) { 887 case 0: 888 Register = ARM::R0; 889 break; 890 case 1: 891 Register = ARM::R1; 892 break; 893 case 2: 894 Register = ARM::R2; 895 break; 896 case 3: 897 Register = ARM::R3; 898 break; 899 case 9: 900 Register = ARM::R9; 901 break; 902 case 12: 903 Register = ARM::R12; 904 break; 905 default: 906 return MCDisassembler::Fail; 907 } 908 909 Inst.addOperand(MCOperand::CreateReg(Register)); 910 return MCDisassembler::Success; 911} 912 913static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 914 uint64_t Address, const void *Decoder) { 915 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 916 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 917} 918 919static const unsigned SPRDecoderTable[] = { 920 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 921 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 922 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 923 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 924 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 925 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 926 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 927 ARM::S28, ARM::S29, ARM::S30, ARM::S31 928}; 929 930static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 931 uint64_t Address, const void *Decoder) { 932 if (RegNo > 31) 933 return MCDisassembler::Fail; 934 935 unsigned Register = SPRDecoderTable[RegNo]; 936 Inst.addOperand(MCOperand::CreateReg(Register)); 937 return MCDisassembler::Success; 938} 939 940static const unsigned DPRDecoderTable[] = { 941 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 942 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 943 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 944 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 945 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 946 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 947 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 948 ARM::D28, ARM::D29, ARM::D30, ARM::D31 949}; 950 951static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 952 uint64_t Address, const void *Decoder) { 953 if (RegNo > 31) 954 return MCDisassembler::Fail; 955 956 unsigned Register = DPRDecoderTable[RegNo]; 957 Inst.addOperand(MCOperand::CreateReg(Register)); 958 return MCDisassembler::Success; 959} 960 961static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 962 uint64_t Address, const void *Decoder) { 963 if (RegNo > 7) 964 return MCDisassembler::Fail; 965 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 966} 967 968static DecodeStatus 969DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 970 uint64_t Address, const void *Decoder) { 971 if (RegNo > 15) 972 return MCDisassembler::Fail; 973 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 974} 975 976static const unsigned QPRDecoderTable[] = { 977 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 978 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 979 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 980 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 981}; 982 983 984static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 985 uint64_t Address, const void *Decoder) { 986 if (RegNo > 31) 987 return MCDisassembler::Fail; 988 RegNo >>= 1; 989 990 unsigned Register = QPRDecoderTable[RegNo]; 991 Inst.addOperand(MCOperand::CreateReg(Register)); 992 return MCDisassembler::Success; 993} 994 995static const unsigned DPairDecoderTable[] = { 996 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 997 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 998 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 999 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1000 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1001 ARM::Q15 1002}; 1003 1004static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 1005 uint64_t Address, const void *Decoder) { 1006 if (RegNo > 30) 1007 return MCDisassembler::Fail; 1008 1009 unsigned Register = DPairDecoderTable[RegNo]; 1010 Inst.addOperand(MCOperand::CreateReg(Register)); 1011 return MCDisassembler::Success; 1012} 1013 1014static const unsigned DPairSpacedDecoderTable[] = { 1015 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1016 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1017 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1018 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1019 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1020 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1021 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1022 ARM::D28_D30, ARM::D29_D31 1023}; 1024 1025static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst, 1026 unsigned RegNo, 1027 uint64_t Address, 1028 const void *Decoder) { 1029 if (RegNo > 29) 1030 return MCDisassembler::Fail; 1031 1032 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1033 Inst.addOperand(MCOperand::CreateReg(Register)); 1034 return MCDisassembler::Success; 1035} 1036 1037static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 1038 uint64_t Address, const void *Decoder) { 1039 if (Val == 0xF) return MCDisassembler::Fail; 1040 // AL predicate is not allowed on Thumb1 branches. 1041 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1042 return MCDisassembler::Fail; 1043 Inst.addOperand(MCOperand::CreateImm(Val)); 1044 if (Val == ARMCC::AL) { 1045 Inst.addOperand(MCOperand::CreateReg(0)); 1046 } else 1047 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1048 return MCDisassembler::Success; 1049} 1050 1051static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1052 uint64_t Address, const void *Decoder) { 1053 if (Val) 1054 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1055 else 1056 Inst.addOperand(MCOperand::CreateReg(0)); 1057 return MCDisassembler::Success; 1058} 1059 1060static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1061 uint64_t Address, const void *Decoder) { 1062 uint32_t imm = Val & 0xFF; 1063 uint32_t rot = (Val & 0xF00) >> 7; 1064 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1065 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1066 return MCDisassembler::Success; 1067} 1068 1069static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1070 uint64_t Address, const void *Decoder) { 1071 DecodeStatus S = MCDisassembler::Success; 1072 1073 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1074 unsigned type = fieldFromInstruction32(Val, 5, 2); 1075 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1076 1077 // Register-immediate 1078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1079 return MCDisassembler::Fail; 1080 1081 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1082 switch (type) { 1083 case 0: 1084 Shift = ARM_AM::lsl; 1085 break; 1086 case 1: 1087 Shift = ARM_AM::lsr; 1088 break; 1089 case 2: 1090 Shift = ARM_AM::asr; 1091 break; 1092 case 3: 1093 Shift = ARM_AM::ror; 1094 break; 1095 } 1096 1097 if (Shift == ARM_AM::ror && imm == 0) 1098 Shift = ARM_AM::rrx; 1099 1100 unsigned Op = Shift | (imm << 3); 1101 Inst.addOperand(MCOperand::CreateImm(Op)); 1102 1103 return S; 1104} 1105 1106static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1107 uint64_t Address, const void *Decoder) { 1108 DecodeStatus S = MCDisassembler::Success; 1109 1110 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1111 unsigned type = fieldFromInstruction32(Val, 5, 2); 1112 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1113 1114 // Register-register 1115 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1116 return MCDisassembler::Fail; 1117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1118 return MCDisassembler::Fail; 1119 1120 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1121 switch (type) { 1122 case 0: 1123 Shift = ARM_AM::lsl; 1124 break; 1125 case 1: 1126 Shift = ARM_AM::lsr; 1127 break; 1128 case 2: 1129 Shift = ARM_AM::asr; 1130 break; 1131 case 3: 1132 Shift = ARM_AM::ror; 1133 break; 1134 } 1135 1136 Inst.addOperand(MCOperand::CreateImm(Shift)); 1137 1138 return S; 1139} 1140 1141static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1142 uint64_t Address, const void *Decoder) { 1143 DecodeStatus S = MCDisassembler::Success; 1144 1145 bool writebackLoad = false; 1146 unsigned writebackReg = 0; 1147 switch (Inst.getOpcode()) { 1148 default: 1149 break; 1150 case ARM::LDMIA_UPD: 1151 case ARM::LDMDB_UPD: 1152 case ARM::LDMIB_UPD: 1153 case ARM::LDMDA_UPD: 1154 case ARM::t2LDMIA_UPD: 1155 case ARM::t2LDMDB_UPD: 1156 writebackLoad = true; 1157 writebackReg = Inst.getOperand(0).getReg(); 1158 break; 1159 } 1160 1161 // Empty register lists are not allowed. 1162 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1163 for (unsigned i = 0; i < 16; ++i) { 1164 if (Val & (1 << i)) { 1165 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1166 return MCDisassembler::Fail; 1167 // Writeback not allowed if Rn is in the target list. 1168 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1169 Check(S, MCDisassembler::SoftFail); 1170 } 1171 } 1172 1173 return S; 1174} 1175 1176static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1177 uint64_t Address, const void *Decoder) { 1178 DecodeStatus S = MCDisassembler::Success; 1179 1180 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1181 unsigned regs = Val & 0xFF; 1182 1183 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1184 return MCDisassembler::Fail; 1185 for (unsigned i = 0; i < (regs - 1); ++i) { 1186 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1187 return MCDisassembler::Fail; 1188 } 1189 1190 return S; 1191} 1192 1193static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1194 uint64_t Address, const void *Decoder) { 1195 DecodeStatus S = MCDisassembler::Success; 1196 1197 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1198 unsigned regs = (Val & 0xFF) / 2; 1199 1200 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1201 return MCDisassembler::Fail; 1202 for (unsigned i = 0; i < (regs - 1); ++i) { 1203 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1204 return MCDisassembler::Fail; 1205 } 1206 1207 return S; 1208} 1209 1210static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1211 uint64_t Address, const void *Decoder) { 1212 // This operand encodes a mask of contiguous zeros between a specified MSB 1213 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1214 // the mask of all bits LSB-and-lower, and then xor them to create 1215 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1216 // create the final mask. 1217 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1218 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1219 1220 DecodeStatus S = MCDisassembler::Success; 1221 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1222 1223 uint32_t msb_mask = 0xFFFFFFFF; 1224 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1225 uint32_t lsb_mask = (1U << lsb) - 1; 1226 1227 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1228 return S; 1229} 1230 1231static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1232 uint64_t Address, const void *Decoder) { 1233 DecodeStatus S = MCDisassembler::Success; 1234 1235 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1236 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1237 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1238 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1239 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1240 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1241 1242 switch (Inst.getOpcode()) { 1243 case ARM::LDC_OFFSET: 1244 case ARM::LDC_PRE: 1245 case ARM::LDC_POST: 1246 case ARM::LDC_OPTION: 1247 case ARM::LDCL_OFFSET: 1248 case ARM::LDCL_PRE: 1249 case ARM::LDCL_POST: 1250 case ARM::LDCL_OPTION: 1251 case ARM::STC_OFFSET: 1252 case ARM::STC_PRE: 1253 case ARM::STC_POST: 1254 case ARM::STC_OPTION: 1255 case ARM::STCL_OFFSET: 1256 case ARM::STCL_PRE: 1257 case ARM::STCL_POST: 1258 case ARM::STCL_OPTION: 1259 case ARM::t2LDC_OFFSET: 1260 case ARM::t2LDC_PRE: 1261 case ARM::t2LDC_POST: 1262 case ARM::t2LDC_OPTION: 1263 case ARM::t2LDCL_OFFSET: 1264 case ARM::t2LDCL_PRE: 1265 case ARM::t2LDCL_POST: 1266 case ARM::t2LDCL_OPTION: 1267 case ARM::t2STC_OFFSET: 1268 case ARM::t2STC_PRE: 1269 case ARM::t2STC_POST: 1270 case ARM::t2STC_OPTION: 1271 case ARM::t2STCL_OFFSET: 1272 case ARM::t2STCL_PRE: 1273 case ARM::t2STCL_POST: 1274 case ARM::t2STCL_OPTION: 1275 if (coproc == 0xA || coproc == 0xB) 1276 return MCDisassembler::Fail; 1277 break; 1278 default: 1279 break; 1280 } 1281 1282 Inst.addOperand(MCOperand::CreateImm(coproc)); 1283 Inst.addOperand(MCOperand::CreateImm(CRd)); 1284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1285 return MCDisassembler::Fail; 1286 1287 switch (Inst.getOpcode()) { 1288 case ARM::t2LDC2_OFFSET: 1289 case ARM::t2LDC2L_OFFSET: 1290 case ARM::t2LDC2_PRE: 1291 case ARM::t2LDC2L_PRE: 1292 case ARM::t2STC2_OFFSET: 1293 case ARM::t2STC2L_OFFSET: 1294 case ARM::t2STC2_PRE: 1295 case ARM::t2STC2L_PRE: 1296 case ARM::LDC2_OFFSET: 1297 case ARM::LDC2L_OFFSET: 1298 case ARM::LDC2_PRE: 1299 case ARM::LDC2L_PRE: 1300 case ARM::STC2_OFFSET: 1301 case ARM::STC2L_OFFSET: 1302 case ARM::STC2_PRE: 1303 case ARM::STC2L_PRE: 1304 case ARM::t2LDC_OFFSET: 1305 case ARM::t2LDCL_OFFSET: 1306 case ARM::t2LDC_PRE: 1307 case ARM::t2LDCL_PRE: 1308 case ARM::t2STC_OFFSET: 1309 case ARM::t2STCL_OFFSET: 1310 case ARM::t2STC_PRE: 1311 case ARM::t2STCL_PRE: 1312 case ARM::LDC_OFFSET: 1313 case ARM::LDCL_OFFSET: 1314 case ARM::LDC_PRE: 1315 case ARM::LDCL_PRE: 1316 case ARM::STC_OFFSET: 1317 case ARM::STCL_OFFSET: 1318 case ARM::STC_PRE: 1319 case ARM::STCL_PRE: 1320 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1321 Inst.addOperand(MCOperand::CreateImm(imm)); 1322 break; 1323 case ARM::t2LDC2_POST: 1324 case ARM::t2LDC2L_POST: 1325 case ARM::t2STC2_POST: 1326 case ARM::t2STC2L_POST: 1327 case ARM::LDC2_POST: 1328 case ARM::LDC2L_POST: 1329 case ARM::STC2_POST: 1330 case ARM::STC2L_POST: 1331 case ARM::t2LDC_POST: 1332 case ARM::t2LDCL_POST: 1333 case ARM::t2STC_POST: 1334 case ARM::t2STCL_POST: 1335 case ARM::LDC_POST: 1336 case ARM::LDCL_POST: 1337 case ARM::STC_POST: 1338 case ARM::STCL_POST: 1339 imm |= U << 8; 1340 // fall through. 1341 default: 1342 // The 'option' variant doesn't encode 'U' in the immediate since 1343 // the immediate is unsigned [0,255]. 1344 Inst.addOperand(MCOperand::CreateImm(imm)); 1345 break; 1346 } 1347 1348 switch (Inst.getOpcode()) { 1349 case ARM::LDC_OFFSET: 1350 case ARM::LDC_PRE: 1351 case ARM::LDC_POST: 1352 case ARM::LDC_OPTION: 1353 case ARM::LDCL_OFFSET: 1354 case ARM::LDCL_PRE: 1355 case ARM::LDCL_POST: 1356 case ARM::LDCL_OPTION: 1357 case ARM::STC_OFFSET: 1358 case ARM::STC_PRE: 1359 case ARM::STC_POST: 1360 case ARM::STC_OPTION: 1361 case ARM::STCL_OFFSET: 1362 case ARM::STCL_PRE: 1363 case ARM::STCL_POST: 1364 case ARM::STCL_OPTION: 1365 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1366 return MCDisassembler::Fail; 1367 break; 1368 default: 1369 break; 1370 } 1371 1372 return S; 1373} 1374 1375static DecodeStatus 1376DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1377 uint64_t Address, const void *Decoder) { 1378 DecodeStatus S = MCDisassembler::Success; 1379 1380 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1381 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1382 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1383 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1384 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1385 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1386 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1387 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1388 1389 // On stores, the writeback operand precedes Rt. 1390 switch (Inst.getOpcode()) { 1391 case ARM::STR_POST_IMM: 1392 case ARM::STR_POST_REG: 1393 case ARM::STRB_POST_IMM: 1394 case ARM::STRB_POST_REG: 1395 case ARM::STRT_POST_REG: 1396 case ARM::STRT_POST_IMM: 1397 case ARM::STRBT_POST_REG: 1398 case ARM::STRBT_POST_IMM: 1399 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1400 return MCDisassembler::Fail; 1401 break; 1402 default: 1403 break; 1404 } 1405 1406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1407 return MCDisassembler::Fail; 1408 1409 // On loads, the writeback operand comes after Rt. 1410 switch (Inst.getOpcode()) { 1411 case ARM::LDR_POST_IMM: 1412 case ARM::LDR_POST_REG: 1413 case ARM::LDRB_POST_IMM: 1414 case ARM::LDRB_POST_REG: 1415 case ARM::LDRBT_POST_REG: 1416 case ARM::LDRBT_POST_IMM: 1417 case ARM::LDRT_POST_REG: 1418 case ARM::LDRT_POST_IMM: 1419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1420 return MCDisassembler::Fail; 1421 break; 1422 default: 1423 break; 1424 } 1425 1426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1427 return MCDisassembler::Fail; 1428 1429 ARM_AM::AddrOpc Op = ARM_AM::add; 1430 if (!fieldFromInstruction32(Insn, 23, 1)) 1431 Op = ARM_AM::sub; 1432 1433 bool writeback = (P == 0) || (W == 1); 1434 unsigned idx_mode = 0; 1435 if (P && writeback) 1436 idx_mode = ARMII::IndexModePre; 1437 else if (!P && writeback) 1438 idx_mode = ARMII::IndexModePost; 1439 1440 if (writeback && (Rn == 15 || Rn == Rt)) 1441 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1442 1443 if (reg) { 1444 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1445 return MCDisassembler::Fail; 1446 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1447 switch( fieldFromInstruction32(Insn, 5, 2)) { 1448 case 0: 1449 Opc = ARM_AM::lsl; 1450 break; 1451 case 1: 1452 Opc = ARM_AM::lsr; 1453 break; 1454 case 2: 1455 Opc = ARM_AM::asr; 1456 break; 1457 case 3: 1458 Opc = ARM_AM::ror; 1459 break; 1460 default: 1461 return MCDisassembler::Fail; 1462 } 1463 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1464 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1465 1466 Inst.addOperand(MCOperand::CreateImm(imm)); 1467 } else { 1468 Inst.addOperand(MCOperand::CreateReg(0)); 1469 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1470 Inst.addOperand(MCOperand::CreateImm(tmp)); 1471 } 1472 1473 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1474 return MCDisassembler::Fail; 1475 1476 return S; 1477} 1478 1479static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1480 uint64_t Address, const void *Decoder) { 1481 DecodeStatus S = MCDisassembler::Success; 1482 1483 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1484 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1485 unsigned type = fieldFromInstruction32(Val, 5, 2); 1486 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1487 unsigned U = fieldFromInstruction32(Val, 12, 1); 1488 1489 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1490 switch (type) { 1491 case 0: 1492 ShOp = ARM_AM::lsl; 1493 break; 1494 case 1: 1495 ShOp = ARM_AM::lsr; 1496 break; 1497 case 2: 1498 ShOp = ARM_AM::asr; 1499 break; 1500 case 3: 1501 ShOp = ARM_AM::ror; 1502 break; 1503 } 1504 1505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1506 return MCDisassembler::Fail; 1507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1508 return MCDisassembler::Fail; 1509 unsigned shift; 1510 if (U) 1511 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1512 else 1513 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1514 Inst.addOperand(MCOperand::CreateImm(shift)); 1515 1516 return S; 1517} 1518 1519static DecodeStatus 1520DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1521 uint64_t Address, const void *Decoder) { 1522 DecodeStatus S = MCDisassembler::Success; 1523 1524 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1525 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1526 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1527 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1528 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1529 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1530 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1531 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1532 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1533 1534 bool writeback = (W == 1) | (P == 0); 1535 1536 // For {LD,ST}RD, Rt must be even, else undefined. 1537 switch (Inst.getOpcode()) { 1538 case ARM::STRD: 1539 case ARM::STRD_PRE: 1540 case ARM::STRD_POST: 1541 case ARM::LDRD: 1542 case ARM::LDRD_PRE: 1543 case ARM::LDRD_POST: 1544 if (Rt & 0x1) return MCDisassembler::Fail; 1545 break; 1546 default: 1547 break; 1548 } 1549 1550 if (writeback) { // Writeback 1551 if (P) 1552 U |= ARMII::IndexModePre << 9; 1553 else 1554 U |= ARMII::IndexModePost << 9; 1555 1556 // On stores, the writeback operand precedes Rt. 1557 switch (Inst.getOpcode()) { 1558 case ARM::STRD: 1559 case ARM::STRD_PRE: 1560 case ARM::STRD_POST: 1561 case ARM::STRH: 1562 case ARM::STRH_PRE: 1563 case ARM::STRH_POST: 1564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1565 return MCDisassembler::Fail; 1566 break; 1567 default: 1568 break; 1569 } 1570 } 1571 1572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1573 return MCDisassembler::Fail; 1574 switch (Inst.getOpcode()) { 1575 case ARM::STRD: 1576 case ARM::STRD_PRE: 1577 case ARM::STRD_POST: 1578 case ARM::LDRD: 1579 case ARM::LDRD_PRE: 1580 case ARM::LDRD_POST: 1581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1582 return MCDisassembler::Fail; 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 if (writeback) { 1589 // On loads, the writeback operand comes after Rt. 1590 switch (Inst.getOpcode()) { 1591 case ARM::LDRD: 1592 case ARM::LDRD_PRE: 1593 case ARM::LDRD_POST: 1594 case ARM::LDRH: 1595 case ARM::LDRH_PRE: 1596 case ARM::LDRH_POST: 1597 case ARM::LDRSH: 1598 case ARM::LDRSH_PRE: 1599 case ARM::LDRSH_POST: 1600 case ARM::LDRSB: 1601 case ARM::LDRSB_PRE: 1602 case ARM::LDRSB_POST: 1603 case ARM::LDRHTr: 1604 case ARM::LDRSBTr: 1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1606 return MCDisassembler::Fail; 1607 break; 1608 default: 1609 break; 1610 } 1611 } 1612 1613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1614 return MCDisassembler::Fail; 1615 1616 if (type) { 1617 Inst.addOperand(MCOperand::CreateReg(0)); 1618 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1619 } else { 1620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1621 return MCDisassembler::Fail; 1622 Inst.addOperand(MCOperand::CreateImm(U)); 1623 } 1624 1625 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1626 return MCDisassembler::Fail; 1627 1628 return S; 1629} 1630 1631static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1632 uint64_t Address, const void *Decoder) { 1633 DecodeStatus S = MCDisassembler::Success; 1634 1635 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1636 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1637 1638 switch (mode) { 1639 case 0: 1640 mode = ARM_AM::da; 1641 break; 1642 case 1: 1643 mode = ARM_AM::ia; 1644 break; 1645 case 2: 1646 mode = ARM_AM::db; 1647 break; 1648 case 3: 1649 mode = ARM_AM::ib; 1650 break; 1651 } 1652 1653 Inst.addOperand(MCOperand::CreateImm(mode)); 1654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1655 return MCDisassembler::Fail; 1656 1657 return S; 1658} 1659 1660static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1661 unsigned Insn, 1662 uint64_t Address, const void *Decoder) { 1663 DecodeStatus S = MCDisassembler::Success; 1664 1665 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1666 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1667 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1668 1669 if (pred == 0xF) { 1670 switch (Inst.getOpcode()) { 1671 case ARM::LDMDA: 1672 Inst.setOpcode(ARM::RFEDA); 1673 break; 1674 case ARM::LDMDA_UPD: 1675 Inst.setOpcode(ARM::RFEDA_UPD); 1676 break; 1677 case ARM::LDMDB: 1678 Inst.setOpcode(ARM::RFEDB); 1679 break; 1680 case ARM::LDMDB_UPD: 1681 Inst.setOpcode(ARM::RFEDB_UPD); 1682 break; 1683 case ARM::LDMIA: 1684 Inst.setOpcode(ARM::RFEIA); 1685 break; 1686 case ARM::LDMIA_UPD: 1687 Inst.setOpcode(ARM::RFEIA_UPD); 1688 break; 1689 case ARM::LDMIB: 1690 Inst.setOpcode(ARM::RFEIB); 1691 break; 1692 case ARM::LDMIB_UPD: 1693 Inst.setOpcode(ARM::RFEIB_UPD); 1694 break; 1695 case ARM::STMDA: 1696 Inst.setOpcode(ARM::SRSDA); 1697 break; 1698 case ARM::STMDA_UPD: 1699 Inst.setOpcode(ARM::SRSDA_UPD); 1700 break; 1701 case ARM::STMDB: 1702 Inst.setOpcode(ARM::SRSDB); 1703 break; 1704 case ARM::STMDB_UPD: 1705 Inst.setOpcode(ARM::SRSDB_UPD); 1706 break; 1707 case ARM::STMIA: 1708 Inst.setOpcode(ARM::SRSIA); 1709 break; 1710 case ARM::STMIA_UPD: 1711 Inst.setOpcode(ARM::SRSIA_UPD); 1712 break; 1713 case ARM::STMIB: 1714 Inst.setOpcode(ARM::SRSIB); 1715 break; 1716 case ARM::STMIB_UPD: 1717 Inst.setOpcode(ARM::SRSIB_UPD); 1718 break; 1719 default: 1720 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1721 } 1722 1723 // For stores (which become SRS's, the only operand is the mode. 1724 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1725 Inst.addOperand( 1726 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1727 return S; 1728 } 1729 1730 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1731 } 1732 1733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1734 return MCDisassembler::Fail; 1735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1736 return MCDisassembler::Fail; // Tied 1737 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1738 return MCDisassembler::Fail; 1739 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1740 return MCDisassembler::Fail; 1741 1742 return S; 1743} 1744 1745static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1746 uint64_t Address, const void *Decoder) { 1747 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1748 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1749 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1750 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1751 1752 DecodeStatus S = MCDisassembler::Success; 1753 1754 // imod == '01' --> UNPREDICTABLE 1755 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1756 // return failure here. The '01' imod value is unprintable, so there's 1757 // nothing useful we could do even if we returned UNPREDICTABLE. 1758 1759 if (imod == 1) return MCDisassembler::Fail; 1760 1761 if (imod && M) { 1762 Inst.setOpcode(ARM::CPS3p); 1763 Inst.addOperand(MCOperand::CreateImm(imod)); 1764 Inst.addOperand(MCOperand::CreateImm(iflags)); 1765 Inst.addOperand(MCOperand::CreateImm(mode)); 1766 } else if (imod && !M) { 1767 Inst.setOpcode(ARM::CPS2p); 1768 Inst.addOperand(MCOperand::CreateImm(imod)); 1769 Inst.addOperand(MCOperand::CreateImm(iflags)); 1770 if (mode) S = MCDisassembler::SoftFail; 1771 } else if (!imod && M) { 1772 Inst.setOpcode(ARM::CPS1p); 1773 Inst.addOperand(MCOperand::CreateImm(mode)); 1774 if (iflags) S = MCDisassembler::SoftFail; 1775 } else { 1776 // imod == '00' && M == '0' --> UNPREDICTABLE 1777 Inst.setOpcode(ARM::CPS1p); 1778 Inst.addOperand(MCOperand::CreateImm(mode)); 1779 S = MCDisassembler::SoftFail; 1780 } 1781 1782 return S; 1783} 1784 1785static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1786 uint64_t Address, const void *Decoder) { 1787 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1788 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1789 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1790 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1791 1792 DecodeStatus S = MCDisassembler::Success; 1793 1794 // imod == '01' --> UNPREDICTABLE 1795 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1796 // return failure here. The '01' imod value is unprintable, so there's 1797 // nothing useful we could do even if we returned UNPREDICTABLE. 1798 1799 if (imod == 1) return MCDisassembler::Fail; 1800 1801 if (imod && M) { 1802 Inst.setOpcode(ARM::t2CPS3p); 1803 Inst.addOperand(MCOperand::CreateImm(imod)); 1804 Inst.addOperand(MCOperand::CreateImm(iflags)); 1805 Inst.addOperand(MCOperand::CreateImm(mode)); 1806 } else if (imod && !M) { 1807 Inst.setOpcode(ARM::t2CPS2p); 1808 Inst.addOperand(MCOperand::CreateImm(imod)); 1809 Inst.addOperand(MCOperand::CreateImm(iflags)); 1810 if (mode) S = MCDisassembler::SoftFail; 1811 } else if (!imod && M) { 1812 Inst.setOpcode(ARM::t2CPS1p); 1813 Inst.addOperand(MCOperand::CreateImm(mode)); 1814 if (iflags) S = MCDisassembler::SoftFail; 1815 } else { 1816 // imod == '00' && M == '0' --> UNPREDICTABLE 1817 Inst.setOpcode(ARM::t2CPS1p); 1818 Inst.addOperand(MCOperand::CreateImm(mode)); 1819 S = MCDisassembler::SoftFail; 1820 } 1821 1822 return S; 1823} 1824 1825static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1826 uint64_t Address, const void *Decoder) { 1827 DecodeStatus S = MCDisassembler::Success; 1828 1829 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1830 unsigned imm = 0; 1831 1832 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1833 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1834 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1835 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1836 1837 if (Inst.getOpcode() == ARM::t2MOVTi16) 1838 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1839 return MCDisassembler::Fail; 1840 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1841 return MCDisassembler::Fail; 1842 1843 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1844 Inst.addOperand(MCOperand::CreateImm(imm)); 1845 1846 return S; 1847} 1848 1849static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1850 uint64_t Address, const void *Decoder) { 1851 DecodeStatus S = MCDisassembler::Success; 1852 1853 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1854 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1855 unsigned imm = 0; 1856 1857 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1858 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1859 1860 if (Inst.getOpcode() == ARM::MOVTi16) 1861 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1862 return MCDisassembler::Fail; 1863 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1864 return MCDisassembler::Fail; 1865 1866 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1867 Inst.addOperand(MCOperand::CreateImm(imm)); 1868 1869 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1870 return MCDisassembler::Fail; 1871 1872 return S; 1873} 1874 1875static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1876 uint64_t Address, const void *Decoder) { 1877 DecodeStatus S = MCDisassembler::Success; 1878 1879 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1880 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1881 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1882 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1883 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1884 1885 if (pred == 0xF) 1886 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1887 1888 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1889 return MCDisassembler::Fail; 1890 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1891 return MCDisassembler::Fail; 1892 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1893 return MCDisassembler::Fail; 1894 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1895 return MCDisassembler::Fail; 1896 1897 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1898 return MCDisassembler::Fail; 1899 1900 return S; 1901} 1902 1903static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1904 uint64_t Address, const void *Decoder) { 1905 DecodeStatus S = MCDisassembler::Success; 1906 1907 unsigned add = fieldFromInstruction32(Val, 12, 1); 1908 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1909 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1910 1911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1912 return MCDisassembler::Fail; 1913 1914 if (!add) imm *= -1; 1915 if (imm == 0 && !add) imm = INT32_MIN; 1916 Inst.addOperand(MCOperand::CreateImm(imm)); 1917 if (Rn == 15) 1918 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1919 1920 return S; 1921} 1922 1923static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1924 uint64_t Address, const void *Decoder) { 1925 DecodeStatus S = MCDisassembler::Success; 1926 1927 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1928 unsigned U = fieldFromInstruction32(Val, 8, 1); 1929 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1930 1931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1932 return MCDisassembler::Fail; 1933 1934 if (U) 1935 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1936 else 1937 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1938 1939 return S; 1940} 1941 1942static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1943 uint64_t Address, const void *Decoder) { 1944 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1945} 1946 1947static DecodeStatus 1948DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1949 uint64_t Address, const void *Decoder) { 1950 DecodeStatus S = MCDisassembler::Success; 1951 1952 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1953 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1954 1955 if (pred == 0xF) { 1956 Inst.setOpcode(ARM::BLXi); 1957 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1958 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 1959 true, 4, Inst, Decoder)) 1960 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1961 return S; 1962 } 1963 1964 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 1965 true, 4, Inst, Decoder)) 1966 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1967 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1968 return MCDisassembler::Fail; 1969 1970 return S; 1971} 1972 1973 1974static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1975 uint64_t Address, const void *Decoder) { 1976 DecodeStatus S = MCDisassembler::Success; 1977 1978 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1979 unsigned align = fieldFromInstruction32(Val, 4, 2); 1980 1981 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1982 return MCDisassembler::Fail; 1983 if (!align) 1984 Inst.addOperand(MCOperand::CreateImm(0)); 1985 else 1986 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1987 1988 return S; 1989} 1990 1991static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1992 uint64_t Address, const void *Decoder) { 1993 DecodeStatus S = MCDisassembler::Success; 1994 1995 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1996 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1997 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1998 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1999 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2000 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2001 2002 // First output register 2003 switch (Inst.getOpcode()) { 2004 case ARM::VLD1q16: 2005 case ARM::VLD1q32: 2006 case ARM::VLD1q64: 2007 case ARM::VLD1q8: 2008 case ARM::VLD1q16wb_fixed: 2009 case ARM::VLD1q16wb_register: 2010 case ARM::VLD1q32wb_fixed: 2011 case ARM::VLD1q32wb_register: 2012 case ARM::VLD1q64wb_fixed: 2013 case ARM::VLD1q64wb_register: 2014 case ARM::VLD1q8wb_fixed: 2015 case ARM::VLD1q8wb_register: 2016 case ARM::VLD2d16: 2017 case ARM::VLD2d32: 2018 case ARM::VLD2d8: 2019 case ARM::VLD2d16wb_fixed: 2020 case ARM::VLD2d16wb_register: 2021 case ARM::VLD2d32wb_fixed: 2022 case ARM::VLD2d32wb_register: 2023 case ARM::VLD2d8wb_fixed: 2024 case ARM::VLD2d8wb_register: 2025 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2026 return MCDisassembler::Fail; 2027 break; 2028 case ARM::VLD2b16: 2029 case ARM::VLD2b32: 2030 case ARM::VLD2b8: 2031 case ARM::VLD2b16wb_fixed: 2032 case ARM::VLD2b16wb_register: 2033 case ARM::VLD2b32wb_fixed: 2034 case ARM::VLD2b32wb_register: 2035 case ARM::VLD2b8wb_fixed: 2036 case ARM::VLD2b8wb_register: 2037 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2038 return MCDisassembler::Fail; 2039 break; 2040 default: 2041 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2042 return MCDisassembler::Fail; 2043 } 2044 2045 // Second output register 2046 switch (Inst.getOpcode()) { 2047 case ARM::VLD3d8: 2048 case ARM::VLD3d16: 2049 case ARM::VLD3d32: 2050 case ARM::VLD3d8_UPD: 2051 case ARM::VLD3d16_UPD: 2052 case ARM::VLD3d32_UPD: 2053 case ARM::VLD4d8: 2054 case ARM::VLD4d16: 2055 case ARM::VLD4d32: 2056 case ARM::VLD4d8_UPD: 2057 case ARM::VLD4d16_UPD: 2058 case ARM::VLD4d32_UPD: 2059 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2060 return MCDisassembler::Fail; 2061 break; 2062 case ARM::VLD3q8: 2063 case ARM::VLD3q16: 2064 case ARM::VLD3q32: 2065 case ARM::VLD3q8_UPD: 2066 case ARM::VLD3q16_UPD: 2067 case ARM::VLD3q32_UPD: 2068 case ARM::VLD4q8: 2069 case ARM::VLD4q16: 2070 case ARM::VLD4q32: 2071 case ARM::VLD4q8_UPD: 2072 case ARM::VLD4q16_UPD: 2073 case ARM::VLD4q32_UPD: 2074 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2075 return MCDisassembler::Fail; 2076 default: 2077 break; 2078 } 2079 2080 // Third output register 2081 switch(Inst.getOpcode()) { 2082 case ARM::VLD3d8: 2083 case ARM::VLD3d16: 2084 case ARM::VLD3d32: 2085 case ARM::VLD3d8_UPD: 2086 case ARM::VLD3d16_UPD: 2087 case ARM::VLD3d32_UPD: 2088 case ARM::VLD4d8: 2089 case ARM::VLD4d16: 2090 case ARM::VLD4d32: 2091 case ARM::VLD4d8_UPD: 2092 case ARM::VLD4d16_UPD: 2093 case ARM::VLD4d32_UPD: 2094 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2095 return MCDisassembler::Fail; 2096 break; 2097 case ARM::VLD3q8: 2098 case ARM::VLD3q16: 2099 case ARM::VLD3q32: 2100 case ARM::VLD3q8_UPD: 2101 case ARM::VLD3q16_UPD: 2102 case ARM::VLD3q32_UPD: 2103 case ARM::VLD4q8: 2104 case ARM::VLD4q16: 2105 case ARM::VLD4q32: 2106 case ARM::VLD4q8_UPD: 2107 case ARM::VLD4q16_UPD: 2108 case ARM::VLD4q32_UPD: 2109 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 break; 2112 default: 2113 break; 2114 } 2115 2116 // Fourth output register 2117 switch (Inst.getOpcode()) { 2118 case ARM::VLD4d8: 2119 case ARM::VLD4d16: 2120 case ARM::VLD4d32: 2121 case ARM::VLD4d8_UPD: 2122 case ARM::VLD4d16_UPD: 2123 case ARM::VLD4d32_UPD: 2124 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2125 return MCDisassembler::Fail; 2126 break; 2127 case ARM::VLD4q8: 2128 case ARM::VLD4q16: 2129 case ARM::VLD4q32: 2130 case ARM::VLD4q8_UPD: 2131 case ARM::VLD4q16_UPD: 2132 case ARM::VLD4q32_UPD: 2133 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2134 return MCDisassembler::Fail; 2135 break; 2136 default: 2137 break; 2138 } 2139 2140 // Writeback operand 2141 switch (Inst.getOpcode()) { 2142 case ARM::VLD1d8wb_fixed: 2143 case ARM::VLD1d16wb_fixed: 2144 case ARM::VLD1d32wb_fixed: 2145 case ARM::VLD1d64wb_fixed: 2146 case ARM::VLD1d8wb_register: 2147 case ARM::VLD1d16wb_register: 2148 case ARM::VLD1d32wb_register: 2149 case ARM::VLD1d64wb_register: 2150 case ARM::VLD1q8wb_fixed: 2151 case ARM::VLD1q16wb_fixed: 2152 case ARM::VLD1q32wb_fixed: 2153 case ARM::VLD1q64wb_fixed: 2154 case ARM::VLD1q8wb_register: 2155 case ARM::VLD1q16wb_register: 2156 case ARM::VLD1q32wb_register: 2157 case ARM::VLD1q64wb_register: 2158 case ARM::VLD1d8Twb_fixed: 2159 case ARM::VLD1d8Twb_register: 2160 case ARM::VLD1d16Twb_fixed: 2161 case ARM::VLD1d16Twb_register: 2162 case ARM::VLD1d32Twb_fixed: 2163 case ARM::VLD1d32Twb_register: 2164 case ARM::VLD1d64Twb_fixed: 2165 case ARM::VLD1d64Twb_register: 2166 case ARM::VLD1d8Qwb_fixed: 2167 case ARM::VLD1d8Qwb_register: 2168 case ARM::VLD1d16Qwb_fixed: 2169 case ARM::VLD1d16Qwb_register: 2170 case ARM::VLD1d32Qwb_fixed: 2171 case ARM::VLD1d32Qwb_register: 2172 case ARM::VLD1d64Qwb_fixed: 2173 case ARM::VLD1d64Qwb_register: 2174 case ARM::VLD2d8wb_fixed: 2175 case ARM::VLD2d16wb_fixed: 2176 case ARM::VLD2d32wb_fixed: 2177 case ARM::VLD2q8wb_fixed: 2178 case ARM::VLD2q16wb_fixed: 2179 case ARM::VLD2q32wb_fixed: 2180 case ARM::VLD2d8wb_register: 2181 case ARM::VLD2d16wb_register: 2182 case ARM::VLD2d32wb_register: 2183 case ARM::VLD2q8wb_register: 2184 case ARM::VLD2q16wb_register: 2185 case ARM::VLD2q32wb_register: 2186 case ARM::VLD2b8wb_fixed: 2187 case ARM::VLD2b16wb_fixed: 2188 case ARM::VLD2b32wb_fixed: 2189 case ARM::VLD2b8wb_register: 2190 case ARM::VLD2b16wb_register: 2191 case ARM::VLD2b32wb_register: 2192 case ARM::VLD3d8_UPD: 2193 case ARM::VLD3d16_UPD: 2194 case ARM::VLD3d32_UPD: 2195 case ARM::VLD3q8_UPD: 2196 case ARM::VLD3q16_UPD: 2197 case ARM::VLD3q32_UPD: 2198 case ARM::VLD4d8_UPD: 2199 case ARM::VLD4d16_UPD: 2200 case ARM::VLD4d32_UPD: 2201 case ARM::VLD4q8_UPD: 2202 case ARM::VLD4q16_UPD: 2203 case ARM::VLD4q32_UPD: 2204 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2205 return MCDisassembler::Fail; 2206 break; 2207 default: 2208 break; 2209 } 2210 2211 // AddrMode6 Base (register+alignment) 2212 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2213 return MCDisassembler::Fail; 2214 2215 // AddrMode6 Offset (register) 2216 switch (Inst.getOpcode()) { 2217 default: 2218 // The below have been updated to have explicit am6offset split 2219 // between fixed and register offset. For those instructions not 2220 // yet updated, we need to add an additional reg0 operand for the 2221 // fixed variant. 2222 // 2223 // The fixed offset encodes as Rm == 0xd, so we check for that. 2224 if (Rm == 0xd) { 2225 Inst.addOperand(MCOperand::CreateReg(0)); 2226 break; 2227 } 2228 // Fall through to handle the register offset variant. 2229 case ARM::VLD1d8wb_fixed: 2230 case ARM::VLD1d16wb_fixed: 2231 case ARM::VLD1d32wb_fixed: 2232 case ARM::VLD1d64wb_fixed: 2233 case ARM::VLD1d8Twb_fixed: 2234 case ARM::VLD1d16Twb_fixed: 2235 case ARM::VLD1d32Twb_fixed: 2236 case ARM::VLD1d64Twb_fixed: 2237 case ARM::VLD1d8Qwb_fixed: 2238 case ARM::VLD1d16Qwb_fixed: 2239 case ARM::VLD1d32Qwb_fixed: 2240 case ARM::VLD1d64Qwb_fixed: 2241 case ARM::VLD1d8wb_register: 2242 case ARM::VLD1d16wb_register: 2243 case ARM::VLD1d32wb_register: 2244 case ARM::VLD1d64wb_register: 2245 case ARM::VLD1q8wb_fixed: 2246 case ARM::VLD1q16wb_fixed: 2247 case ARM::VLD1q32wb_fixed: 2248 case ARM::VLD1q64wb_fixed: 2249 case ARM::VLD1q8wb_register: 2250 case ARM::VLD1q16wb_register: 2251 case ARM::VLD1q32wb_register: 2252 case ARM::VLD1q64wb_register: 2253 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2254 // variant encodes Rm == 0xf. Anything else is a register offset post- 2255 // increment and we need to add the register operand to the instruction. 2256 if (Rm != 0xD && Rm != 0xF && 2257 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2258 return MCDisassembler::Fail; 2259 break; 2260 } 2261 2262 return S; 2263} 2264 2265static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2266 uint64_t Address, const void *Decoder) { 2267 DecodeStatus S = MCDisassembler::Success; 2268 2269 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2270 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2271 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2272 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2273 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2274 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2275 2276 // Writeback Operand 2277 switch (Inst.getOpcode()) { 2278 case ARM::VST1d8wb_fixed: 2279 case ARM::VST1d16wb_fixed: 2280 case ARM::VST1d32wb_fixed: 2281 case ARM::VST1d64wb_fixed: 2282 case ARM::VST1d8wb_register: 2283 case ARM::VST1d16wb_register: 2284 case ARM::VST1d32wb_register: 2285 case ARM::VST1d64wb_register: 2286 case ARM::VST1q8wb_fixed: 2287 case ARM::VST1q16wb_fixed: 2288 case ARM::VST1q32wb_fixed: 2289 case ARM::VST1q64wb_fixed: 2290 case ARM::VST1q8wb_register: 2291 case ARM::VST1q16wb_register: 2292 case ARM::VST1q32wb_register: 2293 case ARM::VST1q64wb_register: 2294 case ARM::VST1d8Twb_fixed: 2295 case ARM::VST1d16Twb_fixed: 2296 case ARM::VST1d32Twb_fixed: 2297 case ARM::VST1d64Twb_fixed: 2298 case ARM::VST1d8Twb_register: 2299 case ARM::VST1d16Twb_register: 2300 case ARM::VST1d32Twb_register: 2301 case ARM::VST1d64Twb_register: 2302 case ARM::VST1d8Qwb_fixed: 2303 case ARM::VST1d16Qwb_fixed: 2304 case ARM::VST1d32Qwb_fixed: 2305 case ARM::VST1d64Qwb_fixed: 2306 case ARM::VST1d8Qwb_register: 2307 case ARM::VST1d16Qwb_register: 2308 case ARM::VST1d32Qwb_register: 2309 case ARM::VST1d64Qwb_register: 2310 case ARM::VST2d8wb_fixed: 2311 case ARM::VST2d16wb_fixed: 2312 case ARM::VST2d32wb_fixed: 2313 case ARM::VST2d8wb_register: 2314 case ARM::VST2d16wb_register: 2315 case ARM::VST2d32wb_register: 2316 case ARM::VST2q8wb_fixed: 2317 case ARM::VST2q16wb_fixed: 2318 case ARM::VST2q32wb_fixed: 2319 case ARM::VST2q8wb_register: 2320 case ARM::VST2q16wb_register: 2321 case ARM::VST2q32wb_register: 2322 case ARM::VST2b8wb_fixed: 2323 case ARM::VST2b16wb_fixed: 2324 case ARM::VST2b32wb_fixed: 2325 case ARM::VST2b8wb_register: 2326 case ARM::VST2b16wb_register: 2327 case ARM::VST2b32wb_register: 2328 case ARM::VST3d8_UPD: 2329 case ARM::VST3d16_UPD: 2330 case ARM::VST3d32_UPD: 2331 case ARM::VST3q8_UPD: 2332 case ARM::VST3q16_UPD: 2333 case ARM::VST3q32_UPD: 2334 case ARM::VST4d8_UPD: 2335 case ARM::VST4d16_UPD: 2336 case ARM::VST4d32_UPD: 2337 case ARM::VST4q8_UPD: 2338 case ARM::VST4q16_UPD: 2339 case ARM::VST4q32_UPD: 2340 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2341 return MCDisassembler::Fail; 2342 break; 2343 default: 2344 break; 2345 } 2346 2347 // AddrMode6 Base (register+alignment) 2348 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2349 return MCDisassembler::Fail; 2350 2351 // AddrMode6 Offset (register) 2352 switch (Inst.getOpcode()) { 2353 default: 2354 if (Rm == 0xD) 2355 Inst.addOperand(MCOperand::CreateReg(0)); 2356 else if (Rm != 0xF) { 2357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2358 return MCDisassembler::Fail; 2359 } 2360 break; 2361 case ARM::VST1d8wb_fixed: 2362 case ARM::VST1d16wb_fixed: 2363 case ARM::VST1d32wb_fixed: 2364 case ARM::VST1d64wb_fixed: 2365 case ARM::VST1q8wb_fixed: 2366 case ARM::VST1q16wb_fixed: 2367 case ARM::VST1q32wb_fixed: 2368 case ARM::VST1q64wb_fixed: 2369 break; 2370 } 2371 2372 2373 // First input register 2374 switch (Inst.getOpcode()) { 2375 case ARM::VST1q16: 2376 case ARM::VST1q32: 2377 case ARM::VST1q64: 2378 case ARM::VST1q8: 2379 case ARM::VST1q16wb_fixed: 2380 case ARM::VST1q16wb_register: 2381 case ARM::VST1q32wb_fixed: 2382 case ARM::VST1q32wb_register: 2383 case ARM::VST1q64wb_fixed: 2384 case ARM::VST1q64wb_register: 2385 case ARM::VST1q8wb_fixed: 2386 case ARM::VST1q8wb_register: 2387 case ARM::VST2d16: 2388 case ARM::VST2d32: 2389 case ARM::VST2d8: 2390 case ARM::VST2d16wb_fixed: 2391 case ARM::VST2d16wb_register: 2392 case ARM::VST2d32wb_fixed: 2393 case ARM::VST2d32wb_register: 2394 case ARM::VST2d8wb_fixed: 2395 case ARM::VST2d8wb_register: 2396 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2397 return MCDisassembler::Fail; 2398 break; 2399 case ARM::VST2b16: 2400 case ARM::VST2b32: 2401 case ARM::VST2b8: 2402 case ARM::VST2b16wb_fixed: 2403 case ARM::VST2b16wb_register: 2404 case ARM::VST2b32wb_fixed: 2405 case ARM::VST2b32wb_register: 2406 case ARM::VST2b8wb_fixed: 2407 case ARM::VST2b8wb_register: 2408 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2409 return MCDisassembler::Fail; 2410 break; 2411 default: 2412 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2413 return MCDisassembler::Fail; 2414 } 2415 2416 // Second input register 2417 switch (Inst.getOpcode()) { 2418 case ARM::VST3d8: 2419 case ARM::VST3d16: 2420 case ARM::VST3d32: 2421 case ARM::VST3d8_UPD: 2422 case ARM::VST3d16_UPD: 2423 case ARM::VST3d32_UPD: 2424 case ARM::VST4d8: 2425 case ARM::VST4d16: 2426 case ARM::VST4d32: 2427 case ARM::VST4d8_UPD: 2428 case ARM::VST4d16_UPD: 2429 case ARM::VST4d32_UPD: 2430 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2431 return MCDisassembler::Fail; 2432 break; 2433 case ARM::VST3q8: 2434 case ARM::VST3q16: 2435 case ARM::VST3q32: 2436 case ARM::VST3q8_UPD: 2437 case ARM::VST3q16_UPD: 2438 case ARM::VST3q32_UPD: 2439 case ARM::VST4q8: 2440 case ARM::VST4q16: 2441 case ARM::VST4q32: 2442 case ARM::VST4q8_UPD: 2443 case ARM::VST4q16_UPD: 2444 case ARM::VST4q32_UPD: 2445 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2446 return MCDisassembler::Fail; 2447 break; 2448 default: 2449 break; 2450 } 2451 2452 // Third input register 2453 switch (Inst.getOpcode()) { 2454 case ARM::VST3d8: 2455 case ARM::VST3d16: 2456 case ARM::VST3d32: 2457 case ARM::VST3d8_UPD: 2458 case ARM::VST3d16_UPD: 2459 case ARM::VST3d32_UPD: 2460 case ARM::VST4d8: 2461 case ARM::VST4d16: 2462 case ARM::VST4d32: 2463 case ARM::VST4d8_UPD: 2464 case ARM::VST4d16_UPD: 2465 case ARM::VST4d32_UPD: 2466 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2467 return MCDisassembler::Fail; 2468 break; 2469 case ARM::VST3q8: 2470 case ARM::VST3q16: 2471 case ARM::VST3q32: 2472 case ARM::VST3q8_UPD: 2473 case ARM::VST3q16_UPD: 2474 case ARM::VST3q32_UPD: 2475 case ARM::VST4q8: 2476 case ARM::VST4q16: 2477 case ARM::VST4q32: 2478 case ARM::VST4q8_UPD: 2479 case ARM::VST4q16_UPD: 2480 case ARM::VST4q32_UPD: 2481 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2482 return MCDisassembler::Fail; 2483 break; 2484 default: 2485 break; 2486 } 2487 2488 // Fourth input register 2489 switch (Inst.getOpcode()) { 2490 case ARM::VST4d8: 2491 case ARM::VST4d16: 2492 case ARM::VST4d32: 2493 case ARM::VST4d8_UPD: 2494 case ARM::VST4d16_UPD: 2495 case ARM::VST4d32_UPD: 2496 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2497 return MCDisassembler::Fail; 2498 break; 2499 case ARM::VST4q8: 2500 case ARM::VST4q16: 2501 case ARM::VST4q32: 2502 case ARM::VST4q8_UPD: 2503 case ARM::VST4q16_UPD: 2504 case ARM::VST4q32_UPD: 2505 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2506 return MCDisassembler::Fail; 2507 break; 2508 default: 2509 break; 2510 } 2511 2512 return S; 2513} 2514 2515static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2516 uint64_t Address, const void *Decoder) { 2517 DecodeStatus S = MCDisassembler::Success; 2518 2519 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2520 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2521 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2522 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2523 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2524 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2525 2526 align *= (1 << size); 2527 2528 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2529 return MCDisassembler::Fail; 2530 if (Rm != 0xF) { 2531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 } 2534 2535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2536 return MCDisassembler::Fail; 2537 Inst.addOperand(MCOperand::CreateImm(align)); 2538 2539 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2540 // variant encodes Rm == 0xf. Anything else is a register offset post- 2541 // increment and we need to add the register operand to the instruction. 2542 if (Rm != 0xD && Rm != 0xF && 2543 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2544 return MCDisassembler::Fail; 2545 2546 return S; 2547} 2548 2549static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2550 uint64_t Address, const void *Decoder) { 2551 DecodeStatus S = MCDisassembler::Success; 2552 2553 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2554 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2555 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2556 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2557 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2558 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2559 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2560 align *= 2*size; 2561 2562 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2563 return MCDisassembler::Fail; 2564 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2565 return MCDisassembler::Fail; 2566 if (Rm != 0xF) { 2567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2568 return MCDisassembler::Fail; 2569 } 2570 2571 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2572 return MCDisassembler::Fail; 2573 Inst.addOperand(MCOperand::CreateImm(align)); 2574 2575 if (Rm == 0xD) 2576 Inst.addOperand(MCOperand::CreateReg(0)); 2577 else if (Rm != 0xF) { 2578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2579 return MCDisassembler::Fail; 2580 } 2581 2582 return S; 2583} 2584 2585static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2586 uint64_t Address, const void *Decoder) { 2587 DecodeStatus S = MCDisassembler::Success; 2588 2589 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2590 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2591 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2592 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2593 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2594 2595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2596 return MCDisassembler::Fail; 2597 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2598 return MCDisassembler::Fail; 2599 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2600 return MCDisassembler::Fail; 2601 if (Rm != 0xF) { 2602 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2603 return MCDisassembler::Fail; 2604 } 2605 2606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2607 return MCDisassembler::Fail; 2608 Inst.addOperand(MCOperand::CreateImm(0)); 2609 2610 if (Rm == 0xD) 2611 Inst.addOperand(MCOperand::CreateReg(0)); 2612 else if (Rm != 0xF) { 2613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2614 return MCDisassembler::Fail; 2615 } 2616 2617 return S; 2618} 2619 2620static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2621 uint64_t Address, const void *Decoder) { 2622 DecodeStatus S = MCDisassembler::Success; 2623 2624 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2625 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2626 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2627 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2628 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2629 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2630 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2631 2632 if (size == 0x3) { 2633 size = 4; 2634 align = 16; 2635 } else { 2636 if (size == 2) { 2637 size = 1 << size; 2638 align *= 8; 2639 } else { 2640 size = 1 << size; 2641 align *= 4*size; 2642 } 2643 } 2644 2645 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2646 return MCDisassembler::Fail; 2647 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2648 return MCDisassembler::Fail; 2649 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2650 return MCDisassembler::Fail; 2651 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2652 return MCDisassembler::Fail; 2653 if (Rm != 0xF) { 2654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2655 return MCDisassembler::Fail; 2656 } 2657 2658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2659 return MCDisassembler::Fail; 2660 Inst.addOperand(MCOperand::CreateImm(align)); 2661 2662 if (Rm == 0xD) 2663 Inst.addOperand(MCOperand::CreateReg(0)); 2664 else if (Rm != 0xF) { 2665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2666 return MCDisassembler::Fail; 2667 } 2668 2669 return S; 2670} 2671 2672static DecodeStatus 2673DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2674 uint64_t Address, const void *Decoder) { 2675 DecodeStatus S = MCDisassembler::Success; 2676 2677 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2678 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2679 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2680 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2681 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2682 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2683 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2684 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2685 2686 if (Q) { 2687 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2688 return MCDisassembler::Fail; 2689 } else { 2690 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2691 return MCDisassembler::Fail; 2692 } 2693 2694 Inst.addOperand(MCOperand::CreateImm(imm)); 2695 2696 switch (Inst.getOpcode()) { 2697 case ARM::VORRiv4i16: 2698 case ARM::VORRiv2i32: 2699 case ARM::VBICiv4i16: 2700 case ARM::VBICiv2i32: 2701 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2702 return MCDisassembler::Fail; 2703 break; 2704 case ARM::VORRiv8i16: 2705 case ARM::VORRiv4i32: 2706 case ARM::VBICiv8i16: 2707 case ARM::VBICiv4i32: 2708 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2709 return MCDisassembler::Fail; 2710 break; 2711 default: 2712 break; 2713 } 2714 2715 return S; 2716} 2717 2718static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2719 uint64_t Address, const void *Decoder) { 2720 DecodeStatus S = MCDisassembler::Success; 2721 2722 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2723 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2724 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2725 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2726 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2727 2728 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2729 return MCDisassembler::Fail; 2730 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2731 return MCDisassembler::Fail; 2732 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2733 2734 return S; 2735} 2736 2737static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2738 uint64_t Address, const void *Decoder) { 2739 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2740 return MCDisassembler::Success; 2741} 2742 2743static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2744 uint64_t Address, const void *Decoder) { 2745 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2746 return MCDisassembler::Success; 2747} 2748 2749static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2750 uint64_t Address, const void *Decoder) { 2751 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2752 return MCDisassembler::Success; 2753} 2754 2755static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2756 uint64_t Address, const void *Decoder) { 2757 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2758 return MCDisassembler::Success; 2759} 2760 2761static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2762 uint64_t Address, const void *Decoder) { 2763 DecodeStatus S = MCDisassembler::Success; 2764 2765 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2766 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2767 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2768 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2769 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2770 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2771 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2772 2773 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2774 return MCDisassembler::Fail; 2775 if (op) { 2776 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2777 return MCDisassembler::Fail; // Writeback 2778 } 2779 2780 switch (Inst.getOpcode()) { 2781 case ARM::VTBL2: 2782 case ARM::VTBX2: 2783 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 2784 return MCDisassembler::Fail; 2785 break; 2786 default: 2787 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 } 2790 2791 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2792 return MCDisassembler::Fail; 2793 2794 return S; 2795} 2796 2797static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2798 uint64_t Address, const void *Decoder) { 2799 DecodeStatus S = MCDisassembler::Success; 2800 2801 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2802 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2803 2804 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2805 return MCDisassembler::Fail; 2806 2807 switch(Inst.getOpcode()) { 2808 default: 2809 return MCDisassembler::Fail; 2810 case ARM::tADR: 2811 break; // tADR does not explicitly represent the PC as an operand. 2812 case ARM::tADDrSPi: 2813 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2814 break; 2815 } 2816 2817 Inst.addOperand(MCOperand::CreateImm(imm)); 2818 return S; 2819} 2820 2821static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2822 uint64_t Address, const void *Decoder) { 2823 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2824 return MCDisassembler::Success; 2825} 2826 2827static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2828 uint64_t Address, const void *Decoder) { 2829 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2830 return MCDisassembler::Success; 2831} 2832 2833static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2834 uint64_t Address, const void *Decoder) { 2835 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2836 return MCDisassembler::Success; 2837} 2838 2839static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2840 uint64_t Address, const void *Decoder) { 2841 DecodeStatus S = MCDisassembler::Success; 2842 2843 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2844 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2845 2846 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2847 return MCDisassembler::Fail; 2848 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2849 return MCDisassembler::Fail; 2850 2851 return S; 2852} 2853 2854static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2855 uint64_t Address, const void *Decoder) { 2856 DecodeStatus S = MCDisassembler::Success; 2857 2858 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2859 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2860 2861 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2862 return MCDisassembler::Fail; 2863 Inst.addOperand(MCOperand::CreateImm(imm)); 2864 2865 return S; 2866} 2867 2868static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2869 uint64_t Address, const void *Decoder) { 2870 unsigned imm = Val << 2; 2871 2872 Inst.addOperand(MCOperand::CreateImm(imm)); 2873 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2874 2875 return MCDisassembler::Success; 2876} 2877 2878static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2879 uint64_t Address, const void *Decoder) { 2880 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2881 Inst.addOperand(MCOperand::CreateImm(Val)); 2882 2883 return MCDisassembler::Success; 2884} 2885 2886static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2887 uint64_t Address, const void *Decoder) { 2888 DecodeStatus S = MCDisassembler::Success; 2889 2890 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2891 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2892 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2893 2894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2895 return MCDisassembler::Fail; 2896 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2897 return MCDisassembler::Fail; 2898 Inst.addOperand(MCOperand::CreateImm(imm)); 2899 2900 return S; 2901} 2902 2903static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2904 uint64_t Address, const void *Decoder) { 2905 DecodeStatus S = MCDisassembler::Success; 2906 2907 switch (Inst.getOpcode()) { 2908 case ARM::t2PLDs: 2909 case ARM::t2PLDWs: 2910 case ARM::t2PLIs: 2911 break; 2912 default: { 2913 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2914 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2915 return MCDisassembler::Fail; 2916 } 2917 } 2918 2919 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2920 if (Rn == 0xF) { 2921 switch (Inst.getOpcode()) { 2922 case ARM::t2LDRBs: 2923 Inst.setOpcode(ARM::t2LDRBpci); 2924 break; 2925 case ARM::t2LDRHs: 2926 Inst.setOpcode(ARM::t2LDRHpci); 2927 break; 2928 case ARM::t2LDRSHs: 2929 Inst.setOpcode(ARM::t2LDRSHpci); 2930 break; 2931 case ARM::t2LDRSBs: 2932 Inst.setOpcode(ARM::t2LDRSBpci); 2933 break; 2934 case ARM::t2PLDs: 2935 Inst.setOpcode(ARM::t2PLDi12); 2936 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2937 break; 2938 default: 2939 return MCDisassembler::Fail; 2940 } 2941 2942 int imm = fieldFromInstruction32(Insn, 0, 12); 2943 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2944 Inst.addOperand(MCOperand::CreateImm(imm)); 2945 2946 return S; 2947 } 2948 2949 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2950 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2951 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2952 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2953 return MCDisassembler::Fail; 2954 2955 return S; 2956} 2957 2958static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2959 uint64_t Address, const void *Decoder) { 2960 int imm = Val & 0xFF; 2961 if (!(Val & 0x100)) imm *= -1; 2962 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2963 2964 return MCDisassembler::Success; 2965} 2966 2967static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2968 uint64_t Address, const void *Decoder) { 2969 DecodeStatus S = MCDisassembler::Success; 2970 2971 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2972 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2973 2974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2975 return MCDisassembler::Fail; 2976 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2977 return MCDisassembler::Fail; 2978 2979 return S; 2980} 2981 2982static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2983 uint64_t Address, const void *Decoder) { 2984 DecodeStatus S = MCDisassembler::Success; 2985 2986 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2987 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2988 2989 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2990 return MCDisassembler::Fail; 2991 2992 Inst.addOperand(MCOperand::CreateImm(imm)); 2993 2994 return S; 2995} 2996 2997static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2998 uint64_t Address, const void *Decoder) { 2999 int imm = Val & 0xFF; 3000 if (Val == 0) 3001 imm = INT32_MIN; 3002 else if (!(Val & 0x100)) 3003 imm *= -1; 3004 Inst.addOperand(MCOperand::CreateImm(imm)); 3005 3006 return MCDisassembler::Success; 3007} 3008 3009 3010static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 3011 uint64_t Address, const void *Decoder) { 3012 DecodeStatus S = MCDisassembler::Success; 3013 3014 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 3015 unsigned imm = fieldFromInstruction32(Val, 0, 9); 3016 3017 // Some instructions always use an additive offset. 3018 switch (Inst.getOpcode()) { 3019 case ARM::t2LDRT: 3020 case ARM::t2LDRBT: 3021 case ARM::t2LDRHT: 3022 case ARM::t2LDRSBT: 3023 case ARM::t2LDRSHT: 3024 case ARM::t2STRT: 3025 case ARM::t2STRBT: 3026 case ARM::t2STRHT: 3027 imm |= 0x100; 3028 break; 3029 default: 3030 break; 3031 } 3032 3033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3034 return MCDisassembler::Fail; 3035 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3036 return MCDisassembler::Fail; 3037 3038 return S; 3039} 3040 3041static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 3042 uint64_t Address, const void *Decoder) { 3043 DecodeStatus S = MCDisassembler::Success; 3044 3045 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3046 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3047 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3048 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 3049 addr |= Rn << 9; 3050 unsigned load = fieldFromInstruction32(Insn, 20, 1); 3051 3052 if (!load) { 3053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3054 return MCDisassembler::Fail; 3055 } 3056 3057 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3058 return MCDisassembler::Fail; 3059 3060 if (load) { 3061 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3062 return MCDisassembler::Fail; 3063 } 3064 3065 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3066 return MCDisassembler::Fail; 3067 3068 return S; 3069} 3070 3071static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 3072 uint64_t Address, const void *Decoder) { 3073 DecodeStatus S = MCDisassembler::Success; 3074 3075 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 3076 unsigned imm = fieldFromInstruction32(Val, 0, 12); 3077 3078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3079 return MCDisassembler::Fail; 3080 Inst.addOperand(MCOperand::CreateImm(imm)); 3081 3082 return S; 3083} 3084 3085 3086static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 3087 uint64_t Address, const void *Decoder) { 3088 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3089 3090 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3091 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3092 Inst.addOperand(MCOperand::CreateImm(imm)); 3093 3094 return MCDisassembler::Success; 3095} 3096 3097static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 3098 uint64_t Address, const void *Decoder) { 3099 DecodeStatus S = MCDisassembler::Success; 3100 3101 if (Inst.getOpcode() == ARM::tADDrSP) { 3102 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3103 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3104 3105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3108 return MCDisassembler::Fail; 3109 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3110 } else if (Inst.getOpcode() == ARM::tADDspr) { 3111 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3112 3113 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3114 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3115 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3116 return MCDisassembler::Fail; 3117 } 3118 3119 return S; 3120} 3121 3122static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 3123 uint64_t Address, const void *Decoder) { 3124 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3125 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3126 3127 Inst.addOperand(MCOperand::CreateImm(imod)); 3128 Inst.addOperand(MCOperand::CreateImm(flags)); 3129 3130 return MCDisassembler::Success; 3131} 3132 3133static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3134 uint64_t Address, const void *Decoder) { 3135 DecodeStatus S = MCDisassembler::Success; 3136 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3137 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3138 3139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3140 return MCDisassembler::Fail; 3141 Inst.addOperand(MCOperand::CreateImm(add)); 3142 3143 return S; 3144} 3145 3146static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3147 uint64_t Address, const void *Decoder) { 3148 if (!tryAddingSymbolicOperand(Address, 3149 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3150 true, 4, Inst, Decoder)) 3151 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3152 return MCDisassembler::Success; 3153} 3154 3155static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3156 uint64_t Address, const void *Decoder) { 3157 if (Val == 0xA || Val == 0xB) 3158 return MCDisassembler::Fail; 3159 3160 Inst.addOperand(MCOperand::CreateImm(Val)); 3161 return MCDisassembler::Success; 3162} 3163 3164static DecodeStatus 3165DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3166 uint64_t Address, const void *Decoder) { 3167 DecodeStatus S = MCDisassembler::Success; 3168 3169 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3170 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3171 3172 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3174 return MCDisassembler::Fail; 3175 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3176 return MCDisassembler::Fail; 3177 return S; 3178} 3179 3180static DecodeStatus 3181DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3182 uint64_t Address, const void *Decoder) { 3183 DecodeStatus S = MCDisassembler::Success; 3184 3185 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3186 if (pred == 0xE || pred == 0xF) { 3187 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3188 switch (opc) { 3189 default: 3190 return MCDisassembler::Fail; 3191 case 0xf3bf8f4: 3192 Inst.setOpcode(ARM::t2DSB); 3193 break; 3194 case 0xf3bf8f5: 3195 Inst.setOpcode(ARM::t2DMB); 3196 break; 3197 case 0xf3bf8f6: 3198 Inst.setOpcode(ARM::t2ISB); 3199 break; 3200 } 3201 3202 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3203 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3204 } 3205 3206 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3207 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3208 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3209 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3210 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3211 3212 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3213 return MCDisassembler::Fail; 3214 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3215 return MCDisassembler::Fail; 3216 3217 return S; 3218} 3219 3220// Decode a shifted immediate operand. These basically consist 3221// of an 8-bit value, and a 4-bit directive that specifies either 3222// a splat operation or a rotation. 3223static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3224 uint64_t Address, const void *Decoder) { 3225 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3226 if (ctrl == 0) { 3227 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3228 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3229 switch (byte) { 3230 case 0: 3231 Inst.addOperand(MCOperand::CreateImm(imm)); 3232 break; 3233 case 1: 3234 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3235 break; 3236 case 2: 3237 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3238 break; 3239 case 3: 3240 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3241 (imm << 8) | imm)); 3242 break; 3243 } 3244 } else { 3245 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3246 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3247 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3248 Inst.addOperand(MCOperand::CreateImm(imm)); 3249 } 3250 3251 return MCDisassembler::Success; 3252} 3253 3254static DecodeStatus 3255DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3256 uint64_t Address, const void *Decoder){ 3257 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3258 return MCDisassembler::Success; 3259} 3260 3261static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3262 uint64_t Address, const void *Decoder){ 3263 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3264 true, 4, Inst, Decoder)) 3265 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3266 return MCDisassembler::Success; 3267} 3268 3269static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3270 uint64_t Address, const void *Decoder) { 3271 switch (Val) { 3272 default: 3273 return MCDisassembler::Fail; 3274 case 0xF: // SY 3275 case 0xE: // ST 3276 case 0xB: // ISH 3277 case 0xA: // ISHST 3278 case 0x7: // NSH 3279 case 0x6: // NSHST 3280 case 0x3: // OSH 3281 case 0x2: // OSHST 3282 break; 3283 } 3284 3285 Inst.addOperand(MCOperand::CreateImm(Val)); 3286 return MCDisassembler::Success; 3287} 3288 3289static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3290 uint64_t Address, const void *Decoder) { 3291 if (!Val) return MCDisassembler::Fail; 3292 Inst.addOperand(MCOperand::CreateImm(Val)); 3293 return MCDisassembler::Success; 3294} 3295 3296static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3297 uint64_t Address, const void *Decoder) { 3298 DecodeStatus S = MCDisassembler::Success; 3299 3300 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3301 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3302 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3303 3304 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3305 3306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3307 return MCDisassembler::Fail; 3308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3309 return MCDisassembler::Fail; 3310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3311 return MCDisassembler::Fail; 3312 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3313 return MCDisassembler::Fail; 3314 3315 return S; 3316} 3317 3318 3319static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3320 uint64_t Address, const void *Decoder){ 3321 DecodeStatus S = MCDisassembler::Success; 3322 3323 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3324 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3325 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3326 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3327 3328 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3329 return MCDisassembler::Fail; 3330 3331 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3332 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3333 3334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3335 return MCDisassembler::Fail; 3336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3337 return MCDisassembler::Fail; 3338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3339 return MCDisassembler::Fail; 3340 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3341 return MCDisassembler::Fail; 3342 3343 return S; 3344} 3345 3346static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3347 uint64_t Address, const void *Decoder) { 3348 DecodeStatus S = MCDisassembler::Success; 3349 3350 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3351 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3352 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3353 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3354 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3355 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3356 3357 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3358 3359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3360 return MCDisassembler::Fail; 3361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3362 return MCDisassembler::Fail; 3363 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3364 return MCDisassembler::Fail; 3365 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 3368 return S; 3369} 3370 3371static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3372 uint64_t Address, const void *Decoder) { 3373 DecodeStatus S = MCDisassembler::Success; 3374 3375 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3376 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3377 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3378 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3379 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3380 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3381 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3382 3383 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3384 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3385 3386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3387 return MCDisassembler::Fail; 3388 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3389 return MCDisassembler::Fail; 3390 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3391 return MCDisassembler::Fail; 3392 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3393 return MCDisassembler::Fail; 3394 3395 return S; 3396} 3397 3398 3399static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3400 uint64_t Address, const void *Decoder) { 3401 DecodeStatus S = MCDisassembler::Success; 3402 3403 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3404 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3405 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3406 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3407 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3408 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3409 3410 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3411 3412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3413 return MCDisassembler::Fail; 3414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3415 return MCDisassembler::Fail; 3416 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3417 return MCDisassembler::Fail; 3418 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3419 return MCDisassembler::Fail; 3420 3421 return S; 3422} 3423 3424static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3425 uint64_t Address, const void *Decoder) { 3426 DecodeStatus S = MCDisassembler::Success; 3427 3428 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3429 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3430 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3431 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3432 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3433 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3434 3435 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3436 3437 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3438 return MCDisassembler::Fail; 3439 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3440 return MCDisassembler::Fail; 3441 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3444 return MCDisassembler::Fail; 3445 3446 return S; 3447} 3448 3449static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3450 uint64_t Address, const void *Decoder) { 3451 DecodeStatus S = MCDisassembler::Success; 3452 3453 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3454 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3455 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3456 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3457 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3458 3459 unsigned align = 0; 3460 unsigned index = 0; 3461 switch (size) { 3462 default: 3463 return MCDisassembler::Fail; 3464 case 0: 3465 if (fieldFromInstruction32(Insn, 4, 1)) 3466 return MCDisassembler::Fail; // UNDEFINED 3467 index = fieldFromInstruction32(Insn, 5, 3); 3468 break; 3469 case 1: 3470 if (fieldFromInstruction32(Insn, 5, 1)) 3471 return MCDisassembler::Fail; // UNDEFINED 3472 index = fieldFromInstruction32(Insn, 6, 2); 3473 if (fieldFromInstruction32(Insn, 4, 1)) 3474 align = 2; 3475 break; 3476 case 2: 3477 if (fieldFromInstruction32(Insn, 6, 1)) 3478 return MCDisassembler::Fail; // UNDEFINED 3479 index = fieldFromInstruction32(Insn, 7, 1); 3480 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3481 align = 4; 3482 } 3483 3484 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3485 return MCDisassembler::Fail; 3486 if (Rm != 0xF) { // Writeback 3487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3488 return MCDisassembler::Fail; 3489 } 3490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3491 return MCDisassembler::Fail; 3492 Inst.addOperand(MCOperand::CreateImm(align)); 3493 if (Rm != 0xF) { 3494 if (Rm != 0xD) { 3495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3496 return MCDisassembler::Fail; 3497 } else 3498 Inst.addOperand(MCOperand::CreateReg(0)); 3499 } 3500 3501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3502 return MCDisassembler::Fail; 3503 Inst.addOperand(MCOperand::CreateImm(index)); 3504 3505 return S; 3506} 3507 3508static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3509 uint64_t Address, const void *Decoder) { 3510 DecodeStatus S = MCDisassembler::Success; 3511 3512 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3513 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3514 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3515 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3516 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3517 3518 unsigned align = 0; 3519 unsigned index = 0; 3520 switch (size) { 3521 default: 3522 return MCDisassembler::Fail; 3523 case 0: 3524 if (fieldFromInstruction32(Insn, 4, 1)) 3525 return MCDisassembler::Fail; // UNDEFINED 3526 index = fieldFromInstruction32(Insn, 5, 3); 3527 break; 3528 case 1: 3529 if (fieldFromInstruction32(Insn, 5, 1)) 3530 return MCDisassembler::Fail; // UNDEFINED 3531 index = fieldFromInstruction32(Insn, 6, 2); 3532 if (fieldFromInstruction32(Insn, 4, 1)) 3533 align = 2; 3534 break; 3535 case 2: 3536 if (fieldFromInstruction32(Insn, 6, 1)) 3537 return MCDisassembler::Fail; // UNDEFINED 3538 index = fieldFromInstruction32(Insn, 7, 1); 3539 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3540 align = 4; 3541 } 3542 3543 if (Rm != 0xF) { // Writeback 3544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3545 return MCDisassembler::Fail; 3546 } 3547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3548 return MCDisassembler::Fail; 3549 Inst.addOperand(MCOperand::CreateImm(align)); 3550 if (Rm != 0xF) { 3551 if (Rm != 0xD) { 3552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3553 return MCDisassembler::Fail; 3554 } else 3555 Inst.addOperand(MCOperand::CreateReg(0)); 3556 } 3557 3558 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3559 return MCDisassembler::Fail; 3560 Inst.addOperand(MCOperand::CreateImm(index)); 3561 3562 return S; 3563} 3564 3565 3566static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3567 uint64_t Address, const void *Decoder) { 3568 DecodeStatus S = MCDisassembler::Success; 3569 3570 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3571 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3572 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3573 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3574 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3575 3576 unsigned align = 0; 3577 unsigned index = 0; 3578 unsigned inc = 1; 3579 switch (size) { 3580 default: 3581 return MCDisassembler::Fail; 3582 case 0: 3583 index = fieldFromInstruction32(Insn, 5, 3); 3584 if (fieldFromInstruction32(Insn, 4, 1)) 3585 align = 2; 3586 break; 3587 case 1: 3588 index = fieldFromInstruction32(Insn, 6, 2); 3589 if (fieldFromInstruction32(Insn, 4, 1)) 3590 align = 4; 3591 if (fieldFromInstruction32(Insn, 5, 1)) 3592 inc = 2; 3593 break; 3594 case 2: 3595 if (fieldFromInstruction32(Insn, 5, 1)) 3596 return MCDisassembler::Fail; // UNDEFINED 3597 index = fieldFromInstruction32(Insn, 7, 1); 3598 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3599 align = 8; 3600 if (fieldFromInstruction32(Insn, 6, 1)) 3601 inc = 2; 3602 break; 3603 } 3604 3605 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3606 return MCDisassembler::Fail; 3607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3608 return MCDisassembler::Fail; 3609 if (Rm != 0xF) { // Writeback 3610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3611 return MCDisassembler::Fail; 3612 } 3613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3614 return MCDisassembler::Fail; 3615 Inst.addOperand(MCOperand::CreateImm(align)); 3616 if (Rm != 0xF) { 3617 if (Rm != 0xD) { 3618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3619 return MCDisassembler::Fail; 3620 } else 3621 Inst.addOperand(MCOperand::CreateReg(0)); 3622 } 3623 3624 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3625 return MCDisassembler::Fail; 3626 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 Inst.addOperand(MCOperand::CreateImm(index)); 3629 3630 return S; 3631} 3632 3633static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3634 uint64_t Address, const void *Decoder) { 3635 DecodeStatus S = MCDisassembler::Success; 3636 3637 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3638 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3639 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3640 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3641 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3642 3643 unsigned align = 0; 3644 unsigned index = 0; 3645 unsigned inc = 1; 3646 switch (size) { 3647 default: 3648 return MCDisassembler::Fail; 3649 case 0: 3650 index = fieldFromInstruction32(Insn, 5, 3); 3651 if (fieldFromInstruction32(Insn, 4, 1)) 3652 align = 2; 3653 break; 3654 case 1: 3655 index = fieldFromInstruction32(Insn, 6, 2); 3656 if (fieldFromInstruction32(Insn, 4, 1)) 3657 align = 4; 3658 if (fieldFromInstruction32(Insn, 5, 1)) 3659 inc = 2; 3660 break; 3661 case 2: 3662 if (fieldFromInstruction32(Insn, 5, 1)) 3663 return MCDisassembler::Fail; // UNDEFINED 3664 index = fieldFromInstruction32(Insn, 7, 1); 3665 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3666 align = 8; 3667 if (fieldFromInstruction32(Insn, 6, 1)) 3668 inc = 2; 3669 break; 3670 } 3671 3672 if (Rm != 0xF) { // Writeback 3673 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3674 return MCDisassembler::Fail; 3675 } 3676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3677 return MCDisassembler::Fail; 3678 Inst.addOperand(MCOperand::CreateImm(align)); 3679 if (Rm != 0xF) { 3680 if (Rm != 0xD) { 3681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3682 return MCDisassembler::Fail; 3683 } else 3684 Inst.addOperand(MCOperand::CreateReg(0)); 3685 } 3686 3687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3688 return MCDisassembler::Fail; 3689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 Inst.addOperand(MCOperand::CreateImm(index)); 3692 3693 return S; 3694} 3695 3696 3697static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3698 uint64_t Address, const void *Decoder) { 3699 DecodeStatus S = MCDisassembler::Success; 3700 3701 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3702 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3703 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3704 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3705 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3706 3707 unsigned align = 0; 3708 unsigned index = 0; 3709 unsigned inc = 1; 3710 switch (size) { 3711 default: 3712 return MCDisassembler::Fail; 3713 case 0: 3714 if (fieldFromInstruction32(Insn, 4, 1)) 3715 return MCDisassembler::Fail; // UNDEFINED 3716 index = fieldFromInstruction32(Insn, 5, 3); 3717 break; 3718 case 1: 3719 if (fieldFromInstruction32(Insn, 4, 1)) 3720 return MCDisassembler::Fail; // UNDEFINED 3721 index = fieldFromInstruction32(Insn, 6, 2); 3722 if (fieldFromInstruction32(Insn, 5, 1)) 3723 inc = 2; 3724 break; 3725 case 2: 3726 if (fieldFromInstruction32(Insn, 4, 2)) 3727 return MCDisassembler::Fail; // UNDEFINED 3728 index = fieldFromInstruction32(Insn, 7, 1); 3729 if (fieldFromInstruction32(Insn, 6, 1)) 3730 inc = 2; 3731 break; 3732 } 3733 3734 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3735 return MCDisassembler::Fail; 3736 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3737 return MCDisassembler::Fail; 3738 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3739 return MCDisassembler::Fail; 3740 3741 if (Rm != 0xF) { // Writeback 3742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3743 return MCDisassembler::Fail; 3744 } 3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3746 return MCDisassembler::Fail; 3747 Inst.addOperand(MCOperand::CreateImm(align)); 3748 if (Rm != 0xF) { 3749 if (Rm != 0xD) { 3750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3751 return MCDisassembler::Fail; 3752 } else 3753 Inst.addOperand(MCOperand::CreateReg(0)); 3754 } 3755 3756 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3757 return MCDisassembler::Fail; 3758 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3759 return MCDisassembler::Fail; 3760 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3761 return MCDisassembler::Fail; 3762 Inst.addOperand(MCOperand::CreateImm(index)); 3763 3764 return S; 3765} 3766 3767static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3768 uint64_t Address, const void *Decoder) { 3769 DecodeStatus S = MCDisassembler::Success; 3770 3771 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3772 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3773 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3774 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3775 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3776 3777 unsigned align = 0; 3778 unsigned index = 0; 3779 unsigned inc = 1; 3780 switch (size) { 3781 default: 3782 return MCDisassembler::Fail; 3783 case 0: 3784 if (fieldFromInstruction32(Insn, 4, 1)) 3785 return MCDisassembler::Fail; // UNDEFINED 3786 index = fieldFromInstruction32(Insn, 5, 3); 3787 break; 3788 case 1: 3789 if (fieldFromInstruction32(Insn, 4, 1)) 3790 return MCDisassembler::Fail; // UNDEFINED 3791 index = fieldFromInstruction32(Insn, 6, 2); 3792 if (fieldFromInstruction32(Insn, 5, 1)) 3793 inc = 2; 3794 break; 3795 case 2: 3796 if (fieldFromInstruction32(Insn, 4, 2)) 3797 return MCDisassembler::Fail; // UNDEFINED 3798 index = fieldFromInstruction32(Insn, 7, 1); 3799 if (fieldFromInstruction32(Insn, 6, 1)) 3800 inc = 2; 3801 break; 3802 } 3803 3804 if (Rm != 0xF) { // Writeback 3805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3806 return MCDisassembler::Fail; 3807 } 3808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3809 return MCDisassembler::Fail; 3810 Inst.addOperand(MCOperand::CreateImm(align)); 3811 if (Rm != 0xF) { 3812 if (Rm != 0xD) { 3813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3814 return MCDisassembler::Fail; 3815 } else 3816 Inst.addOperand(MCOperand::CreateReg(0)); 3817 } 3818 3819 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3820 return MCDisassembler::Fail; 3821 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3822 return MCDisassembler::Fail; 3823 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3824 return MCDisassembler::Fail; 3825 Inst.addOperand(MCOperand::CreateImm(index)); 3826 3827 return S; 3828} 3829 3830 3831static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3832 uint64_t Address, const void *Decoder) { 3833 DecodeStatus S = MCDisassembler::Success; 3834 3835 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3836 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3837 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3838 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3839 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3840 3841 unsigned align = 0; 3842 unsigned index = 0; 3843 unsigned inc = 1; 3844 switch (size) { 3845 default: 3846 return MCDisassembler::Fail; 3847 case 0: 3848 if (fieldFromInstruction32(Insn, 4, 1)) 3849 align = 4; 3850 index = fieldFromInstruction32(Insn, 5, 3); 3851 break; 3852 case 1: 3853 if (fieldFromInstruction32(Insn, 4, 1)) 3854 align = 8; 3855 index = fieldFromInstruction32(Insn, 6, 2); 3856 if (fieldFromInstruction32(Insn, 5, 1)) 3857 inc = 2; 3858 break; 3859 case 2: 3860 if (fieldFromInstruction32(Insn, 4, 2)) 3861 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3862 index = fieldFromInstruction32(Insn, 7, 1); 3863 if (fieldFromInstruction32(Insn, 6, 1)) 3864 inc = 2; 3865 break; 3866 } 3867 3868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3869 return MCDisassembler::Fail; 3870 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3871 return MCDisassembler::Fail; 3872 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3873 return MCDisassembler::Fail; 3874 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3875 return MCDisassembler::Fail; 3876 3877 if (Rm != 0xF) { // Writeback 3878 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3879 return MCDisassembler::Fail; 3880 } 3881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3882 return MCDisassembler::Fail; 3883 Inst.addOperand(MCOperand::CreateImm(align)); 3884 if (Rm != 0xF) { 3885 if (Rm != 0xD) { 3886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3887 return MCDisassembler::Fail; 3888 } else 3889 Inst.addOperand(MCOperand::CreateReg(0)); 3890 } 3891 3892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3893 return MCDisassembler::Fail; 3894 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3895 return MCDisassembler::Fail; 3896 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3897 return MCDisassembler::Fail; 3898 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3899 return MCDisassembler::Fail; 3900 Inst.addOperand(MCOperand::CreateImm(index)); 3901 3902 return S; 3903} 3904 3905static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3906 uint64_t Address, const void *Decoder) { 3907 DecodeStatus S = MCDisassembler::Success; 3908 3909 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3910 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3911 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3912 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3913 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3914 3915 unsigned align = 0; 3916 unsigned index = 0; 3917 unsigned inc = 1; 3918 switch (size) { 3919 default: 3920 return MCDisassembler::Fail; 3921 case 0: 3922 if (fieldFromInstruction32(Insn, 4, 1)) 3923 align = 4; 3924 index = fieldFromInstruction32(Insn, 5, 3); 3925 break; 3926 case 1: 3927 if (fieldFromInstruction32(Insn, 4, 1)) 3928 align = 8; 3929 index = fieldFromInstruction32(Insn, 6, 2); 3930 if (fieldFromInstruction32(Insn, 5, 1)) 3931 inc = 2; 3932 break; 3933 case 2: 3934 if (fieldFromInstruction32(Insn, 4, 2)) 3935 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3936 index = fieldFromInstruction32(Insn, 7, 1); 3937 if (fieldFromInstruction32(Insn, 6, 1)) 3938 inc = 2; 3939 break; 3940 } 3941 3942 if (Rm != 0xF) { // Writeback 3943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3944 return MCDisassembler::Fail; 3945 } 3946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3947 return MCDisassembler::Fail; 3948 Inst.addOperand(MCOperand::CreateImm(align)); 3949 if (Rm != 0xF) { 3950 if (Rm != 0xD) { 3951 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3952 return MCDisassembler::Fail; 3953 } else 3954 Inst.addOperand(MCOperand::CreateReg(0)); 3955 } 3956 3957 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3958 return MCDisassembler::Fail; 3959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3960 return MCDisassembler::Fail; 3961 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3962 return MCDisassembler::Fail; 3963 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3964 return MCDisassembler::Fail; 3965 Inst.addOperand(MCOperand::CreateImm(index)); 3966 3967 return S; 3968} 3969 3970static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3971 uint64_t Address, const void *Decoder) { 3972 DecodeStatus S = MCDisassembler::Success; 3973 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3974 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3975 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3976 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3977 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3978 3979 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3980 S = MCDisassembler::SoftFail; 3981 3982 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3983 return MCDisassembler::Fail; 3984 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3985 return MCDisassembler::Fail; 3986 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3987 return MCDisassembler::Fail; 3988 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3989 return MCDisassembler::Fail; 3990 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3991 return MCDisassembler::Fail; 3992 3993 return S; 3994} 3995 3996static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3997 uint64_t Address, const void *Decoder) { 3998 DecodeStatus S = MCDisassembler::Success; 3999 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4000 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 4001 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 4002 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4003 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 4004 4005 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4006 S = MCDisassembler::SoftFail; 4007 4008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4009 return MCDisassembler::Fail; 4010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4011 return MCDisassembler::Fail; 4012 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4013 return MCDisassembler::Fail; 4014 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4015 return MCDisassembler::Fail; 4016 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4017 return MCDisassembler::Fail; 4018 4019 return S; 4020} 4021 4022static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 4023 uint64_t Address, const void *Decoder) { 4024 DecodeStatus S = MCDisassembler::Success; 4025 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 4026 // The InstPrinter needs to have the low bit of the predicate in 4027 // the mask operand to be able to print it properly. 4028 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 4029 4030 if (pred == 0xF) { 4031 pred = 0xE; 4032 S = MCDisassembler::SoftFail; 4033 } 4034 4035 if ((mask & 0xF) == 0) { 4036 // Preserve the high bit of the mask, which is the low bit of 4037 // the predicate. 4038 mask &= 0x10; 4039 mask |= 0x8; 4040 S = MCDisassembler::SoftFail; 4041 } 4042 4043 Inst.addOperand(MCOperand::CreateImm(pred)); 4044 Inst.addOperand(MCOperand::CreateImm(mask)); 4045 return S; 4046} 4047 4048static DecodeStatus 4049DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 4050 uint64_t Address, const void *Decoder) { 4051 DecodeStatus S = MCDisassembler::Success; 4052 4053 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4054 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4055 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4056 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4057 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4058 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4059 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4060 bool writeback = (W == 1) | (P == 0); 4061 4062 addr |= (U << 8) | (Rn << 9); 4063 4064 if (writeback && (Rn == Rt || Rn == Rt2)) 4065 Check(S, MCDisassembler::SoftFail); 4066 if (Rt == Rt2) 4067 Check(S, MCDisassembler::SoftFail); 4068 4069 // Rt 4070 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4071 return MCDisassembler::Fail; 4072 // Rt2 4073 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4074 return MCDisassembler::Fail; 4075 // Writeback operand 4076 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4077 return MCDisassembler::Fail; 4078 // addr 4079 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4080 return MCDisassembler::Fail; 4081 4082 return S; 4083} 4084 4085static DecodeStatus 4086DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 4087 uint64_t Address, const void *Decoder) { 4088 DecodeStatus S = MCDisassembler::Success; 4089 4090 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4091 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4092 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4093 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4094 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4095 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4096 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4097 bool writeback = (W == 1) | (P == 0); 4098 4099 addr |= (U << 8) | (Rn << 9); 4100 4101 if (writeback && (Rn == Rt || Rn == Rt2)) 4102 Check(S, MCDisassembler::SoftFail); 4103 4104 // Writeback operand 4105 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4106 return MCDisassembler::Fail; 4107 // Rt 4108 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4109 return MCDisassembler::Fail; 4110 // Rt2 4111 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4112 return MCDisassembler::Fail; 4113 // addr 4114 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4115 return MCDisassembler::Fail; 4116 4117 return S; 4118} 4119 4120static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 4121 uint64_t Address, const void *Decoder) { 4122 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4123 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4124 if (sign1 != sign2) return MCDisassembler::Fail; 4125 4126 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4127 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4128 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4129 Val |= sign1 << 12; 4130 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4131 4132 return MCDisassembler::Success; 4133} 4134 4135static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4136 uint64_t Address, 4137 const void *Decoder) { 4138 DecodeStatus S = MCDisassembler::Success; 4139 4140 // Shift of "asr #32" is not allowed in Thumb2 mode. 4141 if (Val == 0x20) S = MCDisassembler::SoftFail; 4142 Inst.addOperand(MCOperand::CreateImm(Val)); 4143 return S; 4144} 4145 4146static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 4147 uint64_t Address, const void *Decoder) { 4148 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4149 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4150 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4151 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4152 4153 if (pred == 0xF) 4154 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4155 4156 DecodeStatus S = MCDisassembler::Success; 4157 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4158 return MCDisassembler::Fail; 4159 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4160 return MCDisassembler::Fail; 4161 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4162 return MCDisassembler::Fail; 4163 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4164 return MCDisassembler::Fail; 4165 4166 return S; 4167} 4168 4169static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 4170 uint64_t Address, const void *Decoder) { 4171 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4172 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4173 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4174 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4175 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4176 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4177 4178 DecodeStatus S = MCDisassembler::Success; 4179 4180 // VMOVv2f32 is ambiguous with these decodings. 4181 if (!(imm & 0x38) && cmode == 0xF) { 4182 Inst.setOpcode(ARM::VMOVv2f32); 4183 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4184 } 4185 4186 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4187 4188 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4189 return MCDisassembler::Fail; 4190 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4191 return MCDisassembler::Fail; 4192 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4193 4194 return S; 4195} 4196 4197static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 4198 uint64_t Address, const void *Decoder) { 4199 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4200 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4201 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4202 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4203 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4204 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4205 4206 DecodeStatus S = MCDisassembler::Success; 4207 4208 // VMOVv4f32 is ambiguous with these decodings. 4209 if (!(imm & 0x38) && cmode == 0xF) { 4210 Inst.setOpcode(ARM::VMOVv4f32); 4211 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4212 } 4213 4214 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4215 4216 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4217 return MCDisassembler::Fail; 4218 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4219 return MCDisassembler::Fail; 4220 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4221 4222 return S; 4223} 4224