ARMDisassembler.cpp revision cdcfa280568d5d48ebeba2dcfc87915105e090d1 
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE "arm-disassembler"
11
12#include "ARM.h"
13#include "ARMRegisterInfo.h"
14#include "ARMSubtarget.h"
15#include "MCTargetDesc/ARMAddressingModes.h"
16#include "MCTargetDesc/ARMMCExpr.h"
17#include "MCTargetDesc/ARMBaseInfo.h"
18#include "llvm/MC/EDInstInfo.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCDisassembler.h"
23#include "llvm/Support/Debug.h"
24#include "llvm/Support/MemoryObject.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/TargetRegistry.h"
27#include "llvm/Support/raw_ostream.h"
28
29using namespace llvm;
30
31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
33namespace {
34/// ARMDisassembler - ARM disassembler for all ARM platforms.
35class ARMDisassembler : public MCDisassembler {
36public:
37  /// Constructor     - Initializes the disassembler.
38  ///
39  ARMDisassembler(const MCSubtargetInfo &STI) :
40    MCDisassembler(STI) {
41  }
42
43  ~ARMDisassembler() {
44  }
45
46  /// getInstruction - See MCDisassembler.
47  DecodeStatus getInstruction(MCInst &instr,
48                              uint64_t &size,
49                              const MemoryObject &region,
50                              uint64_t address,
51                              raw_ostream &vStream,
52                              raw_ostream &cStream) const;
53
54  /// getEDInfo - See MCDisassembler.
55  EDInstInfo *getEDInfo() const;
56private:
57};
58
59/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60class ThumbDisassembler : public MCDisassembler {
61public:
62  /// Constructor     - Initializes the disassembler.
63  ///
64  ThumbDisassembler(const MCSubtargetInfo &STI) :
65    MCDisassembler(STI) {
66  }
67
68  ~ThumbDisassembler() {
69  }
70
71  /// getInstruction - See MCDisassembler.
72  DecodeStatus getInstruction(MCInst &instr,
73                              uint64_t &size,
74                              const MemoryObject &region,
75                              uint64_t address,
76                              raw_ostream &vStream,
77                              raw_ostream &cStream) const;
78
79  /// getEDInfo - See MCDisassembler.
80  EDInstInfo *getEDInfo() const;
81private:
82  mutable std::vector<unsigned> ITBlock;
83  DecodeStatus AddThumbPredicate(MCInst&) const;
84  void UpdateThumbVFPPredicate(MCInst&) const;
85};
86}
87
88static bool Check(DecodeStatus &Out, DecodeStatus In) {
89  switch (In) {
90    case MCDisassembler::Success:
91      // Out stays the same.
92      return true;
93    case MCDisassembler::SoftFail:
94      Out = In;
95      return true;
96    case MCDisassembler::Fail:
97      Out = In;
98      return false;
99  }
100  return false;
101}
102
103
104// Forward declare these because the autogenerated code will reference them.
105// Definitions are further down.
106static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
107                                   uint64_t Address, const void *Decoder);
108static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
109                                               unsigned RegNo, uint64_t Address,
110                                               const void *Decoder);
111static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
112                                   uint64_t Address, const void *Decoder);
113static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
114                                   uint64_t Address, const void *Decoder);
115static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
116                                   uint64_t Address, const void *Decoder);
117static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
118                                   uint64_t Address, const void *Decoder);
119static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
120                                   uint64_t Address, const void *Decoder);
121static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
122                                   uint64_t Address, const void *Decoder);
123static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
124                                                unsigned RegNo,
125                                                uint64_t Address,
126                                                const void *Decoder);
127static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
128                                   uint64_t Address, const void *Decoder);
129
130static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
131                               uint64_t Address, const void *Decoder);
132static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
133                               uint64_t Address, const void *Decoder);
134static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
135                               uint64_t Address, const void *Decoder);
136static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
137                               uint64_t Address, const void *Decoder);
138static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
139                               uint64_t Address, const void *Decoder);
140static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
141                               uint64_t Address, const void *Decoder);
142
143static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
144                               uint64_t Address, const void *Decoder);
145static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
146                               uint64_t Address, const void *Decoder);
147static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
148                                                  unsigned Insn,
149                                                  uint64_t Address,
150                                                  const void *Decoder);
151static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
152                               uint64_t Address, const void *Decoder);
153static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
154                               uint64_t Address, const void *Decoder);
155static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
156                               uint64_t Address, const void *Decoder);
157static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
158                               uint64_t Address, const void *Decoder);
159
160static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
161                                                  unsigned Insn,
162                                                  uint64_t Adddress,
163                                                  const void *Decoder);
164static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165                               uint64_t Address, const void *Decoder);
166static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167                               uint64_t Address, const void *Decoder);
168static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
169                               uint64_t Address, const void *Decoder);
170static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
171                               uint64_t Address, const void *Decoder);
172static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
173                               uint64_t Address, const void *Decoder);
174static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
175                               uint64_t Address, const void *Decoder);
176static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
177                               uint64_t Address, const void *Decoder);
178static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
179                               uint64_t Address, const void *Decoder);
180static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
181                               uint64_t Address, const void *Decoder);
182static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
183                               uint64_t Address, const void *Decoder);
184static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
185                               uint64_t Address, const void *Decoder);
186static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
187                               uint64_t Address, const void *Decoder);
188static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
189                               uint64_t Address, const void *Decoder);
190static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
191                               uint64_t Address, const void *Decoder);
192static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
193                               uint64_t Address, const void *Decoder);
194static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
195                               uint64_t Address, const void *Decoder);
196static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
197                               uint64_t Address, const void *Decoder);
198static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
199                               uint64_t Address, const void *Decoder);
200static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
201                               uint64_t Address, const void *Decoder);
202static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
203                               uint64_t Address, const void *Decoder);
204static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
205                               uint64_t Address, const void *Decoder);
206static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
207                               uint64_t Address, const void *Decoder);
208static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
209                               uint64_t Address, const void *Decoder);
210static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
211                               uint64_t Address, const void *Decoder);
212static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
213                               uint64_t Address, const void *Decoder);
214static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
215                               uint64_t Address, const void *Decoder);
216static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
217                               uint64_t Address, const void *Decoder);
218static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
219                               uint64_t Address, const void *Decoder);
220static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
221                               uint64_t Address, const void *Decoder);
222static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
223                               uint64_t Address, const void *Decoder);
224static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
225                               uint64_t Address, const void *Decoder);
226static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
227                               uint64_t Address, const void *Decoder);
228static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
229                               uint64_t Address, const void *Decoder);
230static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
231                               uint64_t Address, const void *Decoder);
232static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
233                               uint64_t Address, const void *Decoder);
234static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
235                               uint64_t Address, const void *Decoder);
236static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
237                               uint64_t Address, const void *Decoder);
238static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
239                               uint64_t Address, const void *Decoder);
240static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
241                               uint64_t Address, const void *Decoder);
242static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
243                               uint64_t Address, const void *Decoder);
244static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
245                               uint64_t Address, const void *Decoder);
246static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
247                               uint64_t Address, const void *Decoder);
248static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
249                               uint64_t Address, const void *Decoder);
250static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
251                               uint64_t Address, const void *Decoder);
252
253static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
254                               uint64_t Address, const void *Decoder);
255static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
256                               uint64_t Address, const void *Decoder);
257static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
258                               uint64_t Address, const void *Decoder);
259static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
260                               uint64_t Address, const void *Decoder);
261static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
262                               uint64_t Address, const void *Decoder);
263static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
264                               uint64_t Address, const void *Decoder);
265static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
266                               uint64_t Address, const void *Decoder);
267static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
268                               uint64_t Address, const void *Decoder);
269static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
270                               uint64_t Address, const void *Decoder);
271static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
272                               uint64_t Address, const void *Decoder);
273static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
274                               uint64_t Address, const void *Decoder);
275static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
276                               uint64_t Address, const void *Decoder);
277static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
278                               uint64_t Address, const void *Decoder);
279static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
280                               uint64_t Address, const void *Decoder);
281static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
282                               uint64_t Address, const void *Decoder);
283static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
284                               uint64_t Address, const void *Decoder);
285static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
286                                uint64_t Address, const void *Decoder);
287static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
288                                uint64_t Address, const void *Decoder);
289static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
290                                uint64_t Address, const void *Decoder);
291static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
292                                uint64_t Address, const void *Decoder);
293static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
294                                uint64_t Address, const void *Decoder);
295static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
296                                uint64_t Address, const void *Decoder);
297static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
298                                uint64_t Address, const void *Decoder);
299static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
300                                uint64_t Address, const void *Decoder);
301static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
302                                uint64_t Address, const void *Decoder);
303static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
304                                uint64_t Address, const void *Decoder);
305static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
306                               uint64_t Address, const void *Decoder);
307static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
308                               uint64_t Address, const void *Decoder);
309static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
310                                uint64_t Address, const void *Decoder);
311static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
312                                uint64_t Address, const void *Decoder);
313static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
314                                uint64_t Address, const void *Decoder);
315
316
317
318#include "ARMGenDisassemblerTables.inc"
319#include "ARMGenInstrInfo.inc"
320#include "ARMGenEDInfo.inc"
321
322static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
323  return new ARMDisassembler(STI);
324}
325
326static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
327  return new ThumbDisassembler(STI);
328}
329
330EDInstInfo *ARMDisassembler::getEDInfo() const {
331  return instInfoARM;
332}
333
334EDInstInfo *ThumbDisassembler::getEDInfo() const {
335  return instInfoARM;
336}
337
338DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
339                                             const MemoryObject &Region,
340                                             uint64_t Address,
341                                             raw_ostream &os,
342                                             raw_ostream &cs) const {
343  CommentStream = &cs;
344
345  uint8_t bytes[4];
346
347  assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
348         "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
349
350  // We want to read exactly 4 bytes of data.
351  if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
352    Size = 0;
353    return MCDisassembler::Fail;
354  }
355
356  // Encoded as a small-endian 32-bit word in the stream.
357  uint32_t insn = (bytes[3] << 24) |
358                  (bytes[2] << 16) |
359                  (bytes[1] <<  8) |
360                  (bytes[0] <<  0);
361
362  // Calling the auto-generated decoder function.
363  DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
364  if (result != MCDisassembler::Fail) {
365    Size = 4;
366    return result;
367  }
368
369  // VFP and NEON instructions, similarly, are shared between ARM
370  // and Thumb modes.
371  MI.clear();
372  result = decodeVFPInstruction32(MI, insn, Address, this, STI);
373  if (result != MCDisassembler::Fail) {
374    Size = 4;
375    return result;
376  }
377
378  MI.clear();
379  result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
380  if (result != MCDisassembler::Fail) {
381    Size = 4;
382    // Add a fake predicate operand, because we share these instruction
383    // definitions with Thumb2 where these instructions are predicable.
384    if (!DecodePredicateOperand(MI, 0xE, Address, this))
385      return MCDisassembler::Fail;
386    return result;
387  }
388
389  MI.clear();
390  result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
391  if (result != MCDisassembler::Fail) {
392    Size = 4;
393    // Add a fake predicate operand, because we share these instruction
394    // definitions with Thumb2 where these instructions are predicable.
395    if (!DecodePredicateOperand(MI, 0xE, Address, this))
396      return MCDisassembler::Fail;
397    return result;
398  }
399
400  MI.clear();
401  result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
402  if (result != MCDisassembler::Fail) {
403    Size = 4;
404    // Add a fake predicate operand, because we share these instruction
405    // definitions with Thumb2 where these instructions are predicable.
406    if (!DecodePredicateOperand(MI, 0xE, Address, this))
407      return MCDisassembler::Fail;
408    return result;
409  }
410
411  MI.clear();
412
413  Size = 0;
414  return MCDisassembler::Fail;
415}
416
417namespace llvm {
418extern MCInstrDesc ARMInsts[];
419}
420
421/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
422/// immediate Value in the MCInst.  The immediate Value has had any PC
423/// adjustment made by the caller.  If the instruction is a branch instruction
424/// then isBranch is true, else false.  If the getOpInfo() function was set as
425/// part of the setupForSymbolicDisassembly() call then that function is called
426/// to get any symbolic information at the Address for this instruction.  If
427/// that returns non-zero then the symbolic information it returns is used to
428/// create an MCExpr and that is added as an operand to the MCInst.  If
429/// getOpInfo() returns zero and isBranch is true then a symbol look up for
430/// Value is done and if a symbol is found an MCExpr is created with that, else
431/// an MCExpr with Value is created.  This function returns true if it adds an
432/// operand to the MCInst and false otherwise.
433static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
434                                     bool isBranch, uint64_t InstSize,
435                                     MCInst &MI, const void *Decoder) {
436  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
437  LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
438  if (!getOpInfo)
439    return false;
440
441  struct LLVMOpInfo1 SymbolicOp;
442  SymbolicOp.Value = Value;
443  void *DisInfo = Dis->getDisInfoBlock();
444  if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
445    if (isBranch) {
446      LLVMSymbolLookupCallback SymbolLookUp =
447                                            Dis->getLLVMSymbolLookupCallback();
448      if (SymbolLookUp) {
449        uint64_t ReferenceType;
450        ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
451        const char *ReferenceName;
452        const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
453                                        &ReferenceName);
454        if (Name) {
455          SymbolicOp.AddSymbol.Name = Name;
456          SymbolicOp.AddSymbol.Present = true;
457          SymbolicOp.Value = 0;
458        }
459        else {
460          SymbolicOp.Value = Value;
461        }
462        if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
463          (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
464      }
465      else {
466        return false;
467      }
468    }
469    else {
470      return false;
471    }
472  }
473
474  MCContext *Ctx = Dis->getMCContext();
475  const MCExpr *Add = NULL;
476  if (SymbolicOp.AddSymbol.Present) {
477    if (SymbolicOp.AddSymbol.Name) {
478      StringRef Name(SymbolicOp.AddSymbol.Name);
479      MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
480      Add = MCSymbolRefExpr::Create(Sym, *Ctx);
481    } else {
482      Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
483    }
484  }
485
486  const MCExpr *Sub = NULL;
487  if (SymbolicOp.SubtractSymbol.Present) {
488    if (SymbolicOp.SubtractSymbol.Name) {
489      StringRef Name(SymbolicOp.SubtractSymbol.Name);
490      MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
491      Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
492    } else {
493      Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
494    }
495  }
496
497  const MCExpr *Off = NULL;
498  if (SymbolicOp.Value != 0)
499    Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
500
501  const MCExpr *Expr;
502  if (Sub) {
503    const MCExpr *LHS;
504    if (Add)
505      LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
506    else
507      LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
508    if (Off != 0)
509      Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
510    else
511      Expr = LHS;
512  } else if (Add) {
513    if (Off != 0)
514      Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
515    else
516      Expr = Add;
517  } else {
518    if (Off != 0)
519      Expr = Off;
520    else
521      Expr = MCConstantExpr::Create(0, *Ctx);
522  }
523
524  if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
525    MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
526  else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
527    MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
528  else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
529    MI.addOperand(MCOperand::CreateExpr(Expr));
530  else
531    assert(0 && "bad SymbolicOp.VariantKind");
532
533  return true;
534}
535
536/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
537/// referenced by a load instruction with the base register that is the Pc.
538/// These can often be values in a literal pool near the Address of the
539/// instruction.  The Address of the instruction and its immediate Value are
540/// used as a possible literal pool entry.  The SymbolLookUp call back will
541/// return the name of a symbol referenced by the the literal pool's entry if
542/// the referenced address is that of a symbol.  Or it will return a pointer to
543/// a literal 'C' string if the referenced address of the literal pool's entry
544/// is an address into a section with 'C' string literals.
545static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
546					    const void *Decoder) {
547  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
548  LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
549  if (SymbolLookUp) {
550    void *DisInfo = Dis->getDisInfoBlock();
551    uint64_t ReferenceType;
552    ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
553    const char *ReferenceName;
554    (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
555    if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
556       ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
557      (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
558  }
559}
560
561// Thumb1 instructions don't have explicit S bits.  Rather, they
562// implicitly set CPSR.  Since it's not represented in the encoding, the
563// auto-generated decoder won't inject the CPSR operand.  We need to fix
564// that as a post-pass.
565static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
566  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
567  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
568  MCInst::iterator I = MI.begin();
569  for (unsigned i = 0; i < NumOps; ++i, ++I) {
570    if (I == MI.end()) break;
571    if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
572      if (i > 0 && OpInfo[i-1].isPredicate()) continue;
573      MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
574      return;
575    }
576  }
577
578  MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
579}
580
581// Most Thumb instructions don't have explicit predicates in the
582// encoding, but rather get their predicates from IT context.  We need
583// to fix up the predicate operands using this context information as a
584// post-pass.
585MCDisassembler::DecodeStatus
586ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
587  MCDisassembler::DecodeStatus S = Success;
588
589  // A few instructions actually have predicates encoded in them.  Don't
590  // try to overwrite it if we're seeing one of those.
591  switch (MI.getOpcode()) {
592    case ARM::tBcc:
593    case ARM::t2Bcc:
594    case ARM::tCBZ:
595    case ARM::tCBNZ:
596    case ARM::tCPS:
597    case ARM::t2CPS3p:
598    case ARM::t2CPS2p:
599    case ARM::t2CPS1p:
600    case ARM::tMOVSr:
601    case ARM::tSETEND:
602      // Some instructions (mostly conditional branches) are not
603      // allowed in IT blocks.
604      if (!ITBlock.empty())
605        S = SoftFail;
606      else
607        return Success;
608      break;
609    case ARM::tB:
610    case ARM::t2B:
611    case ARM::t2TBB:
612    case ARM::t2TBH:
613      // Some instructions (mostly unconditional branches) can
614      // only appears at the end of, or outside of, an IT.
615      if (ITBlock.size() > 1)
616        S = SoftFail;
617      break;
618    default:
619      break;
620  }
621
622  // If we're in an IT block, base the predicate on that.  Otherwise,
623  // assume a predicate of AL.
624  unsigned CC;
625  if (!ITBlock.empty()) {
626    CC = ITBlock.back();
627    if (CC == 0xF)
628      CC = ARMCC::AL;
629    ITBlock.pop_back();
630  } else
631    CC = ARMCC::AL;
632
633  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
634  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
635  MCInst::iterator I = MI.begin();
636  for (unsigned i = 0; i < NumOps; ++i, ++I) {
637    if (I == MI.end()) break;
638    if (OpInfo[i].isPredicate()) {
639      I = MI.insert(I, MCOperand::CreateImm(CC));
640      ++I;
641      if (CC == ARMCC::AL)
642        MI.insert(I, MCOperand::CreateReg(0));
643      else
644        MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
645      return S;
646    }
647  }
648
649  I = MI.insert(I, MCOperand::CreateImm(CC));
650  ++I;
651  if (CC == ARMCC::AL)
652    MI.insert(I, MCOperand::CreateReg(0));
653  else
654    MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
655
656  return S;
657}
658
659// Thumb VFP instructions are a special case.  Because we share their
660// encodings between ARM and Thumb modes, and they are predicable in ARM
661// mode, the auto-generated decoder will give them an (incorrect)
662// predicate operand.  We need to rewrite these operands based on the IT
663// context as a post-pass.
664void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
665  unsigned CC;
666  if (!ITBlock.empty()) {
667    CC = ITBlock.back();
668    ITBlock.pop_back();
669  } else
670    CC = ARMCC::AL;
671
672  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
673  MCInst::iterator I = MI.begin();
674  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
675  for (unsigned i = 0; i < NumOps; ++i, ++I) {
676    if (OpInfo[i].isPredicate() ) {
677      I->setImm(CC);
678      ++I;
679      if (CC == ARMCC::AL)
680        I->setReg(0);
681      else
682        I->setReg(ARM::CPSR);
683      return;
684    }
685  }
686}
687
688DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
689                                               const MemoryObject &Region,
690                                               uint64_t Address,
691                                               raw_ostream &os,
692                                               raw_ostream &cs) const {
693  CommentStream = &cs;
694
695  uint8_t bytes[4];
696
697  assert((STI.getFeatureBits() & ARM::ModeThumb) &&
698         "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
699
700  // We want to read exactly 2 bytes of data.
701  if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
702    Size = 0;
703    return MCDisassembler::Fail;
704  }
705
706  uint16_t insn16 = (bytes[1] << 8) | bytes[0];
707  DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
708  if (result != MCDisassembler::Fail) {
709    Size = 2;
710    Check(result, AddThumbPredicate(MI));
711    return result;
712  }
713
714  MI.clear();
715  result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
716  if (result) {
717    Size = 2;
718    bool InITBlock = !ITBlock.empty();
719    Check(result, AddThumbPredicate(MI));
720    AddThumb1SBit(MI, InITBlock);
721    return result;
722  }
723
724  MI.clear();
725  result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
726  if (result != MCDisassembler::Fail) {
727    Size = 2;
728
729    // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
730    // the Thumb predicate.
731    if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
732      result = MCDisassembler::SoftFail;
733
734    Check(result, AddThumbPredicate(MI));
735
736    // If we find an IT instruction, we need to parse its condition
737    // code and mask operands so that we can apply them correctly
738    // to the subsequent instructions.
739    if (MI.getOpcode() == ARM::t2IT) {
740
741      // (3 - the number of trailing zeros) is the number of then / else.
742      unsigned firstcond = MI.getOperand(0).getImm();
743      unsigned Mask = MI.getOperand(1).getImm();
744      unsigned CondBit0 = Mask >> 4 & 1;
745      unsigned NumTZ = CountTrailingZeros_32(Mask);
746      assert(NumTZ <= 3 && "Invalid IT mask!");
747      for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
748        bool T = ((Mask >> Pos) & 1) == CondBit0;
749        if (T)
750          ITBlock.insert(ITBlock.begin(), firstcond);
751        else
752          ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
753      }
754
755      ITBlock.push_back(firstcond);
756    }
757
758    return result;
759  }
760
761  // We want to read exactly 4 bytes of data.
762  if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
763    Size = 0;
764    return MCDisassembler::Fail;
765  }
766
767  uint32_t insn32 = (bytes[3] <<  8) |
768                    (bytes[2] <<  0) |
769                    (bytes[1] << 24) |
770                    (bytes[0] << 16);
771  MI.clear();
772  result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
773  if (result != MCDisassembler::Fail) {
774    Size = 4;
775    bool InITBlock = ITBlock.size();
776    Check(result, AddThumbPredicate(MI));
777    AddThumb1SBit(MI, InITBlock);
778    return result;
779  }
780
781  MI.clear();
782  result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
783  if (result != MCDisassembler::Fail) {
784    Size = 4;
785    Check(result, AddThumbPredicate(MI));
786    return result;
787  }
788
789  MI.clear();
790  result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
791  if (result != MCDisassembler::Fail) {
792    Size = 4;
793    UpdateThumbVFPPredicate(MI);
794    return result;
795  }
796
797  MI.clear();
798  result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
799  if (result != MCDisassembler::Fail) {
800    Size = 4;
801    Check(result, AddThumbPredicate(MI));
802    return result;
803  }
804
805  if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
806    MI.clear();
807    uint32_t NEONLdStInsn = insn32;
808    NEONLdStInsn &= 0xF0FFFFFF;
809    NEONLdStInsn |= 0x04000000;
810    result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
811    if (result != MCDisassembler::Fail) {
812      Size = 4;
813      Check(result, AddThumbPredicate(MI));
814      return result;
815    }
816  }
817
818  if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
819    MI.clear();
820    uint32_t NEONDataInsn = insn32;
821    NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
822    NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
823    NEONDataInsn |= 0x12000000; // Set bits 28 and 25
824    result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
825    if (result != MCDisassembler::Fail) {
826      Size = 4;
827      Check(result, AddThumbPredicate(MI));
828      return result;
829    }
830  }
831
832  Size = 0;
833  return MCDisassembler::Fail;
834}
835
836
837extern "C" void LLVMInitializeARMDisassembler() {
838  TargetRegistry::RegisterMCDisassembler(TheARMTarget,
839                                         createARMDisassembler);
840  TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
841                                         createThumbDisassembler);
842}
843
844static const unsigned GPRDecoderTable[] = {
845  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
846  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
847  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
848  ARM::R12, ARM::SP, ARM::LR, ARM::PC
849};
850
851static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
852                                   uint64_t Address, const void *Decoder) {
853  if (RegNo > 15)
854    return MCDisassembler::Fail;
855
856  unsigned Register = GPRDecoderTable[RegNo];
857  Inst.addOperand(MCOperand::CreateReg(Register));
858  return MCDisassembler::Success;
859}
860
861static DecodeStatus
862DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
863                           uint64_t Address, const void *Decoder) {
864  if (RegNo == 15) return MCDisassembler::Fail;
865  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
866}
867
868static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
869                                   uint64_t Address, const void *Decoder) {
870  if (RegNo > 7)
871    return MCDisassembler::Fail;
872  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
873}
874
875static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
876                                   uint64_t Address, const void *Decoder) {
877  unsigned Register = 0;
878  switch (RegNo) {
879    case 0:
880      Register = ARM::R0;
881      break;
882    case 1:
883      Register = ARM::R1;
884      break;
885    case 2:
886      Register = ARM::R2;
887      break;
888    case 3:
889      Register = ARM::R3;
890      break;
891    case 9:
892      Register = ARM::R9;
893      break;
894    case 12:
895      Register = ARM::R12;
896      break;
897    default:
898      return MCDisassembler::Fail;
899    }
900
901  Inst.addOperand(MCOperand::CreateReg(Register));
902  return MCDisassembler::Success;
903}
904
905static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
906                                   uint64_t Address, const void *Decoder) {
907  if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
908  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
909}
910
911static const unsigned SPRDecoderTable[] = {
912     ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
913     ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
914     ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
915    ARM::S12, ARM::S13, ARM::S14, ARM::S15,
916    ARM::S16, ARM::S17, ARM::S18, ARM::S19,
917    ARM::S20, ARM::S21, ARM::S22, ARM::S23,
918    ARM::S24, ARM::S25, ARM::S26, ARM::S27,
919    ARM::S28, ARM::S29, ARM::S30, ARM::S31
920};
921
922static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
923                                   uint64_t Address, const void *Decoder) {
924  if (RegNo > 31)
925    return MCDisassembler::Fail;
926
927  unsigned Register = SPRDecoderTable[RegNo];
928  Inst.addOperand(MCOperand::CreateReg(Register));
929  return MCDisassembler::Success;
930}
931
932static const unsigned DPRDecoderTable[] = {
933     ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
934     ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
935     ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
936    ARM::D12, ARM::D13, ARM::D14, ARM::D15,
937    ARM::D16, ARM::D17, ARM::D18, ARM::D19,
938    ARM::D20, ARM::D21, ARM::D22, ARM::D23,
939    ARM::D24, ARM::D25, ARM::D26, ARM::D27,
940    ARM::D28, ARM::D29, ARM::D30, ARM::D31
941};
942
943static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
944                                   uint64_t Address, const void *Decoder) {
945  if (RegNo > 31)
946    return MCDisassembler::Fail;
947
948  unsigned Register = DPRDecoderTable[RegNo];
949  Inst.addOperand(MCOperand::CreateReg(Register));
950  return MCDisassembler::Success;
951}
952
953static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
954                                   uint64_t Address, const void *Decoder) {
955  if (RegNo > 7)
956    return MCDisassembler::Fail;
957  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
958}
959
960static DecodeStatus
961DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
962                            uint64_t Address, const void *Decoder) {
963  if (RegNo > 15)
964    return MCDisassembler::Fail;
965  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
966}
967
968static const unsigned QPRDecoderTable[] = {
969     ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
970     ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
971     ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
972    ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
973};
974
975
976static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
977                                   uint64_t Address, const void *Decoder) {
978  if (RegNo > 31)
979    return MCDisassembler::Fail;
980  RegNo >>= 1;
981
982  unsigned Register = QPRDecoderTable[RegNo];
983  Inst.addOperand(MCOperand::CreateReg(Register));
984  return MCDisassembler::Success;
985}
986
987static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
988                               uint64_t Address, const void *Decoder) {
989  if (Val == 0xF) return MCDisassembler::Fail;
990  // AL predicate is not allowed on Thumb1 branches.
991  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
992    return MCDisassembler::Fail;
993  Inst.addOperand(MCOperand::CreateImm(Val));
994  if (Val == ARMCC::AL) {
995    Inst.addOperand(MCOperand::CreateReg(0));
996  } else
997    Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
998  return MCDisassembler::Success;
999}
1000
1001static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
1002                               uint64_t Address, const void *Decoder) {
1003  if (Val)
1004    Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1005  else
1006    Inst.addOperand(MCOperand::CreateReg(0));
1007  return MCDisassembler::Success;
1008}
1009
1010static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
1011                               uint64_t Address, const void *Decoder) {
1012  uint32_t imm = Val & 0xFF;
1013  uint32_t rot = (Val & 0xF00) >> 7;
1014  uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1015  Inst.addOperand(MCOperand::CreateImm(rot_imm));
1016  return MCDisassembler::Success;
1017}
1018
1019static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
1020                               uint64_t Address, const void *Decoder) {
1021  DecodeStatus S = MCDisassembler::Success;
1022
1023  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1024  unsigned type = fieldFromInstruction32(Val, 5, 2);
1025  unsigned imm = fieldFromInstruction32(Val, 7, 5);
1026
1027  // Register-immediate
1028  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1029    return MCDisassembler::Fail;
1030
1031  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1032  switch (type) {
1033    case 0:
1034      Shift = ARM_AM::lsl;
1035      break;
1036    case 1:
1037      Shift = ARM_AM::lsr;
1038      break;
1039    case 2:
1040      Shift = ARM_AM::asr;
1041      break;
1042    case 3:
1043      Shift = ARM_AM::ror;
1044      break;
1045  }
1046
1047  if (Shift == ARM_AM::ror && imm == 0)
1048    Shift = ARM_AM::rrx;
1049
1050  unsigned Op = Shift | (imm << 3);
1051  Inst.addOperand(MCOperand::CreateImm(Op));
1052
1053  return S;
1054}
1055
1056static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
1057                               uint64_t Address, const void *Decoder) {
1058  DecodeStatus S = MCDisassembler::Success;
1059
1060  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1061  unsigned type = fieldFromInstruction32(Val, 5, 2);
1062  unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1063
1064  // Register-register
1065  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1066    return MCDisassembler::Fail;
1067  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1068    return MCDisassembler::Fail;
1069
1070  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1071  switch (type) {
1072    case 0:
1073      Shift = ARM_AM::lsl;
1074      break;
1075    case 1:
1076      Shift = ARM_AM::lsr;
1077      break;
1078    case 2:
1079      Shift = ARM_AM::asr;
1080      break;
1081    case 3:
1082      Shift = ARM_AM::ror;
1083      break;
1084  }
1085
1086  Inst.addOperand(MCOperand::CreateImm(Shift));
1087
1088  return S;
1089}
1090
1091static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
1092                                 uint64_t Address, const void *Decoder) {
1093  DecodeStatus S = MCDisassembler::Success;
1094
1095  bool writebackLoad = false;
1096  unsigned writebackReg = 0;
1097  switch (Inst.getOpcode()) {
1098    default:
1099      break;
1100    case ARM::LDMIA_UPD:
1101    case ARM::LDMDB_UPD:
1102    case ARM::LDMIB_UPD:
1103    case ARM::LDMDA_UPD:
1104    case ARM::t2LDMIA_UPD:
1105    case ARM::t2LDMDB_UPD:
1106      writebackLoad = true;
1107      writebackReg = Inst.getOperand(0).getReg();
1108      break;
1109  }
1110
1111  // Empty register lists are not allowed.
1112  if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1113  for (unsigned i = 0; i < 16; ++i) {
1114    if (Val & (1 << i)) {
1115      if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1116        return MCDisassembler::Fail;
1117      // Writeback not allowed if Rn is in the target list.
1118      if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1119        Check(S, MCDisassembler::SoftFail);
1120    }
1121  }
1122
1123  return S;
1124}
1125
1126static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1127                                 uint64_t Address, const void *Decoder) {
1128  DecodeStatus S = MCDisassembler::Success;
1129
1130  unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1131  unsigned regs = Val & 0xFF;
1132
1133  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1134    return MCDisassembler::Fail;
1135  for (unsigned i = 0; i < (regs - 1); ++i) {
1136    if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1137      return MCDisassembler::Fail;
1138  }
1139
1140  return S;
1141}
1142
1143static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1144                                 uint64_t Address, const void *Decoder) {
1145  DecodeStatus S = MCDisassembler::Success;
1146
1147  unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1148  unsigned regs = (Val & 0xFF) / 2;
1149
1150  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1151      return MCDisassembler::Fail;
1152  for (unsigned i = 0; i < (regs - 1); ++i) {
1153    if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1154      return MCDisassembler::Fail;
1155  }
1156
1157  return S;
1158}
1159
1160static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
1161                                      uint64_t Address, const void *Decoder) {
1162  // This operand encodes a mask of contiguous zeros between a specified MSB
1163  // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
1164  // the mask of all bits LSB-and-lower, and then xor them to create
1165  // the mask of that's all ones on [msb, lsb].  Finally we not it to
1166  // create the final mask.
1167  unsigned msb = fieldFromInstruction32(Val, 5, 5);
1168  unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1169
1170  DecodeStatus S = MCDisassembler::Success;
1171  if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1172
1173  uint32_t msb_mask = 0xFFFFFFFF;
1174  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1175  uint32_t lsb_mask = (1U << lsb) - 1;
1176
1177  Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1178  return S;
1179}
1180
1181static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
1182                                  uint64_t Address, const void *Decoder) {
1183  DecodeStatus S = MCDisassembler::Success;
1184
1185  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1186  unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1187  unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1188  unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1189  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1190  unsigned U = fieldFromInstruction32(Insn, 23, 1);
1191
1192  switch (Inst.getOpcode()) {
1193    case ARM::LDC_OFFSET:
1194    case ARM::LDC_PRE:
1195    case ARM::LDC_POST:
1196    case ARM::LDC_OPTION:
1197    case ARM::LDCL_OFFSET:
1198    case ARM::LDCL_PRE:
1199    case ARM::LDCL_POST:
1200    case ARM::LDCL_OPTION:
1201    case ARM::STC_OFFSET:
1202    case ARM::STC_PRE:
1203    case ARM::STC_POST:
1204    case ARM::STC_OPTION:
1205    case ARM::STCL_OFFSET:
1206    case ARM::STCL_PRE:
1207    case ARM::STCL_POST:
1208    case ARM::STCL_OPTION:
1209    case ARM::t2LDC_OFFSET:
1210    case ARM::t2LDC_PRE:
1211    case ARM::t2LDC_POST:
1212    case ARM::t2LDC_OPTION:
1213    case ARM::t2LDCL_OFFSET:
1214    case ARM::t2LDCL_PRE:
1215    case ARM::t2LDCL_POST:
1216    case ARM::t2LDCL_OPTION:
1217    case ARM::t2STC_OFFSET:
1218    case ARM::t2STC_PRE:
1219    case ARM::t2STC_POST:
1220    case ARM::t2STC_OPTION:
1221    case ARM::t2STCL_OFFSET:
1222    case ARM::t2STCL_PRE:
1223    case ARM::t2STCL_POST:
1224    case ARM::t2STCL_OPTION:
1225      if (coproc == 0xA || coproc == 0xB)
1226        return MCDisassembler::Fail;
1227      break;
1228    default:
1229      break;
1230  }
1231
1232  Inst.addOperand(MCOperand::CreateImm(coproc));
1233  Inst.addOperand(MCOperand::CreateImm(CRd));
1234  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1235    return MCDisassembler::Fail;
1236
1237  switch (Inst.getOpcode()) {
1238    case ARM::t2LDC2_OFFSET:
1239    case ARM::t2LDC2L_OFFSET:
1240    case ARM::t2LDC2_PRE:
1241    case ARM::t2LDC2L_PRE:
1242    case ARM::t2STC2_OFFSET:
1243    case ARM::t2STC2L_OFFSET:
1244    case ARM::t2STC2_PRE:
1245    case ARM::t2STC2L_PRE:
1246    case ARM::LDC2_OFFSET:
1247    case ARM::LDC2L_OFFSET:
1248    case ARM::LDC2_PRE:
1249    case ARM::LDC2L_PRE:
1250    case ARM::STC2_OFFSET:
1251    case ARM::STC2L_OFFSET:
1252    case ARM::STC2_PRE:
1253    case ARM::STC2L_PRE:
1254    case ARM::t2LDC_OFFSET:
1255    case ARM::t2LDCL_OFFSET:
1256    case ARM::t2LDC_PRE:
1257    case ARM::t2LDCL_PRE:
1258    case ARM::t2STC_OFFSET:
1259    case ARM::t2STCL_OFFSET:
1260    case ARM::t2STC_PRE:
1261    case ARM::t2STCL_PRE:
1262    case ARM::LDC_OFFSET:
1263    case ARM::LDCL_OFFSET:
1264    case ARM::LDC_PRE:
1265    case ARM::LDCL_PRE:
1266    case ARM::STC_OFFSET:
1267    case ARM::STCL_OFFSET:
1268    case ARM::STC_PRE:
1269    case ARM::STCL_PRE:
1270      imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1271      Inst.addOperand(MCOperand::CreateImm(imm));
1272      break;
1273    case ARM::t2LDC2_POST:
1274    case ARM::t2LDC2L_POST:
1275    case ARM::t2STC2_POST:
1276    case ARM::t2STC2L_POST:
1277    case ARM::LDC2_POST:
1278    case ARM::LDC2L_POST:
1279    case ARM::STC2_POST:
1280    case ARM::STC2L_POST:
1281    case ARM::t2LDC_POST:
1282    case ARM::t2LDCL_POST:
1283    case ARM::t2STC_POST:
1284    case ARM::t2STCL_POST:
1285    case ARM::LDC_POST:
1286    case ARM::LDCL_POST:
1287    case ARM::STC_POST:
1288    case ARM::STCL_POST:
1289      imm |= U << 8;
1290      // fall through.
1291    default:
1292      // The 'option' variant doesn't encode 'U' in the immediate since
1293      // the immediate is unsigned [0,255].
1294      Inst.addOperand(MCOperand::CreateImm(imm));
1295      break;
1296  }
1297
1298  switch (Inst.getOpcode()) {
1299    case ARM::LDC_OFFSET:
1300    case ARM::LDC_PRE:
1301    case ARM::LDC_POST:
1302    case ARM::LDC_OPTION:
1303    case ARM::LDCL_OFFSET:
1304    case ARM::LDCL_PRE:
1305    case ARM::LDCL_POST:
1306    case ARM::LDCL_OPTION:
1307    case ARM::STC_OFFSET:
1308    case ARM::STC_PRE:
1309    case ARM::STC_POST:
1310    case ARM::STC_OPTION:
1311    case ARM::STCL_OFFSET:
1312    case ARM::STCL_PRE:
1313    case ARM::STCL_POST:
1314    case ARM::STCL_OPTION:
1315      if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1316        return MCDisassembler::Fail;
1317      break;
1318    default:
1319      break;
1320  }
1321
1322  return S;
1323}
1324
1325static DecodeStatus
1326DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1327                              uint64_t Address, const void *Decoder) {
1328  DecodeStatus S = MCDisassembler::Success;
1329
1330  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1331  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1332  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1333  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1334  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1335  unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1336  unsigned P = fieldFromInstruction32(Insn, 24, 1);
1337  unsigned W = fieldFromInstruction32(Insn, 21, 1);
1338
1339  // On stores, the writeback operand precedes Rt.
1340  switch (Inst.getOpcode()) {
1341    case ARM::STR_POST_IMM:
1342    case ARM::STR_POST_REG:
1343    case ARM::STRB_POST_IMM:
1344    case ARM::STRB_POST_REG:
1345    case ARM::STRT_POST_REG:
1346    case ARM::STRT_POST_IMM:
1347    case ARM::STRBT_POST_REG:
1348    case ARM::STRBT_POST_IMM:
1349      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1350        return MCDisassembler::Fail;
1351      break;
1352    default:
1353      break;
1354  }
1355
1356  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1357    return MCDisassembler::Fail;
1358
1359  // On loads, the writeback operand comes after Rt.
1360  switch (Inst.getOpcode()) {
1361    case ARM::LDR_POST_IMM:
1362    case ARM::LDR_POST_REG:
1363    case ARM::LDRB_POST_IMM:
1364    case ARM::LDRB_POST_REG:
1365    case ARM::LDRBT_POST_REG:
1366    case ARM::LDRBT_POST_IMM:
1367    case ARM::LDRT_POST_REG:
1368    case ARM::LDRT_POST_IMM:
1369      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1370        return MCDisassembler::Fail;
1371      break;
1372    default:
1373      break;
1374  }
1375
1376  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1377    return MCDisassembler::Fail;
1378
1379  ARM_AM::AddrOpc Op = ARM_AM::add;
1380  if (!fieldFromInstruction32(Insn, 23, 1))
1381    Op = ARM_AM::sub;
1382
1383  bool writeback = (P == 0) || (W == 1);
1384  unsigned idx_mode = 0;
1385  if (P && writeback)
1386    idx_mode = ARMII::IndexModePre;
1387  else if (!P && writeback)
1388    idx_mode = ARMII::IndexModePost;
1389
1390  if (writeback && (Rn == 15 || Rn == Rt))
1391    S = MCDisassembler::SoftFail; // UNPREDICTABLE
1392
1393  if (reg) {
1394    if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1395      return MCDisassembler::Fail;
1396    ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1397    switch( fieldFromInstruction32(Insn, 5, 2)) {
1398      case 0:
1399        Opc = ARM_AM::lsl;
1400        break;
1401      case 1:
1402        Opc = ARM_AM::lsr;
1403        break;
1404      case 2:
1405        Opc = ARM_AM::asr;
1406        break;
1407      case 3:
1408        Opc = ARM_AM::ror;
1409        break;
1410      default:
1411        return MCDisassembler::Fail;
1412    }
1413    unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1414    unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1415
1416    Inst.addOperand(MCOperand::CreateImm(imm));
1417  } else {
1418    Inst.addOperand(MCOperand::CreateReg(0));
1419    unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1420    Inst.addOperand(MCOperand::CreateImm(tmp));
1421  }
1422
1423  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1424    return MCDisassembler::Fail;
1425
1426  return S;
1427}
1428
1429static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1430                                  uint64_t Address, const void *Decoder) {
1431  DecodeStatus S = MCDisassembler::Success;
1432
1433  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1434  unsigned Rm = fieldFromInstruction32(Val,  0, 4);
1435  unsigned type = fieldFromInstruction32(Val, 5, 2);
1436  unsigned imm = fieldFromInstruction32(Val, 7, 5);
1437  unsigned U = fieldFromInstruction32(Val, 12, 1);
1438
1439  ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1440  switch (type) {
1441    case 0:
1442      ShOp = ARM_AM::lsl;
1443      break;
1444    case 1:
1445      ShOp = ARM_AM::lsr;
1446      break;
1447    case 2:
1448      ShOp = ARM_AM::asr;
1449      break;
1450    case 3:
1451      ShOp = ARM_AM::ror;
1452      break;
1453  }
1454
1455  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1456    return MCDisassembler::Fail;
1457  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1458    return MCDisassembler::Fail;
1459  unsigned shift;
1460  if (U)
1461    shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1462  else
1463    shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1464  Inst.addOperand(MCOperand::CreateImm(shift));
1465
1466  return S;
1467}
1468
1469static DecodeStatus
1470DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1471                           uint64_t Address, const void *Decoder) {
1472  DecodeStatus S = MCDisassembler::Success;
1473
1474  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1475  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1476  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1477  unsigned type = fieldFromInstruction32(Insn, 22, 1);
1478  unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1479  unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1480  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1481  unsigned W = fieldFromInstruction32(Insn, 21, 1);
1482  unsigned P = fieldFromInstruction32(Insn, 24, 1);
1483
1484  bool writeback = (W == 1) | (P == 0);
1485
1486  // For {LD,ST}RD, Rt must be even, else undefined.
1487  switch (Inst.getOpcode()) {
1488    case ARM::STRD:
1489    case ARM::STRD_PRE:
1490    case ARM::STRD_POST:
1491    case ARM::LDRD:
1492    case ARM::LDRD_PRE:
1493    case ARM::LDRD_POST:
1494      if (Rt & 0x1) return MCDisassembler::Fail;
1495      break;
1496    default:
1497      break;
1498  }
1499
1500  if (writeback) { // Writeback
1501    if (P)
1502      U |= ARMII::IndexModePre << 9;
1503    else
1504      U |= ARMII::IndexModePost << 9;
1505
1506    // On stores, the writeback operand precedes Rt.
1507    switch (Inst.getOpcode()) {
1508    case ARM::STRD:
1509    case ARM::STRD_PRE:
1510    case ARM::STRD_POST:
1511    case ARM::STRH:
1512    case ARM::STRH_PRE:
1513    case ARM::STRH_POST:
1514      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1515        return MCDisassembler::Fail;
1516      break;
1517    default:
1518      break;
1519    }
1520  }
1521
1522  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1523    return MCDisassembler::Fail;
1524  switch (Inst.getOpcode()) {
1525    case ARM::STRD:
1526    case ARM::STRD_PRE:
1527    case ARM::STRD_POST:
1528    case ARM::LDRD:
1529    case ARM::LDRD_PRE:
1530    case ARM::LDRD_POST:
1531      if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1532        return MCDisassembler::Fail;
1533      break;
1534    default:
1535      break;
1536  }
1537
1538  if (writeback) {
1539    // On loads, the writeback operand comes after Rt.
1540    switch (Inst.getOpcode()) {
1541    case ARM::LDRD:
1542    case ARM::LDRD_PRE:
1543    case ARM::LDRD_POST:
1544    case ARM::LDRH:
1545    case ARM::LDRH_PRE:
1546    case ARM::LDRH_POST:
1547    case ARM::LDRSH:
1548    case ARM::LDRSH_PRE:
1549    case ARM::LDRSH_POST:
1550    case ARM::LDRSB:
1551    case ARM::LDRSB_PRE:
1552    case ARM::LDRSB_POST:
1553    case ARM::LDRHTr:
1554    case ARM::LDRSBTr:
1555      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1556        return MCDisassembler::Fail;
1557      break;
1558    default:
1559      break;
1560    }
1561  }
1562
1563  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1564    return MCDisassembler::Fail;
1565
1566  if (type) {
1567    Inst.addOperand(MCOperand::CreateReg(0));
1568    Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1569  } else {
1570    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1571    return MCDisassembler::Fail;
1572    Inst.addOperand(MCOperand::CreateImm(U));
1573  }
1574
1575  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1576    return MCDisassembler::Fail;
1577
1578  return S;
1579}
1580
1581static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1582                                 uint64_t Address, const void *Decoder) {
1583  DecodeStatus S = MCDisassembler::Success;
1584
1585  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1586  unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1587
1588  switch (mode) {
1589    case 0:
1590      mode = ARM_AM::da;
1591      break;
1592    case 1:
1593      mode = ARM_AM::ia;
1594      break;
1595    case 2:
1596      mode = ARM_AM::db;
1597      break;
1598    case 3:
1599      mode = ARM_AM::ib;
1600      break;
1601  }
1602
1603  Inst.addOperand(MCOperand::CreateImm(mode));
1604  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1605    return MCDisassembler::Fail;
1606
1607  return S;
1608}
1609
1610static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1611                                  unsigned Insn,
1612                                  uint64_t Address, const void *Decoder) {
1613  DecodeStatus S = MCDisassembler::Success;
1614
1615  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1616  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1617  unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1618
1619  if (pred == 0xF) {
1620    switch (Inst.getOpcode()) {
1621      case ARM::LDMDA:
1622        Inst.setOpcode(ARM::RFEDA);
1623        break;
1624      case ARM::LDMDA_UPD:
1625        Inst.setOpcode(ARM::RFEDA_UPD);
1626        break;
1627      case ARM::LDMDB:
1628        Inst.setOpcode(ARM::RFEDB);
1629        break;
1630      case ARM::LDMDB_UPD:
1631        Inst.setOpcode(ARM::RFEDB_UPD);
1632        break;
1633      case ARM::LDMIA:
1634        Inst.setOpcode(ARM::RFEIA);
1635        break;
1636      case ARM::LDMIA_UPD:
1637        Inst.setOpcode(ARM::RFEIA_UPD);
1638        break;
1639      case ARM::LDMIB:
1640        Inst.setOpcode(ARM::RFEIB);
1641        break;
1642      case ARM::LDMIB_UPD:
1643        Inst.setOpcode(ARM::RFEIB_UPD);
1644        break;
1645      case ARM::STMDA:
1646        Inst.setOpcode(ARM::SRSDA);
1647        break;
1648      case ARM::STMDA_UPD:
1649        Inst.setOpcode(ARM::SRSDA_UPD);
1650        break;
1651      case ARM::STMDB:
1652        Inst.setOpcode(ARM::SRSDB);
1653        break;
1654      case ARM::STMDB_UPD:
1655        Inst.setOpcode(ARM::SRSDB_UPD);
1656        break;
1657      case ARM::STMIA:
1658        Inst.setOpcode(ARM::SRSIA);
1659        break;
1660      case ARM::STMIA_UPD:
1661        Inst.setOpcode(ARM::SRSIA_UPD);
1662        break;
1663      case ARM::STMIB:
1664        Inst.setOpcode(ARM::SRSIB);
1665        break;
1666      case ARM::STMIB_UPD:
1667        Inst.setOpcode(ARM::SRSIB_UPD);
1668        break;
1669      default:
1670        if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1671    }
1672
1673    // For stores (which become SRS's, the only operand is the mode.
1674    if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1675      Inst.addOperand(
1676          MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1677      return S;
1678    }
1679
1680    return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1681  }
1682
1683  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1684    return MCDisassembler::Fail;
1685  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1686    return MCDisassembler::Fail; // Tied
1687  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1688    return MCDisassembler::Fail;
1689  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1690    return MCDisassembler::Fail;
1691
1692  return S;
1693}
1694
1695static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1696                                 uint64_t Address, const void *Decoder) {
1697  unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1698  unsigned M = fieldFromInstruction32(Insn, 17, 1);
1699  unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1700  unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1701
1702  DecodeStatus S = MCDisassembler::Success;
1703
1704  // imod == '01' --> UNPREDICTABLE
1705  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1706  // return failure here.  The '01' imod value is unprintable, so there's
1707  // nothing useful we could do even if we returned UNPREDICTABLE.
1708
1709  if (imod == 1) return MCDisassembler::Fail;
1710
1711  if (imod && M) {
1712    Inst.setOpcode(ARM::CPS3p);
1713    Inst.addOperand(MCOperand::CreateImm(imod));
1714    Inst.addOperand(MCOperand::CreateImm(iflags));
1715    Inst.addOperand(MCOperand::CreateImm(mode));
1716  } else if (imod && !M) {
1717    Inst.setOpcode(ARM::CPS2p);
1718    Inst.addOperand(MCOperand::CreateImm(imod));
1719    Inst.addOperand(MCOperand::CreateImm(iflags));
1720    if (mode) S = MCDisassembler::SoftFail;
1721  } else if (!imod && M) {
1722    Inst.setOpcode(ARM::CPS1p);
1723    Inst.addOperand(MCOperand::CreateImm(mode));
1724    if (iflags) S = MCDisassembler::SoftFail;
1725  } else {
1726    // imod == '00' && M == '0' --> UNPREDICTABLE
1727    Inst.setOpcode(ARM::CPS1p);
1728    Inst.addOperand(MCOperand::CreateImm(mode));
1729    S = MCDisassembler::SoftFail;
1730  }
1731
1732  return S;
1733}
1734
1735static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1736                                 uint64_t Address, const void *Decoder) {
1737  unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1738  unsigned M = fieldFromInstruction32(Insn, 8, 1);
1739  unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1740  unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1741
1742  DecodeStatus S = MCDisassembler::Success;
1743
1744  // imod == '01' --> UNPREDICTABLE
1745  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1746  // return failure here.  The '01' imod value is unprintable, so there's
1747  // nothing useful we could do even if we returned UNPREDICTABLE.
1748
1749  if (imod == 1) return MCDisassembler::Fail;
1750
1751  if (imod && M) {
1752    Inst.setOpcode(ARM::t2CPS3p);
1753    Inst.addOperand(MCOperand::CreateImm(imod));
1754    Inst.addOperand(MCOperand::CreateImm(iflags));
1755    Inst.addOperand(MCOperand::CreateImm(mode));
1756  } else if (imod && !M) {
1757    Inst.setOpcode(ARM::t2CPS2p);
1758    Inst.addOperand(MCOperand::CreateImm(imod));
1759    Inst.addOperand(MCOperand::CreateImm(iflags));
1760    if (mode) S = MCDisassembler::SoftFail;
1761  } else if (!imod && M) {
1762    Inst.setOpcode(ARM::t2CPS1p);
1763    Inst.addOperand(MCOperand::CreateImm(mode));
1764    if (iflags) S = MCDisassembler::SoftFail;
1765  } else {
1766    // imod == '00' && M == '0' --> UNPREDICTABLE
1767    Inst.setOpcode(ARM::t2CPS1p);
1768    Inst.addOperand(MCOperand::CreateImm(mode));
1769    S = MCDisassembler::SoftFail;
1770  }
1771
1772  return S;
1773}
1774
1775static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1776                                 uint64_t Address, const void *Decoder) {
1777  DecodeStatus S = MCDisassembler::Success;
1778
1779  unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1780  unsigned imm = 0;
1781
1782  imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1783  imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1784  imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1785  imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1786
1787  if (Inst.getOpcode() == ARM::t2MOVTi16)
1788    if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1789      return MCDisassembler::Fail;
1790  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1791    return MCDisassembler::Fail;
1792
1793  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1794    Inst.addOperand(MCOperand::CreateImm(imm));
1795
1796  return S;
1797}
1798
1799static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1800                                 uint64_t Address, const void *Decoder) {
1801  DecodeStatus S = MCDisassembler::Success;
1802
1803  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1804  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1805  unsigned imm = 0;
1806
1807  imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1808  imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1809
1810  if (Inst.getOpcode() == ARM::MOVTi16)
1811    if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1812      return MCDisassembler::Fail;
1813  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1814    return MCDisassembler::Fail;
1815
1816  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1817    Inst.addOperand(MCOperand::CreateImm(imm));
1818
1819  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1820    return MCDisassembler::Fail;
1821
1822  return S;
1823}
1824
1825static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1826                                 uint64_t Address, const void *Decoder) {
1827  DecodeStatus S = MCDisassembler::Success;
1828
1829  unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1830  unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1831  unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1832  unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1833  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1834
1835  if (pred == 0xF)
1836    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1837
1838  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1839    return MCDisassembler::Fail;
1840  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1841    return MCDisassembler::Fail;
1842  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1843    return MCDisassembler::Fail;
1844  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1845    return MCDisassembler::Fail;
1846
1847  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1848    return MCDisassembler::Fail;
1849
1850  return S;
1851}
1852
1853static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1854                           uint64_t Address, const void *Decoder) {
1855  DecodeStatus S = MCDisassembler::Success;
1856
1857  unsigned add = fieldFromInstruction32(Val, 12, 1);
1858  unsigned imm = fieldFromInstruction32(Val, 0, 12);
1859  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1860
1861  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1862    return MCDisassembler::Fail;
1863
1864  if (!add) imm *= -1;
1865  if (imm == 0 && !add) imm = INT32_MIN;
1866  Inst.addOperand(MCOperand::CreateImm(imm));
1867  if (Rn == 15)
1868    tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
1869
1870  return S;
1871}
1872
1873static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1874                                   uint64_t Address, const void *Decoder) {
1875  DecodeStatus S = MCDisassembler::Success;
1876
1877  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1878  unsigned U = fieldFromInstruction32(Val, 8, 1);
1879  unsigned imm = fieldFromInstruction32(Val, 0, 8);
1880
1881  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1882    return MCDisassembler::Fail;
1883
1884  if (U)
1885    Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1886  else
1887    Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1888
1889  return S;
1890}
1891
1892static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1893                                   uint64_t Address, const void *Decoder) {
1894  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1895}
1896
1897static DecodeStatus
1898DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1899                           uint64_t Address, const void *Decoder) {
1900  DecodeStatus S = MCDisassembler::Success;
1901
1902  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1903  unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1904
1905  if (pred == 0xF) {
1906    Inst.setOpcode(ARM::BLXi);
1907    imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1908    Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1909    return S;
1910  }
1911
1912  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1913                                4, Inst, Decoder))
1914    Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1915  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1916    return MCDisassembler::Fail;
1917
1918  return S;
1919}
1920
1921
1922static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1923                                 uint64_t Address, const void *Decoder) {
1924  Inst.addOperand(MCOperand::CreateImm(64 - Val));
1925  return MCDisassembler::Success;
1926}
1927
1928static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1929                                   uint64_t Address, const void *Decoder) {
1930  DecodeStatus S = MCDisassembler::Success;
1931
1932  unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1933  unsigned align = fieldFromInstruction32(Val, 4, 2);
1934
1935  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1936    return MCDisassembler::Fail;
1937  if (!align)
1938    Inst.addOperand(MCOperand::CreateImm(0));
1939  else
1940    Inst.addOperand(MCOperand::CreateImm(4 << align));
1941
1942  return S;
1943}
1944
1945static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1946                                   uint64_t Address, const void *Decoder) {
1947  DecodeStatus S = MCDisassembler::Success;
1948
1949  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1950  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1951  unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1952  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1953  Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1954  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1955
1956  // First output register
1957  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1958    return MCDisassembler::Fail;
1959
1960  // Second output register
1961  switch (Inst.getOpcode()) {
1962    case ARM::VLD1d8Q:
1963    case ARM::VLD1d16Q:
1964    case ARM::VLD1d32Q:
1965    case ARM::VLD1d64Q:
1966    case ARM::VLD1d8Q_UPD:
1967    case ARM::VLD1d16Q_UPD:
1968    case ARM::VLD1d32Q_UPD:
1969    case ARM::VLD1d64Q_UPD:
1970    case ARM::VLD2d8:
1971    case ARM::VLD2d16:
1972    case ARM::VLD2d32:
1973    case ARM::VLD2d8_UPD:
1974    case ARM::VLD2d16_UPD:
1975    case ARM::VLD2d32_UPD:
1976    case ARM::VLD2q8:
1977    case ARM::VLD2q16:
1978    case ARM::VLD2q32:
1979    case ARM::VLD2q8_UPD:
1980    case ARM::VLD2q16_UPD:
1981    case ARM::VLD2q32_UPD:
1982    case ARM::VLD3d8:
1983    case ARM::VLD3d16:
1984    case ARM::VLD3d32:
1985    case ARM::VLD3d8_UPD:
1986    case ARM::VLD3d16_UPD:
1987    case ARM::VLD3d32_UPD:
1988    case ARM::VLD4d8:
1989    case ARM::VLD4d16:
1990    case ARM::VLD4d32:
1991    case ARM::VLD4d8_UPD:
1992    case ARM::VLD4d16_UPD:
1993    case ARM::VLD4d32_UPD:
1994      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1995        return MCDisassembler::Fail;
1996      break;
1997    case ARM::VLD2b8:
1998    case ARM::VLD2b16:
1999    case ARM::VLD2b32:
2000    case ARM::VLD2b8_UPD:
2001    case ARM::VLD2b16_UPD:
2002    case ARM::VLD2b32_UPD:
2003    case ARM::VLD3q8:
2004    case ARM::VLD3q16:
2005    case ARM::VLD3q32:
2006    case ARM::VLD3q8_UPD:
2007    case ARM::VLD3q16_UPD:
2008    case ARM::VLD3q32_UPD:
2009    case ARM::VLD4q8:
2010    case ARM::VLD4q16:
2011    case ARM::VLD4q32:
2012    case ARM::VLD4q8_UPD:
2013    case ARM::VLD4q16_UPD:
2014    case ARM::VLD4q32_UPD:
2015      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2016        return MCDisassembler::Fail;
2017    default:
2018      break;
2019  }
2020
2021  // Third output register
2022  switch(Inst.getOpcode()) {
2023    case ARM::VLD1d8Q:
2024    case ARM::VLD1d16Q:
2025    case ARM::VLD1d32Q:
2026    case ARM::VLD1d64Q:
2027    case ARM::VLD1d8Q_UPD:
2028    case ARM::VLD1d16Q_UPD:
2029    case ARM::VLD1d32Q_UPD:
2030    case ARM::VLD1d64Q_UPD:
2031    case ARM::VLD2q8:
2032    case ARM::VLD2q16:
2033    case ARM::VLD2q32:
2034    case ARM::VLD2q8_UPD:
2035    case ARM::VLD2q16_UPD:
2036    case ARM::VLD2q32_UPD:
2037    case ARM::VLD3d8:
2038    case ARM::VLD3d16:
2039    case ARM::VLD3d32:
2040    case ARM::VLD3d8_UPD:
2041    case ARM::VLD3d16_UPD:
2042    case ARM::VLD3d32_UPD:
2043    case ARM::VLD4d8:
2044    case ARM::VLD4d16:
2045    case ARM::VLD4d32:
2046    case ARM::VLD4d8_UPD:
2047    case ARM::VLD4d16_UPD:
2048    case ARM::VLD4d32_UPD:
2049      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2050        return MCDisassembler::Fail;
2051      break;
2052    case ARM::VLD3q8:
2053    case ARM::VLD3q16:
2054    case ARM::VLD3q32:
2055    case ARM::VLD3q8_UPD:
2056    case ARM::VLD3q16_UPD:
2057    case ARM::VLD3q32_UPD:
2058    case ARM::VLD4q8:
2059    case ARM::VLD4q16:
2060    case ARM::VLD4q32:
2061    case ARM::VLD4q8_UPD:
2062    case ARM::VLD4q16_UPD:
2063    case ARM::VLD4q32_UPD:
2064      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2065        return MCDisassembler::Fail;
2066      break;
2067    default:
2068      break;
2069  }
2070
2071  // Fourth output register
2072  switch (Inst.getOpcode()) {
2073    case ARM::VLD1d8Q:
2074    case ARM::VLD1d16Q:
2075    case ARM::VLD1d32Q:
2076    case ARM::VLD1d64Q:
2077    case ARM::VLD1d8Q_UPD:
2078    case ARM::VLD1d16Q_UPD:
2079    case ARM::VLD1d32Q_UPD:
2080    case ARM::VLD1d64Q_UPD:
2081    case ARM::VLD2q8:
2082    case ARM::VLD2q16:
2083    case ARM::VLD2q32:
2084    case ARM::VLD2q8_UPD:
2085    case ARM::VLD2q16_UPD:
2086    case ARM::VLD2q32_UPD:
2087    case ARM::VLD4d8:
2088    case ARM::VLD4d16:
2089    case ARM::VLD4d32:
2090    case ARM::VLD4d8_UPD:
2091    case ARM::VLD4d16_UPD:
2092    case ARM::VLD4d32_UPD:
2093      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2094        return MCDisassembler::Fail;
2095      break;
2096    case ARM::VLD4q8:
2097    case ARM::VLD4q16:
2098    case ARM::VLD4q32:
2099    case ARM::VLD4q8_UPD:
2100    case ARM::VLD4q16_UPD:
2101    case ARM::VLD4q32_UPD:
2102      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2103        return MCDisassembler::Fail;
2104      break;
2105    default:
2106      break;
2107  }
2108
2109  // Writeback operand
2110  switch (Inst.getOpcode()) {
2111    case ARM::VLD1d8_UPD:
2112    case ARM::VLD1d16_UPD:
2113    case ARM::VLD1d32_UPD:
2114    case ARM::VLD1d64_UPD:
2115    case ARM::VLD1q8_UPD:
2116    case ARM::VLD1q16_UPD:
2117    case ARM::VLD1q32_UPD:
2118    case ARM::VLD1q64_UPD:
2119    case ARM::VLD1d8T_UPD:
2120    case ARM::VLD1d16T_UPD:
2121    case ARM::VLD1d32T_UPD:
2122    case ARM::VLD1d64T_UPD:
2123    case ARM::VLD1d8Q_UPD:
2124    case ARM::VLD1d16Q_UPD:
2125    case ARM::VLD1d32Q_UPD:
2126    case ARM::VLD1d64Q_UPD:
2127    case ARM::VLD2d8_UPD:
2128    case ARM::VLD2d16_UPD:
2129    case ARM::VLD2d32_UPD:
2130    case ARM::VLD2q8_UPD:
2131    case ARM::VLD2q16_UPD:
2132    case ARM::VLD2q32_UPD:
2133    case ARM::VLD2b8_UPD:
2134    case ARM::VLD2b16_UPD:
2135    case ARM::VLD2b32_UPD:
2136    case ARM::VLD3d8_UPD:
2137    case ARM::VLD3d16_UPD:
2138    case ARM::VLD3d32_UPD:
2139    case ARM::VLD3q8_UPD:
2140    case ARM::VLD3q16_UPD:
2141    case ARM::VLD3q32_UPD:
2142    case ARM::VLD4d8_UPD:
2143    case ARM::VLD4d16_UPD:
2144    case ARM::VLD4d32_UPD:
2145    case ARM::VLD4q8_UPD:
2146    case ARM::VLD4q16_UPD:
2147    case ARM::VLD4q32_UPD:
2148      if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2149        return MCDisassembler::Fail;
2150      break;
2151    default:
2152      break;
2153  }
2154
2155  // AddrMode6 Base (register+alignment)
2156  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2157    return MCDisassembler::Fail;
2158
2159  // AddrMode6 Offset (register)
2160  if (Rm == 0xD)
2161    Inst.addOperand(MCOperand::CreateReg(0));
2162  else if (Rm != 0xF) {
2163    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2164      return MCDisassembler::Fail;
2165  }
2166
2167  return S;
2168}
2169
2170static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
2171                                 uint64_t Address, const void *Decoder) {
2172  DecodeStatus S = MCDisassembler::Success;
2173
2174  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2175  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2176  unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2177  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2178  Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2179  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2180
2181  // Writeback Operand
2182  switch (Inst.getOpcode()) {
2183    case ARM::VST1d8_UPD:
2184    case ARM::VST1d16_UPD:
2185    case ARM::VST1d32_UPD:
2186    case ARM::VST1d64_UPD:
2187    case ARM::VST1q8_UPD:
2188    case ARM::VST1q16_UPD:
2189    case ARM::VST1q32_UPD:
2190    case ARM::VST1q64_UPD:
2191    case ARM::VST1d8T_UPD:
2192    case ARM::VST1d16T_UPD:
2193    case ARM::VST1d32T_UPD:
2194    case ARM::VST1d64T_UPD:
2195    case ARM::VST1d8Q_UPD:
2196    case ARM::VST1d16Q_UPD:
2197    case ARM::VST1d32Q_UPD:
2198    case ARM::VST1d64Q_UPD:
2199    case ARM::VST2d8_UPD:
2200    case ARM::VST2d16_UPD:
2201    case ARM::VST2d32_UPD:
2202    case ARM::VST2q8_UPD:
2203    case ARM::VST2q16_UPD:
2204    case ARM::VST2q32_UPD:
2205    case ARM::VST2b8_UPD:
2206    case ARM::VST2b16_UPD:
2207    case ARM::VST2b32_UPD:
2208    case ARM::VST3d8_UPD:
2209    case ARM::VST3d16_UPD:
2210    case ARM::VST3d32_UPD:
2211    case ARM::VST3q8_UPD:
2212    case ARM::VST3q16_UPD:
2213    case ARM::VST3q32_UPD:
2214    case ARM::VST4d8_UPD:
2215    case ARM::VST4d16_UPD:
2216    case ARM::VST4d32_UPD:
2217    case ARM::VST4q8_UPD:
2218    case ARM::VST4q16_UPD:
2219    case ARM::VST4q32_UPD:
2220      if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2221        return MCDisassembler::Fail;
2222      break;
2223    default:
2224      break;
2225  }
2226
2227  // AddrMode6 Base (register+alignment)
2228  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2229    return MCDisassembler::Fail;
2230
2231  // AddrMode6 Offset (register)
2232  if (Rm == 0xD)
2233    Inst.addOperand(MCOperand::CreateReg(0));
2234  else if (Rm != 0xF) {
2235    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2236    return MCDisassembler::Fail;
2237  }
2238
2239  // First input register
2240  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2241    return MCDisassembler::Fail;
2242
2243  // Second input register
2244  switch (Inst.getOpcode()) {
2245    case ARM::VST1q8:
2246    case ARM::VST1q16:
2247    case ARM::VST1q32:
2248    case ARM::VST1q64:
2249    case ARM::VST1q8_UPD:
2250    case ARM::VST1q16_UPD:
2251    case ARM::VST1q32_UPD:
2252    case ARM::VST1q64_UPD:
2253    case ARM::VST1d8T:
2254    case ARM::VST1d16T:
2255    case ARM::VST1d32T:
2256    case ARM::VST1d64T:
2257    case ARM::VST1d8T_UPD:
2258    case ARM::VST1d16T_UPD:
2259    case ARM::VST1d32T_UPD:
2260    case ARM::VST1d64T_UPD:
2261    case ARM::VST1d8Q:
2262    case ARM::VST1d16Q:
2263    case ARM::VST1d32Q:
2264    case ARM::VST1d64Q:
2265    case ARM::VST1d8Q_UPD:
2266    case ARM::VST1d16Q_UPD:
2267    case ARM::VST1d32Q_UPD:
2268    case ARM::VST1d64Q_UPD:
2269    case ARM::VST2d8:
2270    case ARM::VST2d16:
2271    case ARM::VST2d32:
2272    case ARM::VST2d8_UPD:
2273    case ARM::VST2d16_UPD:
2274    case ARM::VST2d32_UPD:
2275    case ARM::VST2q8:
2276    case ARM::VST2q16:
2277    case ARM::VST2q32:
2278    case ARM::VST2q8_UPD:
2279    case ARM::VST2q16_UPD:
2280    case ARM::VST2q32_UPD:
2281    case ARM::VST3d8:
2282    case ARM::VST3d16:
2283    case ARM::VST3d32:
2284    case ARM::VST3d8_UPD:
2285    case ARM::VST3d16_UPD:
2286    case ARM::VST3d32_UPD:
2287    case ARM::VST4d8:
2288    case ARM::VST4d16:
2289    case ARM::VST4d32:
2290    case ARM::VST4d8_UPD:
2291    case ARM::VST4d16_UPD:
2292    case ARM::VST4d32_UPD:
2293      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2294        return MCDisassembler::Fail;
2295      break;
2296    case ARM::VST2b8:
2297    case ARM::VST2b16:
2298    case ARM::VST2b32:
2299    case ARM::VST2b8_UPD:
2300    case ARM::VST2b16_UPD:
2301    case ARM::VST2b32_UPD:
2302    case ARM::VST3q8:
2303    case ARM::VST3q16:
2304    case ARM::VST3q32:
2305    case ARM::VST3q8_UPD:
2306    case ARM::VST3q16_UPD:
2307    case ARM::VST3q32_UPD:
2308    case ARM::VST4q8:
2309    case ARM::VST4q16:
2310    case ARM::VST4q32:
2311    case ARM::VST4q8_UPD:
2312    case ARM::VST4q16_UPD:
2313    case ARM::VST4q32_UPD:
2314      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2315        return MCDisassembler::Fail;
2316      break;
2317    default:
2318      break;
2319  }
2320
2321  // Third input register
2322  switch (Inst.getOpcode()) {
2323    case ARM::VST1d8T:
2324    case ARM::VST1d16T:
2325    case ARM::VST1d32T:
2326    case ARM::VST1d64T:
2327    case ARM::VST1d8T_UPD:
2328    case ARM::VST1d16T_UPD:
2329    case ARM::VST1d32T_UPD:
2330    case ARM::VST1d64T_UPD:
2331    case ARM::VST1d8Q:
2332    case ARM::VST1d16Q:
2333    case ARM::VST1d32Q:
2334    case ARM::VST1d64Q:
2335    case ARM::VST1d8Q_UPD:
2336    case ARM::VST1d16Q_UPD:
2337    case ARM::VST1d32Q_UPD:
2338    case ARM::VST1d64Q_UPD:
2339    case ARM::VST2q8:
2340    case ARM::VST2q16:
2341    case ARM::VST2q32:
2342    case ARM::VST2q8_UPD:
2343    case ARM::VST2q16_UPD:
2344    case ARM::VST2q32_UPD:
2345    case ARM::VST3d8:
2346    case ARM::VST3d16:
2347    case ARM::VST3d32:
2348    case ARM::VST3d8_UPD:
2349    case ARM::VST3d16_UPD:
2350    case ARM::VST3d32_UPD:
2351    case ARM::VST4d8:
2352    case ARM::VST4d16:
2353    case ARM::VST4d32:
2354    case ARM::VST4d8_UPD:
2355    case ARM::VST4d16_UPD:
2356    case ARM::VST4d32_UPD:
2357      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2358        return MCDisassembler::Fail;
2359      break;
2360    case ARM::VST3q8:
2361    case ARM::VST3q16:
2362    case ARM::VST3q32:
2363    case ARM::VST3q8_UPD:
2364    case ARM::VST3q16_UPD:
2365    case ARM::VST3q32_UPD:
2366    case ARM::VST4q8:
2367    case ARM::VST4q16:
2368    case ARM::VST4q32:
2369    case ARM::VST4q8_UPD:
2370    case ARM::VST4q16_UPD:
2371    case ARM::VST4q32_UPD:
2372      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2373        return MCDisassembler::Fail;
2374      break;
2375    default:
2376      break;
2377  }
2378
2379  // Fourth input register
2380  switch (Inst.getOpcode()) {
2381    case ARM::VST1d8Q:
2382    case ARM::VST1d16Q:
2383    case ARM::VST1d32Q:
2384    case ARM::VST1d64Q:
2385    case ARM::VST1d8Q_UPD:
2386    case ARM::VST1d16Q_UPD:
2387    case ARM::VST1d32Q_UPD:
2388    case ARM::VST1d64Q_UPD:
2389    case ARM::VST2q8:
2390    case ARM::VST2q16:
2391    case ARM::VST2q32:
2392    case ARM::VST2q8_UPD:
2393    case ARM::VST2q16_UPD:
2394    case ARM::VST2q32_UPD:
2395    case ARM::VST4d8:
2396    case ARM::VST4d16:
2397    case ARM::VST4d32:
2398    case ARM::VST4d8_UPD:
2399    case ARM::VST4d16_UPD:
2400    case ARM::VST4d32_UPD:
2401      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2402        return MCDisassembler::Fail;
2403      break;
2404    case ARM::VST4q8:
2405    case ARM::VST4q16:
2406    case ARM::VST4q32:
2407    case ARM::VST4q8_UPD:
2408    case ARM::VST4q16_UPD:
2409    case ARM::VST4q32_UPD:
2410      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2411        return MCDisassembler::Fail;
2412      break;
2413    default:
2414      break;
2415  }
2416
2417  return S;
2418}
2419
2420static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2421                                    uint64_t Address, const void *Decoder) {
2422  DecodeStatus S = MCDisassembler::Success;
2423
2424  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2425  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2426  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2427  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2428  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2429  unsigned size = fieldFromInstruction32(Insn, 6, 2);
2430  unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2431
2432  align *= (1 << size);
2433
2434  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2435    return MCDisassembler::Fail;
2436  if (regs == 2) {
2437    if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2438      return MCDisassembler::Fail;
2439  }
2440  if (Rm != 0xF) {
2441    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2442      return MCDisassembler::Fail;
2443  }
2444
2445  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2446    return MCDisassembler::Fail;
2447  Inst.addOperand(MCOperand::CreateImm(align));
2448
2449  if (Rm == 0xD)
2450    Inst.addOperand(MCOperand::CreateReg(0));
2451  else if (Rm != 0xF) {
2452    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2453      return MCDisassembler::Fail;
2454  }
2455
2456  return S;
2457}
2458
2459static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2460                                    uint64_t Address, const void *Decoder) {
2461  DecodeStatus S = MCDisassembler::Success;
2462
2463  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2464  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2465  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2466  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2467  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2468  unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2469  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2470  align *= 2*size;
2471
2472  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2473    return MCDisassembler::Fail;
2474  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2475    return MCDisassembler::Fail;
2476  if (Rm != 0xF) {
2477    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2478      return MCDisassembler::Fail;
2479  }
2480
2481  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2482    return MCDisassembler::Fail;
2483  Inst.addOperand(MCOperand::CreateImm(align));
2484
2485  if (Rm == 0xD)
2486    Inst.addOperand(MCOperand::CreateReg(0));
2487  else if (Rm != 0xF) {
2488    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2489      return MCDisassembler::Fail;
2490  }
2491
2492  return S;
2493}
2494
2495static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2496                                    uint64_t Address, const void *Decoder) {
2497  DecodeStatus S = MCDisassembler::Success;
2498
2499  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2500  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2501  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2502  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2503  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2504
2505  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2506    return MCDisassembler::Fail;
2507  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2508    return MCDisassembler::Fail;
2509  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2510    return MCDisassembler::Fail;
2511  if (Rm != 0xF) {
2512    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2513      return MCDisassembler::Fail;
2514  }
2515
2516  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2517    return MCDisassembler::Fail;
2518  Inst.addOperand(MCOperand::CreateImm(0));
2519
2520  if (Rm == 0xD)
2521    Inst.addOperand(MCOperand::CreateReg(0));
2522  else if (Rm != 0xF) {
2523    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2524      return MCDisassembler::Fail;
2525  }
2526
2527  return S;
2528}
2529
2530static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2531                                    uint64_t Address, const void *Decoder) {
2532  DecodeStatus S = MCDisassembler::Success;
2533
2534  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2535  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2536  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2537  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2538  unsigned size = fieldFromInstruction32(Insn, 6, 2);
2539  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2540  unsigned align = fieldFromInstruction32(Insn, 4, 1);
2541
2542  if (size == 0x3) {
2543    size = 4;
2544    align = 16;
2545  } else {
2546    if (size == 2) {
2547      size = 1 << size;
2548      align *= 8;
2549    } else {
2550      size = 1 << size;
2551      align *= 4*size;
2552    }
2553  }
2554
2555  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2556    return MCDisassembler::Fail;
2557  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2558    return MCDisassembler::Fail;
2559  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2560    return MCDisassembler::Fail;
2561  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2562    return MCDisassembler::Fail;
2563  if (Rm != 0xF) {
2564    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2565      return MCDisassembler::Fail;
2566  }
2567
2568  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2569    return MCDisassembler::Fail;
2570  Inst.addOperand(MCOperand::CreateImm(align));
2571
2572  if (Rm == 0xD)
2573    Inst.addOperand(MCOperand::CreateReg(0));
2574  else if (Rm != 0xF) {
2575    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2576      return MCDisassembler::Fail;
2577  }
2578
2579  return S;
2580}
2581
2582static DecodeStatus
2583DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2584                            uint64_t Address, const void *Decoder) {
2585  DecodeStatus S = MCDisassembler::Success;
2586
2587  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2588  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2589  unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2590  imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2591  imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2592  imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2593  imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2594  unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2595
2596  if (Q) {
2597    if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2598    return MCDisassembler::Fail;
2599  } else {
2600    if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2601    return MCDisassembler::Fail;
2602  }
2603
2604  Inst.addOperand(MCOperand::CreateImm(imm));
2605
2606  switch (Inst.getOpcode()) {
2607    case ARM::VORRiv4i16:
2608    case ARM::VORRiv2i32:
2609    case ARM::VBICiv4i16:
2610    case ARM::VBICiv2i32:
2611      if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2612        return MCDisassembler::Fail;
2613      break;
2614    case ARM::VORRiv8i16:
2615    case ARM::VORRiv4i32:
2616    case ARM::VBICiv8i16:
2617    case ARM::VBICiv4i32:
2618      if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2619        return MCDisassembler::Fail;
2620      break;
2621    default:
2622      break;
2623  }
2624
2625  return S;
2626}
2627
2628static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2629                                        uint64_t Address, const void *Decoder) {
2630  DecodeStatus S = MCDisassembler::Success;
2631
2632  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2633  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2634  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2635  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2636  unsigned size = fieldFromInstruction32(Insn, 18, 2);
2637
2638  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2639    return MCDisassembler::Fail;
2640  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2641    return MCDisassembler::Fail;
2642  Inst.addOperand(MCOperand::CreateImm(8 << size));
2643
2644  return S;
2645}
2646
2647static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2648                               uint64_t Address, const void *Decoder) {
2649  Inst.addOperand(MCOperand::CreateImm(8 - Val));
2650  return MCDisassembler::Success;
2651}
2652
2653static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2654                               uint64_t Address, const void *Decoder) {
2655  Inst.addOperand(MCOperand::CreateImm(16 - Val));
2656  return MCDisassembler::Success;
2657}
2658
2659static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2660                               uint64_t Address, const void *Decoder) {
2661  Inst.addOperand(MCOperand::CreateImm(32 - Val));
2662  return MCDisassembler::Success;
2663}
2664
2665static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2666                               uint64_t Address, const void *Decoder) {
2667  Inst.addOperand(MCOperand::CreateImm(64 - Val));
2668  return MCDisassembler::Success;
2669}
2670
2671static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2672                               uint64_t Address, const void *Decoder) {
2673  DecodeStatus S = MCDisassembler::Success;
2674
2675  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2676  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2677  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2678  Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2679  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2680  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2681  unsigned op = fieldFromInstruction32(Insn, 6, 1);
2682  unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2683
2684  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2685    return MCDisassembler::Fail;
2686  if (op) {
2687    if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2688    return MCDisassembler::Fail; // Writeback
2689  }
2690
2691  for (unsigned i = 0; i < length; ++i) {
2692    if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2693    return MCDisassembler::Fail;
2694  }
2695
2696  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2697    return MCDisassembler::Fail;
2698
2699  return S;
2700}
2701
2702static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2703                                     uint64_t Address, const void *Decoder) {
2704  DecodeStatus S = MCDisassembler::Success;
2705
2706  unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2707  unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2708
2709  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2710    return MCDisassembler::Fail;
2711
2712  switch(Inst.getOpcode()) {
2713    default:
2714      return MCDisassembler::Fail;
2715    case ARM::tADR:
2716      break; // tADR does not explicitly represent the PC as an operand.
2717    case ARM::tADDrSPi:
2718      Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2719      break;
2720  }
2721
2722  Inst.addOperand(MCOperand::CreateImm(imm));
2723  return S;
2724}
2725
2726static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2727                                 uint64_t Address, const void *Decoder) {
2728  Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2729  return MCDisassembler::Success;
2730}
2731
2732static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2733                                 uint64_t Address, const void *Decoder) {
2734  Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2735  return MCDisassembler::Success;
2736}
2737
2738static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2739                                 uint64_t Address, const void *Decoder) {
2740  Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2741  return MCDisassembler::Success;
2742}
2743
2744static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2745                                 uint64_t Address, const void *Decoder) {
2746  DecodeStatus S = MCDisassembler::Success;
2747
2748  unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2749  unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2750
2751  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2752    return MCDisassembler::Fail;
2753  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2754    return MCDisassembler::Fail;
2755
2756  return S;
2757}
2758
2759static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2760                                  uint64_t Address, const void *Decoder) {
2761  DecodeStatus S = MCDisassembler::Success;
2762
2763  unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2764  unsigned imm = fieldFromInstruction32(Val, 3, 5);
2765
2766  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2767    return MCDisassembler::Fail;
2768  Inst.addOperand(MCOperand::CreateImm(imm));
2769
2770  return S;
2771}
2772
2773static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2774                                  uint64_t Address, const void *Decoder) {
2775  unsigned imm = Val << 2;
2776
2777  Inst.addOperand(MCOperand::CreateImm(imm));
2778  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
2779
2780  return MCDisassembler::Success;
2781}
2782
2783static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2784                                  uint64_t Address, const void *Decoder) {
2785  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2786  Inst.addOperand(MCOperand::CreateImm(Val));
2787
2788  return MCDisassembler::Success;
2789}
2790
2791static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2792                                  uint64_t Address, const void *Decoder) {
2793  DecodeStatus S = MCDisassembler::Success;
2794
2795  unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2796  unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2797  unsigned imm = fieldFromInstruction32(Val, 0, 2);
2798
2799  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2800    return MCDisassembler::Fail;
2801  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2802    return MCDisassembler::Fail;
2803  Inst.addOperand(MCOperand::CreateImm(imm));
2804
2805  return S;
2806}
2807
2808static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2809                              uint64_t Address, const void *Decoder) {
2810  DecodeStatus S = MCDisassembler::Success;
2811
2812  switch (Inst.getOpcode()) {
2813    case ARM::t2PLDs:
2814    case ARM::t2PLDWs:
2815    case ARM::t2PLIs:
2816      break;
2817    default: {
2818      unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2819      if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
2820    return MCDisassembler::Fail;
2821    }
2822  }
2823
2824  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2825  if (Rn == 0xF) {
2826    switch (Inst.getOpcode()) {
2827      case ARM::t2LDRBs:
2828        Inst.setOpcode(ARM::t2LDRBpci);
2829        break;
2830      case ARM::t2LDRHs:
2831        Inst.setOpcode(ARM::t2LDRHpci);
2832        break;
2833      case ARM::t2LDRSHs:
2834        Inst.setOpcode(ARM::t2LDRSHpci);
2835        break;
2836      case ARM::t2LDRSBs:
2837        Inst.setOpcode(ARM::t2LDRSBpci);
2838        break;
2839      case ARM::t2PLDs:
2840        Inst.setOpcode(ARM::t2PLDi12);
2841        Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2842        break;
2843      default:
2844        return MCDisassembler::Fail;
2845    }
2846
2847    int imm = fieldFromInstruction32(Insn, 0, 12);
2848    if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2849    Inst.addOperand(MCOperand::CreateImm(imm));
2850
2851    return S;
2852  }
2853
2854  unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2855  addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2856  addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2857  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2858    return MCDisassembler::Fail;
2859
2860  return S;
2861}
2862
2863static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2864                           uint64_t Address, const void *Decoder) {
2865  int imm = Val & 0xFF;
2866  if (!(Val & 0x100)) imm *= -1;
2867  Inst.addOperand(MCOperand::CreateImm(imm << 2));
2868
2869  return MCDisassembler::Success;
2870}
2871
2872static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2873                                   uint64_t Address, const void *Decoder) {
2874  DecodeStatus S = MCDisassembler::Success;
2875
2876  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2877  unsigned imm = fieldFromInstruction32(Val, 0, 9);
2878
2879  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2880    return MCDisassembler::Fail;
2881  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2882    return MCDisassembler::Fail;
2883
2884  return S;
2885}
2886
2887static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2888                                   uint64_t Address, const void *Decoder) {
2889  DecodeStatus S = MCDisassembler::Success;
2890
2891  unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2892  unsigned imm = fieldFromInstruction32(Val, 0, 8);
2893
2894  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2895    return MCDisassembler::Fail;
2896
2897  Inst.addOperand(MCOperand::CreateImm(imm));
2898
2899  return S;
2900}
2901
2902static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2903                         uint64_t Address, const void *Decoder) {
2904  int imm = Val & 0xFF;
2905  if (Val == 0)
2906    imm = INT32_MIN;
2907  else if (!(Val & 0x100))
2908    imm *= -1;
2909  Inst.addOperand(MCOperand::CreateImm(imm));
2910
2911  return MCDisassembler::Success;
2912}
2913
2914
2915static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2916                                 uint64_t Address, const void *Decoder) {
2917  DecodeStatus S = MCDisassembler::Success;
2918
2919  unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2920  unsigned imm = fieldFromInstruction32(Val, 0, 9);
2921
2922  // Some instructions always use an additive offset.
2923  switch (Inst.getOpcode()) {
2924    case ARM::t2LDRT:
2925    case ARM::t2LDRBT:
2926    case ARM::t2LDRHT:
2927    case ARM::t2LDRSBT:
2928    case ARM::t2LDRSHT:
2929    case ARM::t2STRT:
2930    case ARM::t2STRBT:
2931    case ARM::t2STRHT:
2932      imm |= 0x100;
2933      break;
2934    default:
2935      break;
2936  }
2937
2938  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2939    return MCDisassembler::Fail;
2940  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2941    return MCDisassembler::Fail;
2942
2943  return S;
2944}
2945
2946static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2947                                    uint64_t Address, const void *Decoder) {
2948  DecodeStatus S = MCDisassembler::Success;
2949
2950  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2951  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2952  unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2953  addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2954  addr |= Rn << 9;
2955  unsigned load = fieldFromInstruction32(Insn, 20, 1);
2956
2957  if (!load) {
2958    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2959      return MCDisassembler::Fail;
2960  }
2961
2962  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
2963    return MCDisassembler::Fail;
2964
2965  if (load) {
2966    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2967      return MCDisassembler::Fail;
2968  }
2969
2970  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2971    return MCDisassembler::Fail;
2972
2973  return S;
2974}
2975
2976static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2977                                  uint64_t Address, const void *Decoder) {
2978  DecodeStatus S = MCDisassembler::Success;
2979
2980  unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2981  unsigned imm = fieldFromInstruction32(Val, 0, 12);
2982
2983  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2984    return MCDisassembler::Fail;
2985  Inst.addOperand(MCOperand::CreateImm(imm));
2986
2987  return S;
2988}
2989
2990
2991static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2992                                uint64_t Address, const void *Decoder) {
2993  unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2994
2995  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2996  Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2997  Inst.addOperand(MCOperand::CreateImm(imm));
2998
2999  return MCDisassembler::Success;
3000}
3001
3002static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
3003                                uint64_t Address, const void *Decoder) {
3004  DecodeStatus S = MCDisassembler::Success;
3005
3006  if (Inst.getOpcode() == ARM::tADDrSP) {
3007    unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3008    Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3009
3010    if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3011    return MCDisassembler::Fail;
3012    if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3013    return MCDisassembler::Fail;
3014    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3015  } else if (Inst.getOpcode() == ARM::tADDspr) {
3016    unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3017
3018    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3019    Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3020    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3021    return MCDisassembler::Fail;
3022  }
3023
3024  return S;
3025}
3026
3027static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
3028                           uint64_t Address, const void *Decoder) {
3029  unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3030  unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3031
3032  Inst.addOperand(MCOperand::CreateImm(imod));
3033  Inst.addOperand(MCOperand::CreateImm(flags));
3034
3035  return MCDisassembler::Success;
3036}
3037
3038static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
3039                             uint64_t Address, const void *Decoder) {
3040  DecodeStatus S = MCDisassembler::Success;
3041  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3042  unsigned add = fieldFromInstruction32(Insn, 4, 1);
3043
3044  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3045    return MCDisassembler::Fail;
3046  Inst.addOperand(MCOperand::CreateImm(add));
3047
3048  return S;
3049}
3050
3051static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
3052                                 uint64_t Address, const void *Decoder) {
3053  if (!tryAddingSymbolicOperand(Address,
3054                                (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3055                                true, 4, Inst, Decoder))
3056    Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3057  return MCDisassembler::Success;
3058}
3059
3060static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
3061                              uint64_t Address, const void *Decoder) {
3062  if (Val == 0xA || Val == 0xB)
3063    return MCDisassembler::Fail;
3064
3065  Inst.addOperand(MCOperand::CreateImm(Val));
3066  return MCDisassembler::Success;
3067}
3068
3069static DecodeStatus
3070DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3071                       uint64_t Address, const void *Decoder) {
3072  DecodeStatus S = MCDisassembler::Success;
3073
3074  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3075  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3076
3077  if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3078  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3079    return MCDisassembler::Fail;
3080  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3081    return MCDisassembler::Fail;
3082  return S;
3083}
3084
3085static DecodeStatus
3086DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3087                           uint64_t Address, const void *Decoder) {
3088  DecodeStatus S = MCDisassembler::Success;
3089
3090  unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3091  if (pred == 0xE || pred == 0xF) {
3092    unsigned opc = fieldFromInstruction32(Insn, 4, 28);
3093    switch (opc) {
3094      default:
3095        return MCDisassembler::Fail;
3096      case 0xf3bf8f4:
3097        Inst.setOpcode(ARM::t2DSB);
3098        break;
3099      case 0xf3bf8f5:
3100        Inst.setOpcode(ARM::t2DMB);
3101        break;
3102      case 0xf3bf8f6:
3103        Inst.setOpcode(ARM::t2ISB);
3104        break;
3105    }
3106
3107    unsigned imm = fieldFromInstruction32(Insn, 0, 4);
3108    return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3109  }
3110
3111  unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3112  brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3113  brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3114  brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3115  brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3116
3117  if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3118    return MCDisassembler::Fail;
3119  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3120    return MCDisassembler::Fail;
3121
3122  return S;
3123}
3124
3125// Decode a shifted immediate operand.  These basically consist
3126// of an 8-bit value, and a 4-bit directive that specifies either
3127// a splat operation or a rotation.
3128static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
3129                          uint64_t Address, const void *Decoder) {
3130  unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3131  if (ctrl == 0) {
3132    unsigned byte = fieldFromInstruction32(Val, 8, 2);
3133    unsigned imm = fieldFromInstruction32(Val, 0, 8);
3134    switch (byte) {
3135      case 0:
3136        Inst.addOperand(MCOperand::CreateImm(imm));
3137        break;
3138      case 1:
3139        Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3140        break;
3141      case 2:
3142        Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3143        break;
3144      case 3:
3145        Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3146                                             (imm << 8)  |  imm));
3147        break;
3148    }
3149  } else {
3150    unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3151    unsigned rot = fieldFromInstruction32(Val, 7, 5);
3152    unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3153    Inst.addOperand(MCOperand::CreateImm(imm));
3154  }
3155
3156  return MCDisassembler::Success;
3157}
3158
3159static DecodeStatus
3160DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3161                            uint64_t Address, const void *Decoder){
3162  Inst.addOperand(MCOperand::CreateImm(Val << 1));
3163  return MCDisassembler::Success;
3164}
3165
3166static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
3167                                       uint64_t Address, const void *Decoder){
3168  Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3169  return MCDisassembler::Success;
3170}
3171
3172static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
3173                                   uint64_t Address, const void *Decoder) {
3174  switch (Val) {
3175  default:
3176    return MCDisassembler::Fail;
3177  case 0xF: // SY
3178  case 0xE: // ST
3179  case 0xB: // ISH
3180  case 0xA: // ISHST
3181  case 0x7: // NSH
3182  case 0x6: // NSHST
3183  case 0x3: // OSH
3184  case 0x2: // OSHST
3185    break;
3186  }
3187
3188  Inst.addOperand(MCOperand::CreateImm(Val));
3189  return MCDisassembler::Success;
3190}
3191
3192static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
3193                          uint64_t Address, const void *Decoder) {
3194  if (!Val) return MCDisassembler::Fail;
3195  Inst.addOperand(MCOperand::CreateImm(Val));
3196  return MCDisassembler::Success;
3197}
3198
3199static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
3200                                        uint64_t Address, const void *Decoder) {
3201  DecodeStatus S = MCDisassembler::Success;
3202
3203  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3204  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3205  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3206
3207  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3208
3209  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3210    return MCDisassembler::Fail;
3211  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3212    return MCDisassembler::Fail;
3213  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3214    return MCDisassembler::Fail;
3215  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3216    return MCDisassembler::Fail;
3217
3218  return S;
3219}
3220
3221
3222static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
3223                                         uint64_t Address, const void *Decoder){
3224  DecodeStatus S = MCDisassembler::Success;
3225
3226  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3227  unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3228  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3229  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3230
3231  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3232    return MCDisassembler::Fail;
3233
3234  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3235  if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3236
3237  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3238    return MCDisassembler::Fail;
3239  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3240    return MCDisassembler::Fail;
3241  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3242    return MCDisassembler::Fail;
3243  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3244    return MCDisassembler::Fail;
3245
3246  return S;
3247}
3248
3249static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
3250                            uint64_t Address, const void *Decoder) {
3251  DecodeStatus S = MCDisassembler::Success;
3252
3253  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3254  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3255  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3256  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3257  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3258  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3259
3260  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3261
3262  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3263    return MCDisassembler::Fail;
3264  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3265    return MCDisassembler::Fail;
3266  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3267    return MCDisassembler::Fail;
3268  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3269    return MCDisassembler::Fail;
3270
3271  return S;
3272}
3273
3274static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
3275                            uint64_t Address, const void *Decoder) {
3276  DecodeStatus S = MCDisassembler::Success;
3277
3278  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3279  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3280  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3281  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3282  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3283  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3284  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3285
3286  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3287  if (Rm == 0xF) S = MCDisassembler::SoftFail;
3288
3289  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3290    return MCDisassembler::Fail;
3291  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3292    return MCDisassembler::Fail;
3293  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3294    return MCDisassembler::Fail;
3295  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3296    return MCDisassembler::Fail;
3297
3298  return S;
3299}
3300
3301
3302static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
3303                            uint64_t Address, const void *Decoder) {
3304  DecodeStatus S = MCDisassembler::Success;
3305
3306  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3307  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3308  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3309  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3310  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3311  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3312
3313  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3314
3315  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3316    return MCDisassembler::Fail;
3317  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3318    return MCDisassembler::Fail;
3319  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3320    return MCDisassembler::Fail;
3321  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3322    return MCDisassembler::Fail;
3323
3324  return S;
3325}
3326
3327static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
3328                            uint64_t Address, const void *Decoder) {
3329  DecodeStatus S = MCDisassembler::Success;
3330
3331  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3332  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3333  unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3334  imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3335  imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3336  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3337
3338  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3339
3340  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3341    return MCDisassembler::Fail;
3342  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3343    return MCDisassembler::Fail;
3344  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3345    return MCDisassembler::Fail;
3346  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3347    return MCDisassembler::Fail;
3348
3349  return S;
3350}
3351
3352static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
3353                         uint64_t Address, const void *Decoder) {
3354  DecodeStatus S = MCDisassembler::Success;
3355
3356  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3357  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3358  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3359  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3360  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3361
3362  unsigned align = 0;
3363  unsigned index = 0;
3364  switch (size) {
3365    default:
3366      return MCDisassembler::Fail;
3367    case 0:
3368      if (fieldFromInstruction32(Insn, 4, 1))
3369        return MCDisassembler::Fail; // UNDEFINED
3370      index = fieldFromInstruction32(Insn, 5, 3);
3371      break;
3372    case 1:
3373      if (fieldFromInstruction32(Insn, 5, 1))
3374        return MCDisassembler::Fail; // UNDEFINED
3375      index = fieldFromInstruction32(Insn, 6, 2);
3376      if (fieldFromInstruction32(Insn, 4, 1))
3377        align = 2;
3378      break;
3379    case 2:
3380      if (fieldFromInstruction32(Insn, 6, 1))
3381        return MCDisassembler::Fail; // UNDEFINED
3382      index = fieldFromInstruction32(Insn, 7, 1);
3383      if (fieldFromInstruction32(Insn, 4, 2) != 0)
3384        align = 4;
3385  }
3386
3387  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3388    return MCDisassembler::Fail;
3389  if (Rm != 0xF) { // Writeback
3390    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3391      return MCDisassembler::Fail;
3392  }
3393  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3394    return MCDisassembler::Fail;
3395  Inst.addOperand(MCOperand::CreateImm(align));
3396  if (Rm != 0xF) {
3397    if (Rm != 0xD) {
3398      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3399        return MCDisassembler::Fail;
3400    } else
3401      Inst.addOperand(MCOperand::CreateReg(0));
3402  }
3403
3404  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3405    return MCDisassembler::Fail;
3406  Inst.addOperand(MCOperand::CreateImm(index));
3407
3408  return S;
3409}
3410
3411static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
3412                         uint64_t Address, const void *Decoder) {
3413  DecodeStatus S = MCDisassembler::Success;
3414
3415  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3416  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3417  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3418  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3419  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3420
3421  unsigned align = 0;
3422  unsigned index = 0;
3423  switch (size) {
3424    default:
3425      return MCDisassembler::Fail;
3426    case 0:
3427      if (fieldFromInstruction32(Insn, 4, 1))
3428        return MCDisassembler::Fail; // UNDEFINED
3429      index = fieldFromInstruction32(Insn, 5, 3);
3430      break;
3431    case 1:
3432      if (fieldFromInstruction32(Insn, 5, 1))
3433        return MCDisassembler::Fail; // UNDEFINED
3434      index = fieldFromInstruction32(Insn, 6, 2);
3435      if (fieldFromInstruction32(Insn, 4, 1))
3436        align = 2;
3437      break;
3438    case 2:
3439      if (fieldFromInstruction32(Insn, 6, 1))
3440        return MCDisassembler::Fail; // UNDEFINED
3441      index = fieldFromInstruction32(Insn, 7, 1);
3442      if (fieldFromInstruction32(Insn, 4, 2) != 0)
3443        align = 4;
3444  }
3445
3446  if (Rm != 0xF) { // Writeback
3447    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3448    return MCDisassembler::Fail;
3449  }
3450  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3451    return MCDisassembler::Fail;
3452  Inst.addOperand(MCOperand::CreateImm(align));
3453  if (Rm != 0xF) {
3454    if (Rm != 0xD) {
3455      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3456    return MCDisassembler::Fail;
3457    } else
3458      Inst.addOperand(MCOperand::CreateReg(0));
3459  }
3460
3461  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3462    return MCDisassembler::Fail;
3463  Inst.addOperand(MCOperand::CreateImm(index));
3464
3465  return S;
3466}
3467
3468
3469static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
3470                         uint64_t Address, const void *Decoder) {
3471  DecodeStatus S = MCDisassembler::Success;
3472
3473  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3474  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3475  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3476  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3477  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3478
3479  unsigned align = 0;
3480  unsigned index = 0;
3481  unsigned inc = 1;
3482  switch (size) {
3483    default:
3484      return MCDisassembler::Fail;
3485    case 0:
3486      index = fieldFromInstruction32(Insn, 5, 3);
3487      if (fieldFromInstruction32(Insn, 4, 1))
3488        align = 2;
3489      break;
3490    case 1:
3491      index = fieldFromInstruction32(Insn, 6, 2);
3492      if (fieldFromInstruction32(Insn, 4, 1))
3493        align = 4;
3494      if (fieldFromInstruction32(Insn, 5, 1))
3495        inc = 2;
3496      break;
3497    case 2:
3498      if (fieldFromInstruction32(Insn, 5, 1))
3499        return MCDisassembler::Fail; // UNDEFINED
3500      index = fieldFromInstruction32(Insn, 7, 1);
3501      if (fieldFromInstruction32(Insn, 4, 1) != 0)
3502        align = 8;
3503      if (fieldFromInstruction32(Insn, 6, 1))
3504        inc = 2;
3505      break;
3506  }
3507
3508  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3509    return MCDisassembler::Fail;
3510  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3511    return MCDisassembler::Fail;
3512  if (Rm != 0xF) { // Writeback
3513    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3514      return MCDisassembler::Fail;
3515  }
3516  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3517    return MCDisassembler::Fail;
3518  Inst.addOperand(MCOperand::CreateImm(align));
3519  if (Rm != 0xF) {
3520    if (Rm != 0xD) {
3521      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3522        return MCDisassembler::Fail;
3523    } else
3524      Inst.addOperand(MCOperand::CreateReg(0));
3525  }
3526
3527  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3528    return MCDisassembler::Fail;
3529  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3530    return MCDisassembler::Fail;
3531  Inst.addOperand(MCOperand::CreateImm(index));
3532
3533  return S;
3534}
3535
3536static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
3537                         uint64_t Address, const void *Decoder) {
3538  DecodeStatus S = MCDisassembler::Success;
3539
3540  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3541  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3542  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3543  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3544  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3545
3546  unsigned align = 0;
3547  unsigned index = 0;
3548  unsigned inc = 1;
3549  switch (size) {
3550    default:
3551      return MCDisassembler::Fail;
3552    case 0:
3553      index = fieldFromInstruction32(Insn, 5, 3);
3554      if (fieldFromInstruction32(Insn, 4, 1))
3555        align = 2;
3556      break;
3557    case 1:
3558      index = fieldFromInstruction32(Insn, 6, 2);
3559      if (fieldFromInstruction32(Insn, 4, 1))
3560        align = 4;
3561      if (fieldFromInstruction32(Insn, 5, 1))
3562        inc = 2;
3563      break;
3564    case 2:
3565      if (fieldFromInstruction32(Insn, 5, 1))
3566        return MCDisassembler::Fail; // UNDEFINED
3567      index = fieldFromInstruction32(Insn, 7, 1);
3568      if (fieldFromInstruction32(Insn, 4, 1) != 0)
3569        align = 8;
3570      if (fieldFromInstruction32(Insn, 6, 1))
3571        inc = 2;
3572      break;
3573  }
3574
3575  if (Rm != 0xF) { // Writeback
3576    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3577      return MCDisassembler::Fail;
3578  }
3579  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3580    return MCDisassembler::Fail;
3581  Inst.addOperand(MCOperand::CreateImm(align));
3582  if (Rm != 0xF) {
3583    if (Rm != 0xD) {
3584      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3585        return MCDisassembler::Fail;
3586    } else
3587      Inst.addOperand(MCOperand::CreateReg(0));
3588  }
3589
3590  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3591    return MCDisassembler::Fail;
3592  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3593    return MCDisassembler::Fail;
3594  Inst.addOperand(MCOperand::CreateImm(index));
3595
3596  return S;
3597}
3598
3599
3600static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3601                         uint64_t Address, const void *Decoder) {
3602  DecodeStatus S = MCDisassembler::Success;
3603
3604  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3605  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3606  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3607  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3608  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3609
3610  unsigned align = 0;
3611  unsigned index = 0;
3612  unsigned inc = 1;
3613  switch (size) {
3614    default:
3615      return MCDisassembler::Fail;
3616    case 0:
3617      if (fieldFromInstruction32(Insn, 4, 1))
3618        return MCDisassembler::Fail; // UNDEFINED
3619      index = fieldFromInstruction32(Insn, 5, 3);
3620      break;
3621    case 1:
3622      if (fieldFromInstruction32(Insn, 4, 1))
3623        return MCDisassembler::Fail; // UNDEFINED
3624      index = fieldFromInstruction32(Insn, 6, 2);
3625      if (fieldFromInstruction32(Insn, 5, 1))
3626        inc = 2;
3627      break;
3628    case 2:
3629      if (fieldFromInstruction32(Insn, 4, 2))
3630        return MCDisassembler::Fail; // UNDEFINED
3631      index = fieldFromInstruction32(Insn, 7, 1);
3632      if (fieldFromInstruction32(Insn, 6, 1))
3633        inc = 2;
3634      break;
3635  }
3636
3637  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3638    return MCDisassembler::Fail;
3639  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3640    return MCDisassembler::Fail;
3641  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3642    return MCDisassembler::Fail;
3643
3644  if (Rm != 0xF) { // Writeback
3645    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3646    return MCDisassembler::Fail;
3647  }
3648  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3649    return MCDisassembler::Fail;
3650  Inst.addOperand(MCOperand::CreateImm(align));
3651  if (Rm != 0xF) {
3652    if (Rm != 0xD) {
3653      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3654    return MCDisassembler::Fail;
3655    } else
3656      Inst.addOperand(MCOperand::CreateReg(0));
3657  }
3658
3659  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3660    return MCDisassembler::Fail;
3661  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3662    return MCDisassembler::Fail;
3663  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3664    return MCDisassembler::Fail;
3665  Inst.addOperand(MCOperand::CreateImm(index));
3666
3667  return S;
3668}
3669
3670static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3671                         uint64_t Address, const void *Decoder) {
3672  DecodeStatus S = MCDisassembler::Success;
3673
3674  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3675  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3676  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3677  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3678  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3679
3680  unsigned align = 0;
3681  unsigned index = 0;
3682  unsigned inc = 1;
3683  switch (size) {
3684    default:
3685      return MCDisassembler::Fail;
3686    case 0:
3687      if (fieldFromInstruction32(Insn, 4, 1))
3688        return MCDisassembler::Fail; // UNDEFINED
3689      index = fieldFromInstruction32(Insn, 5, 3);
3690      break;
3691    case 1:
3692      if (fieldFromInstruction32(Insn, 4, 1))
3693        return MCDisassembler::Fail; // UNDEFINED
3694      index = fieldFromInstruction32(Insn, 6, 2);
3695      if (fieldFromInstruction32(Insn, 5, 1))
3696        inc = 2;
3697      break;
3698    case 2:
3699      if (fieldFromInstruction32(Insn, 4, 2))
3700        return MCDisassembler::Fail; // UNDEFINED
3701      index = fieldFromInstruction32(Insn, 7, 1);
3702      if (fieldFromInstruction32(Insn, 6, 1))
3703        inc = 2;
3704      break;
3705  }
3706
3707  if (Rm != 0xF) { // Writeback
3708    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3709    return MCDisassembler::Fail;
3710  }
3711  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3712    return MCDisassembler::Fail;
3713  Inst.addOperand(MCOperand::CreateImm(align));
3714  if (Rm != 0xF) {
3715    if (Rm != 0xD) {
3716      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3717    return MCDisassembler::Fail;
3718    } else
3719      Inst.addOperand(MCOperand::CreateReg(0));
3720  }
3721
3722  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3723    return MCDisassembler::Fail;
3724  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3725    return MCDisassembler::Fail;
3726  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3727    return MCDisassembler::Fail;
3728  Inst.addOperand(MCOperand::CreateImm(index));
3729
3730  return S;
3731}
3732
3733
3734static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3735                         uint64_t Address, const void *Decoder) {
3736  DecodeStatus S = MCDisassembler::Success;
3737
3738  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3739  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3740  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3741  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3742  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3743
3744  unsigned align = 0;
3745  unsigned index = 0;
3746  unsigned inc = 1;
3747  switch (size) {
3748    default:
3749      return MCDisassembler::Fail;
3750    case 0:
3751      if (fieldFromInstruction32(Insn, 4, 1))
3752        align = 4;
3753      index = fieldFromInstruction32(Insn, 5, 3);
3754      break;
3755    case 1:
3756      if (fieldFromInstruction32(Insn, 4, 1))
3757        align = 8;
3758      index = fieldFromInstruction32(Insn, 6, 2);
3759      if (fieldFromInstruction32(Insn, 5, 1))
3760        inc = 2;
3761      break;
3762    case 2:
3763      if (fieldFromInstruction32(Insn, 4, 2))
3764        align = 4 << fieldFromInstruction32(Insn, 4, 2);
3765      index = fieldFromInstruction32(Insn, 7, 1);
3766      if (fieldFromInstruction32(Insn, 6, 1))
3767        inc = 2;
3768      break;
3769  }
3770
3771  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3772    return MCDisassembler::Fail;
3773  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3774    return MCDisassembler::Fail;
3775  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3776    return MCDisassembler::Fail;
3777  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3778    return MCDisassembler::Fail;
3779
3780  if (Rm != 0xF) { // Writeback
3781    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3782      return MCDisassembler::Fail;
3783  }
3784  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3785    return MCDisassembler::Fail;
3786  Inst.addOperand(MCOperand::CreateImm(align));
3787  if (Rm != 0xF) {
3788    if (Rm != 0xD) {
3789      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3790        return MCDisassembler::Fail;
3791    } else
3792      Inst.addOperand(MCOperand::CreateReg(0));
3793  }
3794
3795  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3796    return MCDisassembler::Fail;
3797  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3798    return MCDisassembler::Fail;
3799  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3800    return MCDisassembler::Fail;
3801  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3802    return MCDisassembler::Fail;
3803  Inst.addOperand(MCOperand::CreateImm(index));
3804
3805  return S;
3806}
3807
3808static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3809                         uint64_t Address, const void *Decoder) {
3810  DecodeStatus S = MCDisassembler::Success;
3811
3812  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3813  unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3814  unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3815  Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3816  unsigned size = fieldFromInstruction32(Insn, 10, 2);
3817
3818  unsigned align = 0;
3819  unsigned index = 0;
3820  unsigned inc = 1;
3821  switch (size) {
3822    default:
3823      return MCDisassembler::Fail;
3824    case 0:
3825      if (fieldFromInstruction32(Insn, 4, 1))
3826        align = 4;
3827      index = fieldFromInstruction32(Insn, 5, 3);
3828      break;
3829    case 1:
3830      if (fieldFromInstruction32(Insn, 4, 1))
3831        align = 8;
3832      index = fieldFromInstruction32(Insn, 6, 2);
3833      if (fieldFromInstruction32(Insn, 5, 1))
3834        inc = 2;
3835      break;
3836    case 2:
3837      if (fieldFromInstruction32(Insn, 4, 2))
3838        align = 4 << fieldFromInstruction32(Insn, 4, 2);
3839      index = fieldFromInstruction32(Insn, 7, 1);
3840      if (fieldFromInstruction32(Insn, 6, 1))
3841        inc = 2;
3842      break;
3843  }
3844
3845  if (Rm != 0xF) { // Writeback
3846    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3847    return MCDisassembler::Fail;
3848  }
3849  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3850    return MCDisassembler::Fail;
3851  Inst.addOperand(MCOperand::CreateImm(align));
3852  if (Rm != 0xF) {
3853    if (Rm != 0xD) {
3854      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3855    return MCDisassembler::Fail;
3856    } else
3857      Inst.addOperand(MCOperand::CreateReg(0));
3858  }
3859
3860  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3861    return MCDisassembler::Fail;
3862  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3863    return MCDisassembler::Fail;
3864  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3865    return MCDisassembler::Fail;
3866  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3867    return MCDisassembler::Fail;
3868  Inst.addOperand(MCOperand::CreateImm(index));
3869
3870  return S;
3871}
3872
3873static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3874                                  uint64_t Address, const void *Decoder) {
3875  DecodeStatus S = MCDisassembler::Success;
3876  unsigned Rt  = fieldFromInstruction32(Insn, 12, 4);
3877  unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3878  unsigned Rm  = fieldFromInstruction32(Insn,  0, 4);
3879  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3880  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3881
3882  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3883    S = MCDisassembler::SoftFail;
3884
3885  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
3886    return MCDisassembler::Fail;
3887  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3888    return MCDisassembler::Fail;
3889  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
3890    return MCDisassembler::Fail;
3891  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3892    return MCDisassembler::Fail;
3893  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3894    return MCDisassembler::Fail;
3895
3896  return S;
3897}
3898
3899static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
3900                                  uint64_t Address, const void *Decoder) {
3901  DecodeStatus S = MCDisassembler::Success;
3902  unsigned Rt  = fieldFromInstruction32(Insn, 12, 4);
3903  unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3904  unsigned Rm  = fieldFromInstruction32(Insn,  0, 4);
3905  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3906  Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3907
3908  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3909    S = MCDisassembler::SoftFail;
3910
3911  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
3912    return MCDisassembler::Fail;
3913  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3914    return MCDisassembler::Fail;
3915  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
3916    return MCDisassembler::Fail;
3917  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3918    return MCDisassembler::Fail;
3919  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3920    return MCDisassembler::Fail;
3921
3922  return S;
3923}
3924
3925static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
3926                             uint64_t Address, const void *Decoder) {
3927  DecodeStatus S = MCDisassembler::Success;
3928  unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3929  // The InstPrinter needs to have the low bit of the predicate in
3930  // the mask operand to be able to print it properly.
3931  unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3932
3933  if (pred == 0xF) {
3934    pred = 0xE;
3935    S = MCDisassembler::SoftFail;
3936  }
3937
3938  if ((mask & 0xF) == 0) {
3939    // Preserve the high bit of the mask, which is the low bit of
3940    // the predicate.
3941    mask &= 0x10;
3942    mask |= 0x8;
3943    S = MCDisassembler::SoftFail;
3944  }
3945
3946  Inst.addOperand(MCOperand::CreateImm(pred));
3947  Inst.addOperand(MCOperand::CreateImm(mask));
3948  return S;
3949}
3950
3951static DecodeStatus
3952DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3953                           uint64_t Address, const void *Decoder) {
3954  DecodeStatus S = MCDisassembler::Success;
3955
3956  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3957  unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3958  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3959  unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3960  unsigned W = fieldFromInstruction32(Insn, 21, 1);
3961  unsigned U = fieldFromInstruction32(Insn, 23, 1);
3962  unsigned P = fieldFromInstruction32(Insn, 24, 1);
3963  bool writeback = (W == 1) | (P == 0);
3964
3965  addr |= (U << 8) | (Rn << 9);
3966
3967  if (writeback && (Rn == Rt || Rn == Rt2))
3968    Check(S, MCDisassembler::SoftFail);
3969  if (Rt == Rt2)
3970    Check(S, MCDisassembler::SoftFail);
3971
3972  // Rt
3973  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3974    return MCDisassembler::Fail;
3975  // Rt2
3976  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3977    return MCDisassembler::Fail;
3978  // Writeback operand
3979  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3980    return MCDisassembler::Fail;
3981  // addr
3982  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3983    return MCDisassembler::Fail;
3984
3985  return S;
3986}
3987
3988static DecodeStatus
3989DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3990                           uint64_t Address, const void *Decoder) {
3991  DecodeStatus S = MCDisassembler::Success;
3992
3993  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3994  unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3995  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3996  unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3997  unsigned W = fieldFromInstruction32(Insn, 21, 1);
3998  unsigned U = fieldFromInstruction32(Insn, 23, 1);
3999  unsigned P = fieldFromInstruction32(Insn, 24, 1);
4000  bool writeback = (W == 1) | (P == 0);
4001
4002  addr |= (U << 8) | (Rn << 9);
4003
4004  if (writeback && (Rn == Rt || Rn == Rt2))
4005    Check(S, MCDisassembler::SoftFail);
4006
4007  // Writeback operand
4008  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4009    return MCDisassembler::Fail;
4010  // Rt
4011  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4012    return MCDisassembler::Fail;
4013  // Rt2
4014  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4015    return MCDisassembler::Fail;
4016  // addr
4017  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4018    return MCDisassembler::Fail;
4019
4020  return S;
4021}
4022
4023static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4024                                uint64_t Address, const void *Decoder) {
4025  unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4026  unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4027  if (sign1 != sign2) return MCDisassembler::Fail;
4028
4029  unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4030  Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4031  Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4032  Val |= sign1 << 12;
4033  Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4034
4035  return MCDisassembler::Success;
4036}
4037
4038static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4039                                              uint64_t Address,
4040                                              const void *Decoder) {
4041  DecodeStatus S = MCDisassembler::Success;
4042
4043  // Shift of "asr #32" is not allowed in Thumb2 mode.
4044  if (Val == 0x20) S = MCDisassembler::SoftFail;
4045  Inst.addOperand(MCOperand::CreateImm(Val));
4046  return S;
4047}
4048
4049