ARMDisassembler.cpp revision d04a8d4b33ff316ca4cf961e06c9e312eff8e64f
1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "llvm/MC/MCDisassembler.h" 13#include "MCTargetDesc/ARMAddressingModes.h" 14#include "MCTargetDesc/ARMBaseInfo.h" 15#include "MCTargetDesc/ARMMCExpr.h" 16#include "llvm/MC/EDInstInfo.h" 17#include "llvm/MC/MCContext.h" 18#include "llvm/MC/MCExpr.h" 19#include "llvm/MC/MCFixedLenDisassembler.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCInstrDesc.h" 22#include "llvm/MC/MCSubtargetInfo.h" 23#include "llvm/Support/Debug.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/LEB128.h" 26#include "llvm/Support/MemoryObject.h" 27#include "llvm/Support/TargetRegistry.h" 28#include "llvm/Support/raw_ostream.h" 29#include <vector> 30 31using namespace llvm; 32 33typedef MCDisassembler::DecodeStatus DecodeStatus; 34 35namespace { 36 // Handles the condition code status of instructions in IT blocks 37 class ITStatus 38 { 39 public: 40 // Returns the condition code for instruction in IT block 41 unsigned getITCC() { 42 unsigned CC = ARMCC::AL; 43 if (instrInITBlock()) 44 CC = ITStates.back(); 45 return CC; 46 } 47 48 // Advances the IT block state to the next T or E 49 void advanceITState() { 50 ITStates.pop_back(); 51 } 52 53 // Returns true if the current instruction is in an IT block 54 bool instrInITBlock() { 55 return !ITStates.empty(); 56 } 57 58 // Returns true if current instruction is the last instruction in an IT block 59 bool instrLastInITBlock() { 60 return ITStates.size() == 1; 61 } 62 63 // Called when decoding an IT instruction. Sets the IT state for the following 64 // instructions that for the IT block. Firstcond and Mask correspond to the 65 // fields in the IT instruction encoding. 66 void setITState(char Firstcond, char Mask) { 67 // (3 - the number of trailing zeros) is the number of then / else. 68 unsigned CondBit0 = Firstcond & 1; 69 unsigned NumTZ = CountTrailingZeros_32(Mask); 70 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 71 assert(NumTZ <= 3 && "Invalid IT mask!"); 72 // push condition codes onto the stack the correct order for the pops 73 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 74 bool T = ((Mask >> Pos) & 1) == CondBit0; 75 if (T) 76 ITStates.push_back(CCBits); 77 else 78 ITStates.push_back(CCBits ^ 1); 79 } 80 ITStates.push_back(CCBits); 81 } 82 83 private: 84 std::vector<unsigned char> ITStates; 85 }; 86} 87 88namespace { 89/// ARMDisassembler - ARM disassembler for all ARM platforms. 90class ARMDisassembler : public MCDisassembler { 91public: 92 /// Constructor - Initializes the disassembler. 93 /// 94 ARMDisassembler(const MCSubtargetInfo &STI) : 95 MCDisassembler(STI) { 96 } 97 98 ~ARMDisassembler() { 99 } 100 101 /// getInstruction - See MCDisassembler. 102 DecodeStatus getInstruction(MCInst &instr, 103 uint64_t &size, 104 const MemoryObject ®ion, 105 uint64_t address, 106 raw_ostream &vStream, 107 raw_ostream &cStream) const; 108 109 /// getEDInfo - See MCDisassembler. 110 const EDInstInfo *getEDInfo() const; 111private: 112}; 113 114/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 115class ThumbDisassembler : public MCDisassembler { 116public: 117 /// Constructor - Initializes the disassembler. 118 /// 119 ThumbDisassembler(const MCSubtargetInfo &STI) : 120 MCDisassembler(STI) { 121 } 122 123 ~ThumbDisassembler() { 124 } 125 126 /// getInstruction - See MCDisassembler. 127 DecodeStatus getInstruction(MCInst &instr, 128 uint64_t &size, 129 const MemoryObject ®ion, 130 uint64_t address, 131 raw_ostream &vStream, 132 raw_ostream &cStream) const; 133 134 /// getEDInfo - See MCDisassembler. 135 const EDInstInfo *getEDInfo() const; 136private: 137 mutable ITStatus ITBlock; 138 DecodeStatus AddThumbPredicate(MCInst&) const; 139 void UpdateThumbVFPPredicate(MCInst&) const; 140}; 141} 142 143static bool Check(DecodeStatus &Out, DecodeStatus In) { 144 switch (In) { 145 case MCDisassembler::Success: 146 // Out stays the same. 147 return true; 148 case MCDisassembler::SoftFail: 149 Out = In; 150 return true; 151 case MCDisassembler::Fail: 152 Out = In; 153 return false; 154 } 155 llvm_unreachable("Invalid DecodeStatus!"); 156} 157 158 159// Forward declare these because the autogenerated code will reference them. 160// Definitions are further down. 161static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 164 unsigned RegNo, uint64_t Address, 165 const void *Decoder); 166static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, const void *Decoder); 178static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 179 unsigned RegNo, 180 uint64_t Address, 181 const void *Decoder); 182static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 187 unsigned RegNo, uint64_t Address, 188 const void *Decoder); 189 190static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 203static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 208 unsigned Insn, 209 uint64_t Address, 210 const void *Decoder); 211static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 214 uint64_t Address, const void *Decoder); 215static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 220static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 221 unsigned Insn, 222 uint64_t Adddress, 223 const void *Decoder); 224static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 243 uint64_t Address, const void *Decoder); 244static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 259 uint64_t Address, const void *Decoder); 260static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 319 320static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 321 uint64_t Address, const void *Decoder); 322static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 345 uint64_t Address, const void *Decoder); 346static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 351 uint64_t Address, const void *Decoder); 352static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 353 uint64_t Address, const void *Decoder); 354static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 355 uint64_t Address, const void *Decoder); 356static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void *Decoder); 358static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 367 uint64_t Address, const void *Decoder); 368static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 371 uint64_t Address, const void *Decoder); 372static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 373 uint64_t Address, const void *Decoder); 374static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 375 uint64_t Address, const void *Decoder); 376static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 383static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 386 uint64_t Address, const void *Decoder); 387#include "ARMGenDisassemblerTables.inc" 388#include "ARMGenEDInfo.inc" 389 390static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 391 return new ARMDisassembler(STI); 392} 393 394static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 395 return new ThumbDisassembler(STI); 396} 397 398const EDInstInfo *ARMDisassembler::getEDInfo() const { 399 return instInfoARM; 400} 401 402const EDInstInfo *ThumbDisassembler::getEDInfo() const { 403 return instInfoARM; 404} 405 406DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 407 const MemoryObject &Region, 408 uint64_t Address, 409 raw_ostream &os, 410 raw_ostream &cs) const { 411 CommentStream = &cs; 412 413 uint8_t bytes[4]; 414 415 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 416 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 417 418 // We want to read exactly 4 bytes of data. 419 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 420 Size = 0; 421 return MCDisassembler::Fail; 422 } 423 424 // Encoded as a small-endian 32-bit word in the stream. 425 uint32_t insn = (bytes[3] << 24) | 426 (bytes[2] << 16) | 427 (bytes[1] << 8) | 428 (bytes[0] << 0); 429 430 // Calling the auto-generated decoder function. 431 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 432 Address, this, STI); 433 if (result != MCDisassembler::Fail) { 434 Size = 4; 435 return result; 436 } 437 438 // VFP and NEON instructions, similarly, are shared between ARM 439 // and Thumb modes. 440 MI.clear(); 441 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 442 if (result != MCDisassembler::Fail) { 443 Size = 4; 444 return result; 445 } 446 447 MI.clear(); 448 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 449 this, STI); 450 if (result != MCDisassembler::Fail) { 451 Size = 4; 452 // Add a fake predicate operand, because we share these instruction 453 // definitions with Thumb2 where these instructions are predicable. 454 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 455 return MCDisassembler::Fail; 456 return result; 457 } 458 459 MI.clear(); 460 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 461 this, STI); 462 if (result != MCDisassembler::Fail) { 463 Size = 4; 464 // Add a fake predicate operand, because we share these instruction 465 // definitions with Thumb2 where these instructions are predicable. 466 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 467 return MCDisassembler::Fail; 468 return result; 469 } 470 471 MI.clear(); 472 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 473 this, STI); 474 if (result != MCDisassembler::Fail) { 475 Size = 4; 476 // Add a fake predicate operand, because we share these instruction 477 // definitions with Thumb2 where these instructions are predicable. 478 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 479 return MCDisassembler::Fail; 480 return result; 481 } 482 483 MI.clear(); 484 485 Size = 0; 486 return MCDisassembler::Fail; 487} 488 489namespace llvm { 490extern const MCInstrDesc ARMInsts[]; 491} 492 493/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 494/// immediate Value in the MCInst. The immediate Value has had any PC 495/// adjustment made by the caller. If the instruction is a branch instruction 496/// then isBranch is true, else false. If the getOpInfo() function was set as 497/// part of the setupForSymbolicDisassembly() call then that function is called 498/// to get any symbolic information at the Address for this instruction. If 499/// that returns non-zero then the symbolic information it returns is used to 500/// create an MCExpr and that is added as an operand to the MCInst. If 501/// getOpInfo() returns zero and isBranch is true then a symbol look up for 502/// Value is done and if a symbol is found an MCExpr is created with that, else 503/// an MCExpr with Value is created. This function returns true if it adds an 504/// operand to the MCInst and false otherwise. 505static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 506 bool isBranch, uint64_t InstSize, 507 MCInst &MI, const void *Decoder) { 508 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 509 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 510 struct LLVMOpInfo1 SymbolicOp; 511 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 512 SymbolicOp.Value = Value; 513 void *DisInfo = Dis->getDisInfoBlock(); 514 515 if (!getOpInfo || 516 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 517 // Clear SymbolicOp.Value from above and also all other fields. 518 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 519 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 520 if (!SymbolLookUp) 521 return false; 522 uint64_t ReferenceType; 523 if (isBranch) 524 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 525 else 526 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 527 const char *ReferenceName; 528 uint64_t SymbolValue = 0x00000000ffffffffULL & Value; 529 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType, 530 Address, &ReferenceName); 531 if (Name) { 532 SymbolicOp.AddSymbol.Name = Name; 533 SymbolicOp.AddSymbol.Present = true; 534 } 535 // For branches always create an MCExpr so it gets printed as hex address. 536 else if (isBranch) { 537 SymbolicOp.Value = Value; 538 } 539 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 540 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 541 if (!Name && !isBranch) 542 return false; 543 } 544 545 MCContext *Ctx = Dis->getMCContext(); 546 const MCExpr *Add = NULL; 547 if (SymbolicOp.AddSymbol.Present) { 548 if (SymbolicOp.AddSymbol.Name) { 549 StringRef Name(SymbolicOp.AddSymbol.Name); 550 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 551 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 552 } else { 553 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 554 } 555 } 556 557 const MCExpr *Sub = NULL; 558 if (SymbolicOp.SubtractSymbol.Present) { 559 if (SymbolicOp.SubtractSymbol.Name) { 560 StringRef Name(SymbolicOp.SubtractSymbol.Name); 561 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 562 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 563 } else { 564 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 565 } 566 } 567 568 const MCExpr *Off = NULL; 569 if (SymbolicOp.Value != 0) 570 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 571 572 const MCExpr *Expr; 573 if (Sub) { 574 const MCExpr *LHS; 575 if (Add) 576 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 577 else 578 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 579 if (Off != 0) 580 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 581 else 582 Expr = LHS; 583 } else if (Add) { 584 if (Off != 0) 585 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 586 else 587 Expr = Add; 588 } else { 589 if (Off != 0) 590 Expr = Off; 591 else 592 Expr = MCConstantExpr::Create(0, *Ctx); 593 } 594 595 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 596 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 597 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 598 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 599 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 600 MI.addOperand(MCOperand::CreateExpr(Expr)); 601 else 602 llvm_unreachable("bad SymbolicOp.VariantKind"); 603 604 return true; 605} 606 607/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 608/// referenced by a load instruction with the base register that is the Pc. 609/// These can often be values in a literal pool near the Address of the 610/// instruction. The Address of the instruction and its immediate Value are 611/// used as a possible literal pool entry. The SymbolLookUp call back will 612/// return the name of a symbol referenced by the literal pool's entry if 613/// the referenced address is that of a symbol. Or it will return a pointer to 614/// a literal 'C' string if the referenced address of the literal pool's entry 615/// is an address into a section with 'C' string literals. 616static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 617 const void *Decoder) { 618 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 619 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 620 if (SymbolLookUp) { 621 void *DisInfo = Dis->getDisInfoBlock(); 622 uint64_t ReferenceType; 623 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 624 const char *ReferenceName; 625 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 626 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 627 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 628 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 629 } 630} 631 632// Thumb1 instructions don't have explicit S bits. Rather, they 633// implicitly set CPSR. Since it's not represented in the encoding, the 634// auto-generated decoder won't inject the CPSR operand. We need to fix 635// that as a post-pass. 636static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 637 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 638 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 639 MCInst::iterator I = MI.begin(); 640 for (unsigned i = 0; i < NumOps; ++i, ++I) { 641 if (I == MI.end()) break; 642 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 643 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 644 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 645 return; 646 } 647 } 648 649 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 650} 651 652// Most Thumb instructions don't have explicit predicates in the 653// encoding, but rather get their predicates from IT context. We need 654// to fix up the predicate operands using this context information as a 655// post-pass. 656MCDisassembler::DecodeStatus 657ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 658 MCDisassembler::DecodeStatus S = Success; 659 660 // A few instructions actually have predicates encoded in them. Don't 661 // try to overwrite it if we're seeing one of those. 662 switch (MI.getOpcode()) { 663 case ARM::tBcc: 664 case ARM::t2Bcc: 665 case ARM::tCBZ: 666 case ARM::tCBNZ: 667 case ARM::tCPS: 668 case ARM::t2CPS3p: 669 case ARM::t2CPS2p: 670 case ARM::t2CPS1p: 671 case ARM::tMOVSr: 672 case ARM::tSETEND: 673 // Some instructions (mostly conditional branches) are not 674 // allowed in IT blocks. 675 if (ITBlock.instrInITBlock()) 676 S = SoftFail; 677 else 678 return Success; 679 break; 680 case ARM::tB: 681 case ARM::t2B: 682 case ARM::t2TBB: 683 case ARM::t2TBH: 684 // Some instructions (mostly unconditional branches) can 685 // only appears at the end of, or outside of, an IT. 686 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 687 S = SoftFail; 688 break; 689 default: 690 break; 691 } 692 693 // If we're in an IT block, base the predicate on that. Otherwise, 694 // assume a predicate of AL. 695 unsigned CC; 696 CC = ITBlock.getITCC(); 697 if (CC == 0xF) 698 CC = ARMCC::AL; 699 if (ITBlock.instrInITBlock()) 700 ITBlock.advanceITState(); 701 702 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 703 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 704 MCInst::iterator I = MI.begin(); 705 for (unsigned i = 0; i < NumOps; ++i, ++I) { 706 if (I == MI.end()) break; 707 if (OpInfo[i].isPredicate()) { 708 I = MI.insert(I, MCOperand::CreateImm(CC)); 709 ++I; 710 if (CC == ARMCC::AL) 711 MI.insert(I, MCOperand::CreateReg(0)); 712 else 713 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 714 return S; 715 } 716 } 717 718 I = MI.insert(I, MCOperand::CreateImm(CC)); 719 ++I; 720 if (CC == ARMCC::AL) 721 MI.insert(I, MCOperand::CreateReg(0)); 722 else 723 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 724 725 return S; 726} 727 728// Thumb VFP instructions are a special case. Because we share their 729// encodings between ARM and Thumb modes, and they are predicable in ARM 730// mode, the auto-generated decoder will give them an (incorrect) 731// predicate operand. We need to rewrite these operands based on the IT 732// context as a post-pass. 733void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 734 unsigned CC; 735 CC = ITBlock.getITCC(); 736 if (ITBlock.instrInITBlock()) 737 ITBlock.advanceITState(); 738 739 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 740 MCInst::iterator I = MI.begin(); 741 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 742 for (unsigned i = 0; i < NumOps; ++i, ++I) { 743 if (OpInfo[i].isPredicate() ) { 744 I->setImm(CC); 745 ++I; 746 if (CC == ARMCC::AL) 747 I->setReg(0); 748 else 749 I->setReg(ARM::CPSR); 750 return; 751 } 752 } 753} 754 755DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 756 const MemoryObject &Region, 757 uint64_t Address, 758 raw_ostream &os, 759 raw_ostream &cs) const { 760 CommentStream = &cs; 761 762 uint8_t bytes[4]; 763 764 assert((STI.getFeatureBits() & ARM::ModeThumb) && 765 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 766 767 // We want to read exactly 2 bytes of data. 768 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 769 Size = 0; 770 return MCDisassembler::Fail; 771 } 772 773 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 774 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 775 Address, this, STI); 776 if (result != MCDisassembler::Fail) { 777 Size = 2; 778 Check(result, AddThumbPredicate(MI)); 779 return result; 780 } 781 782 MI.clear(); 783 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 784 Address, this, STI); 785 if (result) { 786 Size = 2; 787 bool InITBlock = ITBlock.instrInITBlock(); 788 Check(result, AddThumbPredicate(MI)); 789 AddThumb1SBit(MI, InITBlock); 790 return result; 791 } 792 793 MI.clear(); 794 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 795 Address, this, STI); 796 if (result != MCDisassembler::Fail) { 797 Size = 2; 798 799 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 800 // the Thumb predicate. 801 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 802 result = MCDisassembler::SoftFail; 803 804 Check(result, AddThumbPredicate(MI)); 805 806 // If we find an IT instruction, we need to parse its condition 807 // code and mask operands so that we can apply them correctly 808 // to the subsequent instructions. 809 if (MI.getOpcode() == ARM::t2IT) { 810 811 unsigned Firstcond = MI.getOperand(0).getImm(); 812 unsigned Mask = MI.getOperand(1).getImm(); 813 ITBlock.setITState(Firstcond, Mask); 814 } 815 816 return result; 817 } 818 819 // We want to read exactly 4 bytes of data. 820 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 821 Size = 0; 822 return MCDisassembler::Fail; 823 } 824 825 uint32_t insn32 = (bytes[3] << 8) | 826 (bytes[2] << 0) | 827 (bytes[1] << 24) | 828 (bytes[0] << 16); 829 MI.clear(); 830 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 831 this, STI); 832 if (result != MCDisassembler::Fail) { 833 Size = 4; 834 bool InITBlock = ITBlock.instrInITBlock(); 835 Check(result, AddThumbPredicate(MI)); 836 AddThumb1SBit(MI, InITBlock); 837 return result; 838 } 839 840 MI.clear(); 841 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 842 this, STI); 843 if (result != MCDisassembler::Fail) { 844 Size = 4; 845 Check(result, AddThumbPredicate(MI)); 846 return result; 847 } 848 849 MI.clear(); 850 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 851 if (result != MCDisassembler::Fail) { 852 Size = 4; 853 UpdateThumbVFPPredicate(MI); 854 return result; 855 } 856 857 MI.clear(); 858 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 859 this, STI); 860 if (result != MCDisassembler::Fail) { 861 Size = 4; 862 Check(result, AddThumbPredicate(MI)); 863 return result; 864 } 865 866 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 867 MI.clear(); 868 uint32_t NEONLdStInsn = insn32; 869 NEONLdStInsn &= 0xF0FFFFFF; 870 NEONLdStInsn |= 0x04000000; 871 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 872 Address, this, STI); 873 if (result != MCDisassembler::Fail) { 874 Size = 4; 875 Check(result, AddThumbPredicate(MI)); 876 return result; 877 } 878 } 879 880 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 881 MI.clear(); 882 uint32_t NEONDataInsn = insn32; 883 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 884 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 885 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 886 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 887 Address, this, STI); 888 if (result != MCDisassembler::Fail) { 889 Size = 4; 890 Check(result, AddThumbPredicate(MI)); 891 return result; 892 } 893 } 894 895 Size = 0; 896 return MCDisassembler::Fail; 897} 898 899 900extern "C" void LLVMInitializeARMDisassembler() { 901 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 902 createARMDisassembler); 903 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 904 createThumbDisassembler); 905} 906 907static const uint16_t GPRDecoderTable[] = { 908 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 909 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 910 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 911 ARM::R12, ARM::SP, ARM::LR, ARM::PC 912}; 913 914static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 915 uint64_t Address, const void *Decoder) { 916 if (RegNo > 15) 917 return MCDisassembler::Fail; 918 919 unsigned Register = GPRDecoderTable[RegNo]; 920 Inst.addOperand(MCOperand::CreateReg(Register)); 921 return MCDisassembler::Success; 922} 923 924static DecodeStatus 925DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 926 uint64_t Address, const void *Decoder) { 927 DecodeStatus S = MCDisassembler::Success; 928 929 if (RegNo == 15) 930 S = MCDisassembler::SoftFail; 931 932 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 933 934 return S; 935} 936 937static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 938 uint64_t Address, const void *Decoder) { 939 if (RegNo > 7) 940 return MCDisassembler::Fail; 941 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 942} 943 944static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 945 uint64_t Address, const void *Decoder) { 946 unsigned Register = 0; 947 switch (RegNo) { 948 case 0: 949 Register = ARM::R0; 950 break; 951 case 1: 952 Register = ARM::R1; 953 break; 954 case 2: 955 Register = ARM::R2; 956 break; 957 case 3: 958 Register = ARM::R3; 959 break; 960 case 9: 961 Register = ARM::R9; 962 break; 963 case 12: 964 Register = ARM::R12; 965 break; 966 default: 967 return MCDisassembler::Fail; 968 } 969 970 Inst.addOperand(MCOperand::CreateReg(Register)); 971 return MCDisassembler::Success; 972} 973 974static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 975 uint64_t Address, const void *Decoder) { 976 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 977 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 978} 979 980static const uint16_t SPRDecoderTable[] = { 981 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 982 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 983 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 984 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 985 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 986 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 987 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 988 ARM::S28, ARM::S29, ARM::S30, ARM::S31 989}; 990 991static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 992 uint64_t Address, const void *Decoder) { 993 if (RegNo > 31) 994 return MCDisassembler::Fail; 995 996 unsigned Register = SPRDecoderTable[RegNo]; 997 Inst.addOperand(MCOperand::CreateReg(Register)); 998 return MCDisassembler::Success; 999} 1000 1001static const uint16_t DPRDecoderTable[] = { 1002 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1004 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1007 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1008 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1009 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1010}; 1011 1012static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1013 uint64_t Address, const void *Decoder) { 1014 if (RegNo > 31) 1015 return MCDisassembler::Fail; 1016 1017 unsigned Register = DPRDecoderTable[RegNo]; 1018 Inst.addOperand(MCOperand::CreateReg(Register)); 1019 return MCDisassembler::Success; 1020} 1021 1022static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1023 uint64_t Address, const void *Decoder) { 1024 if (RegNo > 7) 1025 return MCDisassembler::Fail; 1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1027} 1028 1029static DecodeStatus 1030DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1031 uint64_t Address, const void *Decoder) { 1032 if (RegNo > 15) 1033 return MCDisassembler::Fail; 1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1035} 1036 1037static const uint16_t QPRDecoderTable[] = { 1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1042}; 1043 1044 1045static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1046 uint64_t Address, const void *Decoder) { 1047 if (RegNo > 31) 1048 return MCDisassembler::Fail; 1049 RegNo >>= 1; 1050 1051 unsigned Register = QPRDecoderTable[RegNo]; 1052 Inst.addOperand(MCOperand::CreateReg(Register)); 1053 return MCDisassembler::Success; 1054} 1055 1056static const uint16_t DPairDecoderTable[] = { 1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1062 ARM::Q15 1063}; 1064 1065static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1066 uint64_t Address, const void *Decoder) { 1067 if (RegNo > 30) 1068 return MCDisassembler::Fail; 1069 1070 unsigned Register = DPairDecoderTable[RegNo]; 1071 Inst.addOperand(MCOperand::CreateReg(Register)); 1072 return MCDisassembler::Success; 1073} 1074 1075static const uint16_t DPairSpacedDecoderTable[] = { 1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1083 ARM::D28_D30, ARM::D29_D31 1084}; 1085 1086static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1087 unsigned RegNo, 1088 uint64_t Address, 1089 const void *Decoder) { 1090 if (RegNo > 29) 1091 return MCDisassembler::Fail; 1092 1093 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1094 Inst.addOperand(MCOperand::CreateReg(Register)); 1095 return MCDisassembler::Success; 1096} 1097 1098static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1099 uint64_t Address, const void *Decoder) { 1100 if (Val == 0xF) return MCDisassembler::Fail; 1101 // AL predicate is not allowed on Thumb1 branches. 1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1103 return MCDisassembler::Fail; 1104 Inst.addOperand(MCOperand::CreateImm(Val)); 1105 if (Val == ARMCC::AL) { 1106 Inst.addOperand(MCOperand::CreateReg(0)); 1107 } else 1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1109 return MCDisassembler::Success; 1110} 1111 1112static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1113 uint64_t Address, const void *Decoder) { 1114 if (Val) 1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1116 else 1117 Inst.addOperand(MCOperand::CreateReg(0)); 1118 return MCDisassembler::Success; 1119} 1120 1121static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1122 uint64_t Address, const void *Decoder) { 1123 uint32_t imm = Val & 0xFF; 1124 uint32_t rot = (Val & 0xF00) >> 7; 1125 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1126 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1127 return MCDisassembler::Success; 1128} 1129 1130static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1131 uint64_t Address, const void *Decoder) { 1132 DecodeStatus S = MCDisassembler::Success; 1133 1134 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1135 unsigned type = fieldFromInstruction(Val, 5, 2); 1136 unsigned imm = fieldFromInstruction(Val, 7, 5); 1137 1138 // Register-immediate 1139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1140 return MCDisassembler::Fail; 1141 1142 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1143 switch (type) { 1144 case 0: 1145 Shift = ARM_AM::lsl; 1146 break; 1147 case 1: 1148 Shift = ARM_AM::lsr; 1149 break; 1150 case 2: 1151 Shift = ARM_AM::asr; 1152 break; 1153 case 3: 1154 Shift = ARM_AM::ror; 1155 break; 1156 } 1157 1158 if (Shift == ARM_AM::ror && imm == 0) 1159 Shift = ARM_AM::rrx; 1160 1161 unsigned Op = Shift | (imm << 3); 1162 Inst.addOperand(MCOperand::CreateImm(Op)); 1163 1164 return S; 1165} 1166 1167static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1168 uint64_t Address, const void *Decoder) { 1169 DecodeStatus S = MCDisassembler::Success; 1170 1171 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1172 unsigned type = fieldFromInstruction(Val, 5, 2); 1173 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1174 1175 // Register-register 1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1177 return MCDisassembler::Fail; 1178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1179 return MCDisassembler::Fail; 1180 1181 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1182 switch (type) { 1183 case 0: 1184 Shift = ARM_AM::lsl; 1185 break; 1186 case 1: 1187 Shift = ARM_AM::lsr; 1188 break; 1189 case 2: 1190 Shift = ARM_AM::asr; 1191 break; 1192 case 3: 1193 Shift = ARM_AM::ror; 1194 break; 1195 } 1196 1197 Inst.addOperand(MCOperand::CreateImm(Shift)); 1198 1199 return S; 1200} 1201 1202static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1203 uint64_t Address, const void *Decoder) { 1204 DecodeStatus S = MCDisassembler::Success; 1205 1206 bool writebackLoad = false; 1207 unsigned writebackReg = 0; 1208 switch (Inst.getOpcode()) { 1209 default: 1210 break; 1211 case ARM::LDMIA_UPD: 1212 case ARM::LDMDB_UPD: 1213 case ARM::LDMIB_UPD: 1214 case ARM::LDMDA_UPD: 1215 case ARM::t2LDMIA_UPD: 1216 case ARM::t2LDMDB_UPD: 1217 writebackLoad = true; 1218 writebackReg = Inst.getOperand(0).getReg(); 1219 break; 1220 } 1221 1222 // Empty register lists are not allowed. 1223 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1224 for (unsigned i = 0; i < 16; ++i) { 1225 if (Val & (1 << i)) { 1226 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1227 return MCDisassembler::Fail; 1228 // Writeback not allowed if Rn is in the target list. 1229 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1230 Check(S, MCDisassembler::SoftFail); 1231 } 1232 } 1233 1234 return S; 1235} 1236 1237static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1238 uint64_t Address, const void *Decoder) { 1239 DecodeStatus S = MCDisassembler::Success; 1240 1241 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1242 unsigned regs = fieldFromInstruction(Val, 0, 8); 1243 1244 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1245 return MCDisassembler::Fail; 1246 for (unsigned i = 0; i < (regs - 1); ++i) { 1247 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1248 return MCDisassembler::Fail; 1249 } 1250 1251 return S; 1252} 1253 1254static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1255 uint64_t Address, const void *Decoder) { 1256 DecodeStatus S = MCDisassembler::Success; 1257 1258 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1259 unsigned regs = fieldFromInstruction(Val, 0, 8); 1260 1261 regs = regs >> 1; 1262 1263 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1264 return MCDisassembler::Fail; 1265 for (unsigned i = 0; i < (regs - 1); ++i) { 1266 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1267 return MCDisassembler::Fail; 1268 } 1269 1270 return S; 1271} 1272 1273static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1274 uint64_t Address, const void *Decoder) { 1275 // This operand encodes a mask of contiguous zeros between a specified MSB 1276 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1277 // the mask of all bits LSB-and-lower, and then xor them to create 1278 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1279 // create the final mask. 1280 unsigned msb = fieldFromInstruction(Val, 5, 5); 1281 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1282 1283 DecodeStatus S = MCDisassembler::Success; 1284 if (lsb > msb) { 1285 Check(S, MCDisassembler::SoftFail); 1286 // The check above will cause the warning for the "potentially undefined 1287 // instruction encoding" but we can't build a bad MCOperand value here 1288 // with a lsb > msb or else printing the MCInst will cause a crash. 1289 lsb = msb; 1290 } 1291 1292 uint32_t msb_mask = 0xFFFFFFFF; 1293 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1294 uint32_t lsb_mask = (1U << lsb) - 1; 1295 1296 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1297 return S; 1298} 1299 1300static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1301 uint64_t Address, const void *Decoder) { 1302 DecodeStatus S = MCDisassembler::Success; 1303 1304 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1305 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1306 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1307 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1308 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1309 unsigned U = fieldFromInstruction(Insn, 23, 1); 1310 1311 switch (Inst.getOpcode()) { 1312 case ARM::LDC_OFFSET: 1313 case ARM::LDC_PRE: 1314 case ARM::LDC_POST: 1315 case ARM::LDC_OPTION: 1316 case ARM::LDCL_OFFSET: 1317 case ARM::LDCL_PRE: 1318 case ARM::LDCL_POST: 1319 case ARM::LDCL_OPTION: 1320 case ARM::STC_OFFSET: 1321 case ARM::STC_PRE: 1322 case ARM::STC_POST: 1323 case ARM::STC_OPTION: 1324 case ARM::STCL_OFFSET: 1325 case ARM::STCL_PRE: 1326 case ARM::STCL_POST: 1327 case ARM::STCL_OPTION: 1328 case ARM::t2LDC_OFFSET: 1329 case ARM::t2LDC_PRE: 1330 case ARM::t2LDC_POST: 1331 case ARM::t2LDC_OPTION: 1332 case ARM::t2LDCL_OFFSET: 1333 case ARM::t2LDCL_PRE: 1334 case ARM::t2LDCL_POST: 1335 case ARM::t2LDCL_OPTION: 1336 case ARM::t2STC_OFFSET: 1337 case ARM::t2STC_PRE: 1338 case ARM::t2STC_POST: 1339 case ARM::t2STC_OPTION: 1340 case ARM::t2STCL_OFFSET: 1341 case ARM::t2STCL_PRE: 1342 case ARM::t2STCL_POST: 1343 case ARM::t2STCL_OPTION: 1344 if (coproc == 0xA || coproc == 0xB) 1345 return MCDisassembler::Fail; 1346 break; 1347 default: 1348 break; 1349 } 1350 1351 Inst.addOperand(MCOperand::CreateImm(coproc)); 1352 Inst.addOperand(MCOperand::CreateImm(CRd)); 1353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1354 return MCDisassembler::Fail; 1355 1356 switch (Inst.getOpcode()) { 1357 case ARM::t2LDC2_OFFSET: 1358 case ARM::t2LDC2L_OFFSET: 1359 case ARM::t2LDC2_PRE: 1360 case ARM::t2LDC2L_PRE: 1361 case ARM::t2STC2_OFFSET: 1362 case ARM::t2STC2L_OFFSET: 1363 case ARM::t2STC2_PRE: 1364 case ARM::t2STC2L_PRE: 1365 case ARM::LDC2_OFFSET: 1366 case ARM::LDC2L_OFFSET: 1367 case ARM::LDC2_PRE: 1368 case ARM::LDC2L_PRE: 1369 case ARM::STC2_OFFSET: 1370 case ARM::STC2L_OFFSET: 1371 case ARM::STC2_PRE: 1372 case ARM::STC2L_PRE: 1373 case ARM::t2LDC_OFFSET: 1374 case ARM::t2LDCL_OFFSET: 1375 case ARM::t2LDC_PRE: 1376 case ARM::t2LDCL_PRE: 1377 case ARM::t2STC_OFFSET: 1378 case ARM::t2STCL_OFFSET: 1379 case ARM::t2STC_PRE: 1380 case ARM::t2STCL_PRE: 1381 case ARM::LDC_OFFSET: 1382 case ARM::LDCL_OFFSET: 1383 case ARM::LDC_PRE: 1384 case ARM::LDCL_PRE: 1385 case ARM::STC_OFFSET: 1386 case ARM::STCL_OFFSET: 1387 case ARM::STC_PRE: 1388 case ARM::STCL_PRE: 1389 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1390 Inst.addOperand(MCOperand::CreateImm(imm)); 1391 break; 1392 case ARM::t2LDC2_POST: 1393 case ARM::t2LDC2L_POST: 1394 case ARM::t2STC2_POST: 1395 case ARM::t2STC2L_POST: 1396 case ARM::LDC2_POST: 1397 case ARM::LDC2L_POST: 1398 case ARM::STC2_POST: 1399 case ARM::STC2L_POST: 1400 case ARM::t2LDC_POST: 1401 case ARM::t2LDCL_POST: 1402 case ARM::t2STC_POST: 1403 case ARM::t2STCL_POST: 1404 case ARM::LDC_POST: 1405 case ARM::LDCL_POST: 1406 case ARM::STC_POST: 1407 case ARM::STCL_POST: 1408 imm |= U << 8; 1409 // fall through. 1410 default: 1411 // The 'option' variant doesn't encode 'U' in the immediate since 1412 // the immediate is unsigned [0,255]. 1413 Inst.addOperand(MCOperand::CreateImm(imm)); 1414 break; 1415 } 1416 1417 switch (Inst.getOpcode()) { 1418 case ARM::LDC_OFFSET: 1419 case ARM::LDC_PRE: 1420 case ARM::LDC_POST: 1421 case ARM::LDC_OPTION: 1422 case ARM::LDCL_OFFSET: 1423 case ARM::LDCL_PRE: 1424 case ARM::LDCL_POST: 1425 case ARM::LDCL_OPTION: 1426 case ARM::STC_OFFSET: 1427 case ARM::STC_PRE: 1428 case ARM::STC_POST: 1429 case ARM::STC_OPTION: 1430 case ARM::STCL_OFFSET: 1431 case ARM::STCL_PRE: 1432 case ARM::STCL_POST: 1433 case ARM::STCL_OPTION: 1434 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1435 return MCDisassembler::Fail; 1436 break; 1437 default: 1438 break; 1439 } 1440 1441 return S; 1442} 1443 1444static DecodeStatus 1445DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1446 uint64_t Address, const void *Decoder) { 1447 DecodeStatus S = MCDisassembler::Success; 1448 1449 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1450 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1451 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1452 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1453 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1454 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1455 unsigned P = fieldFromInstruction(Insn, 24, 1); 1456 unsigned W = fieldFromInstruction(Insn, 21, 1); 1457 1458 // On stores, the writeback operand precedes Rt. 1459 switch (Inst.getOpcode()) { 1460 case ARM::STR_POST_IMM: 1461 case ARM::STR_POST_REG: 1462 case ARM::STRB_POST_IMM: 1463 case ARM::STRB_POST_REG: 1464 case ARM::STRT_POST_REG: 1465 case ARM::STRT_POST_IMM: 1466 case ARM::STRBT_POST_REG: 1467 case ARM::STRBT_POST_IMM: 1468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1469 return MCDisassembler::Fail; 1470 break; 1471 default: 1472 break; 1473 } 1474 1475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1476 return MCDisassembler::Fail; 1477 1478 // On loads, the writeback operand comes after Rt. 1479 switch (Inst.getOpcode()) { 1480 case ARM::LDR_POST_IMM: 1481 case ARM::LDR_POST_REG: 1482 case ARM::LDRB_POST_IMM: 1483 case ARM::LDRB_POST_REG: 1484 case ARM::LDRBT_POST_REG: 1485 case ARM::LDRBT_POST_IMM: 1486 case ARM::LDRT_POST_REG: 1487 case ARM::LDRT_POST_IMM: 1488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1489 return MCDisassembler::Fail; 1490 break; 1491 default: 1492 break; 1493 } 1494 1495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1496 return MCDisassembler::Fail; 1497 1498 ARM_AM::AddrOpc Op = ARM_AM::add; 1499 if (!fieldFromInstruction(Insn, 23, 1)) 1500 Op = ARM_AM::sub; 1501 1502 bool writeback = (P == 0) || (W == 1); 1503 unsigned idx_mode = 0; 1504 if (P && writeback) 1505 idx_mode = ARMII::IndexModePre; 1506 else if (!P && writeback) 1507 idx_mode = ARMII::IndexModePost; 1508 1509 if (writeback && (Rn == 15 || Rn == Rt)) 1510 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1511 1512 if (reg) { 1513 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1514 return MCDisassembler::Fail; 1515 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1516 switch( fieldFromInstruction(Insn, 5, 2)) { 1517 case 0: 1518 Opc = ARM_AM::lsl; 1519 break; 1520 case 1: 1521 Opc = ARM_AM::lsr; 1522 break; 1523 case 2: 1524 Opc = ARM_AM::asr; 1525 break; 1526 case 3: 1527 Opc = ARM_AM::ror; 1528 break; 1529 default: 1530 return MCDisassembler::Fail; 1531 } 1532 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1533 if (Opc == ARM_AM::ror && amt == 0) 1534 Opc = ARM_AM::rrx; 1535 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1536 1537 Inst.addOperand(MCOperand::CreateImm(imm)); 1538 } else { 1539 Inst.addOperand(MCOperand::CreateReg(0)); 1540 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1541 Inst.addOperand(MCOperand::CreateImm(tmp)); 1542 } 1543 1544 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1545 return MCDisassembler::Fail; 1546 1547 return S; 1548} 1549 1550static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1551 uint64_t Address, const void *Decoder) { 1552 DecodeStatus S = MCDisassembler::Success; 1553 1554 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1555 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1556 unsigned type = fieldFromInstruction(Val, 5, 2); 1557 unsigned imm = fieldFromInstruction(Val, 7, 5); 1558 unsigned U = fieldFromInstruction(Val, 12, 1); 1559 1560 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1561 switch (type) { 1562 case 0: 1563 ShOp = ARM_AM::lsl; 1564 break; 1565 case 1: 1566 ShOp = ARM_AM::lsr; 1567 break; 1568 case 2: 1569 ShOp = ARM_AM::asr; 1570 break; 1571 case 3: 1572 ShOp = ARM_AM::ror; 1573 break; 1574 } 1575 1576 if (ShOp == ARM_AM::ror && imm == 0) 1577 ShOp = ARM_AM::rrx; 1578 1579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1580 return MCDisassembler::Fail; 1581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1582 return MCDisassembler::Fail; 1583 unsigned shift; 1584 if (U) 1585 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1586 else 1587 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1588 Inst.addOperand(MCOperand::CreateImm(shift)); 1589 1590 return S; 1591} 1592 1593static DecodeStatus 1594DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1595 uint64_t Address, const void *Decoder) { 1596 DecodeStatus S = MCDisassembler::Success; 1597 1598 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1599 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1600 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1601 unsigned type = fieldFromInstruction(Insn, 22, 1); 1602 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1603 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1604 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1605 unsigned W = fieldFromInstruction(Insn, 21, 1); 1606 unsigned P = fieldFromInstruction(Insn, 24, 1); 1607 unsigned Rt2 = Rt + 1; 1608 1609 bool writeback = (W == 1) | (P == 0); 1610 1611 // For {LD,ST}RD, Rt must be even, else undefined. 1612 switch (Inst.getOpcode()) { 1613 case ARM::STRD: 1614 case ARM::STRD_PRE: 1615 case ARM::STRD_POST: 1616 case ARM::LDRD: 1617 case ARM::LDRD_PRE: 1618 case ARM::LDRD_POST: 1619 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1620 break; 1621 default: 1622 break; 1623 } 1624 switch (Inst.getOpcode()) { 1625 case ARM::STRD: 1626 case ARM::STRD_PRE: 1627 case ARM::STRD_POST: 1628 if (P == 0 && W == 1) 1629 S = MCDisassembler::SoftFail; 1630 1631 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1632 S = MCDisassembler::SoftFail; 1633 if (type && Rm == 15) 1634 S = MCDisassembler::SoftFail; 1635 if (Rt2 == 15) 1636 S = MCDisassembler::SoftFail; 1637 if (!type && fieldFromInstruction(Insn, 8, 4)) 1638 S = MCDisassembler::SoftFail; 1639 break; 1640 case ARM::STRH: 1641 case ARM::STRH_PRE: 1642 case ARM::STRH_POST: 1643 if (Rt == 15) 1644 S = MCDisassembler::SoftFail; 1645 if (writeback && (Rn == 15 || Rn == Rt)) 1646 S = MCDisassembler::SoftFail; 1647 if (!type && Rm == 15) 1648 S = MCDisassembler::SoftFail; 1649 break; 1650 case ARM::LDRD: 1651 case ARM::LDRD_PRE: 1652 case ARM::LDRD_POST: 1653 if (type && Rn == 15){ 1654 if (Rt2 == 15) 1655 S = MCDisassembler::SoftFail; 1656 break; 1657 } 1658 if (P == 0 && W == 1) 1659 S = MCDisassembler::SoftFail; 1660 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1661 S = MCDisassembler::SoftFail; 1662 if (!type && writeback && Rn == 15) 1663 S = MCDisassembler::SoftFail; 1664 if (writeback && (Rn == Rt || Rn == Rt2)) 1665 S = MCDisassembler::SoftFail; 1666 break; 1667 case ARM::LDRH: 1668 case ARM::LDRH_PRE: 1669 case ARM::LDRH_POST: 1670 if (type && Rn == 15){ 1671 if (Rt == 15) 1672 S = MCDisassembler::SoftFail; 1673 break; 1674 } 1675 if (Rt == 15) 1676 S = MCDisassembler::SoftFail; 1677 if (!type && Rm == 15) 1678 S = MCDisassembler::SoftFail; 1679 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1680 S = MCDisassembler::SoftFail; 1681 break; 1682 case ARM::LDRSH: 1683 case ARM::LDRSH_PRE: 1684 case ARM::LDRSH_POST: 1685 case ARM::LDRSB: 1686 case ARM::LDRSB_PRE: 1687 case ARM::LDRSB_POST: 1688 if (type && Rn == 15){ 1689 if (Rt == 15) 1690 S = MCDisassembler::SoftFail; 1691 break; 1692 } 1693 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1694 S = MCDisassembler::SoftFail; 1695 if (!type && (Rt == 15 || Rm == 15)) 1696 S = MCDisassembler::SoftFail; 1697 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1698 S = MCDisassembler::SoftFail; 1699 break; 1700 default: 1701 break; 1702 } 1703 1704 if (writeback) { // Writeback 1705 if (P) 1706 U |= ARMII::IndexModePre << 9; 1707 else 1708 U |= ARMII::IndexModePost << 9; 1709 1710 // On stores, the writeback operand precedes Rt. 1711 switch (Inst.getOpcode()) { 1712 case ARM::STRD: 1713 case ARM::STRD_PRE: 1714 case ARM::STRD_POST: 1715 case ARM::STRH: 1716 case ARM::STRH_PRE: 1717 case ARM::STRH_POST: 1718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1719 return MCDisassembler::Fail; 1720 break; 1721 default: 1722 break; 1723 } 1724 } 1725 1726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1727 return MCDisassembler::Fail; 1728 switch (Inst.getOpcode()) { 1729 case ARM::STRD: 1730 case ARM::STRD_PRE: 1731 case ARM::STRD_POST: 1732 case ARM::LDRD: 1733 case ARM::LDRD_PRE: 1734 case ARM::LDRD_POST: 1735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1736 return MCDisassembler::Fail; 1737 break; 1738 default: 1739 break; 1740 } 1741 1742 if (writeback) { 1743 // On loads, the writeback operand comes after Rt. 1744 switch (Inst.getOpcode()) { 1745 case ARM::LDRD: 1746 case ARM::LDRD_PRE: 1747 case ARM::LDRD_POST: 1748 case ARM::LDRH: 1749 case ARM::LDRH_PRE: 1750 case ARM::LDRH_POST: 1751 case ARM::LDRSH: 1752 case ARM::LDRSH_PRE: 1753 case ARM::LDRSH_POST: 1754 case ARM::LDRSB: 1755 case ARM::LDRSB_PRE: 1756 case ARM::LDRSB_POST: 1757 case ARM::LDRHTr: 1758 case ARM::LDRSBTr: 1759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1760 return MCDisassembler::Fail; 1761 break; 1762 default: 1763 break; 1764 } 1765 } 1766 1767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1768 return MCDisassembler::Fail; 1769 1770 if (type) { 1771 Inst.addOperand(MCOperand::CreateReg(0)); 1772 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1773 } else { 1774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1775 return MCDisassembler::Fail; 1776 Inst.addOperand(MCOperand::CreateImm(U)); 1777 } 1778 1779 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1780 return MCDisassembler::Fail; 1781 1782 return S; 1783} 1784 1785static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1786 uint64_t Address, const void *Decoder) { 1787 DecodeStatus S = MCDisassembler::Success; 1788 1789 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1790 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1791 1792 switch (mode) { 1793 case 0: 1794 mode = ARM_AM::da; 1795 break; 1796 case 1: 1797 mode = ARM_AM::ia; 1798 break; 1799 case 2: 1800 mode = ARM_AM::db; 1801 break; 1802 case 3: 1803 mode = ARM_AM::ib; 1804 break; 1805 } 1806 1807 Inst.addOperand(MCOperand::CreateImm(mode)); 1808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1809 return MCDisassembler::Fail; 1810 1811 return S; 1812} 1813 1814static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1815 unsigned Insn, 1816 uint64_t Address, const void *Decoder) { 1817 DecodeStatus S = MCDisassembler::Success; 1818 1819 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1820 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1821 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1822 1823 if (pred == 0xF) { 1824 switch (Inst.getOpcode()) { 1825 case ARM::LDMDA: 1826 Inst.setOpcode(ARM::RFEDA); 1827 break; 1828 case ARM::LDMDA_UPD: 1829 Inst.setOpcode(ARM::RFEDA_UPD); 1830 break; 1831 case ARM::LDMDB: 1832 Inst.setOpcode(ARM::RFEDB); 1833 break; 1834 case ARM::LDMDB_UPD: 1835 Inst.setOpcode(ARM::RFEDB_UPD); 1836 break; 1837 case ARM::LDMIA: 1838 Inst.setOpcode(ARM::RFEIA); 1839 break; 1840 case ARM::LDMIA_UPD: 1841 Inst.setOpcode(ARM::RFEIA_UPD); 1842 break; 1843 case ARM::LDMIB: 1844 Inst.setOpcode(ARM::RFEIB); 1845 break; 1846 case ARM::LDMIB_UPD: 1847 Inst.setOpcode(ARM::RFEIB_UPD); 1848 break; 1849 case ARM::STMDA: 1850 Inst.setOpcode(ARM::SRSDA); 1851 break; 1852 case ARM::STMDA_UPD: 1853 Inst.setOpcode(ARM::SRSDA_UPD); 1854 break; 1855 case ARM::STMDB: 1856 Inst.setOpcode(ARM::SRSDB); 1857 break; 1858 case ARM::STMDB_UPD: 1859 Inst.setOpcode(ARM::SRSDB_UPD); 1860 break; 1861 case ARM::STMIA: 1862 Inst.setOpcode(ARM::SRSIA); 1863 break; 1864 case ARM::STMIA_UPD: 1865 Inst.setOpcode(ARM::SRSIA_UPD); 1866 break; 1867 case ARM::STMIB: 1868 Inst.setOpcode(ARM::SRSIB); 1869 break; 1870 case ARM::STMIB_UPD: 1871 Inst.setOpcode(ARM::SRSIB_UPD); 1872 break; 1873 default: 1874 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1875 } 1876 1877 // For stores (which become SRS's, the only operand is the mode. 1878 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1879 Inst.addOperand( 1880 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1881 return S; 1882 } 1883 1884 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1885 } 1886 1887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1888 return MCDisassembler::Fail; 1889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1890 return MCDisassembler::Fail; // Tied 1891 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1892 return MCDisassembler::Fail; 1893 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1894 return MCDisassembler::Fail; 1895 1896 return S; 1897} 1898 1899static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1900 uint64_t Address, const void *Decoder) { 1901 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1902 unsigned M = fieldFromInstruction(Insn, 17, 1); 1903 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1904 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1905 1906 DecodeStatus S = MCDisassembler::Success; 1907 1908 // imod == '01' --> UNPREDICTABLE 1909 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1910 // return failure here. The '01' imod value is unprintable, so there's 1911 // nothing useful we could do even if we returned UNPREDICTABLE. 1912 1913 if (imod == 1) return MCDisassembler::Fail; 1914 1915 if (imod && M) { 1916 Inst.setOpcode(ARM::CPS3p); 1917 Inst.addOperand(MCOperand::CreateImm(imod)); 1918 Inst.addOperand(MCOperand::CreateImm(iflags)); 1919 Inst.addOperand(MCOperand::CreateImm(mode)); 1920 } else if (imod && !M) { 1921 Inst.setOpcode(ARM::CPS2p); 1922 Inst.addOperand(MCOperand::CreateImm(imod)); 1923 Inst.addOperand(MCOperand::CreateImm(iflags)); 1924 if (mode) S = MCDisassembler::SoftFail; 1925 } else if (!imod && M) { 1926 Inst.setOpcode(ARM::CPS1p); 1927 Inst.addOperand(MCOperand::CreateImm(mode)); 1928 if (iflags) S = MCDisassembler::SoftFail; 1929 } else { 1930 // imod == '00' && M == '0' --> UNPREDICTABLE 1931 Inst.setOpcode(ARM::CPS1p); 1932 Inst.addOperand(MCOperand::CreateImm(mode)); 1933 S = MCDisassembler::SoftFail; 1934 } 1935 1936 return S; 1937} 1938 1939static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1940 uint64_t Address, const void *Decoder) { 1941 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1942 unsigned M = fieldFromInstruction(Insn, 8, 1); 1943 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1944 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1945 1946 DecodeStatus S = MCDisassembler::Success; 1947 1948 // imod == '01' --> UNPREDICTABLE 1949 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1950 // return failure here. The '01' imod value is unprintable, so there's 1951 // nothing useful we could do even if we returned UNPREDICTABLE. 1952 1953 if (imod == 1) return MCDisassembler::Fail; 1954 1955 if (imod && M) { 1956 Inst.setOpcode(ARM::t2CPS3p); 1957 Inst.addOperand(MCOperand::CreateImm(imod)); 1958 Inst.addOperand(MCOperand::CreateImm(iflags)); 1959 Inst.addOperand(MCOperand::CreateImm(mode)); 1960 } else if (imod && !M) { 1961 Inst.setOpcode(ARM::t2CPS2p); 1962 Inst.addOperand(MCOperand::CreateImm(imod)); 1963 Inst.addOperand(MCOperand::CreateImm(iflags)); 1964 if (mode) S = MCDisassembler::SoftFail; 1965 } else if (!imod && M) { 1966 Inst.setOpcode(ARM::t2CPS1p); 1967 Inst.addOperand(MCOperand::CreateImm(mode)); 1968 if (iflags) S = MCDisassembler::SoftFail; 1969 } else { 1970 // imod == '00' && M == '0' --> UNPREDICTABLE 1971 Inst.setOpcode(ARM::t2CPS1p); 1972 Inst.addOperand(MCOperand::CreateImm(mode)); 1973 S = MCDisassembler::SoftFail; 1974 } 1975 1976 return S; 1977} 1978 1979static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 1980 uint64_t Address, const void *Decoder) { 1981 DecodeStatus S = MCDisassembler::Success; 1982 1983 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 1984 unsigned imm = 0; 1985 1986 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 1987 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 1988 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 1989 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 1990 1991 if (Inst.getOpcode() == ARM::t2MOVTi16) 1992 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1993 return MCDisassembler::Fail; 1994 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1995 return MCDisassembler::Fail; 1996 1997 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1998 Inst.addOperand(MCOperand::CreateImm(imm)); 1999 2000 return S; 2001} 2002 2003static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2004 uint64_t Address, const void *Decoder) { 2005 DecodeStatus S = MCDisassembler::Success; 2006 2007 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2008 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2009 unsigned imm = 0; 2010 2011 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2012 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2013 2014 if (Inst.getOpcode() == ARM::MOVTi16) 2015 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2016 return MCDisassembler::Fail; 2017 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2018 return MCDisassembler::Fail; 2019 2020 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2021 Inst.addOperand(MCOperand::CreateImm(imm)); 2022 2023 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2024 return MCDisassembler::Fail; 2025 2026 return S; 2027} 2028 2029static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2030 uint64_t Address, const void *Decoder) { 2031 DecodeStatus S = MCDisassembler::Success; 2032 2033 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2034 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2035 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2036 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2037 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2038 2039 if (pred == 0xF) 2040 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2041 2042 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2043 return MCDisassembler::Fail; 2044 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2045 return MCDisassembler::Fail; 2046 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2047 return MCDisassembler::Fail; 2048 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2049 return MCDisassembler::Fail; 2050 2051 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2052 return MCDisassembler::Fail; 2053 2054 return S; 2055} 2056 2057static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2058 uint64_t Address, const void *Decoder) { 2059 DecodeStatus S = MCDisassembler::Success; 2060 2061 unsigned add = fieldFromInstruction(Val, 12, 1); 2062 unsigned imm = fieldFromInstruction(Val, 0, 12); 2063 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2064 2065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2066 return MCDisassembler::Fail; 2067 2068 if (!add) imm *= -1; 2069 if (imm == 0 && !add) imm = INT32_MIN; 2070 Inst.addOperand(MCOperand::CreateImm(imm)); 2071 if (Rn == 15) 2072 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2073 2074 return S; 2075} 2076 2077static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2078 uint64_t Address, const void *Decoder) { 2079 DecodeStatus S = MCDisassembler::Success; 2080 2081 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2082 unsigned U = fieldFromInstruction(Val, 8, 1); 2083 unsigned imm = fieldFromInstruction(Val, 0, 8); 2084 2085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2086 return MCDisassembler::Fail; 2087 2088 if (U) 2089 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2090 else 2091 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2092 2093 return S; 2094} 2095 2096static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2097 uint64_t Address, const void *Decoder) { 2098 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2099} 2100 2101static DecodeStatus 2102DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2103 uint64_t Address, const void *Decoder) { 2104 DecodeStatus Status = MCDisassembler::Success; 2105 2106 // Note the J1 and J2 values are from the encoded instruction. So here 2107 // change them to I1 and I2 values via as documented: 2108 // I1 = NOT(J1 EOR S); 2109 // I2 = NOT(J2 EOR S); 2110 // and build the imm32 with one trailing zero as documented: 2111 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2112 unsigned S = fieldFromInstruction(Insn, 26, 1); 2113 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2114 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2115 unsigned I1 = !(J1 ^ S); 2116 unsigned I2 = !(J2 ^ S); 2117 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2118 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2119 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2120 int imm32 = SignExtend32<24>(tmp << 1); 2121 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2122 true, 4, Inst, Decoder)) 2123 Inst.addOperand(MCOperand::CreateImm(imm32)); 2124 2125 return Status; 2126} 2127 2128static DecodeStatus 2129DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2130 uint64_t Address, const void *Decoder) { 2131 DecodeStatus S = MCDisassembler::Success; 2132 2133 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2134 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2135 2136 if (pred == 0xF) { 2137 Inst.setOpcode(ARM::BLXi); 2138 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2139 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2140 true, 4, Inst, Decoder)) 2141 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2142 return S; 2143 } 2144 2145 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2146 true, 4, Inst, Decoder)) 2147 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2148 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2149 return MCDisassembler::Fail; 2150 2151 return S; 2152} 2153 2154 2155static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2156 uint64_t Address, const void *Decoder) { 2157 DecodeStatus S = MCDisassembler::Success; 2158 2159 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2160 unsigned align = fieldFromInstruction(Val, 4, 2); 2161 2162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2163 return MCDisassembler::Fail; 2164 if (!align) 2165 Inst.addOperand(MCOperand::CreateImm(0)); 2166 else 2167 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2168 2169 return S; 2170} 2171 2172static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2173 uint64_t Address, const void *Decoder) { 2174 DecodeStatus S = MCDisassembler::Success; 2175 2176 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2177 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2178 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2179 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2180 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2181 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2182 2183 // First output register 2184 switch (Inst.getOpcode()) { 2185 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2186 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2187 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2188 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2189 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2190 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2191 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2192 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2193 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2194 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2195 return MCDisassembler::Fail; 2196 break; 2197 case ARM::VLD2b16: 2198 case ARM::VLD2b32: 2199 case ARM::VLD2b8: 2200 case ARM::VLD2b16wb_fixed: 2201 case ARM::VLD2b16wb_register: 2202 case ARM::VLD2b32wb_fixed: 2203 case ARM::VLD2b32wb_register: 2204 case ARM::VLD2b8wb_fixed: 2205 case ARM::VLD2b8wb_register: 2206 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2207 return MCDisassembler::Fail; 2208 break; 2209 default: 2210 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2211 return MCDisassembler::Fail; 2212 } 2213 2214 // Second output register 2215 switch (Inst.getOpcode()) { 2216 case ARM::VLD3d8: 2217 case ARM::VLD3d16: 2218 case ARM::VLD3d32: 2219 case ARM::VLD3d8_UPD: 2220 case ARM::VLD3d16_UPD: 2221 case ARM::VLD3d32_UPD: 2222 case ARM::VLD4d8: 2223 case ARM::VLD4d16: 2224 case ARM::VLD4d32: 2225 case ARM::VLD4d8_UPD: 2226 case ARM::VLD4d16_UPD: 2227 case ARM::VLD4d32_UPD: 2228 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2229 return MCDisassembler::Fail; 2230 break; 2231 case ARM::VLD3q8: 2232 case ARM::VLD3q16: 2233 case ARM::VLD3q32: 2234 case ARM::VLD3q8_UPD: 2235 case ARM::VLD3q16_UPD: 2236 case ARM::VLD3q32_UPD: 2237 case ARM::VLD4q8: 2238 case ARM::VLD4q16: 2239 case ARM::VLD4q32: 2240 case ARM::VLD4q8_UPD: 2241 case ARM::VLD4q16_UPD: 2242 case ARM::VLD4q32_UPD: 2243 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2244 return MCDisassembler::Fail; 2245 default: 2246 break; 2247 } 2248 2249 // Third output register 2250 switch(Inst.getOpcode()) { 2251 case ARM::VLD3d8: 2252 case ARM::VLD3d16: 2253 case ARM::VLD3d32: 2254 case ARM::VLD3d8_UPD: 2255 case ARM::VLD3d16_UPD: 2256 case ARM::VLD3d32_UPD: 2257 case ARM::VLD4d8: 2258 case ARM::VLD4d16: 2259 case ARM::VLD4d32: 2260 case ARM::VLD4d8_UPD: 2261 case ARM::VLD4d16_UPD: 2262 case ARM::VLD4d32_UPD: 2263 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2264 return MCDisassembler::Fail; 2265 break; 2266 case ARM::VLD3q8: 2267 case ARM::VLD3q16: 2268 case ARM::VLD3q32: 2269 case ARM::VLD3q8_UPD: 2270 case ARM::VLD3q16_UPD: 2271 case ARM::VLD3q32_UPD: 2272 case ARM::VLD4q8: 2273 case ARM::VLD4q16: 2274 case ARM::VLD4q32: 2275 case ARM::VLD4q8_UPD: 2276 case ARM::VLD4q16_UPD: 2277 case ARM::VLD4q32_UPD: 2278 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2279 return MCDisassembler::Fail; 2280 break; 2281 default: 2282 break; 2283 } 2284 2285 // Fourth output register 2286 switch (Inst.getOpcode()) { 2287 case ARM::VLD4d8: 2288 case ARM::VLD4d16: 2289 case ARM::VLD4d32: 2290 case ARM::VLD4d8_UPD: 2291 case ARM::VLD4d16_UPD: 2292 case ARM::VLD4d32_UPD: 2293 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2294 return MCDisassembler::Fail; 2295 break; 2296 case ARM::VLD4q8: 2297 case ARM::VLD4q16: 2298 case ARM::VLD4q32: 2299 case ARM::VLD4q8_UPD: 2300 case ARM::VLD4q16_UPD: 2301 case ARM::VLD4q32_UPD: 2302 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2303 return MCDisassembler::Fail; 2304 break; 2305 default: 2306 break; 2307 } 2308 2309 // Writeback operand 2310 switch (Inst.getOpcode()) { 2311 case ARM::VLD1d8wb_fixed: 2312 case ARM::VLD1d16wb_fixed: 2313 case ARM::VLD1d32wb_fixed: 2314 case ARM::VLD1d64wb_fixed: 2315 case ARM::VLD1d8wb_register: 2316 case ARM::VLD1d16wb_register: 2317 case ARM::VLD1d32wb_register: 2318 case ARM::VLD1d64wb_register: 2319 case ARM::VLD1q8wb_fixed: 2320 case ARM::VLD1q16wb_fixed: 2321 case ARM::VLD1q32wb_fixed: 2322 case ARM::VLD1q64wb_fixed: 2323 case ARM::VLD1q8wb_register: 2324 case ARM::VLD1q16wb_register: 2325 case ARM::VLD1q32wb_register: 2326 case ARM::VLD1q64wb_register: 2327 case ARM::VLD1d8Twb_fixed: 2328 case ARM::VLD1d8Twb_register: 2329 case ARM::VLD1d16Twb_fixed: 2330 case ARM::VLD1d16Twb_register: 2331 case ARM::VLD1d32Twb_fixed: 2332 case ARM::VLD1d32Twb_register: 2333 case ARM::VLD1d64Twb_fixed: 2334 case ARM::VLD1d64Twb_register: 2335 case ARM::VLD1d8Qwb_fixed: 2336 case ARM::VLD1d8Qwb_register: 2337 case ARM::VLD1d16Qwb_fixed: 2338 case ARM::VLD1d16Qwb_register: 2339 case ARM::VLD1d32Qwb_fixed: 2340 case ARM::VLD1d32Qwb_register: 2341 case ARM::VLD1d64Qwb_fixed: 2342 case ARM::VLD1d64Qwb_register: 2343 case ARM::VLD2d8wb_fixed: 2344 case ARM::VLD2d16wb_fixed: 2345 case ARM::VLD2d32wb_fixed: 2346 case ARM::VLD2q8wb_fixed: 2347 case ARM::VLD2q16wb_fixed: 2348 case ARM::VLD2q32wb_fixed: 2349 case ARM::VLD2d8wb_register: 2350 case ARM::VLD2d16wb_register: 2351 case ARM::VLD2d32wb_register: 2352 case ARM::VLD2q8wb_register: 2353 case ARM::VLD2q16wb_register: 2354 case ARM::VLD2q32wb_register: 2355 case ARM::VLD2b8wb_fixed: 2356 case ARM::VLD2b16wb_fixed: 2357 case ARM::VLD2b32wb_fixed: 2358 case ARM::VLD2b8wb_register: 2359 case ARM::VLD2b16wb_register: 2360 case ARM::VLD2b32wb_register: 2361 Inst.addOperand(MCOperand::CreateImm(0)); 2362 break; 2363 case ARM::VLD3d8_UPD: 2364 case ARM::VLD3d16_UPD: 2365 case ARM::VLD3d32_UPD: 2366 case ARM::VLD3q8_UPD: 2367 case ARM::VLD3q16_UPD: 2368 case ARM::VLD3q32_UPD: 2369 case ARM::VLD4d8_UPD: 2370 case ARM::VLD4d16_UPD: 2371 case ARM::VLD4d32_UPD: 2372 case ARM::VLD4q8_UPD: 2373 case ARM::VLD4q16_UPD: 2374 case ARM::VLD4q32_UPD: 2375 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2376 return MCDisassembler::Fail; 2377 break; 2378 default: 2379 break; 2380 } 2381 2382 // AddrMode6 Base (register+alignment) 2383 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2384 return MCDisassembler::Fail; 2385 2386 // AddrMode6 Offset (register) 2387 switch (Inst.getOpcode()) { 2388 default: 2389 // The below have been updated to have explicit am6offset split 2390 // between fixed and register offset. For those instructions not 2391 // yet updated, we need to add an additional reg0 operand for the 2392 // fixed variant. 2393 // 2394 // The fixed offset encodes as Rm == 0xd, so we check for that. 2395 if (Rm == 0xd) { 2396 Inst.addOperand(MCOperand::CreateReg(0)); 2397 break; 2398 } 2399 // Fall through to handle the register offset variant. 2400 case ARM::VLD1d8wb_fixed: 2401 case ARM::VLD1d16wb_fixed: 2402 case ARM::VLD1d32wb_fixed: 2403 case ARM::VLD1d64wb_fixed: 2404 case ARM::VLD1d8Twb_fixed: 2405 case ARM::VLD1d16Twb_fixed: 2406 case ARM::VLD1d32Twb_fixed: 2407 case ARM::VLD1d64Twb_fixed: 2408 case ARM::VLD1d8Qwb_fixed: 2409 case ARM::VLD1d16Qwb_fixed: 2410 case ARM::VLD1d32Qwb_fixed: 2411 case ARM::VLD1d64Qwb_fixed: 2412 case ARM::VLD1d8wb_register: 2413 case ARM::VLD1d16wb_register: 2414 case ARM::VLD1d32wb_register: 2415 case ARM::VLD1d64wb_register: 2416 case ARM::VLD1q8wb_fixed: 2417 case ARM::VLD1q16wb_fixed: 2418 case ARM::VLD1q32wb_fixed: 2419 case ARM::VLD1q64wb_fixed: 2420 case ARM::VLD1q8wb_register: 2421 case ARM::VLD1q16wb_register: 2422 case ARM::VLD1q32wb_register: 2423 case ARM::VLD1q64wb_register: 2424 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2425 // variant encodes Rm == 0xf. Anything else is a register offset post- 2426 // increment and we need to add the register operand to the instruction. 2427 if (Rm != 0xD && Rm != 0xF && 2428 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2429 return MCDisassembler::Fail; 2430 break; 2431 case ARM::VLD2d8wb_fixed: 2432 case ARM::VLD2d16wb_fixed: 2433 case ARM::VLD2d32wb_fixed: 2434 case ARM::VLD2b8wb_fixed: 2435 case ARM::VLD2b16wb_fixed: 2436 case ARM::VLD2b32wb_fixed: 2437 case ARM::VLD2q8wb_fixed: 2438 case ARM::VLD2q16wb_fixed: 2439 case ARM::VLD2q32wb_fixed: 2440 break; 2441 } 2442 2443 return S; 2444} 2445 2446static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2447 uint64_t Address, const void *Decoder) { 2448 DecodeStatus S = MCDisassembler::Success; 2449 2450 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2451 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2452 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2453 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2454 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2455 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2456 2457 // Writeback Operand 2458 switch (Inst.getOpcode()) { 2459 case ARM::VST1d8wb_fixed: 2460 case ARM::VST1d16wb_fixed: 2461 case ARM::VST1d32wb_fixed: 2462 case ARM::VST1d64wb_fixed: 2463 case ARM::VST1d8wb_register: 2464 case ARM::VST1d16wb_register: 2465 case ARM::VST1d32wb_register: 2466 case ARM::VST1d64wb_register: 2467 case ARM::VST1q8wb_fixed: 2468 case ARM::VST1q16wb_fixed: 2469 case ARM::VST1q32wb_fixed: 2470 case ARM::VST1q64wb_fixed: 2471 case ARM::VST1q8wb_register: 2472 case ARM::VST1q16wb_register: 2473 case ARM::VST1q32wb_register: 2474 case ARM::VST1q64wb_register: 2475 case ARM::VST1d8Twb_fixed: 2476 case ARM::VST1d16Twb_fixed: 2477 case ARM::VST1d32Twb_fixed: 2478 case ARM::VST1d64Twb_fixed: 2479 case ARM::VST1d8Twb_register: 2480 case ARM::VST1d16Twb_register: 2481 case ARM::VST1d32Twb_register: 2482 case ARM::VST1d64Twb_register: 2483 case ARM::VST1d8Qwb_fixed: 2484 case ARM::VST1d16Qwb_fixed: 2485 case ARM::VST1d32Qwb_fixed: 2486 case ARM::VST1d64Qwb_fixed: 2487 case ARM::VST1d8Qwb_register: 2488 case ARM::VST1d16Qwb_register: 2489 case ARM::VST1d32Qwb_register: 2490 case ARM::VST1d64Qwb_register: 2491 case ARM::VST2d8wb_fixed: 2492 case ARM::VST2d16wb_fixed: 2493 case ARM::VST2d32wb_fixed: 2494 case ARM::VST2d8wb_register: 2495 case ARM::VST2d16wb_register: 2496 case ARM::VST2d32wb_register: 2497 case ARM::VST2q8wb_fixed: 2498 case ARM::VST2q16wb_fixed: 2499 case ARM::VST2q32wb_fixed: 2500 case ARM::VST2q8wb_register: 2501 case ARM::VST2q16wb_register: 2502 case ARM::VST2q32wb_register: 2503 case ARM::VST2b8wb_fixed: 2504 case ARM::VST2b16wb_fixed: 2505 case ARM::VST2b32wb_fixed: 2506 case ARM::VST2b8wb_register: 2507 case ARM::VST2b16wb_register: 2508 case ARM::VST2b32wb_register: 2509 if (Rm == 0xF) 2510 return MCDisassembler::Fail; 2511 Inst.addOperand(MCOperand::CreateImm(0)); 2512 break; 2513 case ARM::VST3d8_UPD: 2514 case ARM::VST3d16_UPD: 2515 case ARM::VST3d32_UPD: 2516 case ARM::VST3q8_UPD: 2517 case ARM::VST3q16_UPD: 2518 case ARM::VST3q32_UPD: 2519 case ARM::VST4d8_UPD: 2520 case ARM::VST4d16_UPD: 2521 case ARM::VST4d32_UPD: 2522 case ARM::VST4q8_UPD: 2523 case ARM::VST4q16_UPD: 2524 case ARM::VST4q32_UPD: 2525 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2526 return MCDisassembler::Fail; 2527 break; 2528 default: 2529 break; 2530 } 2531 2532 // AddrMode6 Base (register+alignment) 2533 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 2536 // AddrMode6 Offset (register) 2537 switch (Inst.getOpcode()) { 2538 default: 2539 if (Rm == 0xD) 2540 Inst.addOperand(MCOperand::CreateReg(0)); 2541 else if (Rm != 0xF) { 2542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2543 return MCDisassembler::Fail; 2544 } 2545 break; 2546 case ARM::VST1d8wb_fixed: 2547 case ARM::VST1d16wb_fixed: 2548 case ARM::VST1d32wb_fixed: 2549 case ARM::VST1d64wb_fixed: 2550 case ARM::VST1q8wb_fixed: 2551 case ARM::VST1q16wb_fixed: 2552 case ARM::VST1q32wb_fixed: 2553 case ARM::VST1q64wb_fixed: 2554 case ARM::VST1d8Twb_fixed: 2555 case ARM::VST1d16Twb_fixed: 2556 case ARM::VST1d32Twb_fixed: 2557 case ARM::VST1d64Twb_fixed: 2558 case ARM::VST1d8Qwb_fixed: 2559 case ARM::VST1d16Qwb_fixed: 2560 case ARM::VST1d32Qwb_fixed: 2561 case ARM::VST1d64Qwb_fixed: 2562 case ARM::VST2d8wb_fixed: 2563 case ARM::VST2d16wb_fixed: 2564 case ARM::VST2d32wb_fixed: 2565 case ARM::VST2q8wb_fixed: 2566 case ARM::VST2q16wb_fixed: 2567 case ARM::VST2q32wb_fixed: 2568 case ARM::VST2b8wb_fixed: 2569 case ARM::VST2b16wb_fixed: 2570 case ARM::VST2b32wb_fixed: 2571 break; 2572 } 2573 2574 2575 // First input register 2576 switch (Inst.getOpcode()) { 2577 case ARM::VST1q16: 2578 case ARM::VST1q32: 2579 case ARM::VST1q64: 2580 case ARM::VST1q8: 2581 case ARM::VST1q16wb_fixed: 2582 case ARM::VST1q16wb_register: 2583 case ARM::VST1q32wb_fixed: 2584 case ARM::VST1q32wb_register: 2585 case ARM::VST1q64wb_fixed: 2586 case ARM::VST1q64wb_register: 2587 case ARM::VST1q8wb_fixed: 2588 case ARM::VST1q8wb_register: 2589 case ARM::VST2d16: 2590 case ARM::VST2d32: 2591 case ARM::VST2d8: 2592 case ARM::VST2d16wb_fixed: 2593 case ARM::VST2d16wb_register: 2594 case ARM::VST2d32wb_fixed: 2595 case ARM::VST2d32wb_register: 2596 case ARM::VST2d8wb_fixed: 2597 case ARM::VST2d8wb_register: 2598 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2599 return MCDisassembler::Fail; 2600 break; 2601 case ARM::VST2b16: 2602 case ARM::VST2b32: 2603 case ARM::VST2b8: 2604 case ARM::VST2b16wb_fixed: 2605 case ARM::VST2b16wb_register: 2606 case ARM::VST2b32wb_fixed: 2607 case ARM::VST2b32wb_register: 2608 case ARM::VST2b8wb_fixed: 2609 case ARM::VST2b8wb_register: 2610 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2611 return MCDisassembler::Fail; 2612 break; 2613 default: 2614 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2615 return MCDisassembler::Fail; 2616 } 2617 2618 // Second input register 2619 switch (Inst.getOpcode()) { 2620 case ARM::VST3d8: 2621 case ARM::VST3d16: 2622 case ARM::VST3d32: 2623 case ARM::VST3d8_UPD: 2624 case ARM::VST3d16_UPD: 2625 case ARM::VST3d32_UPD: 2626 case ARM::VST4d8: 2627 case ARM::VST4d16: 2628 case ARM::VST4d32: 2629 case ARM::VST4d8_UPD: 2630 case ARM::VST4d16_UPD: 2631 case ARM::VST4d32_UPD: 2632 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2633 return MCDisassembler::Fail; 2634 break; 2635 case ARM::VST3q8: 2636 case ARM::VST3q16: 2637 case ARM::VST3q32: 2638 case ARM::VST3q8_UPD: 2639 case ARM::VST3q16_UPD: 2640 case ARM::VST3q32_UPD: 2641 case ARM::VST4q8: 2642 case ARM::VST4q16: 2643 case ARM::VST4q32: 2644 case ARM::VST4q8_UPD: 2645 case ARM::VST4q16_UPD: 2646 case ARM::VST4q32_UPD: 2647 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2648 return MCDisassembler::Fail; 2649 break; 2650 default: 2651 break; 2652 } 2653 2654 // Third input register 2655 switch (Inst.getOpcode()) { 2656 case ARM::VST3d8: 2657 case ARM::VST3d16: 2658 case ARM::VST3d32: 2659 case ARM::VST3d8_UPD: 2660 case ARM::VST3d16_UPD: 2661 case ARM::VST3d32_UPD: 2662 case ARM::VST4d8: 2663 case ARM::VST4d16: 2664 case ARM::VST4d32: 2665 case ARM::VST4d8_UPD: 2666 case ARM::VST4d16_UPD: 2667 case ARM::VST4d32_UPD: 2668 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2669 return MCDisassembler::Fail; 2670 break; 2671 case ARM::VST3q8: 2672 case ARM::VST3q16: 2673 case ARM::VST3q32: 2674 case ARM::VST3q8_UPD: 2675 case ARM::VST3q16_UPD: 2676 case ARM::VST3q32_UPD: 2677 case ARM::VST4q8: 2678 case ARM::VST4q16: 2679 case ARM::VST4q32: 2680 case ARM::VST4q8_UPD: 2681 case ARM::VST4q16_UPD: 2682 case ARM::VST4q32_UPD: 2683 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2684 return MCDisassembler::Fail; 2685 break; 2686 default: 2687 break; 2688 } 2689 2690 // Fourth input register 2691 switch (Inst.getOpcode()) { 2692 case ARM::VST4d8: 2693 case ARM::VST4d16: 2694 case ARM::VST4d32: 2695 case ARM::VST4d8_UPD: 2696 case ARM::VST4d16_UPD: 2697 case ARM::VST4d32_UPD: 2698 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2699 return MCDisassembler::Fail; 2700 break; 2701 case ARM::VST4q8: 2702 case ARM::VST4q16: 2703 case ARM::VST4q32: 2704 case ARM::VST4q8_UPD: 2705 case ARM::VST4q16_UPD: 2706 case ARM::VST4q32_UPD: 2707 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2708 return MCDisassembler::Fail; 2709 break; 2710 default: 2711 break; 2712 } 2713 2714 return S; 2715} 2716 2717static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2718 uint64_t Address, const void *Decoder) { 2719 DecodeStatus S = MCDisassembler::Success; 2720 2721 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2722 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2723 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2724 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2725 unsigned align = fieldFromInstruction(Insn, 4, 1); 2726 unsigned size = fieldFromInstruction(Insn, 6, 2); 2727 2728 if (size == 0 && align == 1) 2729 return MCDisassembler::Fail; 2730 align *= (1 << size); 2731 2732 switch (Inst.getOpcode()) { 2733 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2734 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2735 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2736 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2737 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2738 return MCDisassembler::Fail; 2739 break; 2740 default: 2741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2742 return MCDisassembler::Fail; 2743 break; 2744 } 2745 if (Rm != 0xF) { 2746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2747 return MCDisassembler::Fail; 2748 } 2749 2750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2751 return MCDisassembler::Fail; 2752 Inst.addOperand(MCOperand::CreateImm(align)); 2753 2754 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2755 // variant encodes Rm == 0xf. Anything else is a register offset post- 2756 // increment and we need to add the register operand to the instruction. 2757 if (Rm != 0xD && Rm != 0xF && 2758 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2759 return MCDisassembler::Fail; 2760 2761 return S; 2762} 2763 2764static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2765 uint64_t Address, const void *Decoder) { 2766 DecodeStatus S = MCDisassembler::Success; 2767 2768 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2769 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2770 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2771 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2772 unsigned align = fieldFromInstruction(Insn, 4, 1); 2773 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2774 align *= 2*size; 2775 2776 switch (Inst.getOpcode()) { 2777 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2778 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2779 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2780 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2781 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2782 return MCDisassembler::Fail; 2783 break; 2784 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2785 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2786 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2787 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2788 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2789 return MCDisassembler::Fail; 2790 break; 2791 default: 2792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 break; 2795 } 2796 2797 if (Rm != 0xF) 2798 Inst.addOperand(MCOperand::CreateImm(0)); 2799 2800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2801 return MCDisassembler::Fail; 2802 Inst.addOperand(MCOperand::CreateImm(align)); 2803 2804 if (Rm != 0xD && Rm != 0xF) { 2805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2806 return MCDisassembler::Fail; 2807 } 2808 2809 return S; 2810} 2811 2812static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2813 uint64_t Address, const void *Decoder) { 2814 DecodeStatus S = MCDisassembler::Success; 2815 2816 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2817 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2818 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2819 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2820 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2821 2822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2823 return MCDisassembler::Fail; 2824 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2825 return MCDisassembler::Fail; 2826 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2827 return MCDisassembler::Fail; 2828 if (Rm != 0xF) { 2829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2830 return MCDisassembler::Fail; 2831 } 2832 2833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 Inst.addOperand(MCOperand::CreateImm(0)); 2836 2837 if (Rm == 0xD) 2838 Inst.addOperand(MCOperand::CreateReg(0)); 2839 else if (Rm != 0xF) { 2840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2841 return MCDisassembler::Fail; 2842 } 2843 2844 return S; 2845} 2846 2847static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2848 uint64_t Address, const void *Decoder) { 2849 DecodeStatus S = MCDisassembler::Success; 2850 2851 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2852 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2853 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2854 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2855 unsigned size = fieldFromInstruction(Insn, 6, 2); 2856 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2857 unsigned align = fieldFromInstruction(Insn, 4, 1); 2858 2859 if (size == 0x3) { 2860 if (align == 0) 2861 return MCDisassembler::Fail; 2862 size = 4; 2863 align = 16; 2864 } else { 2865 if (size == 2) { 2866 size = 1 << size; 2867 align *= 8; 2868 } else { 2869 size = 1 << size; 2870 align *= 4*size; 2871 } 2872 } 2873 2874 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2877 return MCDisassembler::Fail; 2878 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2879 return MCDisassembler::Fail; 2880 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2881 return MCDisassembler::Fail; 2882 if (Rm != 0xF) { 2883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2884 return MCDisassembler::Fail; 2885 } 2886 2887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2888 return MCDisassembler::Fail; 2889 Inst.addOperand(MCOperand::CreateImm(align)); 2890 2891 if (Rm == 0xD) 2892 Inst.addOperand(MCOperand::CreateReg(0)); 2893 else if (Rm != 0xF) { 2894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2895 return MCDisassembler::Fail; 2896 } 2897 2898 return S; 2899} 2900 2901static DecodeStatus 2902DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 2903 uint64_t Address, const void *Decoder) { 2904 DecodeStatus S = MCDisassembler::Success; 2905 2906 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2907 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2908 unsigned imm = fieldFromInstruction(Insn, 0, 4); 2909 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 2910 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 2911 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 2912 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 2913 unsigned Q = fieldFromInstruction(Insn, 6, 1); 2914 2915 if (Q) { 2916 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2917 return MCDisassembler::Fail; 2918 } else { 2919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2920 return MCDisassembler::Fail; 2921 } 2922 2923 Inst.addOperand(MCOperand::CreateImm(imm)); 2924 2925 switch (Inst.getOpcode()) { 2926 case ARM::VORRiv4i16: 2927 case ARM::VORRiv2i32: 2928 case ARM::VBICiv4i16: 2929 case ARM::VBICiv2i32: 2930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2931 return MCDisassembler::Fail; 2932 break; 2933 case ARM::VORRiv8i16: 2934 case ARM::VORRiv4i32: 2935 case ARM::VBICiv8i16: 2936 case ARM::VBICiv4i32: 2937 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2938 return MCDisassembler::Fail; 2939 break; 2940 default: 2941 break; 2942 } 2943 2944 return S; 2945} 2946 2947static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 2948 uint64_t Address, const void *Decoder) { 2949 DecodeStatus S = MCDisassembler::Success; 2950 2951 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2952 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2953 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2954 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 2955 unsigned size = fieldFromInstruction(Insn, 18, 2); 2956 2957 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2958 return MCDisassembler::Fail; 2959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2960 return MCDisassembler::Fail; 2961 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2962 2963 return S; 2964} 2965 2966static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 2967 uint64_t Address, const void *Decoder) { 2968 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2969 return MCDisassembler::Success; 2970} 2971 2972static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 2973 uint64_t Address, const void *Decoder) { 2974 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2975 return MCDisassembler::Success; 2976} 2977 2978static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 2979 uint64_t Address, const void *Decoder) { 2980 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2981 return MCDisassembler::Success; 2982} 2983 2984static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 2985 uint64_t Address, const void *Decoder) { 2986 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2987 return MCDisassembler::Success; 2988} 2989 2990static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 2991 uint64_t Address, const void *Decoder) { 2992 DecodeStatus S = MCDisassembler::Success; 2993 2994 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2995 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2996 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2997 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 2998 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2999 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3000 unsigned op = fieldFromInstruction(Insn, 6, 1); 3001 3002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3003 return MCDisassembler::Fail; 3004 if (op) { 3005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3006 return MCDisassembler::Fail; // Writeback 3007 } 3008 3009 switch (Inst.getOpcode()) { 3010 case ARM::VTBL2: 3011 case ARM::VTBX2: 3012 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3013 return MCDisassembler::Fail; 3014 break; 3015 default: 3016 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3017 return MCDisassembler::Fail; 3018 } 3019 3020 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3021 return MCDisassembler::Fail; 3022 3023 return S; 3024} 3025 3026static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3027 uint64_t Address, const void *Decoder) { 3028 DecodeStatus S = MCDisassembler::Success; 3029 3030 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3031 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3032 3033 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3034 return MCDisassembler::Fail; 3035 3036 switch(Inst.getOpcode()) { 3037 default: 3038 return MCDisassembler::Fail; 3039 case ARM::tADR: 3040 break; // tADR does not explicitly represent the PC as an operand. 3041 case ARM::tADDrSPi: 3042 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3043 break; 3044 } 3045 3046 Inst.addOperand(MCOperand::CreateImm(imm)); 3047 return S; 3048} 3049 3050static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3051 uint64_t Address, const void *Decoder) { 3052 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3053 true, 2, Inst, Decoder)) 3054 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3055 return MCDisassembler::Success; 3056} 3057 3058static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3059 uint64_t Address, const void *Decoder) { 3060 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3061 true, 4, Inst, Decoder)) 3062 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3063 return MCDisassembler::Success; 3064} 3065 3066static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3067 uint64_t Address, const void *Decoder) { 3068 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4, 3069 true, 2, Inst, Decoder)) 3070 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 3071 return MCDisassembler::Success; 3072} 3073 3074static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3075 uint64_t Address, const void *Decoder) { 3076 DecodeStatus S = MCDisassembler::Success; 3077 3078 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3079 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3080 3081 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3082 return MCDisassembler::Fail; 3083 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3084 return MCDisassembler::Fail; 3085 3086 return S; 3087} 3088 3089static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3090 uint64_t Address, const void *Decoder) { 3091 DecodeStatus S = MCDisassembler::Success; 3092 3093 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3094 unsigned imm = fieldFromInstruction(Val, 3, 5); 3095 3096 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3097 return MCDisassembler::Fail; 3098 Inst.addOperand(MCOperand::CreateImm(imm)); 3099 3100 return S; 3101} 3102 3103static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3104 uint64_t Address, const void *Decoder) { 3105 unsigned imm = Val << 2; 3106 3107 Inst.addOperand(MCOperand::CreateImm(imm)); 3108 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3109 3110 return MCDisassembler::Success; 3111} 3112 3113static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3114 uint64_t Address, const void *Decoder) { 3115 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3116 Inst.addOperand(MCOperand::CreateImm(Val)); 3117 3118 return MCDisassembler::Success; 3119} 3120 3121static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3122 uint64_t Address, const void *Decoder) { 3123 DecodeStatus S = MCDisassembler::Success; 3124 3125 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3126 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3127 unsigned imm = fieldFromInstruction(Val, 0, 2); 3128 3129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3130 return MCDisassembler::Fail; 3131 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3132 return MCDisassembler::Fail; 3133 Inst.addOperand(MCOperand::CreateImm(imm)); 3134 3135 return S; 3136} 3137 3138static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3139 uint64_t Address, const void *Decoder) { 3140 DecodeStatus S = MCDisassembler::Success; 3141 3142 switch (Inst.getOpcode()) { 3143 case ARM::t2PLDs: 3144 case ARM::t2PLDWs: 3145 case ARM::t2PLIs: 3146 break; 3147 default: { 3148 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3149 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3150 return MCDisassembler::Fail; 3151 } 3152 } 3153 3154 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3155 if (Rn == 0xF) { 3156 switch (Inst.getOpcode()) { 3157 case ARM::t2LDRBs: 3158 Inst.setOpcode(ARM::t2LDRBpci); 3159 break; 3160 case ARM::t2LDRHs: 3161 Inst.setOpcode(ARM::t2LDRHpci); 3162 break; 3163 case ARM::t2LDRSHs: 3164 Inst.setOpcode(ARM::t2LDRSHpci); 3165 break; 3166 case ARM::t2LDRSBs: 3167 Inst.setOpcode(ARM::t2LDRSBpci); 3168 break; 3169 case ARM::t2PLDs: 3170 Inst.setOpcode(ARM::t2PLDi12); 3171 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 3172 break; 3173 default: 3174 return MCDisassembler::Fail; 3175 } 3176 3177 int imm = fieldFromInstruction(Insn, 0, 12); 3178 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1; 3179 Inst.addOperand(MCOperand::CreateImm(imm)); 3180 3181 return S; 3182 } 3183 3184 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3185 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3186 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3187 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3188 return MCDisassembler::Fail; 3189 3190 return S; 3191} 3192 3193static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3194 uint64_t Address, const void *Decoder) { 3195 if (Val == 0) 3196 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3197 else { 3198 int imm = Val & 0xFF; 3199 3200 if (!(Val & 0x100)) imm *= -1; 3201 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3202 } 3203 3204 return MCDisassembler::Success; 3205} 3206 3207static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3208 uint64_t Address, const void *Decoder) { 3209 DecodeStatus S = MCDisassembler::Success; 3210 3211 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3212 unsigned imm = fieldFromInstruction(Val, 0, 9); 3213 3214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3215 return MCDisassembler::Fail; 3216 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3217 return MCDisassembler::Fail; 3218 3219 return S; 3220} 3221 3222static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3223 uint64_t Address, const void *Decoder) { 3224 DecodeStatus S = MCDisassembler::Success; 3225 3226 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3227 unsigned imm = fieldFromInstruction(Val, 0, 8); 3228 3229 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 3232 Inst.addOperand(MCOperand::CreateImm(imm)); 3233 3234 return S; 3235} 3236 3237static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3238 uint64_t Address, const void *Decoder) { 3239 int imm = Val & 0xFF; 3240 if (Val == 0) 3241 imm = INT32_MIN; 3242 else if (!(Val & 0x100)) 3243 imm *= -1; 3244 Inst.addOperand(MCOperand::CreateImm(imm)); 3245 3246 return MCDisassembler::Success; 3247} 3248 3249 3250static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3251 uint64_t Address, const void *Decoder) { 3252 DecodeStatus S = MCDisassembler::Success; 3253 3254 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3255 unsigned imm = fieldFromInstruction(Val, 0, 9); 3256 3257 // Some instructions always use an additive offset. 3258 switch (Inst.getOpcode()) { 3259 case ARM::t2LDRT: 3260 case ARM::t2LDRBT: 3261 case ARM::t2LDRHT: 3262 case ARM::t2LDRSBT: 3263 case ARM::t2LDRSHT: 3264 case ARM::t2STRT: 3265 case ARM::t2STRBT: 3266 case ARM::t2STRHT: 3267 imm |= 0x100; 3268 break; 3269 default: 3270 break; 3271 } 3272 3273 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3274 return MCDisassembler::Fail; 3275 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3276 return MCDisassembler::Fail; 3277 3278 return S; 3279} 3280 3281static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3282 uint64_t Address, const void *Decoder) { 3283 DecodeStatus S = MCDisassembler::Success; 3284 3285 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3286 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3287 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3288 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3289 addr |= Rn << 9; 3290 unsigned load = fieldFromInstruction(Insn, 20, 1); 3291 3292 if (!load) { 3293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3294 return MCDisassembler::Fail; 3295 } 3296 3297 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3298 return MCDisassembler::Fail; 3299 3300 if (load) { 3301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3302 return MCDisassembler::Fail; 3303 } 3304 3305 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 3308 return S; 3309} 3310 3311static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3312 uint64_t Address, const void *Decoder) { 3313 DecodeStatus S = MCDisassembler::Success; 3314 3315 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3316 unsigned imm = fieldFromInstruction(Val, 0, 12); 3317 3318 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3319 return MCDisassembler::Fail; 3320 Inst.addOperand(MCOperand::CreateImm(imm)); 3321 3322 return S; 3323} 3324 3325 3326static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3327 uint64_t Address, const void *Decoder) { 3328 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3329 3330 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3331 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3332 Inst.addOperand(MCOperand::CreateImm(imm)); 3333 3334 return MCDisassembler::Success; 3335} 3336 3337static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3338 uint64_t Address, const void *Decoder) { 3339 DecodeStatus S = MCDisassembler::Success; 3340 3341 if (Inst.getOpcode() == ARM::tADDrSP) { 3342 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3343 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3344 3345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3346 return MCDisassembler::Fail; 3347 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3349 return MCDisassembler::Fail; 3350 } else if (Inst.getOpcode() == ARM::tADDspr) { 3351 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3352 3353 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3354 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3356 return MCDisassembler::Fail; 3357 } 3358 3359 return S; 3360} 3361 3362static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3363 uint64_t Address, const void *Decoder) { 3364 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3365 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3366 3367 Inst.addOperand(MCOperand::CreateImm(imod)); 3368 Inst.addOperand(MCOperand::CreateImm(flags)); 3369 3370 return MCDisassembler::Success; 3371} 3372 3373static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3374 uint64_t Address, const void *Decoder) { 3375 DecodeStatus S = MCDisassembler::Success; 3376 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3377 unsigned add = fieldFromInstruction(Insn, 4, 1); 3378 3379 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3380 return MCDisassembler::Fail; 3381 Inst.addOperand(MCOperand::CreateImm(add)); 3382 3383 return S; 3384} 3385 3386static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3387 uint64_t Address, const void *Decoder) { 3388 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3389 // Note only one trailing zero not two. Also the J1 and J2 values are from 3390 // the encoded instruction. So here change to I1 and I2 values via: 3391 // I1 = NOT(J1 EOR S); 3392 // I2 = NOT(J2 EOR S); 3393 // and build the imm32 with two trailing zeros as documented: 3394 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3395 unsigned S = (Val >> 23) & 1; 3396 unsigned J1 = (Val >> 22) & 1; 3397 unsigned J2 = (Val >> 21) & 1; 3398 unsigned I1 = !(J1 ^ S); 3399 unsigned I2 = !(J2 ^ S); 3400 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3401 int imm32 = SignExtend32<25>(tmp << 1); 3402 3403 if (!tryAddingSymbolicOperand(Address, 3404 (Address & ~2u) + imm32 + 4, 3405 true, 4, Inst, Decoder)) 3406 Inst.addOperand(MCOperand::CreateImm(imm32)); 3407 return MCDisassembler::Success; 3408} 3409 3410static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3411 uint64_t Address, const void *Decoder) { 3412 if (Val == 0xA || Val == 0xB) 3413 return MCDisassembler::Fail; 3414 3415 Inst.addOperand(MCOperand::CreateImm(Val)); 3416 return MCDisassembler::Success; 3417} 3418 3419static DecodeStatus 3420DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3421 uint64_t Address, const void *Decoder) { 3422 DecodeStatus S = MCDisassembler::Success; 3423 3424 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3425 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3426 3427 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3431 return MCDisassembler::Fail; 3432 return S; 3433} 3434 3435static DecodeStatus 3436DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3437 uint64_t Address, const void *Decoder) { 3438 DecodeStatus S = MCDisassembler::Success; 3439 3440 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3441 if (pred == 0xE || pred == 0xF) { 3442 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3443 switch (opc) { 3444 default: 3445 return MCDisassembler::Fail; 3446 case 0xf3bf8f4: 3447 Inst.setOpcode(ARM::t2DSB); 3448 break; 3449 case 0xf3bf8f5: 3450 Inst.setOpcode(ARM::t2DMB); 3451 break; 3452 case 0xf3bf8f6: 3453 Inst.setOpcode(ARM::t2ISB); 3454 break; 3455 } 3456 3457 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3458 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3459 } 3460 3461 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3462 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3463 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3464 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3465 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3466 3467 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3468 return MCDisassembler::Fail; 3469 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3470 return MCDisassembler::Fail; 3471 3472 return S; 3473} 3474 3475// Decode a shifted immediate operand. These basically consist 3476// of an 8-bit value, and a 4-bit directive that specifies either 3477// a splat operation or a rotation. 3478static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3479 uint64_t Address, const void *Decoder) { 3480 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3481 if (ctrl == 0) { 3482 unsigned byte = fieldFromInstruction(Val, 8, 2); 3483 unsigned imm = fieldFromInstruction(Val, 0, 8); 3484 switch (byte) { 3485 case 0: 3486 Inst.addOperand(MCOperand::CreateImm(imm)); 3487 break; 3488 case 1: 3489 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3490 break; 3491 case 2: 3492 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3493 break; 3494 case 3: 3495 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3496 (imm << 8) | imm)); 3497 break; 3498 } 3499 } else { 3500 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3501 unsigned rot = fieldFromInstruction(Val, 7, 5); 3502 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3503 Inst.addOperand(MCOperand::CreateImm(imm)); 3504 } 3505 3506 return MCDisassembler::Success; 3507} 3508 3509static DecodeStatus 3510DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3511 uint64_t Address, const void *Decoder){ 3512 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3513 true, 2, Inst, Decoder)) 3514 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3515 return MCDisassembler::Success; 3516} 3517 3518static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3519 uint64_t Address, const void *Decoder){ 3520 // Val is passed in as S:J1:J2:imm10:imm11 3521 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3522 // the encoded instruction. So here change to I1 and I2 values via: 3523 // I1 = NOT(J1 EOR S); 3524 // I2 = NOT(J2 EOR S); 3525 // and build the imm32 with one trailing zero as documented: 3526 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3527 unsigned S = (Val >> 23) & 1; 3528 unsigned J1 = (Val >> 22) & 1; 3529 unsigned J2 = (Val >> 21) & 1; 3530 unsigned I1 = !(J1 ^ S); 3531 unsigned I2 = !(J2 ^ S); 3532 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3533 int imm32 = SignExtend32<25>(tmp << 1); 3534 3535 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3536 true, 4, Inst, Decoder)) 3537 Inst.addOperand(MCOperand::CreateImm(imm32)); 3538 return MCDisassembler::Success; 3539} 3540 3541static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3542 uint64_t Address, const void *Decoder) { 3543 if (Val & ~0xf) 3544 return MCDisassembler::Fail; 3545 3546 Inst.addOperand(MCOperand::CreateImm(Val)); 3547 return MCDisassembler::Success; 3548} 3549 3550static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3551 uint64_t Address, const void *Decoder) { 3552 if (!Val) return MCDisassembler::Fail; 3553 Inst.addOperand(MCOperand::CreateImm(Val)); 3554 return MCDisassembler::Success; 3555} 3556 3557static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3558 uint64_t Address, const void *Decoder) { 3559 DecodeStatus S = MCDisassembler::Success; 3560 3561 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3562 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3563 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3564 3565 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3566 3567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3568 return MCDisassembler::Fail; 3569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3570 return MCDisassembler::Fail; 3571 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3572 return MCDisassembler::Fail; 3573 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3574 return MCDisassembler::Fail; 3575 3576 return S; 3577} 3578 3579 3580static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3581 uint64_t Address, const void *Decoder){ 3582 DecodeStatus S = MCDisassembler::Success; 3583 3584 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3585 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3586 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3587 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3588 3589 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3590 return MCDisassembler::Fail; 3591 3592 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3593 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3594 3595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3600 return MCDisassembler::Fail; 3601 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3602 return MCDisassembler::Fail; 3603 3604 return S; 3605} 3606 3607static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 3608 uint64_t Address, const void *Decoder) { 3609 DecodeStatus S = MCDisassembler::Success; 3610 3611 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3612 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3613 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3614 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3615 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3616 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3617 3618 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3619 3620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3621 return MCDisassembler::Fail; 3622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3623 return MCDisassembler::Fail; 3624 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3625 return MCDisassembler::Fail; 3626 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 3629 return S; 3630} 3631 3632static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 3633 uint64_t Address, const void *Decoder) { 3634 DecodeStatus S = MCDisassembler::Success; 3635 3636 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3637 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3638 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3639 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3640 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3641 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3642 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3643 3644 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3645 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3646 3647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3648 return MCDisassembler::Fail; 3649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3650 return MCDisassembler::Fail; 3651 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3652 return MCDisassembler::Fail; 3653 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3654 return MCDisassembler::Fail; 3655 3656 return S; 3657} 3658 3659 3660static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 3661 uint64_t Address, const void *Decoder) { 3662 DecodeStatus S = MCDisassembler::Success; 3663 3664 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3665 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3666 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3667 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3668 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3669 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3670 3671 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3672 3673 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3674 return MCDisassembler::Fail; 3675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3676 return MCDisassembler::Fail; 3677 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3678 return MCDisassembler::Fail; 3679 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 3682 return S; 3683} 3684 3685static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 3686 uint64_t Address, const void *Decoder) { 3687 DecodeStatus S = MCDisassembler::Success; 3688 3689 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3690 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3691 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3692 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 3693 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 3694 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3695 3696 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3697 3698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3699 return MCDisassembler::Fail; 3700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3701 return MCDisassembler::Fail; 3702 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3703 return MCDisassembler::Fail; 3704 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3705 return MCDisassembler::Fail; 3706 3707 return S; 3708} 3709 3710static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 3711 uint64_t Address, const void *Decoder) { 3712 DecodeStatus S = MCDisassembler::Success; 3713 3714 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3715 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3716 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3717 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3718 unsigned size = fieldFromInstruction(Insn, 10, 2); 3719 3720 unsigned align = 0; 3721 unsigned index = 0; 3722 switch (size) { 3723 default: 3724 return MCDisassembler::Fail; 3725 case 0: 3726 if (fieldFromInstruction(Insn, 4, 1)) 3727 return MCDisassembler::Fail; // UNDEFINED 3728 index = fieldFromInstruction(Insn, 5, 3); 3729 break; 3730 case 1: 3731 if (fieldFromInstruction(Insn, 5, 1)) 3732 return MCDisassembler::Fail; // UNDEFINED 3733 index = fieldFromInstruction(Insn, 6, 2); 3734 if (fieldFromInstruction(Insn, 4, 1)) 3735 align = 2; 3736 break; 3737 case 2: 3738 if (fieldFromInstruction(Insn, 6, 1)) 3739 return MCDisassembler::Fail; // UNDEFINED 3740 index = fieldFromInstruction(Insn, 7, 1); 3741 3742 switch (fieldFromInstruction(Insn, 4, 2)) { 3743 case 0 : 3744 align = 0; break; 3745 case 3: 3746 align = 4; break; 3747 default: 3748 return MCDisassembler::Fail; 3749 } 3750 break; 3751 } 3752 3753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3754 return MCDisassembler::Fail; 3755 if (Rm != 0xF) { // Writeback 3756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3757 return MCDisassembler::Fail; 3758 } 3759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 Inst.addOperand(MCOperand::CreateImm(align)); 3762 if (Rm != 0xF) { 3763 if (Rm != 0xD) { 3764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3765 return MCDisassembler::Fail; 3766 } else 3767 Inst.addOperand(MCOperand::CreateReg(0)); 3768 } 3769 3770 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3771 return MCDisassembler::Fail; 3772 Inst.addOperand(MCOperand::CreateImm(index)); 3773 3774 return S; 3775} 3776 3777static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 3778 uint64_t Address, const void *Decoder) { 3779 DecodeStatus S = MCDisassembler::Success; 3780 3781 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3782 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3783 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3784 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3785 unsigned size = fieldFromInstruction(Insn, 10, 2); 3786 3787 unsigned align = 0; 3788 unsigned index = 0; 3789 switch (size) { 3790 default: 3791 return MCDisassembler::Fail; 3792 case 0: 3793 if (fieldFromInstruction(Insn, 4, 1)) 3794 return MCDisassembler::Fail; // UNDEFINED 3795 index = fieldFromInstruction(Insn, 5, 3); 3796 break; 3797 case 1: 3798 if (fieldFromInstruction(Insn, 5, 1)) 3799 return MCDisassembler::Fail; // UNDEFINED 3800 index = fieldFromInstruction(Insn, 6, 2); 3801 if (fieldFromInstruction(Insn, 4, 1)) 3802 align = 2; 3803 break; 3804 case 2: 3805 if (fieldFromInstruction(Insn, 6, 1)) 3806 return MCDisassembler::Fail; // UNDEFINED 3807 index = fieldFromInstruction(Insn, 7, 1); 3808 3809 switch (fieldFromInstruction(Insn, 4, 2)) { 3810 case 0: 3811 align = 0; break; 3812 case 3: 3813 align = 4; break; 3814 default: 3815 return MCDisassembler::Fail; 3816 } 3817 break; 3818 } 3819 3820 if (Rm != 0xF) { // Writeback 3821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3822 return MCDisassembler::Fail; 3823 } 3824 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3825 return MCDisassembler::Fail; 3826 Inst.addOperand(MCOperand::CreateImm(align)); 3827 if (Rm != 0xF) { 3828 if (Rm != 0xD) { 3829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3830 return MCDisassembler::Fail; 3831 } else 3832 Inst.addOperand(MCOperand::CreateReg(0)); 3833 } 3834 3835 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3836 return MCDisassembler::Fail; 3837 Inst.addOperand(MCOperand::CreateImm(index)); 3838 3839 return S; 3840} 3841 3842 3843static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 3844 uint64_t Address, const void *Decoder) { 3845 DecodeStatus S = MCDisassembler::Success; 3846 3847 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3848 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3849 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3850 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3851 unsigned size = fieldFromInstruction(Insn, 10, 2); 3852 3853 unsigned align = 0; 3854 unsigned index = 0; 3855 unsigned inc = 1; 3856 switch (size) { 3857 default: 3858 return MCDisassembler::Fail; 3859 case 0: 3860 index = fieldFromInstruction(Insn, 5, 3); 3861 if (fieldFromInstruction(Insn, 4, 1)) 3862 align = 2; 3863 break; 3864 case 1: 3865 index = fieldFromInstruction(Insn, 6, 2); 3866 if (fieldFromInstruction(Insn, 4, 1)) 3867 align = 4; 3868 if (fieldFromInstruction(Insn, 5, 1)) 3869 inc = 2; 3870 break; 3871 case 2: 3872 if (fieldFromInstruction(Insn, 5, 1)) 3873 return MCDisassembler::Fail; // UNDEFINED 3874 index = fieldFromInstruction(Insn, 7, 1); 3875 if (fieldFromInstruction(Insn, 4, 1) != 0) 3876 align = 8; 3877 if (fieldFromInstruction(Insn, 6, 1)) 3878 inc = 2; 3879 break; 3880 } 3881 3882 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3883 return MCDisassembler::Fail; 3884 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3885 return MCDisassembler::Fail; 3886 if (Rm != 0xF) { // Writeback 3887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3888 return MCDisassembler::Fail; 3889 } 3890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3891 return MCDisassembler::Fail; 3892 Inst.addOperand(MCOperand::CreateImm(align)); 3893 if (Rm != 0xF) { 3894 if (Rm != 0xD) { 3895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3896 return MCDisassembler::Fail; 3897 } else 3898 Inst.addOperand(MCOperand::CreateReg(0)); 3899 } 3900 3901 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3902 return MCDisassembler::Fail; 3903 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3904 return MCDisassembler::Fail; 3905 Inst.addOperand(MCOperand::CreateImm(index)); 3906 3907 return S; 3908} 3909 3910static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 3911 uint64_t Address, const void *Decoder) { 3912 DecodeStatus S = MCDisassembler::Success; 3913 3914 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3915 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3916 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3917 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3918 unsigned size = fieldFromInstruction(Insn, 10, 2); 3919 3920 unsigned align = 0; 3921 unsigned index = 0; 3922 unsigned inc = 1; 3923 switch (size) { 3924 default: 3925 return MCDisassembler::Fail; 3926 case 0: 3927 index = fieldFromInstruction(Insn, 5, 3); 3928 if (fieldFromInstruction(Insn, 4, 1)) 3929 align = 2; 3930 break; 3931 case 1: 3932 index = fieldFromInstruction(Insn, 6, 2); 3933 if (fieldFromInstruction(Insn, 4, 1)) 3934 align = 4; 3935 if (fieldFromInstruction(Insn, 5, 1)) 3936 inc = 2; 3937 break; 3938 case 2: 3939 if (fieldFromInstruction(Insn, 5, 1)) 3940 return MCDisassembler::Fail; // UNDEFINED 3941 index = fieldFromInstruction(Insn, 7, 1); 3942 if (fieldFromInstruction(Insn, 4, 1) != 0) 3943 align = 8; 3944 if (fieldFromInstruction(Insn, 6, 1)) 3945 inc = 2; 3946 break; 3947 } 3948 3949 if (Rm != 0xF) { // Writeback 3950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3951 return MCDisassembler::Fail; 3952 } 3953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3954 return MCDisassembler::Fail; 3955 Inst.addOperand(MCOperand::CreateImm(align)); 3956 if (Rm != 0xF) { 3957 if (Rm != 0xD) { 3958 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3959 return MCDisassembler::Fail; 3960 } else 3961 Inst.addOperand(MCOperand::CreateReg(0)); 3962 } 3963 3964 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3965 return MCDisassembler::Fail; 3966 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3967 return MCDisassembler::Fail; 3968 Inst.addOperand(MCOperand::CreateImm(index)); 3969 3970 return S; 3971} 3972 3973 3974static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 3975 uint64_t Address, const void *Decoder) { 3976 DecodeStatus S = MCDisassembler::Success; 3977 3978 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3979 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3980 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3981 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3982 unsigned size = fieldFromInstruction(Insn, 10, 2); 3983 3984 unsigned align = 0; 3985 unsigned index = 0; 3986 unsigned inc = 1; 3987 switch (size) { 3988 default: 3989 return MCDisassembler::Fail; 3990 case 0: 3991 if (fieldFromInstruction(Insn, 4, 1)) 3992 return MCDisassembler::Fail; // UNDEFINED 3993 index = fieldFromInstruction(Insn, 5, 3); 3994 break; 3995 case 1: 3996 if (fieldFromInstruction(Insn, 4, 1)) 3997 return MCDisassembler::Fail; // UNDEFINED 3998 index = fieldFromInstruction(Insn, 6, 2); 3999 if (fieldFromInstruction(Insn, 5, 1)) 4000 inc = 2; 4001 break; 4002 case 2: 4003 if (fieldFromInstruction(Insn, 4, 2)) 4004 return MCDisassembler::Fail; // UNDEFINED 4005 index = fieldFromInstruction(Insn, 7, 1); 4006 if (fieldFromInstruction(Insn, 6, 1)) 4007 inc = 2; 4008 break; 4009 } 4010 4011 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4014 return MCDisassembler::Fail; 4015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4016 return MCDisassembler::Fail; 4017 4018 if (Rm != 0xF) { // Writeback 4019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 } 4022 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 Inst.addOperand(MCOperand::CreateImm(align)); 4025 if (Rm != 0xF) { 4026 if (Rm != 0xD) { 4027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4028 return MCDisassembler::Fail; 4029 } else 4030 Inst.addOperand(MCOperand::CreateReg(0)); 4031 } 4032 4033 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4034 return MCDisassembler::Fail; 4035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4036 return MCDisassembler::Fail; 4037 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4038 return MCDisassembler::Fail; 4039 Inst.addOperand(MCOperand::CreateImm(index)); 4040 4041 return S; 4042} 4043 4044static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4045 uint64_t Address, const void *Decoder) { 4046 DecodeStatus S = MCDisassembler::Success; 4047 4048 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4049 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4050 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4051 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4052 unsigned size = fieldFromInstruction(Insn, 10, 2); 4053 4054 unsigned align = 0; 4055 unsigned index = 0; 4056 unsigned inc = 1; 4057 switch (size) { 4058 default: 4059 return MCDisassembler::Fail; 4060 case 0: 4061 if (fieldFromInstruction(Insn, 4, 1)) 4062 return MCDisassembler::Fail; // UNDEFINED 4063 index = fieldFromInstruction(Insn, 5, 3); 4064 break; 4065 case 1: 4066 if (fieldFromInstruction(Insn, 4, 1)) 4067 return MCDisassembler::Fail; // UNDEFINED 4068 index = fieldFromInstruction(Insn, 6, 2); 4069 if (fieldFromInstruction(Insn, 5, 1)) 4070 inc = 2; 4071 break; 4072 case 2: 4073 if (fieldFromInstruction(Insn, 4, 2)) 4074 return MCDisassembler::Fail; // UNDEFINED 4075 index = fieldFromInstruction(Insn, 7, 1); 4076 if (fieldFromInstruction(Insn, 6, 1)) 4077 inc = 2; 4078 break; 4079 } 4080 4081 if (Rm != 0xF) { // Writeback 4082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4083 return MCDisassembler::Fail; 4084 } 4085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4086 return MCDisassembler::Fail; 4087 Inst.addOperand(MCOperand::CreateImm(align)); 4088 if (Rm != 0xF) { 4089 if (Rm != 0xD) { 4090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4091 return MCDisassembler::Fail; 4092 } else 4093 Inst.addOperand(MCOperand::CreateReg(0)); 4094 } 4095 4096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4097 return MCDisassembler::Fail; 4098 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4099 return MCDisassembler::Fail; 4100 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4101 return MCDisassembler::Fail; 4102 Inst.addOperand(MCOperand::CreateImm(index)); 4103 4104 return S; 4105} 4106 4107 4108static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4109 uint64_t Address, const void *Decoder) { 4110 DecodeStatus S = MCDisassembler::Success; 4111 4112 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4113 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4114 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4115 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4116 unsigned size = fieldFromInstruction(Insn, 10, 2); 4117 4118 unsigned align = 0; 4119 unsigned index = 0; 4120 unsigned inc = 1; 4121 switch (size) { 4122 default: 4123 return MCDisassembler::Fail; 4124 case 0: 4125 if (fieldFromInstruction(Insn, 4, 1)) 4126 align = 4; 4127 index = fieldFromInstruction(Insn, 5, 3); 4128 break; 4129 case 1: 4130 if (fieldFromInstruction(Insn, 4, 1)) 4131 align = 8; 4132 index = fieldFromInstruction(Insn, 6, 2); 4133 if (fieldFromInstruction(Insn, 5, 1)) 4134 inc = 2; 4135 break; 4136 case 2: 4137 switch (fieldFromInstruction(Insn, 4, 2)) { 4138 case 0: 4139 align = 0; break; 4140 case 3: 4141 return MCDisassembler::Fail; 4142 default: 4143 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4144 } 4145 4146 index = fieldFromInstruction(Insn, 7, 1); 4147 if (fieldFromInstruction(Insn, 6, 1)) 4148 inc = 2; 4149 break; 4150 } 4151 4152 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4153 return MCDisassembler::Fail; 4154 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4155 return MCDisassembler::Fail; 4156 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4157 return MCDisassembler::Fail; 4158 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4159 return MCDisassembler::Fail; 4160 4161 if (Rm != 0xF) { // Writeback 4162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4163 return MCDisassembler::Fail; 4164 } 4165 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4166 return MCDisassembler::Fail; 4167 Inst.addOperand(MCOperand::CreateImm(align)); 4168 if (Rm != 0xF) { 4169 if (Rm != 0xD) { 4170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4171 return MCDisassembler::Fail; 4172 } else 4173 Inst.addOperand(MCOperand::CreateReg(0)); 4174 } 4175 4176 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4177 return MCDisassembler::Fail; 4178 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4179 return MCDisassembler::Fail; 4180 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4181 return MCDisassembler::Fail; 4182 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4183 return MCDisassembler::Fail; 4184 Inst.addOperand(MCOperand::CreateImm(index)); 4185 4186 return S; 4187} 4188 4189static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4190 uint64_t Address, const void *Decoder) { 4191 DecodeStatus S = MCDisassembler::Success; 4192 4193 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4194 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4195 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4196 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4197 unsigned size = fieldFromInstruction(Insn, 10, 2); 4198 4199 unsigned align = 0; 4200 unsigned index = 0; 4201 unsigned inc = 1; 4202 switch (size) { 4203 default: 4204 return MCDisassembler::Fail; 4205 case 0: 4206 if (fieldFromInstruction(Insn, 4, 1)) 4207 align = 4; 4208 index = fieldFromInstruction(Insn, 5, 3); 4209 break; 4210 case 1: 4211 if (fieldFromInstruction(Insn, 4, 1)) 4212 align = 8; 4213 index = fieldFromInstruction(Insn, 6, 2); 4214 if (fieldFromInstruction(Insn, 5, 1)) 4215 inc = 2; 4216 break; 4217 case 2: 4218 switch (fieldFromInstruction(Insn, 4, 2)) { 4219 case 0: 4220 align = 0; break; 4221 case 3: 4222 return MCDisassembler::Fail; 4223 default: 4224 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4225 } 4226 4227 index = fieldFromInstruction(Insn, 7, 1); 4228 if (fieldFromInstruction(Insn, 6, 1)) 4229 inc = 2; 4230 break; 4231 } 4232 4233 if (Rm != 0xF) { // Writeback 4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 } 4237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4238 return MCDisassembler::Fail; 4239 Inst.addOperand(MCOperand::CreateImm(align)); 4240 if (Rm != 0xF) { 4241 if (Rm != 0xD) { 4242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4243 return MCDisassembler::Fail; 4244 } else 4245 Inst.addOperand(MCOperand::CreateReg(0)); 4246 } 4247 4248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4249 return MCDisassembler::Fail; 4250 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4251 return MCDisassembler::Fail; 4252 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4253 return MCDisassembler::Fail; 4254 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4255 return MCDisassembler::Fail; 4256 Inst.addOperand(MCOperand::CreateImm(index)); 4257 4258 return S; 4259} 4260 4261static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4262 uint64_t Address, const void *Decoder) { 4263 DecodeStatus S = MCDisassembler::Success; 4264 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4265 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4266 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4267 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4268 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4269 4270 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4271 S = MCDisassembler::SoftFail; 4272 4273 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4274 return MCDisassembler::Fail; 4275 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4276 return MCDisassembler::Fail; 4277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4278 return MCDisassembler::Fail; 4279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4280 return MCDisassembler::Fail; 4281 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4282 return MCDisassembler::Fail; 4283 4284 return S; 4285} 4286 4287static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4288 uint64_t Address, const void *Decoder) { 4289 DecodeStatus S = MCDisassembler::Success; 4290 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4291 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4292 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4293 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4294 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4295 4296 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4297 S = MCDisassembler::SoftFail; 4298 4299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4302 return MCDisassembler::Fail; 4303 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4306 return MCDisassembler::Fail; 4307 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4308 return MCDisassembler::Fail; 4309 4310 return S; 4311} 4312 4313static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4314 uint64_t Address, const void *Decoder) { 4315 DecodeStatus S = MCDisassembler::Success; 4316 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4317 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4318 4319 if (pred == 0xF) { 4320 pred = 0xE; 4321 S = MCDisassembler::SoftFail; 4322 } 4323 4324 if (mask == 0x0) { 4325 mask |= 0x8; 4326 S = MCDisassembler::SoftFail; 4327 } 4328 4329 Inst.addOperand(MCOperand::CreateImm(pred)); 4330 Inst.addOperand(MCOperand::CreateImm(mask)); 4331 return S; 4332} 4333 4334static DecodeStatus 4335DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4336 uint64_t Address, const void *Decoder) { 4337 DecodeStatus S = MCDisassembler::Success; 4338 4339 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4340 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4341 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4342 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4343 unsigned W = fieldFromInstruction(Insn, 21, 1); 4344 unsigned U = fieldFromInstruction(Insn, 23, 1); 4345 unsigned P = fieldFromInstruction(Insn, 24, 1); 4346 bool writeback = (W == 1) | (P == 0); 4347 4348 addr |= (U << 8) | (Rn << 9); 4349 4350 if (writeback && (Rn == Rt || Rn == Rt2)) 4351 Check(S, MCDisassembler::SoftFail); 4352 if (Rt == Rt2) 4353 Check(S, MCDisassembler::SoftFail); 4354 4355 // Rt 4356 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4357 return MCDisassembler::Fail; 4358 // Rt2 4359 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4360 return MCDisassembler::Fail; 4361 // Writeback operand 4362 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 // addr 4365 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 4368 return S; 4369} 4370 4371static DecodeStatus 4372DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4373 uint64_t Address, const void *Decoder) { 4374 DecodeStatus S = MCDisassembler::Success; 4375 4376 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4377 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4378 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4379 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4380 unsigned W = fieldFromInstruction(Insn, 21, 1); 4381 unsigned U = fieldFromInstruction(Insn, 23, 1); 4382 unsigned P = fieldFromInstruction(Insn, 24, 1); 4383 bool writeback = (W == 1) | (P == 0); 4384 4385 addr |= (U << 8) | (Rn << 9); 4386 4387 if (writeback && (Rn == Rt || Rn == Rt2)) 4388 Check(S, MCDisassembler::SoftFail); 4389 4390 // Writeback operand 4391 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4392 return MCDisassembler::Fail; 4393 // Rt 4394 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4395 return MCDisassembler::Fail; 4396 // Rt2 4397 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4398 return MCDisassembler::Fail; 4399 // addr 4400 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4401 return MCDisassembler::Fail; 4402 4403 return S; 4404} 4405 4406static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4407 uint64_t Address, const void *Decoder) { 4408 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4409 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4410 if (sign1 != sign2) return MCDisassembler::Fail; 4411 4412 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4413 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4414 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4415 Val |= sign1 << 12; 4416 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4417 4418 return MCDisassembler::Success; 4419} 4420 4421static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4422 uint64_t Address, 4423 const void *Decoder) { 4424 DecodeStatus S = MCDisassembler::Success; 4425 4426 // Shift of "asr #32" is not allowed in Thumb2 mode. 4427 if (Val == 0x20) S = MCDisassembler::SoftFail; 4428 Inst.addOperand(MCOperand::CreateImm(Val)); 4429 return S; 4430} 4431 4432static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4433 uint64_t Address, const void *Decoder) { 4434 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4435 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4436 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4437 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4438 4439 if (pred == 0xF) 4440 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4441 4442 DecodeStatus S = MCDisassembler::Success; 4443 4444 if (Rt == Rn || Rn == Rt2) 4445 S = MCDisassembler::SoftFail; 4446 4447 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4448 return MCDisassembler::Fail; 4449 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4450 return MCDisassembler::Fail; 4451 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4452 return MCDisassembler::Fail; 4453 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4454 return MCDisassembler::Fail; 4455 4456 return S; 4457} 4458 4459static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4460 uint64_t Address, const void *Decoder) { 4461 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4462 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4463 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4464 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4465 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4466 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4467 4468 DecodeStatus S = MCDisassembler::Success; 4469 4470 // VMOVv2f32 is ambiguous with these decodings. 4471 if (!(imm & 0x38) && cmode == 0xF) { 4472 Inst.setOpcode(ARM::VMOVv2f32); 4473 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4474 } 4475 4476 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4477 4478 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4479 return MCDisassembler::Fail; 4480 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4481 return MCDisassembler::Fail; 4482 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4483 4484 return S; 4485} 4486 4487static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4488 uint64_t Address, const void *Decoder) { 4489 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4490 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4491 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4492 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4493 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4494 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4495 4496 DecodeStatus S = MCDisassembler::Success; 4497 4498 // VMOVv4f32 is ambiguous with these decodings. 4499 if (!(imm & 0x38) && cmode == 0xF) { 4500 Inst.setOpcode(ARM::VMOVv4f32); 4501 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4502 } 4503 4504 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4505 4506 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4507 return MCDisassembler::Fail; 4508 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4509 return MCDisassembler::Fail; 4510 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4511 4512 return S; 4513} 4514 4515static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4516 uint64_t Address, const void *Decoder) { 4517 DecodeStatus S = MCDisassembler::Success; 4518 4519 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4520 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4521 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4522 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4523 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4524 4525 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4526 S = MCDisassembler::SoftFail; 4527 4528 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4529 return MCDisassembler::Fail; 4530 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4531 return MCDisassembler::Fail; 4532 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4533 return MCDisassembler::Fail; 4534 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4535 return MCDisassembler::Fail; 4536 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4537 return MCDisassembler::Fail; 4538 4539 return S; 4540} 4541 4542static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4543 uint64_t Address, const void *Decoder) { 4544 4545 DecodeStatus S = MCDisassembler::Success; 4546 4547 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4548 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4549 unsigned cop = fieldFromInstruction(Val, 8, 4); 4550 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4551 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4552 4553 if ((cop & ~0x1) == 0xa) 4554 return MCDisassembler::Fail; 4555 4556 if (Rt == Rt2) 4557 S = MCDisassembler::SoftFail; 4558 4559 Inst.addOperand(MCOperand::CreateImm(cop)); 4560 Inst.addOperand(MCOperand::CreateImm(opc1)); 4561 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4562 return MCDisassembler::Fail; 4563 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4564 return MCDisassembler::Fail; 4565 Inst.addOperand(MCOperand::CreateImm(CRm)); 4566 4567 return S; 4568} 4569 4570