ARMDisassembler.cpp revision d2fc31b3f75700dc89305cb161f3bca7f1a39bef
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "ARM.h" 13#include "ARMRegisterInfo.h" 14#include "ARMSubtarget.h" 15#include "MCTargetDesc/ARMAddressingModes.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "llvm/MC/EDInstInfo.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCContext.h" 21#include "llvm/MC/MCDisassembler.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/MemoryObject.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/TargetRegistry.h" 26#include "llvm/Support/raw_ostream.h" 27 28using namespace llvm; 29 30typedef MCDisassembler::DecodeStatus DecodeStatus; 31 32namespace { 33/// ARMDisassembler - ARM disassembler for all ARM platforms. 34class ARMDisassembler : public MCDisassembler { 35public: 36 /// Constructor - Initializes the disassembler. 37 /// 38 ARMDisassembler(const MCSubtargetInfo &STI) : 39 MCDisassembler(STI) { 40 } 41 42 ~ARMDisassembler() { 43 } 44 45 /// getInstruction - See MCDisassembler. 46 DecodeStatus getInstruction(MCInst &instr, 47 uint64_t &size, 48 const MemoryObject ®ion, 49 uint64_t address, 50 raw_ostream &vStream) const; 51 52 /// getEDInfo - See MCDisassembler. 53 EDInstInfo *getEDInfo() const; 54private: 55}; 56 57/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 58class ThumbDisassembler : public MCDisassembler { 59public: 60 /// Constructor - Initializes the disassembler. 61 /// 62 ThumbDisassembler(const MCSubtargetInfo &STI) : 63 MCDisassembler(STI) { 64 } 65 66 ~ThumbDisassembler() { 67 } 68 69 /// getInstruction - See MCDisassembler. 70 DecodeStatus getInstruction(MCInst &instr, 71 uint64_t &size, 72 const MemoryObject ®ion, 73 uint64_t address, 74 raw_ostream &vStream) const; 75 76 /// getEDInfo - See MCDisassembler. 77 EDInstInfo *getEDInfo() const; 78private: 79 mutable std::vector<unsigned> ITBlock; 80 DecodeStatus AddThumbPredicate(MCInst&) const; 81 void UpdateThumbVFPPredicate(MCInst&) const; 82}; 83} 84 85static bool Check(DecodeStatus &Out, DecodeStatus In) { 86 switch (In) { 87 case MCDisassembler::Success: 88 // Out stays the same. 89 return true; 90 case MCDisassembler::SoftFail: 91 Out = In; 92 return true; 93 case MCDisassembler::Fail: 94 Out = In; 95 return false; 96 } 97 return false; 98} 99 100 101// Forward declare these because the autogenerated code will reference them. 102// Definitions are further down. 103static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 104 uint64_t Address, const void *Decoder); 105static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 106 unsigned RegNo, uint64_t Address, 107 const void *Decoder); 108static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 109 uint64_t Address, const void *Decoder); 110static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 111 uint64_t Address, const void *Decoder); 112static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 113 uint64_t Address, const void *Decoder); 114static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, const void *Decoder); 116static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 117 uint64_t Address, const void *Decoder); 118static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 119 uint64_t Address, const void *Decoder); 120static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 121 unsigned RegNo, 122 uint64_t Address, 123 const void *Decoder); 124static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 125 uint64_t Address, const void *Decoder); 126 127static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 128 uint64_t Address, const void *Decoder); 129static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 138 uint64_t Address, const void *Decoder); 139 140static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 145 unsigned Insn, 146 uint64_t Address, 147 const void *Decoder); 148static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 151 uint64_t Address, const void *Decoder); 152static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 157static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 158 unsigned Insn, 159 uint64_t Adddress, 160 const void *Decoder); 161static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 166 uint64_t Address, const void *Decoder); 167static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 168 uint64_t Address, const void *Decoder); 169static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 172 uint64_t Address, const void *Decoder); 173static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 174 uint64_t Address, const void *Decoder); 175static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 192 uint64_t Address, const void *Decoder); 193static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 240 uint64_t Address, const void *Decoder); 241static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 242 uint64_t Address, const void *Decoder); 243static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 248static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 249 uint64_t Address, const void *Decoder); 250static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 277 uint64_t Address, const void *Decoder); 278static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 279 uint64_t Address, const void *Decoder); 280static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 281 uint64_t Address, const void *Decoder); 282static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 291 uint64_t Address, const void *Decoder); 292static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 297 uint64_t Address, const void *Decoder); 298static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 301#include "ARMGenDisassemblerTables.inc" 302#include "ARMGenInstrInfo.inc" 303#include "ARMGenEDInfo.inc" 304 305static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 306 return new ARMDisassembler(STI); 307} 308 309static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 310 return new ThumbDisassembler(STI); 311} 312 313EDInstInfo *ARMDisassembler::getEDInfo() const { 314 return instInfoARM; 315} 316 317EDInstInfo *ThumbDisassembler::getEDInfo() const { 318 return instInfoARM; 319} 320 321DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 322 const MemoryObject &Region, 323 uint64_t Address, 324 raw_ostream &os) const { 325 uint8_t bytes[4]; 326 327 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 328 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 329 330 // We want to read exactly 4 bytes of data. 331 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 332 Size = 0; 333 return MCDisassembler::Fail; 334 } 335 336 // Encoded as a small-endian 32-bit word in the stream. 337 uint32_t insn = (bytes[3] << 24) | 338 (bytes[2] << 16) | 339 (bytes[1] << 8) | 340 (bytes[0] << 0); 341 342 // Calling the auto-generated decoder function. 343 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 344 if (result != MCDisassembler::Fail) { 345 Size = 4; 346 return result; 347 } 348 349 // VFP and NEON instructions, similarly, are shared between ARM 350 // and Thumb modes. 351 MI.clear(); 352 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 353 if (result != MCDisassembler::Fail) { 354 Size = 4; 355 return result; 356 } 357 358 MI.clear(); 359 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 360 if (result != MCDisassembler::Fail) { 361 Size = 4; 362 // Add a fake predicate operand, because we share these instruction 363 // definitions with Thumb2 where these instructions are predicable. 364 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 365 return MCDisassembler::Fail; 366 return result; 367 } 368 369 MI.clear(); 370 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 371 if (result != MCDisassembler::Fail) { 372 Size = 4; 373 // Add a fake predicate operand, because we share these instruction 374 // definitions with Thumb2 where these instructions are predicable. 375 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 376 return MCDisassembler::Fail; 377 return result; 378 } 379 380 MI.clear(); 381 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 382 if (result != MCDisassembler::Fail) { 383 Size = 4; 384 // Add a fake predicate operand, because we share these instruction 385 // definitions with Thumb2 where these instructions are predicable. 386 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 387 return MCDisassembler::Fail; 388 return result; 389 } 390 391 MI.clear(); 392 393 Size = 0; 394 return MCDisassembler::Fail; 395} 396 397namespace llvm { 398extern MCInstrDesc ARMInsts[]; 399} 400 401// Thumb1 instructions don't have explicit S bits. Rather, they 402// implicitly set CPSR. Since it's not represented in the encoding, the 403// auto-generated decoder won't inject the CPSR operand. We need to fix 404// that as a post-pass. 405static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 406 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 407 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 408 MCInst::iterator I = MI.begin(); 409 for (unsigned i = 0; i < NumOps; ++i, ++I) { 410 if (I == MI.end()) break; 411 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 412 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 413 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 414 return; 415 } 416 } 417 418 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 419} 420 421// Most Thumb instructions don't have explicit predicates in the 422// encoding, but rather get their predicates from IT context. We need 423// to fix up the predicate operands using this context information as a 424// post-pass. 425MCDisassembler::DecodeStatus 426ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 427 // A few instructions actually have predicates encoded in them. Don't 428 // try to overwrite it if we're seeing one of those. 429 switch (MI.getOpcode()) { 430 case ARM::tBcc: 431 case ARM::t2Bcc: 432 return Success; 433 case ARM::tCBZ: 434 case ARM::tCBNZ: 435 // Some instructions are not allowed in IT blocks. 436 if (!ITBlock.empty()) 437 return SoftFail; 438 break; 439 default: 440 break; 441 } 442 443 // If we're in an IT block, base the predicate on that. Otherwise, 444 // assume a predicate of AL. 445 unsigned CC; 446 if (!ITBlock.empty()) { 447 CC = ITBlock.back(); 448 if (CC == 0xF) 449 CC = ARMCC::AL; 450 ITBlock.pop_back(); 451 } else 452 CC = ARMCC::AL; 453 454 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 455 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 456 MCInst::iterator I = MI.begin(); 457 for (unsigned i = 0; i < NumOps; ++i, ++I) { 458 if (I == MI.end()) break; 459 if (OpInfo[i].isPredicate()) { 460 I = MI.insert(I, MCOperand::CreateImm(CC)); 461 ++I; 462 if (CC == ARMCC::AL) 463 MI.insert(I, MCOperand::CreateReg(0)); 464 else 465 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 466 return Success; 467 } 468 } 469 470 I = MI.insert(I, MCOperand::CreateImm(CC)); 471 ++I; 472 if (CC == ARMCC::AL) 473 MI.insert(I, MCOperand::CreateReg(0)); 474 else 475 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 476 477 return Success; 478} 479 480// Thumb VFP instructions are a special case. Because we share their 481// encodings between ARM and Thumb modes, and they are predicable in ARM 482// mode, the auto-generated decoder will give them an (incorrect) 483// predicate operand. We need to rewrite these operands based on the IT 484// context as a post-pass. 485void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 486 unsigned CC; 487 if (!ITBlock.empty()) { 488 CC = ITBlock.back(); 489 ITBlock.pop_back(); 490 } else 491 CC = ARMCC::AL; 492 493 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 494 MCInst::iterator I = MI.begin(); 495 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 496 for (unsigned i = 0; i < NumOps; ++i, ++I) { 497 if (OpInfo[i].isPredicate() ) { 498 I->setImm(CC); 499 ++I; 500 if (CC == ARMCC::AL) 501 I->setReg(0); 502 else 503 I->setReg(ARM::CPSR); 504 return; 505 } 506 } 507} 508 509DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 510 const MemoryObject &Region, 511 uint64_t Address, 512 raw_ostream &os) const { 513 uint8_t bytes[4]; 514 515 assert((STI.getFeatureBits() & ARM::ModeThumb) && 516 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 517 518 // We want to read exactly 2 bytes of data. 519 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 520 Size = 0; 521 return MCDisassembler::Fail; 522 } 523 524 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 525 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 526 if (result != MCDisassembler::Fail) { 527 Size = 2; 528 Check(result, AddThumbPredicate(MI)); 529 return result; 530 } 531 532 MI.clear(); 533 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 534 if (result) { 535 Size = 2; 536 bool InITBlock = !ITBlock.empty(); 537 Check(result, AddThumbPredicate(MI)); 538 AddThumb1SBit(MI, InITBlock); 539 return result; 540 } 541 542 MI.clear(); 543 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 544 if (result != MCDisassembler::Fail) { 545 Size = 2; 546 Check(result, AddThumbPredicate(MI)); 547 548 // If we find an IT instruction, we need to parse its condition 549 // code and mask operands so that we can apply them correctly 550 // to the subsequent instructions. 551 if (MI.getOpcode() == ARM::t2IT) { 552 // (3 - the number of trailing zeros) is the number of then / else. 553 unsigned firstcond = MI.getOperand(0).getImm(); 554 unsigned Mask = MI.getOperand(1).getImm(); 555 unsigned CondBit0 = Mask >> 4 & 1; 556 unsigned NumTZ = CountTrailingZeros_32(Mask); 557 assert(NumTZ <= 3 && "Invalid IT mask!"); 558 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 559 bool T = ((Mask >> Pos) & 1) == CondBit0; 560 if (T) 561 ITBlock.insert(ITBlock.begin(), firstcond); 562 else 563 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 564 } 565 566 ITBlock.push_back(firstcond); 567 } 568 569 return result; 570 } 571 572 // We want to read exactly 4 bytes of data. 573 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 574 Size = 0; 575 return MCDisassembler::Fail; 576 } 577 578 uint32_t insn32 = (bytes[3] << 8) | 579 (bytes[2] << 0) | 580 (bytes[1] << 24) | 581 (bytes[0] << 16); 582 MI.clear(); 583 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 584 if (result != MCDisassembler::Fail) { 585 Size = 4; 586 bool InITBlock = ITBlock.size(); 587 Check(result, AddThumbPredicate(MI)); 588 AddThumb1SBit(MI, InITBlock); 589 return result; 590 } 591 592 MI.clear(); 593 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 594 if (result != MCDisassembler::Fail) { 595 Size = 4; 596 Check(result, AddThumbPredicate(MI)); 597 return result; 598 } 599 600 MI.clear(); 601 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 602 if (result != MCDisassembler::Fail) { 603 Size = 4; 604 UpdateThumbVFPPredicate(MI); 605 return result; 606 } 607 608 MI.clear(); 609 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 610 if (result != MCDisassembler::Fail) { 611 Size = 4; 612 Check(result, AddThumbPredicate(MI)); 613 return result; 614 } 615 616 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 617 MI.clear(); 618 uint32_t NEONLdStInsn = insn32; 619 NEONLdStInsn &= 0xF0FFFFFF; 620 NEONLdStInsn |= 0x04000000; 621 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 622 if (result != MCDisassembler::Fail) { 623 Size = 4; 624 Check(result, AddThumbPredicate(MI)); 625 return result; 626 } 627 } 628 629 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 630 MI.clear(); 631 uint32_t NEONDataInsn = insn32; 632 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 633 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 634 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 635 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 636 if (result != MCDisassembler::Fail) { 637 Size = 4; 638 Check(result, AddThumbPredicate(MI)); 639 return result; 640 } 641 } 642 643 Size = 0; 644 return MCDisassembler::Fail; 645} 646 647 648extern "C" void LLVMInitializeARMDisassembler() { 649 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 650 createARMDisassembler); 651 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 652 createThumbDisassembler); 653} 654 655static const unsigned GPRDecoderTable[] = { 656 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 657 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 658 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 659 ARM::R12, ARM::SP, ARM::LR, ARM::PC 660}; 661 662static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 663 uint64_t Address, const void *Decoder) { 664 if (RegNo > 15) 665 return MCDisassembler::Fail; 666 667 unsigned Register = GPRDecoderTable[RegNo]; 668 Inst.addOperand(MCOperand::CreateReg(Register)); 669 return MCDisassembler::Success; 670} 671 672static DecodeStatus 673DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 674 uint64_t Address, const void *Decoder) { 675 if (RegNo == 15) return MCDisassembler::Fail; 676 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 677} 678 679static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 680 uint64_t Address, const void *Decoder) { 681 if (RegNo > 7) 682 return MCDisassembler::Fail; 683 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 684} 685 686static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 687 uint64_t Address, const void *Decoder) { 688 unsigned Register = 0; 689 switch (RegNo) { 690 case 0: 691 Register = ARM::R0; 692 break; 693 case 1: 694 Register = ARM::R1; 695 break; 696 case 2: 697 Register = ARM::R2; 698 break; 699 case 3: 700 Register = ARM::R3; 701 break; 702 case 9: 703 Register = ARM::R9; 704 break; 705 case 12: 706 Register = ARM::R12; 707 break; 708 default: 709 return MCDisassembler::Fail; 710 } 711 712 Inst.addOperand(MCOperand::CreateReg(Register)); 713 return MCDisassembler::Success; 714} 715 716static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 717 uint64_t Address, const void *Decoder) { 718 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 719 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 720} 721 722static const unsigned SPRDecoderTable[] = { 723 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 724 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 725 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 726 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 727 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 728 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 729 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 730 ARM::S28, ARM::S29, ARM::S30, ARM::S31 731}; 732 733static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 734 uint64_t Address, const void *Decoder) { 735 if (RegNo > 31) 736 return MCDisassembler::Fail; 737 738 unsigned Register = SPRDecoderTable[RegNo]; 739 Inst.addOperand(MCOperand::CreateReg(Register)); 740 return MCDisassembler::Success; 741} 742 743static const unsigned DPRDecoderTable[] = { 744 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 745 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 746 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 747 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 748 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 749 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 750 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 751 ARM::D28, ARM::D29, ARM::D30, ARM::D31 752}; 753 754static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 755 uint64_t Address, const void *Decoder) { 756 if (RegNo > 31) 757 return MCDisassembler::Fail; 758 759 unsigned Register = DPRDecoderTable[RegNo]; 760 Inst.addOperand(MCOperand::CreateReg(Register)); 761 return MCDisassembler::Success; 762} 763 764static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 765 uint64_t Address, const void *Decoder) { 766 if (RegNo > 7) 767 return MCDisassembler::Fail; 768 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 769} 770 771static DecodeStatus 772DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 773 uint64_t Address, const void *Decoder) { 774 if (RegNo > 15) 775 return MCDisassembler::Fail; 776 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 777} 778 779static const unsigned QPRDecoderTable[] = { 780 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 781 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 782 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 783 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 784}; 785 786 787static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 788 uint64_t Address, const void *Decoder) { 789 if (RegNo > 31) 790 return MCDisassembler::Fail; 791 RegNo >>= 1; 792 793 unsigned Register = QPRDecoderTable[RegNo]; 794 Inst.addOperand(MCOperand::CreateReg(Register)); 795 return MCDisassembler::Success; 796} 797 798static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 799 uint64_t Address, const void *Decoder) { 800 if (Val == 0xF) return MCDisassembler::Fail; 801 // AL predicate is not allowed on Thumb1 branches. 802 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 803 return MCDisassembler::Fail; 804 Inst.addOperand(MCOperand::CreateImm(Val)); 805 if (Val == ARMCC::AL) { 806 Inst.addOperand(MCOperand::CreateReg(0)); 807 } else 808 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 809 return MCDisassembler::Success; 810} 811 812static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 813 uint64_t Address, const void *Decoder) { 814 if (Val) 815 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 816 else 817 Inst.addOperand(MCOperand::CreateReg(0)); 818 return MCDisassembler::Success; 819} 820 821static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 822 uint64_t Address, const void *Decoder) { 823 uint32_t imm = Val & 0xFF; 824 uint32_t rot = (Val & 0xF00) >> 7; 825 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 826 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 827 return MCDisassembler::Success; 828} 829 830static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 831 uint64_t Address, const void *Decoder) { 832 DecodeStatus S = MCDisassembler::Success; 833 834 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 835 unsigned type = fieldFromInstruction32(Val, 5, 2); 836 unsigned imm = fieldFromInstruction32(Val, 7, 5); 837 838 // Register-immediate 839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 840 return MCDisassembler::Fail; 841 842 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 843 switch (type) { 844 case 0: 845 Shift = ARM_AM::lsl; 846 break; 847 case 1: 848 Shift = ARM_AM::lsr; 849 break; 850 case 2: 851 Shift = ARM_AM::asr; 852 break; 853 case 3: 854 Shift = ARM_AM::ror; 855 break; 856 } 857 858 if (Shift == ARM_AM::ror && imm == 0) 859 Shift = ARM_AM::rrx; 860 861 unsigned Op = Shift | (imm << 3); 862 Inst.addOperand(MCOperand::CreateImm(Op)); 863 864 return S; 865} 866 867static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 868 uint64_t Address, const void *Decoder) { 869 DecodeStatus S = MCDisassembler::Success; 870 871 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 872 unsigned type = fieldFromInstruction32(Val, 5, 2); 873 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 874 875 // Register-register 876 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 877 return MCDisassembler::Fail; 878 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 879 return MCDisassembler::Fail; 880 881 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 882 switch (type) { 883 case 0: 884 Shift = ARM_AM::lsl; 885 break; 886 case 1: 887 Shift = ARM_AM::lsr; 888 break; 889 case 2: 890 Shift = ARM_AM::asr; 891 break; 892 case 3: 893 Shift = ARM_AM::ror; 894 break; 895 } 896 897 Inst.addOperand(MCOperand::CreateImm(Shift)); 898 899 return S; 900} 901 902static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 903 uint64_t Address, const void *Decoder) { 904 DecodeStatus S = MCDisassembler::Success; 905 906 // Empty register lists are not allowed. 907 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 908 for (unsigned i = 0; i < 16; ++i) { 909 if (Val & (1 << i)) { 910 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 911 return MCDisassembler::Fail; 912 } 913 } 914 915 return S; 916} 917 918static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 919 uint64_t Address, const void *Decoder) { 920 DecodeStatus S = MCDisassembler::Success; 921 922 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 923 unsigned regs = Val & 0xFF; 924 925 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 926 return MCDisassembler::Fail; 927 for (unsigned i = 0; i < (regs - 1); ++i) { 928 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 929 return MCDisassembler::Fail; 930 } 931 932 return S; 933} 934 935static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 936 uint64_t Address, const void *Decoder) { 937 DecodeStatus S = MCDisassembler::Success; 938 939 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 940 unsigned regs = (Val & 0xFF) / 2; 941 942 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 943 return MCDisassembler::Fail; 944 for (unsigned i = 0; i < (regs - 1); ++i) { 945 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 946 return MCDisassembler::Fail; 947 } 948 949 return S; 950} 951 952static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 953 uint64_t Address, const void *Decoder) { 954 // This operand encodes a mask of contiguous zeros between a specified MSB 955 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 956 // the mask of all bits LSB-and-lower, and then xor them to create 957 // the mask of that's all ones on [msb, lsb]. Finally we not it to 958 // create the final mask. 959 unsigned msb = fieldFromInstruction32(Val, 5, 5); 960 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 961 uint32_t msb_mask = (1 << (msb+1)) - 1; 962 uint32_t lsb_mask = (1 << lsb) - 1; 963 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 964 return MCDisassembler::Success; 965} 966 967static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 968 uint64_t Address, const void *Decoder) { 969 DecodeStatus S = MCDisassembler::Success; 970 971 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 972 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 973 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 974 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 975 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 976 unsigned U = fieldFromInstruction32(Insn, 23, 1); 977 978 switch (Inst.getOpcode()) { 979 case ARM::LDC_OFFSET: 980 case ARM::LDC_PRE: 981 case ARM::LDC_POST: 982 case ARM::LDC_OPTION: 983 case ARM::LDCL_OFFSET: 984 case ARM::LDCL_PRE: 985 case ARM::LDCL_POST: 986 case ARM::LDCL_OPTION: 987 case ARM::STC_OFFSET: 988 case ARM::STC_PRE: 989 case ARM::STC_POST: 990 case ARM::STC_OPTION: 991 case ARM::STCL_OFFSET: 992 case ARM::STCL_PRE: 993 case ARM::STCL_POST: 994 case ARM::STCL_OPTION: 995 case ARM::t2LDC_OFFSET: 996 case ARM::t2LDC_PRE: 997 case ARM::t2LDC_POST: 998 case ARM::t2LDC_OPTION: 999 case ARM::t2LDCL_OFFSET: 1000 case ARM::t2LDCL_PRE: 1001 case ARM::t2LDCL_POST: 1002 case ARM::t2LDCL_OPTION: 1003 case ARM::t2STC_OFFSET: 1004 case ARM::t2STC_PRE: 1005 case ARM::t2STC_POST: 1006 case ARM::t2STC_OPTION: 1007 case ARM::t2STCL_OFFSET: 1008 case ARM::t2STCL_PRE: 1009 case ARM::t2STCL_POST: 1010 case ARM::t2STCL_OPTION: 1011 if (coproc == 0xA || coproc == 0xB) 1012 return MCDisassembler::Fail; 1013 break; 1014 default: 1015 break; 1016 } 1017 1018 Inst.addOperand(MCOperand::CreateImm(coproc)); 1019 Inst.addOperand(MCOperand::CreateImm(CRd)); 1020 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1021 return MCDisassembler::Fail; 1022 switch (Inst.getOpcode()) { 1023 case ARM::LDC_OPTION: 1024 case ARM::LDCL_OPTION: 1025 case ARM::LDC2_OPTION: 1026 case ARM::LDC2L_OPTION: 1027 case ARM::STC_OPTION: 1028 case ARM::STCL_OPTION: 1029 case ARM::STC2_OPTION: 1030 case ARM::STC2L_OPTION: 1031 case ARM::LDCL_POST: 1032 case ARM::STCL_POST: 1033 case ARM::LDC2L_POST: 1034 case ARM::STC2L_POST: 1035 case ARM::t2LDC_OPTION: 1036 case ARM::t2LDCL_OPTION: 1037 case ARM::t2STC_OPTION: 1038 case ARM::t2STCL_OPTION: 1039 case ARM::t2LDCL_POST: 1040 case ARM::t2STCL_POST: 1041 break; 1042 default: 1043 Inst.addOperand(MCOperand::CreateReg(0)); 1044 break; 1045 } 1046 1047 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1048 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1049 1050 bool writeback = (P == 0) || (W == 1); 1051 unsigned idx_mode = 0; 1052 if (P && writeback) 1053 idx_mode = ARMII::IndexModePre; 1054 else if (!P && writeback) 1055 idx_mode = ARMII::IndexModePost; 1056 1057 switch (Inst.getOpcode()) { 1058 case ARM::LDCL_POST: 1059 case ARM::STCL_POST: 1060 case ARM::t2LDCL_POST: 1061 case ARM::t2STCL_POST: 1062 case ARM::LDC2L_POST: 1063 case ARM::STC2L_POST: 1064 imm |= U << 8; 1065 case ARM::LDC_OPTION: 1066 case ARM::LDCL_OPTION: 1067 case ARM::LDC2_OPTION: 1068 case ARM::LDC2L_OPTION: 1069 case ARM::STC_OPTION: 1070 case ARM::STCL_OPTION: 1071 case ARM::STC2_OPTION: 1072 case ARM::STC2L_OPTION: 1073 case ARM::t2LDC_OPTION: 1074 case ARM::t2LDCL_OPTION: 1075 case ARM::t2STC_OPTION: 1076 case ARM::t2STCL_OPTION: 1077 Inst.addOperand(MCOperand::CreateImm(imm)); 1078 break; 1079 default: 1080 if (U) 1081 Inst.addOperand(MCOperand::CreateImm( 1082 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 1083 else 1084 Inst.addOperand(MCOperand::CreateImm( 1085 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 1086 break; 1087 } 1088 1089 switch (Inst.getOpcode()) { 1090 case ARM::LDC_OFFSET: 1091 case ARM::LDC_PRE: 1092 case ARM::LDC_POST: 1093 case ARM::LDC_OPTION: 1094 case ARM::LDCL_OFFSET: 1095 case ARM::LDCL_PRE: 1096 case ARM::LDCL_POST: 1097 case ARM::LDCL_OPTION: 1098 case ARM::STC_OFFSET: 1099 case ARM::STC_PRE: 1100 case ARM::STC_POST: 1101 case ARM::STC_OPTION: 1102 case ARM::STCL_OFFSET: 1103 case ARM::STCL_PRE: 1104 case ARM::STCL_POST: 1105 case ARM::STCL_OPTION: 1106 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1107 return MCDisassembler::Fail; 1108 break; 1109 default: 1110 break; 1111 } 1112 1113 return S; 1114} 1115 1116static DecodeStatus 1117DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1118 uint64_t Address, const void *Decoder) { 1119 DecodeStatus S = MCDisassembler::Success; 1120 1121 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1122 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1123 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1124 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1125 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1126 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1127 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1128 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1129 1130 // On stores, the writeback operand precedes Rt. 1131 switch (Inst.getOpcode()) { 1132 case ARM::STR_POST_IMM: 1133 case ARM::STR_POST_REG: 1134 case ARM::STRB_POST_IMM: 1135 case ARM::STRB_POST_REG: 1136 case ARM::STRT_POST_REG: 1137 case ARM::STRT_POST_IMM: 1138 case ARM::STRBT_POST_REG: 1139 case ARM::STRBT_POST_IMM: 1140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1141 return MCDisassembler::Fail; 1142 break; 1143 default: 1144 break; 1145 } 1146 1147 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1148 return MCDisassembler::Fail; 1149 1150 // On loads, the writeback operand comes after Rt. 1151 switch (Inst.getOpcode()) { 1152 case ARM::LDR_POST_IMM: 1153 case ARM::LDR_POST_REG: 1154 case ARM::LDRB_POST_IMM: 1155 case ARM::LDRB_POST_REG: 1156 case ARM::LDRBT_POST_REG: 1157 case ARM::LDRBT_POST_IMM: 1158 case ARM::LDRT_POST_REG: 1159 case ARM::LDRT_POST_IMM: 1160 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1161 return MCDisassembler::Fail; 1162 break; 1163 default: 1164 break; 1165 } 1166 1167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1168 return MCDisassembler::Fail; 1169 1170 ARM_AM::AddrOpc Op = ARM_AM::add; 1171 if (!fieldFromInstruction32(Insn, 23, 1)) 1172 Op = ARM_AM::sub; 1173 1174 bool writeback = (P == 0) || (W == 1); 1175 unsigned idx_mode = 0; 1176 if (P && writeback) 1177 idx_mode = ARMII::IndexModePre; 1178 else if (!P && writeback) 1179 idx_mode = ARMII::IndexModePost; 1180 1181 if (writeback && (Rn == 15 || Rn == Rt)) 1182 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1183 1184 if (reg) { 1185 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1186 return MCDisassembler::Fail; 1187 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1188 switch( fieldFromInstruction32(Insn, 5, 2)) { 1189 case 0: 1190 Opc = ARM_AM::lsl; 1191 break; 1192 case 1: 1193 Opc = ARM_AM::lsr; 1194 break; 1195 case 2: 1196 Opc = ARM_AM::asr; 1197 break; 1198 case 3: 1199 Opc = ARM_AM::ror; 1200 break; 1201 default: 1202 return MCDisassembler::Fail; 1203 } 1204 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1205 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1206 1207 Inst.addOperand(MCOperand::CreateImm(imm)); 1208 } else { 1209 Inst.addOperand(MCOperand::CreateReg(0)); 1210 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1211 Inst.addOperand(MCOperand::CreateImm(tmp)); 1212 } 1213 1214 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1215 return MCDisassembler::Fail; 1216 1217 return S; 1218} 1219 1220static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1221 uint64_t Address, const void *Decoder) { 1222 DecodeStatus S = MCDisassembler::Success; 1223 1224 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1225 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1226 unsigned type = fieldFromInstruction32(Val, 5, 2); 1227 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1228 unsigned U = fieldFromInstruction32(Val, 12, 1); 1229 1230 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1231 switch (type) { 1232 case 0: 1233 ShOp = ARM_AM::lsl; 1234 break; 1235 case 1: 1236 ShOp = ARM_AM::lsr; 1237 break; 1238 case 2: 1239 ShOp = ARM_AM::asr; 1240 break; 1241 case 3: 1242 ShOp = ARM_AM::ror; 1243 break; 1244 } 1245 1246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1247 return MCDisassembler::Fail; 1248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1249 return MCDisassembler::Fail; 1250 unsigned shift; 1251 if (U) 1252 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1253 else 1254 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1255 Inst.addOperand(MCOperand::CreateImm(shift)); 1256 1257 return S; 1258} 1259 1260static DecodeStatus 1261DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1262 uint64_t Address, const void *Decoder) { 1263 DecodeStatus S = MCDisassembler::Success; 1264 1265 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1266 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1267 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1268 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1269 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1270 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1271 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1272 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1273 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1274 1275 bool writeback = (W == 1) | (P == 0); 1276 1277 // For {LD,ST}RD, Rt must be even, else undefined. 1278 switch (Inst.getOpcode()) { 1279 case ARM::STRD: 1280 case ARM::STRD_PRE: 1281 case ARM::STRD_POST: 1282 case ARM::LDRD: 1283 case ARM::LDRD_PRE: 1284 case ARM::LDRD_POST: 1285 if (Rt & 0x1) return MCDisassembler::Fail; 1286 break; 1287 default: 1288 break; 1289 } 1290 1291 if (writeback) { // Writeback 1292 if (P) 1293 U |= ARMII::IndexModePre << 9; 1294 else 1295 U |= ARMII::IndexModePost << 9; 1296 1297 // On stores, the writeback operand precedes Rt. 1298 switch (Inst.getOpcode()) { 1299 case ARM::STRD: 1300 case ARM::STRD_PRE: 1301 case ARM::STRD_POST: 1302 case ARM::STRH: 1303 case ARM::STRH_PRE: 1304 case ARM::STRH_POST: 1305 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1306 return MCDisassembler::Fail; 1307 break; 1308 default: 1309 break; 1310 } 1311 } 1312 1313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1314 return MCDisassembler::Fail; 1315 switch (Inst.getOpcode()) { 1316 case ARM::STRD: 1317 case ARM::STRD_PRE: 1318 case ARM::STRD_POST: 1319 case ARM::LDRD: 1320 case ARM::LDRD_PRE: 1321 case ARM::LDRD_POST: 1322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1323 return MCDisassembler::Fail; 1324 break; 1325 default: 1326 break; 1327 } 1328 1329 if (writeback) { 1330 // On loads, the writeback operand comes after Rt. 1331 switch (Inst.getOpcode()) { 1332 case ARM::LDRD: 1333 case ARM::LDRD_PRE: 1334 case ARM::LDRD_POST: 1335 case ARM::LDRH: 1336 case ARM::LDRH_PRE: 1337 case ARM::LDRH_POST: 1338 case ARM::LDRSH: 1339 case ARM::LDRSH_PRE: 1340 case ARM::LDRSH_POST: 1341 case ARM::LDRSB: 1342 case ARM::LDRSB_PRE: 1343 case ARM::LDRSB_POST: 1344 case ARM::LDRHTr: 1345 case ARM::LDRSBTr: 1346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1347 return MCDisassembler::Fail; 1348 break; 1349 default: 1350 break; 1351 } 1352 } 1353 1354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1355 return MCDisassembler::Fail; 1356 1357 if (type) { 1358 Inst.addOperand(MCOperand::CreateReg(0)); 1359 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1360 } else { 1361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1362 return MCDisassembler::Fail; 1363 Inst.addOperand(MCOperand::CreateImm(U)); 1364 } 1365 1366 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1367 return MCDisassembler::Fail; 1368 1369 return S; 1370} 1371 1372static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1373 uint64_t Address, const void *Decoder) { 1374 DecodeStatus S = MCDisassembler::Success; 1375 1376 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1377 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1378 1379 switch (mode) { 1380 case 0: 1381 mode = ARM_AM::da; 1382 break; 1383 case 1: 1384 mode = ARM_AM::ia; 1385 break; 1386 case 2: 1387 mode = ARM_AM::db; 1388 break; 1389 case 3: 1390 mode = ARM_AM::ib; 1391 break; 1392 } 1393 1394 Inst.addOperand(MCOperand::CreateImm(mode)); 1395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1396 return MCDisassembler::Fail; 1397 1398 return S; 1399} 1400 1401static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1402 unsigned Insn, 1403 uint64_t Address, const void *Decoder) { 1404 DecodeStatus S = MCDisassembler::Success; 1405 1406 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1407 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1408 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1409 1410 if (pred == 0xF) { 1411 switch (Inst.getOpcode()) { 1412 case ARM::LDMDA: 1413 Inst.setOpcode(ARM::RFEDA); 1414 break; 1415 case ARM::LDMDA_UPD: 1416 Inst.setOpcode(ARM::RFEDA_UPD); 1417 break; 1418 case ARM::LDMDB: 1419 Inst.setOpcode(ARM::RFEDB); 1420 break; 1421 case ARM::LDMDB_UPD: 1422 Inst.setOpcode(ARM::RFEDB_UPD); 1423 break; 1424 case ARM::LDMIA: 1425 Inst.setOpcode(ARM::RFEIA); 1426 break; 1427 case ARM::LDMIA_UPD: 1428 Inst.setOpcode(ARM::RFEIA_UPD); 1429 break; 1430 case ARM::LDMIB: 1431 Inst.setOpcode(ARM::RFEIB); 1432 break; 1433 case ARM::LDMIB_UPD: 1434 Inst.setOpcode(ARM::RFEIB_UPD); 1435 break; 1436 case ARM::STMDA: 1437 Inst.setOpcode(ARM::SRSDA); 1438 break; 1439 case ARM::STMDA_UPD: 1440 Inst.setOpcode(ARM::SRSDA_UPD); 1441 break; 1442 case ARM::STMDB: 1443 Inst.setOpcode(ARM::SRSDB); 1444 break; 1445 case ARM::STMDB_UPD: 1446 Inst.setOpcode(ARM::SRSDB_UPD); 1447 break; 1448 case ARM::STMIA: 1449 Inst.setOpcode(ARM::SRSIA); 1450 break; 1451 case ARM::STMIA_UPD: 1452 Inst.setOpcode(ARM::SRSIA_UPD); 1453 break; 1454 case ARM::STMIB: 1455 Inst.setOpcode(ARM::SRSIB); 1456 break; 1457 case ARM::STMIB_UPD: 1458 Inst.setOpcode(ARM::SRSIB_UPD); 1459 break; 1460 default: 1461 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1462 } 1463 1464 // For stores (which become SRS's, the only operand is the mode. 1465 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1466 Inst.addOperand( 1467 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1468 return S; 1469 } 1470 1471 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1472 } 1473 1474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1475 return MCDisassembler::Fail; 1476 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1477 return MCDisassembler::Fail; // Tied 1478 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1479 return MCDisassembler::Fail; 1480 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1481 return MCDisassembler::Fail; 1482 1483 return S; 1484} 1485 1486static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1487 uint64_t Address, const void *Decoder) { 1488 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1489 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1490 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1491 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1492 1493 DecodeStatus S = MCDisassembler::Success; 1494 1495 // imod == '01' --> UNPREDICTABLE 1496 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1497 // return failure here. The '01' imod value is unprintable, so there's 1498 // nothing useful we could do even if we returned UNPREDICTABLE. 1499 1500 if (imod == 1) return MCDisassembler::Fail; 1501 1502 if (imod && M) { 1503 Inst.setOpcode(ARM::CPS3p); 1504 Inst.addOperand(MCOperand::CreateImm(imod)); 1505 Inst.addOperand(MCOperand::CreateImm(iflags)); 1506 Inst.addOperand(MCOperand::CreateImm(mode)); 1507 } else if (imod && !M) { 1508 Inst.setOpcode(ARM::CPS2p); 1509 Inst.addOperand(MCOperand::CreateImm(imod)); 1510 Inst.addOperand(MCOperand::CreateImm(iflags)); 1511 if (mode) S = MCDisassembler::SoftFail; 1512 } else if (!imod && M) { 1513 Inst.setOpcode(ARM::CPS1p); 1514 Inst.addOperand(MCOperand::CreateImm(mode)); 1515 if (iflags) S = MCDisassembler::SoftFail; 1516 } else { 1517 // imod == '00' && M == '0' --> UNPREDICTABLE 1518 Inst.setOpcode(ARM::CPS1p); 1519 Inst.addOperand(MCOperand::CreateImm(mode)); 1520 S = MCDisassembler::SoftFail; 1521 } 1522 1523 return S; 1524} 1525 1526static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1527 uint64_t Address, const void *Decoder) { 1528 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1529 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1530 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1531 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1532 1533 DecodeStatus S = MCDisassembler::Success; 1534 1535 // imod == '01' --> UNPREDICTABLE 1536 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1537 // return failure here. The '01' imod value is unprintable, so there's 1538 // nothing useful we could do even if we returned UNPREDICTABLE. 1539 1540 if (imod == 1) return MCDisassembler::Fail; 1541 1542 if (imod && M) { 1543 Inst.setOpcode(ARM::t2CPS3p); 1544 Inst.addOperand(MCOperand::CreateImm(imod)); 1545 Inst.addOperand(MCOperand::CreateImm(iflags)); 1546 Inst.addOperand(MCOperand::CreateImm(mode)); 1547 } else if (imod && !M) { 1548 Inst.setOpcode(ARM::t2CPS2p); 1549 Inst.addOperand(MCOperand::CreateImm(imod)); 1550 Inst.addOperand(MCOperand::CreateImm(iflags)); 1551 if (mode) S = MCDisassembler::SoftFail; 1552 } else if (!imod && M) { 1553 Inst.setOpcode(ARM::t2CPS1p); 1554 Inst.addOperand(MCOperand::CreateImm(mode)); 1555 if (iflags) S = MCDisassembler::SoftFail; 1556 } else { 1557 // imod == '00' && M == '0' --> UNPREDICTABLE 1558 Inst.setOpcode(ARM::t2CPS1p); 1559 Inst.addOperand(MCOperand::CreateImm(mode)); 1560 S = MCDisassembler::SoftFail; 1561 } 1562 1563 return S; 1564} 1565 1566 1567static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1568 uint64_t Address, const void *Decoder) { 1569 DecodeStatus S = MCDisassembler::Success; 1570 1571 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1572 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1573 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1574 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1575 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1576 1577 if (pred == 0xF) 1578 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1579 1580 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1581 return MCDisassembler::Fail; 1582 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1583 return MCDisassembler::Fail; 1584 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1585 return MCDisassembler::Fail; 1586 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1587 return MCDisassembler::Fail; 1588 1589 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1590 return MCDisassembler::Fail; 1591 1592 return S; 1593} 1594 1595static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1596 uint64_t Address, const void *Decoder) { 1597 DecodeStatus S = MCDisassembler::Success; 1598 1599 unsigned add = fieldFromInstruction32(Val, 12, 1); 1600 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1601 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1602 1603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1604 return MCDisassembler::Fail; 1605 1606 if (!add) imm *= -1; 1607 if (imm == 0 && !add) imm = INT32_MIN; 1608 Inst.addOperand(MCOperand::CreateImm(imm)); 1609 1610 return S; 1611} 1612 1613static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1614 uint64_t Address, const void *Decoder) { 1615 DecodeStatus S = MCDisassembler::Success; 1616 1617 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1618 unsigned U = fieldFromInstruction32(Val, 8, 1); 1619 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1620 1621 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1622 return MCDisassembler::Fail; 1623 1624 if (U) 1625 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1626 else 1627 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1628 1629 return S; 1630} 1631 1632static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1633 uint64_t Address, const void *Decoder) { 1634 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1635} 1636 1637static DecodeStatus 1638DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1639 uint64_t Address, const void *Decoder) { 1640 DecodeStatus S = MCDisassembler::Success; 1641 1642 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1643 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1644 1645 if (pred == 0xF) { 1646 Inst.setOpcode(ARM::BLXi); 1647 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1648 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1649 return S; 1650 } 1651 1652 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1653 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1654 return MCDisassembler::Fail; 1655 1656 return S; 1657} 1658 1659 1660static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1661 uint64_t Address, const void *Decoder) { 1662 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1663 return MCDisassembler::Success; 1664} 1665 1666static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1667 uint64_t Address, const void *Decoder) { 1668 DecodeStatus S = MCDisassembler::Success; 1669 1670 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1671 unsigned align = fieldFromInstruction32(Val, 4, 2); 1672 1673 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1674 return MCDisassembler::Fail; 1675 if (!align) 1676 Inst.addOperand(MCOperand::CreateImm(0)); 1677 else 1678 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1679 1680 return S; 1681} 1682 1683static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1684 uint64_t Address, const void *Decoder) { 1685 DecodeStatus S = MCDisassembler::Success; 1686 1687 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1688 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1689 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1690 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1691 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1692 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1693 1694 // First output register 1695 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1696 return MCDisassembler::Fail; 1697 1698 // Second output register 1699 switch (Inst.getOpcode()) { 1700 case ARM::VLD1q8: 1701 case ARM::VLD1q16: 1702 case ARM::VLD1q32: 1703 case ARM::VLD1q64: 1704 case ARM::VLD1q8_UPD: 1705 case ARM::VLD1q16_UPD: 1706 case ARM::VLD1q32_UPD: 1707 case ARM::VLD1q64_UPD: 1708 case ARM::VLD1d8T: 1709 case ARM::VLD1d16T: 1710 case ARM::VLD1d32T: 1711 case ARM::VLD1d64T: 1712 case ARM::VLD1d8T_UPD: 1713 case ARM::VLD1d16T_UPD: 1714 case ARM::VLD1d32T_UPD: 1715 case ARM::VLD1d64T_UPD: 1716 case ARM::VLD1d8Q: 1717 case ARM::VLD1d16Q: 1718 case ARM::VLD1d32Q: 1719 case ARM::VLD1d64Q: 1720 case ARM::VLD1d8Q_UPD: 1721 case ARM::VLD1d16Q_UPD: 1722 case ARM::VLD1d32Q_UPD: 1723 case ARM::VLD1d64Q_UPD: 1724 case ARM::VLD2d8: 1725 case ARM::VLD2d16: 1726 case ARM::VLD2d32: 1727 case ARM::VLD2d8_UPD: 1728 case ARM::VLD2d16_UPD: 1729 case ARM::VLD2d32_UPD: 1730 case ARM::VLD2q8: 1731 case ARM::VLD2q16: 1732 case ARM::VLD2q32: 1733 case ARM::VLD2q8_UPD: 1734 case ARM::VLD2q16_UPD: 1735 case ARM::VLD2q32_UPD: 1736 case ARM::VLD3d8: 1737 case ARM::VLD3d16: 1738 case ARM::VLD3d32: 1739 case ARM::VLD3d8_UPD: 1740 case ARM::VLD3d16_UPD: 1741 case ARM::VLD3d32_UPD: 1742 case ARM::VLD4d8: 1743 case ARM::VLD4d16: 1744 case ARM::VLD4d32: 1745 case ARM::VLD4d8_UPD: 1746 case ARM::VLD4d16_UPD: 1747 case ARM::VLD4d32_UPD: 1748 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1749 return MCDisassembler::Fail; 1750 break; 1751 case ARM::VLD2b8: 1752 case ARM::VLD2b16: 1753 case ARM::VLD2b32: 1754 case ARM::VLD2b8_UPD: 1755 case ARM::VLD2b16_UPD: 1756 case ARM::VLD2b32_UPD: 1757 case ARM::VLD3q8: 1758 case ARM::VLD3q16: 1759 case ARM::VLD3q32: 1760 case ARM::VLD3q8_UPD: 1761 case ARM::VLD3q16_UPD: 1762 case ARM::VLD3q32_UPD: 1763 case ARM::VLD4q8: 1764 case ARM::VLD4q16: 1765 case ARM::VLD4q32: 1766 case ARM::VLD4q8_UPD: 1767 case ARM::VLD4q16_UPD: 1768 case ARM::VLD4q32_UPD: 1769 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1770 return MCDisassembler::Fail; 1771 default: 1772 break; 1773 } 1774 1775 // Third output register 1776 switch(Inst.getOpcode()) { 1777 case ARM::VLD1d8T: 1778 case ARM::VLD1d16T: 1779 case ARM::VLD1d32T: 1780 case ARM::VLD1d64T: 1781 case ARM::VLD1d8T_UPD: 1782 case ARM::VLD1d16T_UPD: 1783 case ARM::VLD1d32T_UPD: 1784 case ARM::VLD1d64T_UPD: 1785 case ARM::VLD1d8Q: 1786 case ARM::VLD1d16Q: 1787 case ARM::VLD1d32Q: 1788 case ARM::VLD1d64Q: 1789 case ARM::VLD1d8Q_UPD: 1790 case ARM::VLD1d16Q_UPD: 1791 case ARM::VLD1d32Q_UPD: 1792 case ARM::VLD1d64Q_UPD: 1793 case ARM::VLD2q8: 1794 case ARM::VLD2q16: 1795 case ARM::VLD2q32: 1796 case ARM::VLD2q8_UPD: 1797 case ARM::VLD2q16_UPD: 1798 case ARM::VLD2q32_UPD: 1799 case ARM::VLD3d8: 1800 case ARM::VLD3d16: 1801 case ARM::VLD3d32: 1802 case ARM::VLD3d8_UPD: 1803 case ARM::VLD3d16_UPD: 1804 case ARM::VLD3d32_UPD: 1805 case ARM::VLD4d8: 1806 case ARM::VLD4d16: 1807 case ARM::VLD4d32: 1808 case ARM::VLD4d8_UPD: 1809 case ARM::VLD4d16_UPD: 1810 case ARM::VLD4d32_UPD: 1811 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1812 return MCDisassembler::Fail; 1813 break; 1814 case ARM::VLD3q8: 1815 case ARM::VLD3q16: 1816 case ARM::VLD3q32: 1817 case ARM::VLD3q8_UPD: 1818 case ARM::VLD3q16_UPD: 1819 case ARM::VLD3q32_UPD: 1820 case ARM::VLD4q8: 1821 case ARM::VLD4q16: 1822 case ARM::VLD4q32: 1823 case ARM::VLD4q8_UPD: 1824 case ARM::VLD4q16_UPD: 1825 case ARM::VLD4q32_UPD: 1826 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 1827 return MCDisassembler::Fail; 1828 break; 1829 default: 1830 break; 1831 } 1832 1833 // Fourth output register 1834 switch (Inst.getOpcode()) { 1835 case ARM::VLD1d8Q: 1836 case ARM::VLD1d16Q: 1837 case ARM::VLD1d32Q: 1838 case ARM::VLD1d64Q: 1839 case ARM::VLD1d8Q_UPD: 1840 case ARM::VLD1d16Q_UPD: 1841 case ARM::VLD1d32Q_UPD: 1842 case ARM::VLD1d64Q_UPD: 1843 case ARM::VLD2q8: 1844 case ARM::VLD2q16: 1845 case ARM::VLD2q32: 1846 case ARM::VLD2q8_UPD: 1847 case ARM::VLD2q16_UPD: 1848 case ARM::VLD2q32_UPD: 1849 case ARM::VLD4d8: 1850 case ARM::VLD4d16: 1851 case ARM::VLD4d32: 1852 case ARM::VLD4d8_UPD: 1853 case ARM::VLD4d16_UPD: 1854 case ARM::VLD4d32_UPD: 1855 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 1856 return MCDisassembler::Fail; 1857 break; 1858 case ARM::VLD4q8: 1859 case ARM::VLD4q16: 1860 case ARM::VLD4q32: 1861 case ARM::VLD4q8_UPD: 1862 case ARM::VLD4q16_UPD: 1863 case ARM::VLD4q32_UPD: 1864 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 1865 return MCDisassembler::Fail; 1866 break; 1867 default: 1868 break; 1869 } 1870 1871 // Writeback operand 1872 switch (Inst.getOpcode()) { 1873 case ARM::VLD1d8_UPD: 1874 case ARM::VLD1d16_UPD: 1875 case ARM::VLD1d32_UPD: 1876 case ARM::VLD1d64_UPD: 1877 case ARM::VLD1q8_UPD: 1878 case ARM::VLD1q16_UPD: 1879 case ARM::VLD1q32_UPD: 1880 case ARM::VLD1q64_UPD: 1881 case ARM::VLD1d8T_UPD: 1882 case ARM::VLD1d16T_UPD: 1883 case ARM::VLD1d32T_UPD: 1884 case ARM::VLD1d64T_UPD: 1885 case ARM::VLD1d8Q_UPD: 1886 case ARM::VLD1d16Q_UPD: 1887 case ARM::VLD1d32Q_UPD: 1888 case ARM::VLD1d64Q_UPD: 1889 case ARM::VLD2d8_UPD: 1890 case ARM::VLD2d16_UPD: 1891 case ARM::VLD2d32_UPD: 1892 case ARM::VLD2q8_UPD: 1893 case ARM::VLD2q16_UPD: 1894 case ARM::VLD2q32_UPD: 1895 case ARM::VLD2b8_UPD: 1896 case ARM::VLD2b16_UPD: 1897 case ARM::VLD2b32_UPD: 1898 case ARM::VLD3d8_UPD: 1899 case ARM::VLD3d16_UPD: 1900 case ARM::VLD3d32_UPD: 1901 case ARM::VLD3q8_UPD: 1902 case ARM::VLD3q16_UPD: 1903 case ARM::VLD3q32_UPD: 1904 case ARM::VLD4d8_UPD: 1905 case ARM::VLD4d16_UPD: 1906 case ARM::VLD4d32_UPD: 1907 case ARM::VLD4q8_UPD: 1908 case ARM::VLD4q16_UPD: 1909 case ARM::VLD4q32_UPD: 1910 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1911 return MCDisassembler::Fail; 1912 break; 1913 default: 1914 break; 1915 } 1916 1917 // AddrMode6 Base (register+alignment) 1918 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1919 return MCDisassembler::Fail; 1920 1921 // AddrMode6 Offset (register) 1922 if (Rm == 0xD) 1923 Inst.addOperand(MCOperand::CreateReg(0)); 1924 else if (Rm != 0xF) { 1925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1926 return MCDisassembler::Fail; 1927 } 1928 1929 return S; 1930} 1931 1932static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1933 uint64_t Address, const void *Decoder) { 1934 DecodeStatus S = MCDisassembler::Success; 1935 1936 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1937 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1938 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1939 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1940 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1941 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1942 1943 // Writeback Operand 1944 switch (Inst.getOpcode()) { 1945 case ARM::VST1d8_UPD: 1946 case ARM::VST1d16_UPD: 1947 case ARM::VST1d32_UPD: 1948 case ARM::VST1d64_UPD: 1949 case ARM::VST1q8_UPD: 1950 case ARM::VST1q16_UPD: 1951 case ARM::VST1q32_UPD: 1952 case ARM::VST1q64_UPD: 1953 case ARM::VST1d8T_UPD: 1954 case ARM::VST1d16T_UPD: 1955 case ARM::VST1d32T_UPD: 1956 case ARM::VST1d64T_UPD: 1957 case ARM::VST1d8Q_UPD: 1958 case ARM::VST1d16Q_UPD: 1959 case ARM::VST1d32Q_UPD: 1960 case ARM::VST1d64Q_UPD: 1961 case ARM::VST2d8_UPD: 1962 case ARM::VST2d16_UPD: 1963 case ARM::VST2d32_UPD: 1964 case ARM::VST2q8_UPD: 1965 case ARM::VST2q16_UPD: 1966 case ARM::VST2q32_UPD: 1967 case ARM::VST2b8_UPD: 1968 case ARM::VST2b16_UPD: 1969 case ARM::VST2b32_UPD: 1970 case ARM::VST3d8_UPD: 1971 case ARM::VST3d16_UPD: 1972 case ARM::VST3d32_UPD: 1973 case ARM::VST3q8_UPD: 1974 case ARM::VST3q16_UPD: 1975 case ARM::VST3q32_UPD: 1976 case ARM::VST4d8_UPD: 1977 case ARM::VST4d16_UPD: 1978 case ARM::VST4d32_UPD: 1979 case ARM::VST4q8_UPD: 1980 case ARM::VST4q16_UPD: 1981 case ARM::VST4q32_UPD: 1982 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 1983 return MCDisassembler::Fail; 1984 break; 1985 default: 1986 break; 1987 } 1988 1989 // AddrMode6 Base (register+alignment) 1990 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 1991 return MCDisassembler::Fail; 1992 1993 // AddrMode6 Offset (register) 1994 if (Rm == 0xD) 1995 Inst.addOperand(MCOperand::CreateReg(0)); 1996 else if (Rm != 0xF) { 1997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1998 return MCDisassembler::Fail; 1999 } 2000 2001 // First input register 2002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2003 return MCDisassembler::Fail; 2004 2005 // Second input register 2006 switch (Inst.getOpcode()) { 2007 case ARM::VST1q8: 2008 case ARM::VST1q16: 2009 case ARM::VST1q32: 2010 case ARM::VST1q64: 2011 case ARM::VST1q8_UPD: 2012 case ARM::VST1q16_UPD: 2013 case ARM::VST1q32_UPD: 2014 case ARM::VST1q64_UPD: 2015 case ARM::VST1d8T: 2016 case ARM::VST1d16T: 2017 case ARM::VST1d32T: 2018 case ARM::VST1d64T: 2019 case ARM::VST1d8T_UPD: 2020 case ARM::VST1d16T_UPD: 2021 case ARM::VST1d32T_UPD: 2022 case ARM::VST1d64T_UPD: 2023 case ARM::VST1d8Q: 2024 case ARM::VST1d16Q: 2025 case ARM::VST1d32Q: 2026 case ARM::VST1d64Q: 2027 case ARM::VST1d8Q_UPD: 2028 case ARM::VST1d16Q_UPD: 2029 case ARM::VST1d32Q_UPD: 2030 case ARM::VST1d64Q_UPD: 2031 case ARM::VST2d8: 2032 case ARM::VST2d16: 2033 case ARM::VST2d32: 2034 case ARM::VST2d8_UPD: 2035 case ARM::VST2d16_UPD: 2036 case ARM::VST2d32_UPD: 2037 case ARM::VST2q8: 2038 case ARM::VST2q16: 2039 case ARM::VST2q32: 2040 case ARM::VST2q8_UPD: 2041 case ARM::VST2q16_UPD: 2042 case ARM::VST2q32_UPD: 2043 case ARM::VST3d8: 2044 case ARM::VST3d16: 2045 case ARM::VST3d32: 2046 case ARM::VST3d8_UPD: 2047 case ARM::VST3d16_UPD: 2048 case ARM::VST3d32_UPD: 2049 case ARM::VST4d8: 2050 case ARM::VST4d16: 2051 case ARM::VST4d32: 2052 case ARM::VST4d8_UPD: 2053 case ARM::VST4d16_UPD: 2054 case ARM::VST4d32_UPD: 2055 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2056 return MCDisassembler::Fail; 2057 break; 2058 case ARM::VST2b8: 2059 case ARM::VST2b16: 2060 case ARM::VST2b32: 2061 case ARM::VST2b8_UPD: 2062 case ARM::VST2b16_UPD: 2063 case ARM::VST2b32_UPD: 2064 case ARM::VST3q8: 2065 case ARM::VST3q16: 2066 case ARM::VST3q32: 2067 case ARM::VST3q8_UPD: 2068 case ARM::VST3q16_UPD: 2069 case ARM::VST3q32_UPD: 2070 case ARM::VST4q8: 2071 case ARM::VST4q16: 2072 case ARM::VST4q32: 2073 case ARM::VST4q8_UPD: 2074 case ARM::VST4q16_UPD: 2075 case ARM::VST4q32_UPD: 2076 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2077 return MCDisassembler::Fail; 2078 break; 2079 default: 2080 break; 2081 } 2082 2083 // Third input register 2084 switch (Inst.getOpcode()) { 2085 case ARM::VST1d8T: 2086 case ARM::VST1d16T: 2087 case ARM::VST1d32T: 2088 case ARM::VST1d64T: 2089 case ARM::VST1d8T_UPD: 2090 case ARM::VST1d16T_UPD: 2091 case ARM::VST1d32T_UPD: 2092 case ARM::VST1d64T_UPD: 2093 case ARM::VST1d8Q: 2094 case ARM::VST1d16Q: 2095 case ARM::VST1d32Q: 2096 case ARM::VST1d64Q: 2097 case ARM::VST1d8Q_UPD: 2098 case ARM::VST1d16Q_UPD: 2099 case ARM::VST1d32Q_UPD: 2100 case ARM::VST1d64Q_UPD: 2101 case ARM::VST2q8: 2102 case ARM::VST2q16: 2103 case ARM::VST2q32: 2104 case ARM::VST2q8_UPD: 2105 case ARM::VST2q16_UPD: 2106 case ARM::VST2q32_UPD: 2107 case ARM::VST3d8: 2108 case ARM::VST3d16: 2109 case ARM::VST3d32: 2110 case ARM::VST3d8_UPD: 2111 case ARM::VST3d16_UPD: 2112 case ARM::VST3d32_UPD: 2113 case ARM::VST4d8: 2114 case ARM::VST4d16: 2115 case ARM::VST4d32: 2116 case ARM::VST4d8_UPD: 2117 case ARM::VST4d16_UPD: 2118 case ARM::VST4d32_UPD: 2119 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2120 return MCDisassembler::Fail; 2121 break; 2122 case ARM::VST3q8: 2123 case ARM::VST3q16: 2124 case ARM::VST3q32: 2125 case ARM::VST3q8_UPD: 2126 case ARM::VST3q16_UPD: 2127 case ARM::VST3q32_UPD: 2128 case ARM::VST4q8: 2129 case ARM::VST4q16: 2130 case ARM::VST4q32: 2131 case ARM::VST4q8_UPD: 2132 case ARM::VST4q16_UPD: 2133 case ARM::VST4q32_UPD: 2134 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2135 return MCDisassembler::Fail; 2136 break; 2137 default: 2138 break; 2139 } 2140 2141 // Fourth input register 2142 switch (Inst.getOpcode()) { 2143 case ARM::VST1d8Q: 2144 case ARM::VST1d16Q: 2145 case ARM::VST1d32Q: 2146 case ARM::VST1d64Q: 2147 case ARM::VST1d8Q_UPD: 2148 case ARM::VST1d16Q_UPD: 2149 case ARM::VST1d32Q_UPD: 2150 case ARM::VST1d64Q_UPD: 2151 case ARM::VST2q8: 2152 case ARM::VST2q16: 2153 case ARM::VST2q32: 2154 case ARM::VST2q8_UPD: 2155 case ARM::VST2q16_UPD: 2156 case ARM::VST2q32_UPD: 2157 case ARM::VST4d8: 2158 case ARM::VST4d16: 2159 case ARM::VST4d32: 2160 case ARM::VST4d8_UPD: 2161 case ARM::VST4d16_UPD: 2162 case ARM::VST4d32_UPD: 2163 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2164 return MCDisassembler::Fail; 2165 break; 2166 case ARM::VST4q8: 2167 case ARM::VST4q16: 2168 case ARM::VST4q32: 2169 case ARM::VST4q8_UPD: 2170 case ARM::VST4q16_UPD: 2171 case ARM::VST4q32_UPD: 2172 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2173 return MCDisassembler::Fail; 2174 break; 2175 default: 2176 break; 2177 } 2178 2179 return S; 2180} 2181 2182static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2183 uint64_t Address, const void *Decoder) { 2184 DecodeStatus S = MCDisassembler::Success; 2185 2186 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2187 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2188 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2189 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2190 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2191 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2192 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2193 2194 align *= (1 << size); 2195 2196 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2197 return MCDisassembler::Fail; 2198 if (regs == 2) { 2199 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2200 return MCDisassembler::Fail; 2201 } 2202 if (Rm != 0xF) { 2203 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2204 return MCDisassembler::Fail; 2205 } 2206 2207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2208 return MCDisassembler::Fail; 2209 Inst.addOperand(MCOperand::CreateImm(align)); 2210 2211 if (Rm == 0xD) 2212 Inst.addOperand(MCOperand::CreateReg(0)); 2213 else if (Rm != 0xF) { 2214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2215 return MCDisassembler::Fail; 2216 } 2217 2218 return S; 2219} 2220 2221static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2222 uint64_t Address, const void *Decoder) { 2223 DecodeStatus S = MCDisassembler::Success; 2224 2225 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2226 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2227 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2228 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2229 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2230 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2231 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2232 align *= 2*size; 2233 2234 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2235 return MCDisassembler::Fail; 2236 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2237 return MCDisassembler::Fail; 2238 if (Rm != 0xF) { 2239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2240 return MCDisassembler::Fail; 2241 } 2242 2243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2244 return MCDisassembler::Fail; 2245 Inst.addOperand(MCOperand::CreateImm(align)); 2246 2247 if (Rm == 0xD) 2248 Inst.addOperand(MCOperand::CreateReg(0)); 2249 else if (Rm != 0xF) { 2250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2251 return MCDisassembler::Fail; 2252 } 2253 2254 return S; 2255} 2256 2257static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2258 uint64_t Address, const void *Decoder) { 2259 DecodeStatus S = MCDisassembler::Success; 2260 2261 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2262 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2263 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2264 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2265 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2266 2267 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2268 return MCDisassembler::Fail; 2269 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2270 return MCDisassembler::Fail; 2271 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2272 return MCDisassembler::Fail; 2273 if (Rm != 0xF) { 2274 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2275 return MCDisassembler::Fail; 2276 } 2277 2278 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2279 return MCDisassembler::Fail; 2280 Inst.addOperand(MCOperand::CreateImm(0)); 2281 2282 if (Rm == 0xD) 2283 Inst.addOperand(MCOperand::CreateReg(0)); 2284 else if (Rm != 0xF) { 2285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2286 return MCDisassembler::Fail; 2287 } 2288 2289 return S; 2290} 2291 2292static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2293 uint64_t Address, const void *Decoder) { 2294 DecodeStatus S = MCDisassembler::Success; 2295 2296 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2297 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2298 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2299 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2300 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2301 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2302 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2303 2304 if (size == 0x3) { 2305 size = 4; 2306 align = 16; 2307 } else { 2308 if (size == 2) { 2309 size = 1 << size; 2310 align *= 8; 2311 } else { 2312 size = 1 << size; 2313 align *= 4*size; 2314 } 2315 } 2316 2317 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2318 return MCDisassembler::Fail; 2319 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2320 return MCDisassembler::Fail; 2321 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2322 return MCDisassembler::Fail; 2323 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2324 return MCDisassembler::Fail; 2325 if (Rm != 0xF) { 2326 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2327 return MCDisassembler::Fail; 2328 } 2329 2330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2331 return MCDisassembler::Fail; 2332 Inst.addOperand(MCOperand::CreateImm(align)); 2333 2334 if (Rm == 0xD) 2335 Inst.addOperand(MCOperand::CreateReg(0)); 2336 else if (Rm != 0xF) { 2337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2338 return MCDisassembler::Fail; 2339 } 2340 2341 return S; 2342} 2343 2344static DecodeStatus 2345DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2346 uint64_t Address, const void *Decoder) { 2347 DecodeStatus S = MCDisassembler::Success; 2348 2349 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2350 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2351 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2352 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2353 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2354 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2355 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2356 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2357 2358 if (Q) { 2359 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2360 return MCDisassembler::Fail; 2361 } else { 2362 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2363 return MCDisassembler::Fail; 2364 } 2365 2366 Inst.addOperand(MCOperand::CreateImm(imm)); 2367 2368 switch (Inst.getOpcode()) { 2369 case ARM::VORRiv4i16: 2370 case ARM::VORRiv2i32: 2371 case ARM::VBICiv4i16: 2372 case ARM::VBICiv2i32: 2373 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2374 return MCDisassembler::Fail; 2375 break; 2376 case ARM::VORRiv8i16: 2377 case ARM::VORRiv4i32: 2378 case ARM::VBICiv8i16: 2379 case ARM::VBICiv4i32: 2380 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2381 return MCDisassembler::Fail; 2382 break; 2383 default: 2384 break; 2385 } 2386 2387 return S; 2388} 2389 2390static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2391 uint64_t Address, const void *Decoder) { 2392 DecodeStatus S = MCDisassembler::Success; 2393 2394 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2395 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2396 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2397 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2398 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2399 2400 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2401 return MCDisassembler::Fail; 2402 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2403 return MCDisassembler::Fail; 2404 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2405 2406 return S; 2407} 2408 2409static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2410 uint64_t Address, const void *Decoder) { 2411 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2412 return MCDisassembler::Success; 2413} 2414 2415static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2416 uint64_t Address, const void *Decoder) { 2417 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2418 return MCDisassembler::Success; 2419} 2420 2421static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2422 uint64_t Address, const void *Decoder) { 2423 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2424 return MCDisassembler::Success; 2425} 2426 2427static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2428 uint64_t Address, const void *Decoder) { 2429 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2430 return MCDisassembler::Success; 2431} 2432 2433static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2434 uint64_t Address, const void *Decoder) { 2435 DecodeStatus S = MCDisassembler::Success; 2436 2437 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2438 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2439 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2440 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2441 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2442 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2443 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2444 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2445 2446 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2447 return MCDisassembler::Fail; 2448 if (op) { 2449 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2450 return MCDisassembler::Fail; // Writeback 2451 } 2452 2453 for (unsigned i = 0; i < length; ++i) { 2454 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2455 return MCDisassembler::Fail; 2456 } 2457 2458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2459 return MCDisassembler::Fail; 2460 2461 return S; 2462} 2463 2464static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2465 uint64_t Address, const void *Decoder) { 2466 // The immediate needs to be a fully instantiated float. However, the 2467 // auto-generated decoder is only able to fill in some of the bits 2468 // necessary. For instance, the 'b' bit is replicated multiple times, 2469 // and is even present in inverted form in one bit. We do a little 2470 // binary parsing here to fill in those missing bits, and then 2471 // reinterpret it all as a float. 2472 union { 2473 uint32_t integer; 2474 float fp; 2475 } fp_conv; 2476 2477 fp_conv.integer = Val; 2478 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2479 fp_conv.integer |= b << 26; 2480 fp_conv.integer |= b << 27; 2481 fp_conv.integer |= b << 28; 2482 fp_conv.integer |= b << 29; 2483 fp_conv.integer |= (~b & 0x1) << 30; 2484 2485 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2486 return MCDisassembler::Success; 2487} 2488 2489static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2490 uint64_t Address, const void *Decoder) { 2491 DecodeStatus S = MCDisassembler::Success; 2492 2493 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2494 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2495 2496 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2497 return MCDisassembler::Fail; 2498 2499 switch(Inst.getOpcode()) { 2500 default: 2501 return MCDisassembler::Fail; 2502 case ARM::tADR: 2503 break; // tADR does not explicitly represent the PC as an operand. 2504 case ARM::tADDrSPi: 2505 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2506 break; 2507 } 2508 2509 Inst.addOperand(MCOperand::CreateImm(imm)); 2510 return S; 2511} 2512 2513static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2514 uint64_t Address, const void *Decoder) { 2515 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2516 return MCDisassembler::Success; 2517} 2518 2519static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2520 uint64_t Address, const void *Decoder) { 2521 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2522 return MCDisassembler::Success; 2523} 2524 2525static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2526 uint64_t Address, const void *Decoder) { 2527 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2528 return MCDisassembler::Success; 2529} 2530 2531static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2532 uint64_t Address, const void *Decoder) { 2533 DecodeStatus S = MCDisassembler::Success; 2534 2535 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2536 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2537 2538 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2539 return MCDisassembler::Fail; 2540 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2541 return MCDisassembler::Fail; 2542 2543 return S; 2544} 2545 2546static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2547 uint64_t Address, const void *Decoder) { 2548 DecodeStatus S = MCDisassembler::Success; 2549 2550 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2551 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2552 2553 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2554 return MCDisassembler::Fail; 2555 Inst.addOperand(MCOperand::CreateImm(imm)); 2556 2557 return S; 2558} 2559 2560static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2561 uint64_t Address, const void *Decoder) { 2562 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2563 2564 return MCDisassembler::Success; 2565} 2566 2567static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2568 uint64_t Address, const void *Decoder) { 2569 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2570 Inst.addOperand(MCOperand::CreateImm(Val)); 2571 2572 return MCDisassembler::Success; 2573} 2574 2575static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2576 uint64_t Address, const void *Decoder) { 2577 DecodeStatus S = MCDisassembler::Success; 2578 2579 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2580 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2581 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2582 2583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2584 return MCDisassembler::Fail; 2585 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2586 return MCDisassembler::Fail; 2587 Inst.addOperand(MCOperand::CreateImm(imm)); 2588 2589 return S; 2590} 2591 2592static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2593 uint64_t Address, const void *Decoder) { 2594 DecodeStatus S = MCDisassembler::Success; 2595 2596 switch (Inst.getOpcode()) { 2597 case ARM::t2PLDs: 2598 case ARM::t2PLDWs: 2599 case ARM::t2PLIs: 2600 break; 2601 default: { 2602 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2604 return MCDisassembler::Fail; 2605 } 2606 } 2607 2608 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2609 if (Rn == 0xF) { 2610 switch (Inst.getOpcode()) { 2611 case ARM::t2LDRBs: 2612 Inst.setOpcode(ARM::t2LDRBpci); 2613 break; 2614 case ARM::t2LDRHs: 2615 Inst.setOpcode(ARM::t2LDRHpci); 2616 break; 2617 case ARM::t2LDRSHs: 2618 Inst.setOpcode(ARM::t2LDRSHpci); 2619 break; 2620 case ARM::t2LDRSBs: 2621 Inst.setOpcode(ARM::t2LDRSBpci); 2622 break; 2623 case ARM::t2PLDs: 2624 Inst.setOpcode(ARM::t2PLDi12); 2625 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2626 break; 2627 default: 2628 return MCDisassembler::Fail; 2629 } 2630 2631 int imm = fieldFromInstruction32(Insn, 0, 12); 2632 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2633 Inst.addOperand(MCOperand::CreateImm(imm)); 2634 2635 return S; 2636 } 2637 2638 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2639 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2640 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2641 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2642 return MCDisassembler::Fail; 2643 2644 return S; 2645} 2646 2647static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2648 uint64_t Address, const void *Decoder) { 2649 int imm = Val & 0xFF; 2650 if (!(Val & 0x100)) imm *= -1; 2651 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2652 2653 return MCDisassembler::Success; 2654} 2655 2656static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2657 uint64_t Address, const void *Decoder) { 2658 DecodeStatus S = MCDisassembler::Success; 2659 2660 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2661 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2662 2663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2664 return MCDisassembler::Fail; 2665 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2666 return MCDisassembler::Fail; 2667 2668 return S; 2669} 2670 2671static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2672 uint64_t Address, const void *Decoder) { 2673 int imm = Val & 0xFF; 2674 if (!(Val & 0x100)) imm *= -1; 2675 Inst.addOperand(MCOperand::CreateImm(imm)); 2676 2677 return MCDisassembler::Success; 2678} 2679 2680 2681static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2682 uint64_t Address, const void *Decoder) { 2683 DecodeStatus S = MCDisassembler::Success; 2684 2685 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2686 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2687 2688 // Some instructions always use an additive offset. 2689 switch (Inst.getOpcode()) { 2690 case ARM::t2LDRT: 2691 case ARM::t2LDRBT: 2692 case ARM::t2LDRHT: 2693 case ARM::t2LDRSBT: 2694 case ARM::t2LDRSHT: 2695 imm |= 0x100; 2696 break; 2697 default: 2698 break; 2699 } 2700 2701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2702 return MCDisassembler::Fail; 2703 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2704 return MCDisassembler::Fail; 2705 2706 return S; 2707} 2708 2709 2710static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2711 uint64_t Address, const void *Decoder) { 2712 DecodeStatus S = MCDisassembler::Success; 2713 2714 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2715 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2716 2717 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2718 return MCDisassembler::Fail; 2719 Inst.addOperand(MCOperand::CreateImm(imm)); 2720 2721 return S; 2722} 2723 2724 2725static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2726 uint64_t Address, const void *Decoder) { 2727 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2728 2729 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2730 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2731 Inst.addOperand(MCOperand::CreateImm(imm)); 2732 2733 return MCDisassembler::Success; 2734} 2735 2736static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2737 uint64_t Address, const void *Decoder) { 2738 DecodeStatus S = MCDisassembler::Success; 2739 2740 if (Inst.getOpcode() == ARM::tADDrSP) { 2741 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2742 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2743 2744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2745 return MCDisassembler::Fail; 2746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2747 return MCDisassembler::Fail; 2748 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2749 } else if (Inst.getOpcode() == ARM::tADDspr) { 2750 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2751 2752 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2753 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2755 return MCDisassembler::Fail; 2756 } 2757 2758 return S; 2759} 2760 2761static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2762 uint64_t Address, const void *Decoder) { 2763 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2764 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2765 2766 Inst.addOperand(MCOperand::CreateImm(imod)); 2767 Inst.addOperand(MCOperand::CreateImm(flags)); 2768 2769 return MCDisassembler::Success; 2770} 2771 2772static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2773 uint64_t Address, const void *Decoder) { 2774 DecodeStatus S = MCDisassembler::Success; 2775 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2776 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2777 2778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2779 return MCDisassembler::Fail; 2780 Inst.addOperand(MCOperand::CreateImm(add)); 2781 2782 return S; 2783} 2784 2785static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2786 uint64_t Address, const void *Decoder) { 2787 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2788 return MCDisassembler::Success; 2789} 2790 2791static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2792 uint64_t Address, const void *Decoder) { 2793 if (Val == 0xA || Val == 0xB) 2794 return MCDisassembler::Fail; 2795 2796 Inst.addOperand(MCOperand::CreateImm(Val)); 2797 return MCDisassembler::Success; 2798} 2799 2800static DecodeStatus 2801DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2802 uint64_t Address, const void *Decoder) { 2803 DecodeStatus S = MCDisassembler::Success; 2804 2805 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2806 if (pred == 0xE || pred == 0xF) { 2807 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 2808 switch (opc) { 2809 default: 2810 return MCDisassembler::Fail; 2811 case 0xf3bf8f4: 2812 Inst.setOpcode(ARM::t2DSB); 2813 break; 2814 case 0xf3bf8f5: 2815 Inst.setOpcode(ARM::t2DMB); 2816 break; 2817 case 0xf3bf8f6: 2818 Inst.setOpcode(ARM::t2ISB); 2819 break; 2820 } 2821 2822 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2823 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2824 } 2825 2826 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2827 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2828 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2829 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2830 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2831 2832 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 2833 return MCDisassembler::Fail; 2834 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2835 return MCDisassembler::Fail; 2836 2837 return S; 2838} 2839 2840// Decode a shifted immediate operand. These basically consist 2841// of an 8-bit value, and a 4-bit directive that specifies either 2842// a splat operation or a rotation. 2843static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2844 uint64_t Address, const void *Decoder) { 2845 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2846 if (ctrl == 0) { 2847 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2848 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2849 switch (byte) { 2850 case 0: 2851 Inst.addOperand(MCOperand::CreateImm(imm)); 2852 break; 2853 case 1: 2854 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2855 break; 2856 case 2: 2857 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2858 break; 2859 case 3: 2860 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2861 (imm << 8) | imm)); 2862 break; 2863 } 2864 } else { 2865 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2866 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2867 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2868 Inst.addOperand(MCOperand::CreateImm(imm)); 2869 } 2870 2871 return MCDisassembler::Success; 2872} 2873 2874static DecodeStatus 2875DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2876 uint64_t Address, const void *Decoder){ 2877 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2878 return MCDisassembler::Success; 2879} 2880 2881static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2882 uint64_t Address, const void *Decoder){ 2883 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2884 return MCDisassembler::Success; 2885} 2886 2887static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2888 uint64_t Address, const void *Decoder) { 2889 switch (Val) { 2890 default: 2891 return MCDisassembler::Fail; 2892 case 0xF: // SY 2893 case 0xE: // ST 2894 case 0xB: // ISH 2895 case 0xA: // ISHST 2896 case 0x7: // NSH 2897 case 0x6: // NSHST 2898 case 0x3: // OSH 2899 case 0x2: // OSHST 2900 break; 2901 } 2902 2903 Inst.addOperand(MCOperand::CreateImm(Val)); 2904 return MCDisassembler::Success; 2905} 2906 2907static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2908 uint64_t Address, const void *Decoder) { 2909 if (!Val) return MCDisassembler::Fail; 2910 Inst.addOperand(MCOperand::CreateImm(Val)); 2911 return MCDisassembler::Success; 2912} 2913 2914static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2915 uint64_t Address, const void *Decoder) { 2916 DecodeStatus S = MCDisassembler::Success; 2917 2918 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2919 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2920 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2921 2922 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2923 2924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2925 return MCDisassembler::Fail; 2926 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2927 return MCDisassembler::Fail; 2928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2929 return MCDisassembler::Fail; 2930 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2931 return MCDisassembler::Fail; 2932 2933 return S; 2934} 2935 2936 2937static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2938 uint64_t Address, const void *Decoder){ 2939 DecodeStatus S = MCDisassembler::Success; 2940 2941 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2942 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2943 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2944 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2945 2946 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2947 return MCDisassembler::Fail; 2948 2949 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 2950 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 2951 2952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2953 return MCDisassembler::Fail; 2954 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2955 return MCDisassembler::Fail; 2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2959 return MCDisassembler::Fail; 2960 2961 return S; 2962} 2963 2964static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 2965 uint64_t Address, const void *Decoder) { 2966 DecodeStatus S = MCDisassembler::Success; 2967 2968 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2969 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2970 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2971 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2972 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2973 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2974 2975 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 2976 2977 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2978 return MCDisassembler::Fail; 2979 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2980 return MCDisassembler::Fail; 2981 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 2982 return MCDisassembler::Fail; 2983 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 2986 return S; 2987} 2988 2989static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 2990 uint64_t Address, const void *Decoder) { 2991 DecodeStatus S = MCDisassembler::Success; 2992 2993 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2994 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2995 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2996 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2997 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2998 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2999 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3000 3001 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3002 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3003 3004 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3005 return MCDisassembler::Fail; 3006 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3007 return MCDisassembler::Fail; 3008 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3009 return MCDisassembler::Fail; 3010 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3011 return MCDisassembler::Fail; 3012 3013 return S; 3014} 3015 3016 3017static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3018 uint64_t Address, const void *Decoder) { 3019 DecodeStatus S = MCDisassembler::Success; 3020 3021 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3022 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3023 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3024 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3025 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3026 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3027 3028 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3029 3030 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3031 return MCDisassembler::Fail; 3032 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3033 return MCDisassembler::Fail; 3034 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3035 return MCDisassembler::Fail; 3036 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3037 return MCDisassembler::Fail; 3038 3039 return S; 3040} 3041 3042static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3043 uint64_t Address, const void *Decoder) { 3044 DecodeStatus S = MCDisassembler::Success; 3045 3046 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3047 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3048 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3049 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3050 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3051 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3052 3053 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3054 3055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3056 return MCDisassembler::Fail; 3057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3058 return MCDisassembler::Fail; 3059 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3060 return MCDisassembler::Fail; 3061 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3062 return MCDisassembler::Fail; 3063 3064 return S; 3065} 3066 3067static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3068 uint64_t Address, const void *Decoder) { 3069 DecodeStatus S = MCDisassembler::Success; 3070 3071 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3072 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3073 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3074 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3075 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3076 3077 unsigned align = 0; 3078 unsigned index = 0; 3079 switch (size) { 3080 default: 3081 return MCDisassembler::Fail; 3082 case 0: 3083 if (fieldFromInstruction32(Insn, 4, 1)) 3084 return MCDisassembler::Fail; // UNDEFINED 3085 index = fieldFromInstruction32(Insn, 5, 3); 3086 break; 3087 case 1: 3088 if (fieldFromInstruction32(Insn, 5, 1)) 3089 return MCDisassembler::Fail; // UNDEFINED 3090 index = fieldFromInstruction32(Insn, 6, 2); 3091 if (fieldFromInstruction32(Insn, 4, 1)) 3092 align = 2; 3093 break; 3094 case 2: 3095 if (fieldFromInstruction32(Insn, 6, 1)) 3096 return MCDisassembler::Fail; // UNDEFINED 3097 index = fieldFromInstruction32(Insn, 7, 1); 3098 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3099 align = 4; 3100 } 3101 3102 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3103 return MCDisassembler::Fail; 3104 if (Rm != 0xF) { // Writeback 3105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 } 3108 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3109 return MCDisassembler::Fail; 3110 Inst.addOperand(MCOperand::CreateImm(align)); 3111 if (Rm != 0xF) { 3112 if (Rm != 0xD) { 3113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3114 return MCDisassembler::Fail; 3115 } else 3116 Inst.addOperand(MCOperand::CreateReg(0)); 3117 } 3118 3119 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3120 return MCDisassembler::Fail; 3121 Inst.addOperand(MCOperand::CreateImm(index)); 3122 3123 return S; 3124} 3125 3126static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3127 uint64_t Address, const void *Decoder) { 3128 DecodeStatus S = MCDisassembler::Success; 3129 3130 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3131 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3132 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3133 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3134 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3135 3136 unsigned align = 0; 3137 unsigned index = 0; 3138 switch (size) { 3139 default: 3140 return MCDisassembler::Fail; 3141 case 0: 3142 if (fieldFromInstruction32(Insn, 4, 1)) 3143 return MCDisassembler::Fail; // UNDEFINED 3144 index = fieldFromInstruction32(Insn, 5, 3); 3145 break; 3146 case 1: 3147 if (fieldFromInstruction32(Insn, 5, 1)) 3148 return MCDisassembler::Fail; // UNDEFINED 3149 index = fieldFromInstruction32(Insn, 6, 2); 3150 if (fieldFromInstruction32(Insn, 4, 1)) 3151 align = 2; 3152 break; 3153 case 2: 3154 if (fieldFromInstruction32(Insn, 6, 1)) 3155 return MCDisassembler::Fail; // UNDEFINED 3156 index = fieldFromInstruction32(Insn, 7, 1); 3157 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3158 align = 4; 3159 } 3160 3161 if (Rm != 0xF) { // Writeback 3162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3163 return MCDisassembler::Fail; 3164 } 3165 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3166 return MCDisassembler::Fail; 3167 Inst.addOperand(MCOperand::CreateImm(align)); 3168 if (Rm != 0xF) { 3169 if (Rm != 0xD) { 3170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3171 return MCDisassembler::Fail; 3172 } else 3173 Inst.addOperand(MCOperand::CreateReg(0)); 3174 } 3175 3176 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3177 return MCDisassembler::Fail; 3178 Inst.addOperand(MCOperand::CreateImm(index)); 3179 3180 return S; 3181} 3182 3183 3184static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3185 uint64_t Address, const void *Decoder) { 3186 DecodeStatus S = MCDisassembler::Success; 3187 3188 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3189 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3190 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3191 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3192 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3193 3194 unsigned align = 0; 3195 unsigned index = 0; 3196 unsigned inc = 1; 3197 switch (size) { 3198 default: 3199 return MCDisassembler::Fail; 3200 case 0: 3201 index = fieldFromInstruction32(Insn, 5, 3); 3202 if (fieldFromInstruction32(Insn, 4, 1)) 3203 align = 2; 3204 break; 3205 case 1: 3206 index = fieldFromInstruction32(Insn, 6, 2); 3207 if (fieldFromInstruction32(Insn, 4, 1)) 3208 align = 4; 3209 if (fieldFromInstruction32(Insn, 5, 1)) 3210 inc = 2; 3211 break; 3212 case 2: 3213 if (fieldFromInstruction32(Insn, 5, 1)) 3214 return MCDisassembler::Fail; // UNDEFINED 3215 index = fieldFromInstruction32(Insn, 7, 1); 3216 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3217 align = 8; 3218 if (fieldFromInstruction32(Insn, 6, 1)) 3219 inc = 2; 3220 break; 3221 } 3222 3223 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3224 return MCDisassembler::Fail; 3225 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3226 return MCDisassembler::Fail; 3227 if (Rm != 0xF) { // Writeback 3228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 } 3231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3232 return MCDisassembler::Fail; 3233 Inst.addOperand(MCOperand::CreateImm(align)); 3234 if (Rm != 0xF) { 3235 if (Rm != 0xD) { 3236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3237 return MCDisassembler::Fail; 3238 } else 3239 Inst.addOperand(MCOperand::CreateReg(0)); 3240 } 3241 3242 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3243 return MCDisassembler::Fail; 3244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3245 return MCDisassembler::Fail; 3246 Inst.addOperand(MCOperand::CreateImm(index)); 3247 3248 return S; 3249} 3250 3251static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3252 uint64_t Address, const void *Decoder) { 3253 DecodeStatus S = MCDisassembler::Success; 3254 3255 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3256 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3257 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3258 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3259 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3260 3261 unsigned align = 0; 3262 unsigned index = 0; 3263 unsigned inc = 1; 3264 switch (size) { 3265 default: 3266 return MCDisassembler::Fail; 3267 case 0: 3268 index = fieldFromInstruction32(Insn, 5, 3); 3269 if (fieldFromInstruction32(Insn, 4, 1)) 3270 align = 2; 3271 break; 3272 case 1: 3273 index = fieldFromInstruction32(Insn, 6, 2); 3274 if (fieldFromInstruction32(Insn, 4, 1)) 3275 align = 4; 3276 if (fieldFromInstruction32(Insn, 5, 1)) 3277 inc = 2; 3278 break; 3279 case 2: 3280 if (fieldFromInstruction32(Insn, 5, 1)) 3281 return MCDisassembler::Fail; // UNDEFINED 3282 index = fieldFromInstruction32(Insn, 7, 1); 3283 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3284 align = 8; 3285 if (fieldFromInstruction32(Insn, 6, 1)) 3286 inc = 2; 3287 break; 3288 } 3289 3290 if (Rm != 0xF) { // Writeback 3291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 } 3294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3295 return MCDisassembler::Fail; 3296 Inst.addOperand(MCOperand::CreateImm(align)); 3297 if (Rm != 0xF) { 3298 if (Rm != 0xD) { 3299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3300 return MCDisassembler::Fail; 3301 } else 3302 Inst.addOperand(MCOperand::CreateReg(0)); 3303 } 3304 3305 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3308 return MCDisassembler::Fail; 3309 Inst.addOperand(MCOperand::CreateImm(index)); 3310 3311 return S; 3312} 3313 3314 3315static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3316 uint64_t Address, const void *Decoder) { 3317 DecodeStatus S = MCDisassembler::Success; 3318 3319 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3320 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3321 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3322 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3323 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3324 3325 unsigned align = 0; 3326 unsigned index = 0; 3327 unsigned inc = 1; 3328 switch (size) { 3329 default: 3330 return MCDisassembler::Fail; 3331 case 0: 3332 if (fieldFromInstruction32(Insn, 4, 1)) 3333 return MCDisassembler::Fail; // UNDEFINED 3334 index = fieldFromInstruction32(Insn, 5, 3); 3335 break; 3336 case 1: 3337 if (fieldFromInstruction32(Insn, 4, 1)) 3338 return MCDisassembler::Fail; // UNDEFINED 3339 index = fieldFromInstruction32(Insn, 6, 2); 3340 if (fieldFromInstruction32(Insn, 5, 1)) 3341 inc = 2; 3342 break; 3343 case 2: 3344 if (fieldFromInstruction32(Insn, 4, 2)) 3345 return MCDisassembler::Fail; // UNDEFINED 3346 index = fieldFromInstruction32(Insn, 7, 1); 3347 if (fieldFromInstruction32(Insn, 6, 1)) 3348 inc = 2; 3349 break; 3350 } 3351 3352 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3353 return MCDisassembler::Fail; 3354 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3357 return MCDisassembler::Fail; 3358 3359 if (Rm != 0xF) { // Writeback 3360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3361 return MCDisassembler::Fail; 3362 } 3363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3364 return MCDisassembler::Fail; 3365 Inst.addOperand(MCOperand::CreateImm(align)); 3366 if (Rm != 0xF) { 3367 if (Rm != 0xD) { 3368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3369 return MCDisassembler::Fail; 3370 } else 3371 Inst.addOperand(MCOperand::CreateReg(0)); 3372 } 3373 3374 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3375 return MCDisassembler::Fail; 3376 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3377 return MCDisassembler::Fail; 3378 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3379 return MCDisassembler::Fail; 3380 Inst.addOperand(MCOperand::CreateImm(index)); 3381 3382 return S; 3383} 3384 3385static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3386 uint64_t Address, const void *Decoder) { 3387 DecodeStatus S = MCDisassembler::Success; 3388 3389 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3390 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3391 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3392 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3393 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3394 3395 unsigned align = 0; 3396 unsigned index = 0; 3397 unsigned inc = 1; 3398 switch (size) { 3399 default: 3400 return MCDisassembler::Fail; 3401 case 0: 3402 if (fieldFromInstruction32(Insn, 4, 1)) 3403 return MCDisassembler::Fail; // UNDEFINED 3404 index = fieldFromInstruction32(Insn, 5, 3); 3405 break; 3406 case 1: 3407 if (fieldFromInstruction32(Insn, 4, 1)) 3408 return MCDisassembler::Fail; // UNDEFINED 3409 index = fieldFromInstruction32(Insn, 6, 2); 3410 if (fieldFromInstruction32(Insn, 5, 1)) 3411 inc = 2; 3412 break; 3413 case 2: 3414 if (fieldFromInstruction32(Insn, 4, 2)) 3415 return MCDisassembler::Fail; // UNDEFINED 3416 index = fieldFromInstruction32(Insn, 7, 1); 3417 if (fieldFromInstruction32(Insn, 6, 1)) 3418 inc = 2; 3419 break; 3420 } 3421 3422 if (Rm != 0xF) { // Writeback 3423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3424 return MCDisassembler::Fail; 3425 } 3426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3427 return MCDisassembler::Fail; 3428 Inst.addOperand(MCOperand::CreateImm(align)); 3429 if (Rm != 0xF) { 3430 if (Rm != 0xD) { 3431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3432 return MCDisassembler::Fail; 3433 } else 3434 Inst.addOperand(MCOperand::CreateReg(0)); 3435 } 3436 3437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3438 return MCDisassembler::Fail; 3439 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3440 return MCDisassembler::Fail; 3441 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 Inst.addOperand(MCOperand::CreateImm(index)); 3444 3445 return S; 3446} 3447 3448 3449static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3450 uint64_t Address, const void *Decoder) { 3451 DecodeStatus S = MCDisassembler::Success; 3452 3453 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3454 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3455 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3456 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3457 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3458 3459 unsigned align = 0; 3460 unsigned index = 0; 3461 unsigned inc = 1; 3462 switch (size) { 3463 default: 3464 return MCDisassembler::Fail; 3465 case 0: 3466 if (fieldFromInstruction32(Insn, 4, 1)) 3467 align = 4; 3468 index = fieldFromInstruction32(Insn, 5, 3); 3469 break; 3470 case 1: 3471 if (fieldFromInstruction32(Insn, 4, 1)) 3472 align = 8; 3473 index = fieldFromInstruction32(Insn, 6, 2); 3474 if (fieldFromInstruction32(Insn, 5, 1)) 3475 inc = 2; 3476 break; 3477 case 2: 3478 if (fieldFromInstruction32(Insn, 4, 2)) 3479 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3480 index = fieldFromInstruction32(Insn, 7, 1); 3481 if (fieldFromInstruction32(Insn, 6, 1)) 3482 inc = 2; 3483 break; 3484 } 3485 3486 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3487 return MCDisassembler::Fail; 3488 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3489 return MCDisassembler::Fail; 3490 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3491 return MCDisassembler::Fail; 3492 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3493 return MCDisassembler::Fail; 3494 3495 if (Rm != 0xF) { // Writeback 3496 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3497 return MCDisassembler::Fail; 3498 } 3499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 Inst.addOperand(MCOperand::CreateImm(align)); 3502 if (Rm != 0xF) { 3503 if (Rm != 0xD) { 3504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3505 return MCDisassembler::Fail; 3506 } else 3507 Inst.addOperand(MCOperand::CreateReg(0)); 3508 } 3509 3510 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3511 return MCDisassembler::Fail; 3512 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3513 return MCDisassembler::Fail; 3514 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3515 return MCDisassembler::Fail; 3516 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3517 return MCDisassembler::Fail; 3518 Inst.addOperand(MCOperand::CreateImm(index)); 3519 3520 return S; 3521} 3522 3523static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3524 uint64_t Address, const void *Decoder) { 3525 DecodeStatus S = MCDisassembler::Success; 3526 3527 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3528 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3529 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3530 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3531 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3532 3533 unsigned align = 0; 3534 unsigned index = 0; 3535 unsigned inc = 1; 3536 switch (size) { 3537 default: 3538 return MCDisassembler::Fail; 3539 case 0: 3540 if (fieldFromInstruction32(Insn, 4, 1)) 3541 align = 4; 3542 index = fieldFromInstruction32(Insn, 5, 3); 3543 break; 3544 case 1: 3545 if (fieldFromInstruction32(Insn, 4, 1)) 3546 align = 8; 3547 index = fieldFromInstruction32(Insn, 6, 2); 3548 if (fieldFromInstruction32(Insn, 5, 1)) 3549 inc = 2; 3550 break; 3551 case 2: 3552 if (fieldFromInstruction32(Insn, 4, 2)) 3553 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3554 index = fieldFromInstruction32(Insn, 7, 1); 3555 if (fieldFromInstruction32(Insn, 6, 1)) 3556 inc = 2; 3557 break; 3558 } 3559 3560 if (Rm != 0xF) { // Writeback 3561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3562 return MCDisassembler::Fail; 3563 } 3564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3565 return MCDisassembler::Fail; 3566 Inst.addOperand(MCOperand::CreateImm(align)); 3567 if (Rm != 0xF) { 3568 if (Rm != 0xD) { 3569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3570 return MCDisassembler::Fail; 3571 } else 3572 Inst.addOperand(MCOperand::CreateReg(0)); 3573 } 3574 3575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3576 return MCDisassembler::Fail; 3577 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3580 return MCDisassembler::Fail; 3581 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 Inst.addOperand(MCOperand::CreateImm(index)); 3584 3585 return S; 3586} 3587 3588static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3589 uint64_t Address, const void *Decoder) { 3590 DecodeStatus S = MCDisassembler::Success; 3591 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3592 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3593 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3594 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3595 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3596 3597 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3598 S = MCDisassembler::SoftFail; 3599 3600 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3601 return MCDisassembler::Fail; 3602 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3603 return MCDisassembler::Fail; 3604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3605 return MCDisassembler::Fail; 3606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3607 return MCDisassembler::Fail; 3608 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3609 return MCDisassembler::Fail; 3610 3611 return S; 3612} 3613 3614static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3615 uint64_t Address, const void *Decoder) { 3616 DecodeStatus S = MCDisassembler::Success; 3617 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3618 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3619 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3620 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3621 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3622 3623 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3624 S = MCDisassembler::SoftFail; 3625 3626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3629 return MCDisassembler::Fail; 3630 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3631 return MCDisassembler::Fail; 3632 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3633 return MCDisassembler::Fail; 3634 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 3637 return S; 3638} 3639 3640static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3641 uint64_t Address, const void *Decoder) { 3642 DecodeStatus S = MCDisassembler::Success; 3643 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3644 // The InstPrinter needs to have the low bit of the predicate in 3645 // the mask operand to be able to print it properly. 3646 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3647 3648 if (pred == 0xF) { 3649 pred = 0xE; 3650 S = MCDisassembler::SoftFail; 3651 } 3652 3653 if ((mask & 0xF) == 0) { 3654 // Preserve the high bit of the mask, which is the low bit of 3655 // the predicate. 3656 mask &= 0x10; 3657 mask |= 0x8; 3658 S = MCDisassembler::SoftFail; 3659 } 3660 3661 Inst.addOperand(MCOperand::CreateImm(pred)); 3662 Inst.addOperand(MCOperand::CreateImm(mask)); 3663 return S; 3664} 3665 3666static DecodeStatus 3667DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3668 uint64_t Address, const void *Decoder) { 3669 DecodeStatus S = MCDisassembler::Success; 3670 3671 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3672 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3673 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3674 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3675 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3676 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3677 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3678 bool writeback = (W == 1) | (P == 0); 3679 3680 addr |= (U << 8) | (Rn << 9); 3681 3682 if (writeback && (Rn == Rt || Rn == Rt2)) 3683 Check(S, MCDisassembler::SoftFail); 3684 if (Rt == Rt2) 3685 Check(S, MCDisassembler::SoftFail); 3686 3687 // Rt 3688 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3689 return MCDisassembler::Fail; 3690 // Rt2 3691 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3692 return MCDisassembler::Fail; 3693 // Writeback operand 3694 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3695 return MCDisassembler::Fail; 3696 // addr 3697 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3698 return MCDisassembler::Fail; 3699 3700 return S; 3701} 3702 3703static DecodeStatus 3704DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3705 uint64_t Address, const void *Decoder) { 3706 DecodeStatus S = MCDisassembler::Success; 3707 3708 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3709 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3710 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3711 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3712 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3713 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3714 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3715 bool writeback = (W == 1) | (P == 0); 3716 3717 addr |= (U << 8) | (Rn << 9); 3718 3719 if (writeback && (Rn == Rt || Rn == Rt2)) 3720 Check(S, MCDisassembler::SoftFail); 3721 3722 // Writeback operand 3723 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3724 return MCDisassembler::Fail; 3725 // Rt 3726 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3727 return MCDisassembler::Fail; 3728 // Rt2 3729 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3730 return MCDisassembler::Fail; 3731 // addr 3732 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3733 return MCDisassembler::Fail; 3734 3735 return S; 3736} 3737