ARMDisassembler.cpp revision e234d02204e0e546c3555e7e894b8521d22a2121
1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "arm-disassembler" 11 12#include "ARMDisassembler.h" 13#include "ARM.h" 14#include "ARMRegisterInfo.h" 15#include "MCTargetDesc/ARMAddressingModes.h" 16#include "MCTargetDesc/ARMBaseInfo.h" 17#include "llvm/MC/EDInstInfo.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCContext.h" 21#include "llvm/Target/TargetRegistry.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/MemoryObject.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/raw_ostream.h" 26 27// Pull DecodeStatus and its enum values into the global namespace. 28typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 29#define Success llvm::MCDisassembler::Success 30#define Unpredictable llvm::MCDisassembler::SoftFail 31#define Fail llvm::MCDisassembler::Fail 32 33// Helper macro to perform setwise reduction of the current running status 34// and another status, and return if the new status is Fail. 35#define CHECK(S,X) do { \ 36 S = (DecodeStatus) ((int)S & (X)); \ 37 if (S == Fail) return Fail; \ 38 } while(0) 39 40// Forward declare these because the autogenerated code will reference them. 41// Definitions are further down. 42static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 43 uint64_t Address, const void *Decoder); 44static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 45 unsigned RegNo, uint64_t Address, 46 const void *Decoder); 47static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 50 uint64_t Address, const void *Decoder); 51static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 52 uint64_t Address, const void *Decoder); 53static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 54 uint64_t Address, const void *Decoder); 55static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 56 uint64_t Address, const void *Decoder); 57static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 58 uint64_t Address, const void *Decoder); 59static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 60 unsigned RegNo, 61 uint64_t Address, 62 const void *Decoder); 63static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 64 uint64_t Address, const void *Decoder); 65 66static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 67 uint64_t Address, const void *Decoder); 68static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 69 uint64_t Address, const void *Decoder); 70static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 71 uint64_t Address, const void *Decoder); 72static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 73 uint64_t Address, const void *Decoder); 74static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 75 uint64_t Address, const void *Decoder); 76static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 77 uint64_t Address, const void *Decoder); 78static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 79 uint64_t Address, const void *Decoder); 80 81static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 82 uint64_t Address, const void *Decoder); 83static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 84 uint64_t Address, const void *Decoder); 85static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 86 unsigned Insn, 87 uint64_t Address, 88 const void *Decoder); 89static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 90 uint64_t Address, const void *Decoder); 91static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 92 uint64_t Address, const void *Decoder); 93static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 94 uint64_t Address, const void *Decoder); 95static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 96 uint64_t Address, const void *Decoder); 97 98static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 99 unsigned Insn, 100 uint64_t Adddress, 101 const void *Decoder); 102static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 103 uint64_t Address, const void *Decoder); 104static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 105 uint64_t Address, const void *Decoder); 106static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 107 uint64_t Address, const void *Decoder); 108static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 115 uint64_t Address, const void *Decoder); 116static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 125 uint64_t Address, const void *Decoder); 126static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 129 uint64_t Address, const void *Decoder); 130static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 131 uint64_t Address, const void *Decoder); 132static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 133 uint64_t Address, const void *Decoder); 134static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 143 uint64_t Address, const void *Decoder); 144static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 145 uint64_t Address, const void *Decoder); 146static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 147 uint64_t Address, const void *Decoder); 148static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 159 uint64_t Address, const void *Decoder); 160static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 179 uint64_t Address, const void *Decoder); 180static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 181 uint64_t Address, const void *Decoder); 182static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 183 uint64_t Address, const void *Decoder); 184 185static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 186 uint64_t Address, const void *Decoder); 187static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 204 uint64_t Address, const void *Decoder); 205static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 206 uint64_t Address, const void *Decoder); 207static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 208 uint64_t Address, const void *Decoder); 209static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 210 uint64_t Address, const void *Decoder); 211static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 212 uint64_t Address, const void *Decoder); 213static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 214 uint64_t Address, const void *Decoder); 215static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 216 uint64_t Address, const void *Decoder); 217static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 218 uint64_t Address, const void *Decoder); 219static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 222 uint64_t Address, const void *Decoder); 223static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 224 uint64_t Address, const void *Decoder); 225static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 226 uint64_t Address, const void *Decoder); 227static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 228 uint64_t Address, const void *Decoder); 229static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 234#include "ARMGenDisassemblerTables.inc" 235#include "ARMGenInstrInfo.inc" 236#include "ARMGenEDInfo.inc" 237 238using namespace llvm; 239 240static MCDisassembler *createARMDisassembler(const Target &T) { 241 return new ARMDisassembler; 242} 243 244static MCDisassembler *createThumbDisassembler(const Target &T) { 245 return new ThumbDisassembler; 246} 247 248EDInstInfo *ARMDisassembler::getEDInfo() const { 249 return instInfoARM; 250} 251 252EDInstInfo *ThumbDisassembler::getEDInfo() const { 253 return instInfoARM; 254} 255 256DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 257 const MemoryObject &Region, 258 uint64_t Address, 259 raw_ostream &os) const { 260 uint8_t bytes[4]; 261 262 // We want to read exactly 4 bytes of data. 263 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 264 return Fail; 265 266 // Encoded as a small-endian 32-bit word in the stream. 267 uint32_t insn = (bytes[3] << 24) | 268 (bytes[2] << 16) | 269 (bytes[1] << 8) | 270 (bytes[0] << 0); 271 272 // Calling the auto-generated decoder function. 273 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); 274 if (result != Fail) { 275 Size = 4; 276 return result; 277 } 278 279 // Instructions that are shared between ARM and Thumb modes. 280 // FIXME: This shouldn't really exist. It's an artifact of the 281 // fact that we fail to encode a few instructions properly for Thumb. 282 MI.clear(); 283 result = decodeCommonInstruction32(MI, insn, Address, this); 284 if (result != Fail) { 285 Size = 4; 286 return result; 287 } 288 289 // VFP and NEON instructions, similarly, are shared between ARM 290 // and Thumb modes. 291 MI.clear(); 292 result = decodeVFPInstruction32(MI, insn, Address, this); 293 if (result != Fail) { 294 Size = 4; 295 return result; 296 } 297 298 MI.clear(); 299 result = decodeNEONDataInstruction32(MI, insn, Address, this); 300 if (result != Fail) { 301 Size = 4; 302 // Add a fake predicate operand, because we share these instruction 303 // definitions with Thumb2 where these instructions are predicable. 304 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 305 return result; 306 } 307 308 MI.clear(); 309 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 310 if (result != Fail) { 311 Size = 4; 312 // Add a fake predicate operand, because we share these instruction 313 // definitions with Thumb2 where these instructions are predicable. 314 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 315 return result; 316 } 317 318 MI.clear(); 319 result = decodeNEONDupInstruction32(MI, insn, Address, this); 320 if (result != Fail) { 321 Size = 4; 322 // Add a fake predicate operand, because we share these instruction 323 // definitions with Thumb2 where these instructions are predicable. 324 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 325 return result; 326 } 327 328 MI.clear(); 329 330 return Fail; 331} 332 333namespace llvm { 334extern MCInstrDesc ARMInsts[]; 335} 336 337// Thumb1 instructions don't have explicit S bits. Rather, they 338// implicitly set CPSR. Since it's not represented in the encoding, the 339// auto-generated decoder won't inject the CPSR operand. We need to fix 340// that as a post-pass. 341static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 342 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 343 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 344 MCInst::iterator I = MI.begin(); 345 for (unsigned i = 0; i < NumOps; ++i, ++I) { 346 if (I == MI.end()) break; 347 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 348 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 349 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 350 return; 351 } 352 } 353 354 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 355} 356 357// Most Thumb instructions don't have explicit predicates in the 358// encoding, but rather get their predicates from IT context. We need 359// to fix up the predicate operands using this context information as a 360// post-pass. 361void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 362 // A few instructions actually have predicates encoded in them. Don't 363 // try to overwrite it if we're seeing one of those. 364 switch (MI.getOpcode()) { 365 case ARM::tBcc: 366 case ARM::t2Bcc: 367 return; 368 default: 369 break; 370 } 371 372 // If we're in an IT block, base the predicate on that. Otherwise, 373 // assume a predicate of AL. 374 unsigned CC; 375 if (!ITBlock.empty()) { 376 CC = ITBlock.back(); 377 ITBlock.pop_back(); 378 } else 379 CC = ARMCC::AL; 380 381 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 382 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 383 MCInst::iterator I = MI.begin(); 384 for (unsigned i = 0; i < NumOps; ++i, ++I) { 385 if (I == MI.end()) break; 386 if (OpInfo[i].isPredicate()) { 387 I = MI.insert(I, MCOperand::CreateImm(CC)); 388 ++I; 389 if (CC == ARMCC::AL) 390 MI.insert(I, MCOperand::CreateReg(0)); 391 else 392 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 393 return; 394 } 395 } 396 397 I = MI.insert(I, MCOperand::CreateImm(CC)); 398 ++I; 399 if (CC == ARMCC::AL) 400 MI.insert(I, MCOperand::CreateReg(0)); 401 else 402 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 403} 404 405// Thumb VFP instructions are a special case. Because we share their 406// encodings between ARM and Thumb modes, and they are predicable in ARM 407// mode, the auto-generated decoder will give them an (incorrect) 408// predicate operand. We need to rewrite these operands based on the IT 409// context as a post-pass. 410void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 411 unsigned CC; 412 if (!ITBlock.empty()) { 413 CC = ITBlock.back(); 414 ITBlock.pop_back(); 415 } else 416 CC = ARMCC::AL; 417 418 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 419 MCInst::iterator I = MI.begin(); 420 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 421 if (OpInfo[i].isPredicate() ) { 422 I->setImm(CC); 423 ++I; 424 if (CC == ARMCC::AL) 425 I->setReg(0); 426 else 427 I->setReg(ARM::CPSR); 428 return; 429 } 430 } 431} 432 433DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 434 const MemoryObject &Region, 435 uint64_t Address, 436 raw_ostream &os) const { 437 uint8_t bytes[4]; 438 439 // We want to read exactly 2 bytes of data. 440 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 441 return Fail; 442 443 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 444 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); 445 if (result != Fail) { 446 Size = 2; 447 AddThumbPredicate(MI); 448 return result; 449 } 450 451 MI.clear(); 452 result = decodeThumbSBitInstruction16(MI, insn16, Address, this); 453 if (result) { 454 Size = 2; 455 bool InITBlock = !ITBlock.empty(); 456 AddThumbPredicate(MI); 457 AddThumb1SBit(MI, InITBlock); 458 return result; 459 } 460 461 MI.clear(); 462 result = decodeThumb2Instruction16(MI, insn16, Address, this); 463 if (result != Fail) { 464 Size = 2; 465 AddThumbPredicate(MI); 466 467 // If we find an IT instruction, we need to parse its condition 468 // code and mask operands so that we can apply them correctly 469 // to the subsequent instructions. 470 if (MI.getOpcode() == ARM::t2IT) { 471 unsigned firstcond = MI.getOperand(0).getImm(); 472 uint32_t mask = MI.getOperand(1).getImm(); 473 unsigned zeros = CountTrailingZeros_32(mask); 474 mask >>= zeros+1; 475 476 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 477 if (firstcond ^ (mask & 1)) 478 ITBlock.push_back(firstcond ^ 1); 479 else 480 ITBlock.push_back(firstcond); 481 mask >>= 1; 482 } 483 ITBlock.push_back(firstcond); 484 } 485 486 return result; 487 } 488 489 // We want to read exactly 4 bytes of data. 490 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 491 return Fail; 492 493 uint32_t insn32 = (bytes[3] << 8) | 494 (bytes[2] << 0) | 495 (bytes[1] << 24) | 496 (bytes[0] << 16); 497 MI.clear(); 498 result = decodeThumbInstruction32(MI, insn32, Address, this); 499 if (result != Fail) { 500 Size = 4; 501 bool InITBlock = ITBlock.size(); 502 AddThumbPredicate(MI); 503 AddThumb1SBit(MI, InITBlock); 504 return result; 505 } 506 507 MI.clear(); 508 result = decodeThumb2Instruction32(MI, insn32, Address, this); 509 if (result != Fail) { 510 Size = 4; 511 AddThumbPredicate(MI); 512 return result; 513 } 514 515 MI.clear(); 516 result = decodeCommonInstruction32(MI, insn32, Address, this); 517 if (result != Fail) { 518 Size = 4; 519 AddThumbPredicate(MI); 520 return result; 521 } 522 523 MI.clear(); 524 result = decodeVFPInstruction32(MI, insn32, Address, this); 525 if (result != Fail) { 526 Size = 4; 527 UpdateThumbVFPPredicate(MI); 528 return result; 529 } 530 531 MI.clear(); 532 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 533 if (result != Fail) { 534 Size = 4; 535 AddThumbPredicate(MI); 536 return result; 537 } 538 539 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 540 MI.clear(); 541 uint32_t NEONLdStInsn = insn32; 542 NEONLdStInsn &= 0xF0FFFFFF; 543 NEONLdStInsn |= 0x04000000; 544 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 545 if (result != Fail) { 546 Size = 4; 547 AddThumbPredicate(MI); 548 return result; 549 } 550 } 551 552 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 553 MI.clear(); 554 uint32_t NEONDataInsn = insn32; 555 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 556 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 557 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 558 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 559 if (result != Fail) { 560 Size = 4; 561 AddThumbPredicate(MI); 562 return result; 563 } 564 } 565 566 return Fail; 567} 568 569 570extern "C" void LLVMInitializeARMDisassembler() { 571 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 572 createARMDisassembler); 573 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 574 createThumbDisassembler); 575} 576 577static const unsigned GPRDecoderTable[] = { 578 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 579 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 580 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 581 ARM::R12, ARM::SP, ARM::LR, ARM::PC 582}; 583 584static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 585 uint64_t Address, const void *Decoder) { 586 if (RegNo > 15) 587 return Fail; 588 589 unsigned Register = GPRDecoderTable[RegNo]; 590 Inst.addOperand(MCOperand::CreateReg(Register)); 591 return Success; 592} 593 594static DecodeStatus 595DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 596 uint64_t Address, const void *Decoder) { 597 if (RegNo == 15) return Fail; 598 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 599} 600 601static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 602 uint64_t Address, const void *Decoder) { 603 if (RegNo > 7) 604 return Fail; 605 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 606} 607 608static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 609 uint64_t Address, const void *Decoder) { 610 unsigned Register = 0; 611 switch (RegNo) { 612 case 0: 613 Register = ARM::R0; 614 break; 615 case 1: 616 Register = ARM::R1; 617 break; 618 case 2: 619 Register = ARM::R2; 620 break; 621 case 3: 622 Register = ARM::R3; 623 break; 624 case 9: 625 Register = ARM::R9; 626 break; 627 case 12: 628 Register = ARM::R12; 629 break; 630 default: 631 return Fail; 632 } 633 634 Inst.addOperand(MCOperand::CreateReg(Register)); 635 return Success; 636} 637 638static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 639 uint64_t Address, const void *Decoder) { 640 if (RegNo == 13 || RegNo == 15) return Fail; 641 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 642} 643 644static const unsigned SPRDecoderTable[] = { 645 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 646 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 647 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 648 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 649 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 650 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 651 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 652 ARM::S28, ARM::S29, ARM::S30, ARM::S31 653}; 654 655static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 656 uint64_t Address, const void *Decoder) { 657 if (RegNo > 31) 658 return Fail; 659 660 unsigned Register = SPRDecoderTable[RegNo]; 661 Inst.addOperand(MCOperand::CreateReg(Register)); 662 return Success; 663} 664 665static const unsigned DPRDecoderTable[] = { 666 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 667 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 668 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 669 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 670 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 671 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 672 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 673 ARM::D28, ARM::D29, ARM::D30, ARM::D31 674}; 675 676static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 677 uint64_t Address, const void *Decoder) { 678 if (RegNo > 31) 679 return Fail; 680 681 unsigned Register = DPRDecoderTable[RegNo]; 682 Inst.addOperand(MCOperand::CreateReg(Register)); 683 return Success; 684} 685 686static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 687 uint64_t Address, const void *Decoder) { 688 if (RegNo > 7) 689 return Fail; 690 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 691} 692 693static DecodeStatus 694DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 695 uint64_t Address, const void *Decoder) { 696 if (RegNo > 15) 697 return Fail; 698 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 699} 700 701static const unsigned QPRDecoderTable[] = { 702 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 703 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 704 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 705 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 706}; 707 708 709static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 710 uint64_t Address, const void *Decoder) { 711 if (RegNo > 31) 712 return Fail; 713 RegNo >>= 1; 714 715 unsigned Register = QPRDecoderTable[RegNo]; 716 Inst.addOperand(MCOperand::CreateReg(Register)); 717 return Success; 718} 719 720static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 721 uint64_t Address, const void *Decoder) { 722 if (Val == 0xF) return Fail; 723 // AL predicate is not allowed on Thumb1 branches. 724 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 725 return Fail; 726 Inst.addOperand(MCOperand::CreateImm(Val)); 727 if (Val == ARMCC::AL) { 728 Inst.addOperand(MCOperand::CreateReg(0)); 729 } else 730 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 731 return Success; 732} 733 734static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 735 uint64_t Address, const void *Decoder) { 736 if (Val) 737 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 738 else 739 Inst.addOperand(MCOperand::CreateReg(0)); 740 return Success; 741} 742 743static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 744 uint64_t Address, const void *Decoder) { 745 uint32_t imm = Val & 0xFF; 746 uint32_t rot = (Val & 0xF00) >> 7; 747 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 748 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 749 return Success; 750} 751 752static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 753 uint64_t Address, const void *Decoder) { 754 Val <<= 2; 755 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 756 return Success; 757} 758 759static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 760 uint64_t Address, const void *Decoder) { 761 DecodeStatus S = Success; 762 763 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 764 unsigned type = fieldFromInstruction32(Val, 5, 2); 765 unsigned imm = fieldFromInstruction32(Val, 7, 5); 766 767 // Register-immediate 768 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 769 770 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 771 switch (type) { 772 case 0: 773 Shift = ARM_AM::lsl; 774 break; 775 case 1: 776 Shift = ARM_AM::lsr; 777 break; 778 case 2: 779 Shift = ARM_AM::asr; 780 break; 781 case 3: 782 Shift = ARM_AM::ror; 783 break; 784 } 785 786 if (Shift == ARM_AM::ror && imm == 0) 787 Shift = ARM_AM::rrx; 788 789 unsigned Op = Shift | (imm << 3); 790 Inst.addOperand(MCOperand::CreateImm(Op)); 791 792 return S; 793} 794 795static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 796 uint64_t Address, const void *Decoder) { 797 DecodeStatus S = Success; 798 799 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 800 unsigned type = fieldFromInstruction32(Val, 5, 2); 801 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 802 803 // Register-register 804 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 805 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); 806 807 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 808 switch (type) { 809 case 0: 810 Shift = ARM_AM::lsl; 811 break; 812 case 1: 813 Shift = ARM_AM::lsr; 814 break; 815 case 2: 816 Shift = ARM_AM::asr; 817 break; 818 case 3: 819 Shift = ARM_AM::ror; 820 break; 821 } 822 823 Inst.addOperand(MCOperand::CreateImm(Shift)); 824 825 return S; 826} 827 828static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 829 uint64_t Address, const void *Decoder) { 830 DecodeStatus S = Success; 831 832 // Empty register lists are not allowed. 833 if (CountPopulation_32(Val) == 0) return Fail; 834 for (unsigned i = 0; i < 16; ++i) { 835 if (Val & (1 << i)) { 836 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); 837 } 838 } 839 840 return S; 841} 842 843static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 844 uint64_t Address, const void *Decoder) { 845 DecodeStatus S = Success; 846 847 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 848 unsigned regs = Val & 0xFF; 849 850 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); 851 for (unsigned i = 0; i < (regs - 1); ++i) { 852 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); 853 } 854 855 return S; 856} 857 858static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 859 uint64_t Address, const void *Decoder) { 860 DecodeStatus S = Success; 861 862 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 863 unsigned regs = (Val & 0xFF) / 2; 864 865 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); 866 for (unsigned i = 0; i < (regs - 1); ++i) { 867 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); 868 } 869 870 return S; 871} 872 873static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 874 uint64_t Address, const void *Decoder) { 875 // This operand encodes a mask of contiguous zeros between a specified MSB 876 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 877 // the mask of all bits LSB-and-lower, and then xor them to create 878 // the mask of that's all ones on [msb, lsb]. Finally we not it to 879 // create the final mask. 880 unsigned msb = fieldFromInstruction32(Val, 5, 5); 881 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 882 uint32_t msb_mask = (1 << (msb+1)) - 1; 883 uint32_t lsb_mask = (1 << lsb) - 1; 884 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 885 return Success; 886} 887 888static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 889 uint64_t Address, const void *Decoder) { 890 DecodeStatus S = Success; 891 892 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 893 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 894 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 895 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 896 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 897 unsigned U = fieldFromInstruction32(Insn, 23, 1); 898 899 switch (Inst.getOpcode()) { 900 case ARM::LDC_OFFSET: 901 case ARM::LDC_PRE: 902 case ARM::LDC_POST: 903 case ARM::LDC_OPTION: 904 case ARM::LDCL_OFFSET: 905 case ARM::LDCL_PRE: 906 case ARM::LDCL_POST: 907 case ARM::LDCL_OPTION: 908 case ARM::STC_OFFSET: 909 case ARM::STC_PRE: 910 case ARM::STC_POST: 911 case ARM::STC_OPTION: 912 case ARM::STCL_OFFSET: 913 case ARM::STCL_PRE: 914 case ARM::STCL_POST: 915 case ARM::STCL_OPTION: 916 if (coproc == 0xA || coproc == 0xB) 917 return Fail; 918 break; 919 default: 920 break; 921 } 922 923 Inst.addOperand(MCOperand::CreateImm(coproc)); 924 Inst.addOperand(MCOperand::CreateImm(CRd)); 925 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 926 switch (Inst.getOpcode()) { 927 case ARM::LDC_OPTION: 928 case ARM::LDCL_OPTION: 929 case ARM::LDC2_OPTION: 930 case ARM::LDC2L_OPTION: 931 case ARM::STC_OPTION: 932 case ARM::STCL_OPTION: 933 case ARM::STC2_OPTION: 934 case ARM::STC2L_OPTION: 935 case ARM::LDCL_POST: 936 case ARM::STCL_POST: 937 case ARM::LDC2L_POST: 938 case ARM::STC2L_POST: 939 break; 940 default: 941 Inst.addOperand(MCOperand::CreateReg(0)); 942 break; 943 } 944 945 unsigned P = fieldFromInstruction32(Insn, 24, 1); 946 unsigned W = fieldFromInstruction32(Insn, 21, 1); 947 948 bool writeback = (P == 0) || (W == 1); 949 unsigned idx_mode = 0; 950 if (P && writeback) 951 idx_mode = ARMII::IndexModePre; 952 else if (!P && writeback) 953 idx_mode = ARMII::IndexModePost; 954 955 switch (Inst.getOpcode()) { 956 case ARM::LDCL_POST: 957 case ARM::STCL_POST: 958 case ARM::LDC2L_POST: 959 case ARM::STC2L_POST: 960 imm |= U << 8; 961 case ARM::LDC_OPTION: 962 case ARM::LDCL_OPTION: 963 case ARM::LDC2_OPTION: 964 case ARM::LDC2L_OPTION: 965 case ARM::STC_OPTION: 966 case ARM::STCL_OPTION: 967 case ARM::STC2_OPTION: 968 case ARM::STC2L_OPTION: 969 Inst.addOperand(MCOperand::CreateImm(imm)); 970 break; 971 default: 972 if (U) 973 Inst.addOperand(MCOperand::CreateImm( 974 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 975 else 976 Inst.addOperand(MCOperand::CreateImm( 977 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 978 break; 979 } 980 981 switch (Inst.getOpcode()) { 982 case ARM::LDC_OFFSET: 983 case ARM::LDC_PRE: 984 case ARM::LDC_POST: 985 case ARM::LDC_OPTION: 986 case ARM::LDCL_OFFSET: 987 case ARM::LDCL_PRE: 988 case ARM::LDCL_POST: 989 case ARM::LDCL_OPTION: 990 case ARM::STC_OFFSET: 991 case ARM::STC_PRE: 992 case ARM::STC_POST: 993 case ARM::STC_OPTION: 994 case ARM::STCL_OFFSET: 995 case ARM::STCL_PRE: 996 case ARM::STCL_POST: 997 case ARM::STCL_OPTION: 998 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 999 break; 1000 default: 1001 break; 1002 } 1003 1004 return S; 1005} 1006 1007static DecodeStatus 1008DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1009 uint64_t Address, const void *Decoder) { 1010 DecodeStatus S = Success; 1011 1012 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1013 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1014 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1015 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1016 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1017 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1018 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1019 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1020 1021 // On stores, the writeback operand precedes Rt. 1022 switch (Inst.getOpcode()) { 1023 case ARM::STR_POST_IMM: 1024 case ARM::STR_POST_REG: 1025 case ARM::STRB_POST_IMM: 1026 case ARM::STRB_POST_REG: 1027 case ARM::STRT_POST_REG: 1028 case ARM::STRT_POST_IMM: 1029 case ARM::STRBT_POST_REG: 1030 case ARM::STRBT_POST_IMM: 1031 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1032 break; 1033 default: 1034 break; 1035 } 1036 1037 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1038 1039 // On loads, the writeback operand comes after Rt. 1040 switch (Inst.getOpcode()) { 1041 case ARM::LDR_POST_IMM: 1042 case ARM::LDR_POST_REG: 1043 case ARM::LDRB_POST_IMM: 1044 case ARM::LDRB_POST_REG: 1045 case ARM::LDR_PRE: 1046 case ARM::LDRB_PRE: 1047 case ARM::LDRBT_POST_REG: 1048 case ARM::LDRBT_POST_IMM: 1049 case ARM::LDRT_POST_REG: 1050 case ARM::LDRT_POST_IMM: 1051 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1052 break; 1053 default: 1054 break; 1055 } 1056 1057 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1058 1059 ARM_AM::AddrOpc Op = ARM_AM::add; 1060 if (!fieldFromInstruction32(Insn, 23, 1)) 1061 Op = ARM_AM::sub; 1062 1063 bool writeback = (P == 0) || (W == 1); 1064 unsigned idx_mode = 0; 1065 if (P && writeback) 1066 idx_mode = ARMII::IndexModePre; 1067 else if (!P && writeback) 1068 idx_mode = ARMII::IndexModePost; 1069 1070 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE 1071 1072 if (reg) { 1073 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1074 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1075 switch( fieldFromInstruction32(Insn, 5, 2)) { 1076 case 0: 1077 Opc = ARM_AM::lsl; 1078 break; 1079 case 1: 1080 Opc = ARM_AM::lsr; 1081 break; 1082 case 2: 1083 Opc = ARM_AM::asr; 1084 break; 1085 case 3: 1086 Opc = ARM_AM::ror; 1087 break; 1088 default: 1089 return Fail; 1090 } 1091 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1092 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1093 1094 Inst.addOperand(MCOperand::CreateImm(imm)); 1095 } else { 1096 Inst.addOperand(MCOperand::CreateReg(0)); 1097 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1098 Inst.addOperand(MCOperand::CreateImm(tmp)); 1099 } 1100 1101 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1102 1103 return S; 1104} 1105 1106static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1107 uint64_t Address, const void *Decoder) { 1108 DecodeStatus S = Success; 1109 1110 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1111 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1112 unsigned type = fieldFromInstruction32(Val, 5, 2); 1113 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1114 unsigned U = fieldFromInstruction32(Val, 12, 1); 1115 1116 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1117 switch (type) { 1118 case 0: 1119 ShOp = ARM_AM::lsl; 1120 break; 1121 case 1: 1122 ShOp = ARM_AM::lsr; 1123 break; 1124 case 2: 1125 ShOp = ARM_AM::asr; 1126 break; 1127 case 3: 1128 ShOp = ARM_AM::ror; 1129 break; 1130 } 1131 1132 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1133 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1134 unsigned shift; 1135 if (U) 1136 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1137 else 1138 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1139 Inst.addOperand(MCOperand::CreateImm(shift)); 1140 1141 return S; 1142} 1143 1144static DecodeStatus 1145DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1146 uint64_t Address, const void *Decoder) { 1147 DecodeStatus S = Success; 1148 1149 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1150 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1151 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1152 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1153 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1154 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1155 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1156 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1157 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1158 1159 bool writeback = (W == 1) | (P == 0); 1160 1161 // For {LD,ST}RD, Rt must be even, else undefined. 1162 switch (Inst.getOpcode()) { 1163 case ARM::STRD: 1164 case ARM::STRD_PRE: 1165 case ARM::STRD_POST: 1166 case ARM::LDRD: 1167 case ARM::LDRD_PRE: 1168 case ARM::LDRD_POST: 1169 if (Rt & 0x1) return Fail; 1170 break; 1171 default: 1172 break; 1173 } 1174 1175 if (writeback) { // Writeback 1176 if (P) 1177 U |= ARMII::IndexModePre << 9; 1178 else 1179 U |= ARMII::IndexModePost << 9; 1180 1181 // On stores, the writeback operand precedes Rt. 1182 switch (Inst.getOpcode()) { 1183 case ARM::STRD: 1184 case ARM::STRD_PRE: 1185 case ARM::STRD_POST: 1186 case ARM::STRH: 1187 case ARM::STRH_PRE: 1188 case ARM::STRH_POST: 1189 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1190 break; 1191 default: 1192 break; 1193 } 1194 } 1195 1196 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1197 switch (Inst.getOpcode()) { 1198 case ARM::STRD: 1199 case ARM::STRD_PRE: 1200 case ARM::STRD_POST: 1201 case ARM::LDRD: 1202 case ARM::LDRD_PRE: 1203 case ARM::LDRD_POST: 1204 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 1205 break; 1206 default: 1207 break; 1208 } 1209 1210 if (writeback) { 1211 // On loads, the writeback operand comes after Rt. 1212 switch (Inst.getOpcode()) { 1213 case ARM::LDRD: 1214 case ARM::LDRD_PRE: 1215 case ARM::LDRD_POST: 1216 case ARM::LDRH: 1217 case ARM::LDRH_PRE: 1218 case ARM::LDRH_POST: 1219 case ARM::LDRSH: 1220 case ARM::LDRSH_PRE: 1221 case ARM::LDRSH_POST: 1222 case ARM::LDRSB: 1223 case ARM::LDRSB_PRE: 1224 case ARM::LDRSB_POST: 1225 case ARM::LDRHTr: 1226 case ARM::LDRSBTr: 1227 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1228 break; 1229 default: 1230 break; 1231 } 1232 } 1233 1234 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1235 1236 if (type) { 1237 Inst.addOperand(MCOperand::CreateReg(0)); 1238 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1239 } else { 1240 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1241 Inst.addOperand(MCOperand::CreateImm(U)); 1242 } 1243 1244 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1245 1246 return S; 1247} 1248 1249static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1250 uint64_t Address, const void *Decoder) { 1251 DecodeStatus S = Success; 1252 1253 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1254 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1255 1256 switch (mode) { 1257 case 0: 1258 mode = ARM_AM::da; 1259 break; 1260 case 1: 1261 mode = ARM_AM::ia; 1262 break; 1263 case 2: 1264 mode = ARM_AM::db; 1265 break; 1266 case 3: 1267 mode = ARM_AM::ib; 1268 break; 1269 } 1270 1271 Inst.addOperand(MCOperand::CreateImm(mode)); 1272 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1273 1274 return S; 1275} 1276 1277static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1278 unsigned Insn, 1279 uint64_t Address, const void *Decoder) { 1280 DecodeStatus S = Success; 1281 1282 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1283 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1284 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1285 1286 if (pred == 0xF) { 1287 switch (Inst.getOpcode()) { 1288 case ARM::LDMDA: 1289 Inst.setOpcode(ARM::RFEDA); 1290 break; 1291 case ARM::LDMDA_UPD: 1292 Inst.setOpcode(ARM::RFEDA_UPD); 1293 break; 1294 case ARM::LDMDB: 1295 Inst.setOpcode(ARM::RFEDB); 1296 break; 1297 case ARM::LDMDB_UPD: 1298 Inst.setOpcode(ARM::RFEDB_UPD); 1299 break; 1300 case ARM::LDMIA: 1301 Inst.setOpcode(ARM::RFEIA); 1302 break; 1303 case ARM::LDMIA_UPD: 1304 Inst.setOpcode(ARM::RFEIA_UPD); 1305 break; 1306 case ARM::LDMIB: 1307 Inst.setOpcode(ARM::RFEIB); 1308 break; 1309 case ARM::LDMIB_UPD: 1310 Inst.setOpcode(ARM::RFEIB_UPD); 1311 break; 1312 case ARM::STMDA: 1313 Inst.setOpcode(ARM::SRSDA); 1314 break; 1315 case ARM::STMDA_UPD: 1316 Inst.setOpcode(ARM::SRSDA_UPD); 1317 break; 1318 case ARM::STMDB: 1319 Inst.setOpcode(ARM::SRSDB); 1320 break; 1321 case ARM::STMDB_UPD: 1322 Inst.setOpcode(ARM::SRSDB_UPD); 1323 break; 1324 case ARM::STMIA: 1325 Inst.setOpcode(ARM::SRSIA); 1326 break; 1327 case ARM::STMIA_UPD: 1328 Inst.setOpcode(ARM::SRSIA_UPD); 1329 break; 1330 case ARM::STMIB: 1331 Inst.setOpcode(ARM::SRSIB); 1332 break; 1333 case ARM::STMIB_UPD: 1334 Inst.setOpcode(ARM::SRSIB_UPD); 1335 break; 1336 default: 1337 CHECK(S, Fail); 1338 } 1339 1340 // For stores (which become SRS's, the only operand is the mode. 1341 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1342 Inst.addOperand( 1343 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1344 return S; 1345 } 1346 1347 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1348 } 1349 1350 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1351 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied 1352 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1353 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); 1354 1355 return S; 1356} 1357 1358static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1359 uint64_t Address, const void *Decoder) { 1360 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1361 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1362 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1363 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1364 1365 DecodeStatus S = Success; 1366 1367 // imod == '01' --> UNPREDICTABLE 1368 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1369 // return failure here. The '01' imod value is unprintable, so there's 1370 // nothing useful we could do even if we returned UNPREDICTABLE. 1371 1372 if (imod == 1) CHECK(S, Fail); 1373 1374 if (imod && M) { 1375 Inst.setOpcode(ARM::CPS3p); 1376 Inst.addOperand(MCOperand::CreateImm(imod)); 1377 Inst.addOperand(MCOperand::CreateImm(iflags)); 1378 Inst.addOperand(MCOperand::CreateImm(mode)); 1379 } else if (imod && !M) { 1380 Inst.setOpcode(ARM::CPS2p); 1381 Inst.addOperand(MCOperand::CreateImm(imod)); 1382 Inst.addOperand(MCOperand::CreateImm(iflags)); 1383 if (mode) CHECK(S, Unpredictable); 1384 } else if (!imod && M) { 1385 Inst.setOpcode(ARM::CPS1p); 1386 Inst.addOperand(MCOperand::CreateImm(mode)); 1387 if (iflags) CHECK(S, Unpredictable); 1388 } else { 1389 // imod == '00' && M == '0' --> UNPREDICTABLE 1390 Inst.setOpcode(ARM::CPS1p); 1391 Inst.addOperand(MCOperand::CreateImm(mode)); 1392 CHECK(S, Unpredictable); 1393 } 1394 1395 return S; 1396} 1397 1398static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1399 uint64_t Address, const void *Decoder) { 1400 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1401 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1402 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1403 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1404 1405 DecodeStatus S = Success; 1406 1407 // imod == '01' --> UNPREDICTABLE 1408 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1409 // return failure here. The '01' imod value is unprintable, so there's 1410 // nothing useful we could do even if we returned UNPREDICTABLE. 1411 1412 if (imod == 1) CHECK(S, Fail); 1413 1414 if (imod && M) { 1415 Inst.setOpcode(ARM::t2CPS3p); 1416 Inst.addOperand(MCOperand::CreateImm(imod)); 1417 Inst.addOperand(MCOperand::CreateImm(iflags)); 1418 Inst.addOperand(MCOperand::CreateImm(mode)); 1419 } else if (imod && !M) { 1420 Inst.setOpcode(ARM::t2CPS2p); 1421 Inst.addOperand(MCOperand::CreateImm(imod)); 1422 Inst.addOperand(MCOperand::CreateImm(iflags)); 1423 if (mode) CHECK(S, Unpredictable); 1424 } else if (!imod && M) { 1425 Inst.setOpcode(ARM::t2CPS1p); 1426 Inst.addOperand(MCOperand::CreateImm(mode)); 1427 if (iflags) CHECK(S, Unpredictable); 1428 } else { 1429 // imod == '00' && M == '0' --> UNPREDICTABLE 1430 Inst.setOpcode(ARM::t2CPS1p); 1431 Inst.addOperand(MCOperand::CreateImm(mode)); 1432 CHECK(S, Unpredictable); 1433 } 1434 1435 return S; 1436} 1437 1438 1439static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1440 uint64_t Address, const void *Decoder) { 1441 DecodeStatus S = Success; 1442 1443 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1444 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1445 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1446 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1447 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1448 1449 if (pred == 0xF) 1450 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1451 1452 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); 1453 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); 1454 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1455 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); 1456 1457 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1458 1459 return S; 1460} 1461 1462static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1463 uint64_t Address, const void *Decoder) { 1464 DecodeStatus S = Success; 1465 1466 unsigned add = fieldFromInstruction32(Val, 12, 1); 1467 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1468 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1469 1470 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1471 1472 if (!add) imm *= -1; 1473 if (imm == 0 && !add) imm = INT32_MIN; 1474 Inst.addOperand(MCOperand::CreateImm(imm)); 1475 1476 return S; 1477} 1478 1479static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1480 uint64_t Address, const void *Decoder) { 1481 DecodeStatus S = Success; 1482 1483 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1484 unsigned U = fieldFromInstruction32(Val, 8, 1); 1485 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1486 1487 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1488 1489 if (U) 1490 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1491 else 1492 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1493 1494 return S; 1495} 1496 1497static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1498 uint64_t Address, const void *Decoder) { 1499 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1500} 1501 1502static DecodeStatus 1503DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1504 uint64_t Address, const void *Decoder) { 1505 DecodeStatus S = Success; 1506 1507 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1508 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1509 1510 if (pred == 0xF) { 1511 Inst.setOpcode(ARM::BLXi); 1512 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1513 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1514 return S; 1515 } 1516 1517 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1518 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1519 1520 return S; 1521} 1522 1523 1524static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1525 uint64_t Address, const void *Decoder) { 1526 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1527 return Success; 1528} 1529 1530static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1531 uint64_t Address, const void *Decoder) { 1532 DecodeStatus S = Success; 1533 1534 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1535 unsigned align = fieldFromInstruction32(Val, 4, 2); 1536 1537 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1538 if (!align) 1539 Inst.addOperand(MCOperand::CreateImm(0)); 1540 else 1541 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1542 1543 return S; 1544} 1545 1546static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1547 uint64_t Address, const void *Decoder) { 1548 DecodeStatus S = Success; 1549 1550 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1551 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1552 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1553 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1554 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1555 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1556 1557 // First output register 1558 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1559 1560 // Second output register 1561 switch (Inst.getOpcode()) { 1562 case ARM::VLD1q8: 1563 case ARM::VLD1q16: 1564 case ARM::VLD1q32: 1565 case ARM::VLD1q64: 1566 case ARM::VLD1q8_UPD: 1567 case ARM::VLD1q16_UPD: 1568 case ARM::VLD1q32_UPD: 1569 case ARM::VLD1q64_UPD: 1570 case ARM::VLD1d8T: 1571 case ARM::VLD1d16T: 1572 case ARM::VLD1d32T: 1573 case ARM::VLD1d64T: 1574 case ARM::VLD1d8T_UPD: 1575 case ARM::VLD1d16T_UPD: 1576 case ARM::VLD1d32T_UPD: 1577 case ARM::VLD1d64T_UPD: 1578 case ARM::VLD1d8Q: 1579 case ARM::VLD1d16Q: 1580 case ARM::VLD1d32Q: 1581 case ARM::VLD1d64Q: 1582 case ARM::VLD1d8Q_UPD: 1583 case ARM::VLD1d16Q_UPD: 1584 case ARM::VLD1d32Q_UPD: 1585 case ARM::VLD1d64Q_UPD: 1586 case ARM::VLD2d8: 1587 case ARM::VLD2d16: 1588 case ARM::VLD2d32: 1589 case ARM::VLD2d8_UPD: 1590 case ARM::VLD2d16_UPD: 1591 case ARM::VLD2d32_UPD: 1592 case ARM::VLD2q8: 1593 case ARM::VLD2q16: 1594 case ARM::VLD2q32: 1595 case ARM::VLD2q8_UPD: 1596 case ARM::VLD2q16_UPD: 1597 case ARM::VLD2q32_UPD: 1598 case ARM::VLD3d8: 1599 case ARM::VLD3d16: 1600 case ARM::VLD3d32: 1601 case ARM::VLD3d8_UPD: 1602 case ARM::VLD3d16_UPD: 1603 case ARM::VLD3d32_UPD: 1604 case ARM::VLD4d8: 1605 case ARM::VLD4d16: 1606 case ARM::VLD4d32: 1607 case ARM::VLD4d8_UPD: 1608 case ARM::VLD4d16_UPD: 1609 case ARM::VLD4d32_UPD: 1610 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1611 break; 1612 case ARM::VLD2b8: 1613 case ARM::VLD2b16: 1614 case ARM::VLD2b32: 1615 case ARM::VLD2b8_UPD: 1616 case ARM::VLD2b16_UPD: 1617 case ARM::VLD2b32_UPD: 1618 case ARM::VLD3q8: 1619 case ARM::VLD3q16: 1620 case ARM::VLD3q32: 1621 case ARM::VLD3q8_UPD: 1622 case ARM::VLD3q16_UPD: 1623 case ARM::VLD3q32_UPD: 1624 case ARM::VLD4q8: 1625 case ARM::VLD4q16: 1626 case ARM::VLD4q32: 1627 case ARM::VLD4q8_UPD: 1628 case ARM::VLD4q16_UPD: 1629 case ARM::VLD4q32_UPD: 1630 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1631 default: 1632 break; 1633 } 1634 1635 // Third output register 1636 switch(Inst.getOpcode()) { 1637 case ARM::VLD1d8T: 1638 case ARM::VLD1d16T: 1639 case ARM::VLD1d32T: 1640 case ARM::VLD1d64T: 1641 case ARM::VLD1d8T_UPD: 1642 case ARM::VLD1d16T_UPD: 1643 case ARM::VLD1d32T_UPD: 1644 case ARM::VLD1d64T_UPD: 1645 case ARM::VLD1d8Q: 1646 case ARM::VLD1d16Q: 1647 case ARM::VLD1d32Q: 1648 case ARM::VLD1d64Q: 1649 case ARM::VLD1d8Q_UPD: 1650 case ARM::VLD1d16Q_UPD: 1651 case ARM::VLD1d32Q_UPD: 1652 case ARM::VLD1d64Q_UPD: 1653 case ARM::VLD2q8: 1654 case ARM::VLD2q16: 1655 case ARM::VLD2q32: 1656 case ARM::VLD2q8_UPD: 1657 case ARM::VLD2q16_UPD: 1658 case ARM::VLD2q32_UPD: 1659 case ARM::VLD3d8: 1660 case ARM::VLD3d16: 1661 case ARM::VLD3d32: 1662 case ARM::VLD3d8_UPD: 1663 case ARM::VLD3d16_UPD: 1664 case ARM::VLD3d32_UPD: 1665 case ARM::VLD4d8: 1666 case ARM::VLD4d16: 1667 case ARM::VLD4d32: 1668 case ARM::VLD4d8_UPD: 1669 case ARM::VLD4d16_UPD: 1670 case ARM::VLD4d32_UPD: 1671 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1672 break; 1673 case ARM::VLD3q8: 1674 case ARM::VLD3q16: 1675 case ARM::VLD3q32: 1676 case ARM::VLD3q8_UPD: 1677 case ARM::VLD3q16_UPD: 1678 case ARM::VLD3q32_UPD: 1679 case ARM::VLD4q8: 1680 case ARM::VLD4q16: 1681 case ARM::VLD4q32: 1682 case ARM::VLD4q8_UPD: 1683 case ARM::VLD4q16_UPD: 1684 case ARM::VLD4q32_UPD: 1685 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1686 break; 1687 default: 1688 break; 1689 } 1690 1691 // Fourth output register 1692 switch (Inst.getOpcode()) { 1693 case ARM::VLD1d8Q: 1694 case ARM::VLD1d16Q: 1695 case ARM::VLD1d32Q: 1696 case ARM::VLD1d64Q: 1697 case ARM::VLD1d8Q_UPD: 1698 case ARM::VLD1d16Q_UPD: 1699 case ARM::VLD1d32Q_UPD: 1700 case ARM::VLD1d64Q_UPD: 1701 case ARM::VLD2q8: 1702 case ARM::VLD2q16: 1703 case ARM::VLD2q32: 1704 case ARM::VLD2q8_UPD: 1705 case ARM::VLD2q16_UPD: 1706 case ARM::VLD2q32_UPD: 1707 case ARM::VLD4d8: 1708 case ARM::VLD4d16: 1709 case ARM::VLD4d32: 1710 case ARM::VLD4d8_UPD: 1711 case ARM::VLD4d16_UPD: 1712 case ARM::VLD4d32_UPD: 1713 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1714 break; 1715 case ARM::VLD4q8: 1716 case ARM::VLD4q16: 1717 case ARM::VLD4q32: 1718 case ARM::VLD4q8_UPD: 1719 case ARM::VLD4q16_UPD: 1720 case ARM::VLD4q32_UPD: 1721 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1722 break; 1723 default: 1724 break; 1725 } 1726 1727 // Writeback operand 1728 switch (Inst.getOpcode()) { 1729 case ARM::VLD1d8_UPD: 1730 case ARM::VLD1d16_UPD: 1731 case ARM::VLD1d32_UPD: 1732 case ARM::VLD1d64_UPD: 1733 case ARM::VLD1q8_UPD: 1734 case ARM::VLD1q16_UPD: 1735 case ARM::VLD1q32_UPD: 1736 case ARM::VLD1q64_UPD: 1737 case ARM::VLD1d8T_UPD: 1738 case ARM::VLD1d16T_UPD: 1739 case ARM::VLD1d32T_UPD: 1740 case ARM::VLD1d64T_UPD: 1741 case ARM::VLD1d8Q_UPD: 1742 case ARM::VLD1d16Q_UPD: 1743 case ARM::VLD1d32Q_UPD: 1744 case ARM::VLD1d64Q_UPD: 1745 case ARM::VLD2d8_UPD: 1746 case ARM::VLD2d16_UPD: 1747 case ARM::VLD2d32_UPD: 1748 case ARM::VLD2q8_UPD: 1749 case ARM::VLD2q16_UPD: 1750 case ARM::VLD2q32_UPD: 1751 case ARM::VLD2b8_UPD: 1752 case ARM::VLD2b16_UPD: 1753 case ARM::VLD2b32_UPD: 1754 case ARM::VLD3d8_UPD: 1755 case ARM::VLD3d16_UPD: 1756 case ARM::VLD3d32_UPD: 1757 case ARM::VLD3q8_UPD: 1758 case ARM::VLD3q16_UPD: 1759 case ARM::VLD3q32_UPD: 1760 case ARM::VLD4d8_UPD: 1761 case ARM::VLD4d16_UPD: 1762 case ARM::VLD4d32_UPD: 1763 case ARM::VLD4q8_UPD: 1764 case ARM::VLD4q16_UPD: 1765 case ARM::VLD4q32_UPD: 1766 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1767 break; 1768 default: 1769 break; 1770 } 1771 1772 // AddrMode6 Base (register+alignment) 1773 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1774 1775 // AddrMode6 Offset (register) 1776 if (Rm == 0xD) 1777 Inst.addOperand(MCOperand::CreateReg(0)); 1778 else if (Rm != 0xF) { 1779 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1780 } 1781 1782 return S; 1783} 1784 1785static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1786 uint64_t Address, const void *Decoder) { 1787 DecodeStatus S = Success; 1788 1789 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1790 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1791 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1792 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1793 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1794 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1795 1796 // Writeback Operand 1797 switch (Inst.getOpcode()) { 1798 case ARM::VST1d8_UPD: 1799 case ARM::VST1d16_UPD: 1800 case ARM::VST1d32_UPD: 1801 case ARM::VST1d64_UPD: 1802 case ARM::VST1q8_UPD: 1803 case ARM::VST1q16_UPD: 1804 case ARM::VST1q32_UPD: 1805 case ARM::VST1q64_UPD: 1806 case ARM::VST1d8T_UPD: 1807 case ARM::VST1d16T_UPD: 1808 case ARM::VST1d32T_UPD: 1809 case ARM::VST1d64T_UPD: 1810 case ARM::VST1d8Q_UPD: 1811 case ARM::VST1d16Q_UPD: 1812 case ARM::VST1d32Q_UPD: 1813 case ARM::VST1d64Q_UPD: 1814 case ARM::VST2d8_UPD: 1815 case ARM::VST2d16_UPD: 1816 case ARM::VST2d32_UPD: 1817 case ARM::VST2q8_UPD: 1818 case ARM::VST2q16_UPD: 1819 case ARM::VST2q32_UPD: 1820 case ARM::VST2b8_UPD: 1821 case ARM::VST2b16_UPD: 1822 case ARM::VST2b32_UPD: 1823 case ARM::VST3d8_UPD: 1824 case ARM::VST3d16_UPD: 1825 case ARM::VST3d32_UPD: 1826 case ARM::VST3q8_UPD: 1827 case ARM::VST3q16_UPD: 1828 case ARM::VST3q32_UPD: 1829 case ARM::VST4d8_UPD: 1830 case ARM::VST4d16_UPD: 1831 case ARM::VST4d32_UPD: 1832 case ARM::VST4q8_UPD: 1833 case ARM::VST4q16_UPD: 1834 case ARM::VST4q32_UPD: 1835 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1836 break; 1837 default: 1838 break; 1839 } 1840 1841 // AddrMode6 Base (register+alignment) 1842 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1843 1844 // AddrMode6 Offset (register) 1845 if (Rm == 0xD) 1846 Inst.addOperand(MCOperand::CreateReg(0)); 1847 else if (Rm != 0xF) { 1848 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1849 } 1850 1851 // First input register 1852 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1853 1854 // Second input register 1855 switch (Inst.getOpcode()) { 1856 case ARM::VST1q8: 1857 case ARM::VST1q16: 1858 case ARM::VST1q32: 1859 case ARM::VST1q64: 1860 case ARM::VST1q8_UPD: 1861 case ARM::VST1q16_UPD: 1862 case ARM::VST1q32_UPD: 1863 case ARM::VST1q64_UPD: 1864 case ARM::VST1d8T: 1865 case ARM::VST1d16T: 1866 case ARM::VST1d32T: 1867 case ARM::VST1d64T: 1868 case ARM::VST1d8T_UPD: 1869 case ARM::VST1d16T_UPD: 1870 case ARM::VST1d32T_UPD: 1871 case ARM::VST1d64T_UPD: 1872 case ARM::VST1d8Q: 1873 case ARM::VST1d16Q: 1874 case ARM::VST1d32Q: 1875 case ARM::VST1d64Q: 1876 case ARM::VST1d8Q_UPD: 1877 case ARM::VST1d16Q_UPD: 1878 case ARM::VST1d32Q_UPD: 1879 case ARM::VST1d64Q_UPD: 1880 case ARM::VST2d8: 1881 case ARM::VST2d16: 1882 case ARM::VST2d32: 1883 case ARM::VST2d8_UPD: 1884 case ARM::VST2d16_UPD: 1885 case ARM::VST2d32_UPD: 1886 case ARM::VST2q8: 1887 case ARM::VST2q16: 1888 case ARM::VST2q32: 1889 case ARM::VST2q8_UPD: 1890 case ARM::VST2q16_UPD: 1891 case ARM::VST2q32_UPD: 1892 case ARM::VST3d8: 1893 case ARM::VST3d16: 1894 case ARM::VST3d32: 1895 case ARM::VST3d8_UPD: 1896 case ARM::VST3d16_UPD: 1897 case ARM::VST3d32_UPD: 1898 case ARM::VST4d8: 1899 case ARM::VST4d16: 1900 case ARM::VST4d32: 1901 case ARM::VST4d8_UPD: 1902 case ARM::VST4d16_UPD: 1903 case ARM::VST4d32_UPD: 1904 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1905 break; 1906 case ARM::VST2b8: 1907 case ARM::VST2b16: 1908 case ARM::VST2b32: 1909 case ARM::VST2b8_UPD: 1910 case ARM::VST2b16_UPD: 1911 case ARM::VST2b32_UPD: 1912 case ARM::VST3q8: 1913 case ARM::VST3q16: 1914 case ARM::VST3q32: 1915 case ARM::VST3q8_UPD: 1916 case ARM::VST3q16_UPD: 1917 case ARM::VST3q32_UPD: 1918 case ARM::VST4q8: 1919 case ARM::VST4q16: 1920 case ARM::VST4q32: 1921 case ARM::VST4q8_UPD: 1922 case ARM::VST4q16_UPD: 1923 case ARM::VST4q32_UPD: 1924 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1925 break; 1926 default: 1927 break; 1928 } 1929 1930 // Third input register 1931 switch (Inst.getOpcode()) { 1932 case ARM::VST1d8T: 1933 case ARM::VST1d16T: 1934 case ARM::VST1d32T: 1935 case ARM::VST1d64T: 1936 case ARM::VST1d8T_UPD: 1937 case ARM::VST1d16T_UPD: 1938 case ARM::VST1d32T_UPD: 1939 case ARM::VST1d64T_UPD: 1940 case ARM::VST1d8Q: 1941 case ARM::VST1d16Q: 1942 case ARM::VST1d32Q: 1943 case ARM::VST1d64Q: 1944 case ARM::VST1d8Q_UPD: 1945 case ARM::VST1d16Q_UPD: 1946 case ARM::VST1d32Q_UPD: 1947 case ARM::VST1d64Q_UPD: 1948 case ARM::VST2q8: 1949 case ARM::VST2q16: 1950 case ARM::VST2q32: 1951 case ARM::VST2q8_UPD: 1952 case ARM::VST2q16_UPD: 1953 case ARM::VST2q32_UPD: 1954 case ARM::VST3d8: 1955 case ARM::VST3d16: 1956 case ARM::VST3d32: 1957 case ARM::VST3d8_UPD: 1958 case ARM::VST3d16_UPD: 1959 case ARM::VST3d32_UPD: 1960 case ARM::VST4d8: 1961 case ARM::VST4d16: 1962 case ARM::VST4d32: 1963 case ARM::VST4d8_UPD: 1964 case ARM::VST4d16_UPD: 1965 case ARM::VST4d32_UPD: 1966 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1967 break; 1968 case ARM::VST3q8: 1969 case ARM::VST3q16: 1970 case ARM::VST3q32: 1971 case ARM::VST3q8_UPD: 1972 case ARM::VST3q16_UPD: 1973 case ARM::VST3q32_UPD: 1974 case ARM::VST4q8: 1975 case ARM::VST4q16: 1976 case ARM::VST4q32: 1977 case ARM::VST4q8_UPD: 1978 case ARM::VST4q16_UPD: 1979 case ARM::VST4q32_UPD: 1980 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1981 break; 1982 default: 1983 break; 1984 } 1985 1986 // Fourth input register 1987 switch (Inst.getOpcode()) { 1988 case ARM::VST1d8Q: 1989 case ARM::VST1d16Q: 1990 case ARM::VST1d32Q: 1991 case ARM::VST1d64Q: 1992 case ARM::VST1d8Q_UPD: 1993 case ARM::VST1d16Q_UPD: 1994 case ARM::VST1d32Q_UPD: 1995 case ARM::VST1d64Q_UPD: 1996 case ARM::VST2q8: 1997 case ARM::VST2q16: 1998 case ARM::VST2q32: 1999 case ARM::VST2q8_UPD: 2000 case ARM::VST2q16_UPD: 2001 case ARM::VST2q32_UPD: 2002 case ARM::VST4d8: 2003 case ARM::VST4d16: 2004 case ARM::VST4d32: 2005 case ARM::VST4d8_UPD: 2006 case ARM::VST4d16_UPD: 2007 case ARM::VST4d32_UPD: 2008 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 2009 break; 2010 case ARM::VST4q8: 2011 case ARM::VST4q16: 2012 case ARM::VST4q32: 2013 case ARM::VST4q8_UPD: 2014 case ARM::VST4q16_UPD: 2015 case ARM::VST4q32_UPD: 2016 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 2017 break; 2018 default: 2019 break; 2020 } 2021 2022 return S; 2023} 2024 2025static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2026 uint64_t Address, const void *Decoder) { 2027 DecodeStatus S = Success; 2028 2029 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2030 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2031 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2032 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2033 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2034 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2035 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2036 2037 align *= (1 << size); 2038 2039 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2040 if (regs == 2) { 2041 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 2042 } 2043 if (Rm != 0xF) { 2044 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2045 } 2046 2047 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2048 Inst.addOperand(MCOperand::CreateImm(align)); 2049 2050 if (Rm == 0xD) 2051 Inst.addOperand(MCOperand::CreateReg(0)); 2052 else if (Rm != 0xF) { 2053 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2054 } 2055 2056 return S; 2057} 2058 2059static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2060 uint64_t Address, const void *Decoder) { 2061 DecodeStatus S = Success; 2062 2063 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2064 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2065 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2066 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2067 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2068 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2069 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2070 align *= 2*size; 2071 2072 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2073 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2074 if (Rm != 0xF) { 2075 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2076 } 2077 2078 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2079 Inst.addOperand(MCOperand::CreateImm(align)); 2080 2081 if (Rm == 0xD) 2082 Inst.addOperand(MCOperand::CreateReg(0)); 2083 else if (Rm != 0xF) { 2084 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2085 } 2086 2087 return S; 2088} 2089 2090static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2091 uint64_t Address, const void *Decoder) { 2092 DecodeStatus S = Success; 2093 2094 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2095 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2096 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2097 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2098 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2099 2100 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2101 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2102 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2103 if (Rm != 0xF) { 2104 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2105 } 2106 2107 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2108 Inst.addOperand(MCOperand::CreateImm(0)); 2109 2110 if (Rm == 0xD) 2111 Inst.addOperand(MCOperand::CreateReg(0)); 2112 else if (Rm != 0xF) { 2113 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2114 } 2115 2116 return S; 2117} 2118 2119static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2120 uint64_t Address, const void *Decoder) { 2121 DecodeStatus S = Success; 2122 2123 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2124 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2125 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2126 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2127 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2128 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2129 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2130 2131 if (size == 0x3) { 2132 size = 4; 2133 align = 16; 2134 } else { 2135 if (size == 2) { 2136 size = 1 << size; 2137 align *= 8; 2138 } else { 2139 size = 1 << size; 2140 align *= 4*size; 2141 } 2142 } 2143 2144 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2145 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2146 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2147 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); 2148 if (Rm != 0xF) { 2149 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2150 } 2151 2152 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2153 Inst.addOperand(MCOperand::CreateImm(align)); 2154 2155 if (Rm == 0xD) 2156 Inst.addOperand(MCOperand::CreateReg(0)); 2157 else if (Rm != 0xF) { 2158 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2159 } 2160 2161 return S; 2162} 2163 2164static DecodeStatus 2165DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2166 uint64_t Address, const void *Decoder) { 2167 DecodeStatus S = Success; 2168 2169 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2170 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2171 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2172 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2173 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2174 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2175 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2176 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2177 2178 if (Q) { 2179 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2180 } else { 2181 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2182 } 2183 2184 Inst.addOperand(MCOperand::CreateImm(imm)); 2185 2186 switch (Inst.getOpcode()) { 2187 case ARM::VORRiv4i16: 2188 case ARM::VORRiv2i32: 2189 case ARM::VBICiv4i16: 2190 case ARM::VBICiv2i32: 2191 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2192 break; 2193 case ARM::VORRiv8i16: 2194 case ARM::VORRiv4i32: 2195 case ARM::VBICiv8i16: 2196 case ARM::VBICiv4i32: 2197 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2198 break; 2199 default: 2200 break; 2201 } 2202 2203 return S; 2204} 2205 2206static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2207 uint64_t Address, const void *Decoder) { 2208 DecodeStatus S = Success; 2209 2210 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2211 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2212 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2213 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2214 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2215 2216 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2217 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2218 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2219 2220 return S; 2221} 2222 2223static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2224 uint64_t Address, const void *Decoder) { 2225 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2226 return Success; 2227} 2228 2229static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2230 uint64_t Address, const void *Decoder) { 2231 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2232 return Success; 2233} 2234 2235static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2236 uint64_t Address, const void *Decoder) { 2237 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2238 return Success; 2239} 2240 2241static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2242 uint64_t Address, const void *Decoder) { 2243 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2244 return Success; 2245} 2246 2247static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2248 uint64_t Address, const void *Decoder) { 2249 DecodeStatus S = Success; 2250 2251 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2252 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2253 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2254 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2255 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2256 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2257 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2258 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2259 2260 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2261 if (op) { 2262 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback 2263 } 2264 2265 for (unsigned i = 0; i < length; ++i) { 2266 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)); 2267 } 2268 2269 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2270 2271 return S; 2272} 2273 2274static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2275 uint64_t Address, const void *Decoder) { 2276 // The immediate needs to be a fully instantiated float. However, the 2277 // auto-generated decoder is only able to fill in some of the bits 2278 // necessary. For instance, the 'b' bit is replicated multiple times, 2279 // and is even present in inverted form in one bit. We do a little 2280 // binary parsing here to fill in those missing bits, and then 2281 // reinterpret it all as a float. 2282 union { 2283 uint32_t integer; 2284 float fp; 2285 } fp_conv; 2286 2287 fp_conv.integer = Val; 2288 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2289 fp_conv.integer |= b << 26; 2290 fp_conv.integer |= b << 27; 2291 fp_conv.integer |= b << 28; 2292 fp_conv.integer |= b << 29; 2293 fp_conv.integer |= (~b & 0x1) << 30; 2294 2295 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2296 return Success; 2297} 2298 2299static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2300 uint64_t Address, const void *Decoder) { 2301 DecodeStatus S = Success; 2302 2303 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2304 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2305 2306 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); 2307 2308 if (Inst.getOpcode() == ARM::tADR) 2309 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2310 else if (Inst.getOpcode() == ARM::tADDrSPi) 2311 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2312 else 2313 return Fail; 2314 2315 Inst.addOperand(MCOperand::CreateImm(imm)); 2316 return S; 2317} 2318 2319static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2320 uint64_t Address, const void *Decoder) { 2321 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2322 return Success; 2323} 2324 2325static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2326 uint64_t Address, const void *Decoder) { 2327 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2328 return Success; 2329} 2330 2331static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2332 uint64_t Address, const void *Decoder) { 2333 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2334 return Success; 2335} 2336 2337static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2338 uint64_t Address, const void *Decoder) { 2339 DecodeStatus S = Success; 2340 2341 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2342 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2343 2344 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2345 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); 2346 2347 return S; 2348} 2349 2350static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2351 uint64_t Address, const void *Decoder) { 2352 DecodeStatus S = Success; 2353 2354 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2355 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2356 2357 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2358 Inst.addOperand(MCOperand::CreateImm(imm)); 2359 2360 return S; 2361} 2362 2363static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2364 uint64_t Address, const void *Decoder) { 2365 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2366 2367 return Success; 2368} 2369 2370static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2371 uint64_t Address, const void *Decoder) { 2372 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2373 Inst.addOperand(MCOperand::CreateImm(Val)); 2374 2375 return Success; 2376} 2377 2378static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2379 uint64_t Address, const void *Decoder) { 2380 DecodeStatus S = Success; 2381 2382 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2383 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2384 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2385 2386 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2387 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); 2388 Inst.addOperand(MCOperand::CreateImm(imm)); 2389 2390 return S; 2391} 2392 2393static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2394 uint64_t Address, const void *Decoder) { 2395 DecodeStatus S = Success; 2396 2397 switch (Inst.getOpcode()) { 2398 case ARM::t2PLDs: 2399 case ARM::t2PLDWs: 2400 case ARM::t2PLIs: 2401 break; 2402 default: { 2403 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2404 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2405 } 2406 } 2407 2408 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2409 if (Rn == 0xF) { 2410 switch (Inst.getOpcode()) { 2411 case ARM::t2LDRBs: 2412 Inst.setOpcode(ARM::t2LDRBpci); 2413 break; 2414 case ARM::t2LDRHs: 2415 Inst.setOpcode(ARM::t2LDRHpci); 2416 break; 2417 case ARM::t2LDRSHs: 2418 Inst.setOpcode(ARM::t2LDRSHpci); 2419 break; 2420 case ARM::t2LDRSBs: 2421 Inst.setOpcode(ARM::t2LDRSBpci); 2422 break; 2423 case ARM::t2PLDs: 2424 Inst.setOpcode(ARM::t2PLDi12); 2425 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2426 break; 2427 default: 2428 return Fail; 2429 } 2430 2431 int imm = fieldFromInstruction32(Insn, 0, 12); 2432 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2433 Inst.addOperand(MCOperand::CreateImm(imm)); 2434 2435 return S; 2436 } 2437 2438 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2439 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2440 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2441 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); 2442 2443 return S; 2444} 2445 2446static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2447 uint64_t Address, const void *Decoder) { 2448 int imm = Val & 0xFF; 2449 if (!(Val & 0x100)) imm *= -1; 2450 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2451 2452 return Success; 2453} 2454 2455static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2456 uint64_t Address, const void *Decoder) { 2457 DecodeStatus S = Success; 2458 2459 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2460 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2461 2462 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2463 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); 2464 2465 return S; 2466} 2467 2468static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2469 uint64_t Address, const void *Decoder) { 2470 int imm = Val & 0xFF; 2471 if (!(Val & 0x100)) imm *= -1; 2472 Inst.addOperand(MCOperand::CreateImm(imm)); 2473 2474 return Success; 2475} 2476 2477 2478static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2479 uint64_t Address, const void *Decoder) { 2480 DecodeStatus S = Success; 2481 2482 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2483 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2484 2485 // Some instructions always use an additive offset. 2486 switch (Inst.getOpcode()) { 2487 case ARM::t2LDRT: 2488 case ARM::t2LDRBT: 2489 case ARM::t2LDRHT: 2490 case ARM::t2LDRSBT: 2491 case ARM::t2LDRSHT: 2492 imm |= 0x100; 2493 break; 2494 default: 2495 break; 2496 } 2497 2498 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2499 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); 2500 2501 return S; 2502} 2503 2504 2505static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2506 uint64_t Address, const void *Decoder) { 2507 DecodeStatus S = Success; 2508 2509 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2510 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2511 2512 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2513 Inst.addOperand(MCOperand::CreateImm(imm)); 2514 2515 return S; 2516} 2517 2518 2519static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2520 uint64_t Address, const void *Decoder) { 2521 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2522 2523 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2524 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2525 Inst.addOperand(MCOperand::CreateImm(imm)); 2526 2527 return Success; 2528} 2529 2530static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2531 uint64_t Address, const void *Decoder) { 2532 DecodeStatus S = Success; 2533 2534 if (Inst.getOpcode() == ARM::tADDrSP) { 2535 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2536 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2537 2538 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2539 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2540 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2541 } else if (Inst.getOpcode() == ARM::tADDspr) { 2542 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2543 2544 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2545 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2546 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2547 } 2548 2549 return S; 2550} 2551 2552static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2553 uint64_t Address, const void *Decoder) { 2554 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2555 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2556 2557 Inst.addOperand(MCOperand::CreateImm(imod)); 2558 Inst.addOperand(MCOperand::CreateImm(flags)); 2559 2560 return Success; 2561} 2562 2563static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2564 uint64_t Address, const void *Decoder) { 2565 DecodeStatus S = Success; 2566 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2567 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2568 2569 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; 2570 Inst.addOperand(MCOperand::CreateImm(add)); 2571 2572 return S; 2573} 2574 2575static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2576 uint64_t Address, const void *Decoder) { 2577 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2578 return Success; 2579} 2580 2581static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2582 uint64_t Address, const void *Decoder) { 2583 if (Val == 0xA || Val == 0xB) 2584 return Fail; 2585 2586 Inst.addOperand(MCOperand::CreateImm(Val)); 2587 return Success; 2588} 2589 2590static DecodeStatus 2591DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2592 uint64_t Address, const void *Decoder) { 2593 DecodeStatus S = Success; 2594 2595 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2596 if (pred == 0xE || pred == 0xF) { 2597 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2598 switch (opc) { 2599 default: 2600 return Fail; 2601 case 0: 2602 Inst.setOpcode(ARM::t2DSB); 2603 break; 2604 case 1: 2605 Inst.setOpcode(ARM::t2DMB); 2606 break; 2607 case 2: 2608 Inst.setOpcode(ARM::t2ISB); 2609 return Success; 2610 } 2611 2612 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2613 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2614 } 2615 2616 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2617 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2618 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2619 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2620 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2621 2622 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); 2623 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2624 2625 return S; 2626} 2627 2628// Decode a shifted immediate operand. These basically consist 2629// of an 8-bit value, and a 4-bit directive that specifies either 2630// a splat operation or a rotation. 2631static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2632 uint64_t Address, const void *Decoder) { 2633 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2634 if (ctrl == 0) { 2635 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2636 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2637 switch (byte) { 2638 case 0: 2639 Inst.addOperand(MCOperand::CreateImm(imm)); 2640 break; 2641 case 1: 2642 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2643 break; 2644 case 2: 2645 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2646 break; 2647 case 3: 2648 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2649 (imm << 8) | imm)); 2650 break; 2651 } 2652 } else { 2653 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2654 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2655 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2656 Inst.addOperand(MCOperand::CreateImm(imm)); 2657 } 2658 2659 return Success; 2660} 2661 2662static DecodeStatus 2663DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2664 uint64_t Address, const void *Decoder){ 2665 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2666 return Success; 2667} 2668 2669static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2670 uint64_t Address, const void *Decoder){ 2671 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2672 return Success; 2673} 2674 2675static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2676 uint64_t Address, const void *Decoder) { 2677 switch (Val) { 2678 default: 2679 return Fail; 2680 case 0xF: // SY 2681 case 0xE: // ST 2682 case 0xB: // ISH 2683 case 0xA: // ISHST 2684 case 0x7: // NSH 2685 case 0x6: // NSHST 2686 case 0x3: // OSH 2687 case 0x2: // OSHST 2688 break; 2689 } 2690 2691 Inst.addOperand(MCOperand::CreateImm(Val)); 2692 return Success; 2693} 2694 2695static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2696 uint64_t Address, const void *Decoder) { 2697 if (!Val) return Fail; 2698 Inst.addOperand(MCOperand::CreateImm(Val)); 2699 return Success; 2700} 2701 2702static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2703 uint64_t Address, const void *Decoder) { 2704 DecodeStatus S = Success; 2705 2706 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2707 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2708 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2709 2710 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2711 2712 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2713 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2714 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2715 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2716 2717 return S; 2718} 2719 2720 2721static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2722 uint64_t Address, const void *Decoder){ 2723 DecodeStatus S = Success; 2724 2725 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2726 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2727 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2728 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2729 2730 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); 2731 2732 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2733 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; 2734 2735 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2736 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2737 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2738 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2739 2740 return S; 2741} 2742 2743static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2744 uint64_t Address, const void *Decoder) { 2745 DecodeStatus S = Success; 2746 2747 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2748 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2749 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2750 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2751 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2752 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2753 2754 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2755 2756 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2757 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2758 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); 2759 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2760 2761 return S; 2762} 2763 2764static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2765 uint64_t Address, const void *Decoder) { 2766 DecodeStatus S = Success; 2767 2768 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2769 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2770 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2771 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2772 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2773 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2774 2775 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2776 2777 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2778 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2779 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); 2780 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2781 2782 return S; 2783} 2784 2785static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2786 uint64_t Address, const void *Decoder) { 2787 DecodeStatus S = Success; 2788 2789 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2790 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2791 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2792 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2793 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2794 2795 unsigned align = 0; 2796 unsigned index = 0; 2797 switch (size) { 2798 default: 2799 return Fail; 2800 case 0: 2801 if (fieldFromInstruction32(Insn, 4, 1)) 2802 return Fail; // UNDEFINED 2803 index = fieldFromInstruction32(Insn, 5, 3); 2804 break; 2805 case 1: 2806 if (fieldFromInstruction32(Insn, 5, 1)) 2807 return Fail; // UNDEFINED 2808 index = fieldFromInstruction32(Insn, 6, 2); 2809 if (fieldFromInstruction32(Insn, 4, 1)) 2810 align = 2; 2811 break; 2812 case 2: 2813 if (fieldFromInstruction32(Insn, 6, 1)) 2814 return Fail; // UNDEFINED 2815 index = fieldFromInstruction32(Insn, 7, 1); 2816 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2817 align = 4; 2818 } 2819 2820 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2821 if (Rm != 0xF) { // Writeback 2822 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2823 } 2824 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2825 Inst.addOperand(MCOperand::CreateImm(align)); 2826 if (Rm != 0xF) { 2827 if (Rm != 0xD) 2828 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2829 else 2830 Inst.addOperand(MCOperand::CreateReg(0)); 2831 } 2832 2833 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2834 Inst.addOperand(MCOperand::CreateImm(index)); 2835 2836 return S; 2837} 2838 2839static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2840 uint64_t Address, const void *Decoder) { 2841 DecodeStatus S = Success; 2842 2843 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2844 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2845 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2846 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2847 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2848 2849 unsigned align = 0; 2850 unsigned index = 0; 2851 switch (size) { 2852 default: 2853 return Fail; 2854 case 0: 2855 if (fieldFromInstruction32(Insn, 4, 1)) 2856 return Fail; // UNDEFINED 2857 index = fieldFromInstruction32(Insn, 5, 3); 2858 break; 2859 case 1: 2860 if (fieldFromInstruction32(Insn, 5, 1)) 2861 return Fail; // UNDEFINED 2862 index = fieldFromInstruction32(Insn, 6, 2); 2863 if (fieldFromInstruction32(Insn, 4, 1)) 2864 align = 2; 2865 break; 2866 case 2: 2867 if (fieldFromInstruction32(Insn, 6, 1)) 2868 return Fail; // UNDEFINED 2869 index = fieldFromInstruction32(Insn, 7, 1); 2870 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2871 align = 4; 2872 } 2873 2874 if (Rm != 0xF) { // Writeback 2875 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2876 } 2877 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2878 Inst.addOperand(MCOperand::CreateImm(align)); 2879 if (Rm != 0xF) { 2880 if (Rm != 0xD) 2881 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2882 else 2883 Inst.addOperand(MCOperand::CreateReg(0)); 2884 } 2885 2886 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2887 Inst.addOperand(MCOperand::CreateImm(index)); 2888 2889 return S; 2890} 2891 2892 2893static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2894 uint64_t Address, const void *Decoder) { 2895 DecodeStatus S = Success; 2896 2897 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2898 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2899 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2900 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2901 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2902 2903 unsigned align = 0; 2904 unsigned index = 0; 2905 unsigned inc = 1; 2906 switch (size) { 2907 default: 2908 return Fail; 2909 case 0: 2910 index = fieldFromInstruction32(Insn, 5, 3); 2911 if (fieldFromInstruction32(Insn, 4, 1)) 2912 align = 2; 2913 break; 2914 case 1: 2915 index = fieldFromInstruction32(Insn, 6, 2); 2916 if (fieldFromInstruction32(Insn, 4, 1)) 2917 align = 4; 2918 if (fieldFromInstruction32(Insn, 5, 1)) 2919 inc = 2; 2920 break; 2921 case 2: 2922 if (fieldFromInstruction32(Insn, 5, 1)) 2923 return Fail; // UNDEFINED 2924 index = fieldFromInstruction32(Insn, 7, 1); 2925 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2926 align = 8; 2927 if (fieldFromInstruction32(Insn, 6, 1)) 2928 inc = 2; 2929 break; 2930 } 2931 2932 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2933 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2934 if (Rm != 0xF) { // Writeback 2935 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2936 } 2937 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2938 Inst.addOperand(MCOperand::CreateImm(align)); 2939 if (Rm != 0xF) { 2940 if (Rm != 0xD) 2941 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2942 else 2943 Inst.addOperand(MCOperand::CreateReg(0)); 2944 } 2945 2946 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2947 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2948 Inst.addOperand(MCOperand::CreateImm(index)); 2949 2950 return S; 2951} 2952 2953static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2954 uint64_t Address, const void *Decoder) { 2955 DecodeStatus S = Success; 2956 2957 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2958 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2959 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2960 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2961 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2962 2963 unsigned align = 0; 2964 unsigned index = 0; 2965 unsigned inc = 1; 2966 switch (size) { 2967 default: 2968 return Fail; 2969 case 0: 2970 index = fieldFromInstruction32(Insn, 5, 3); 2971 if (fieldFromInstruction32(Insn, 4, 1)) 2972 align = 2; 2973 break; 2974 case 1: 2975 index = fieldFromInstruction32(Insn, 6, 2); 2976 if (fieldFromInstruction32(Insn, 4, 1)) 2977 align = 4; 2978 if (fieldFromInstruction32(Insn, 5, 1)) 2979 inc = 2; 2980 break; 2981 case 2: 2982 if (fieldFromInstruction32(Insn, 5, 1)) 2983 return Fail; // UNDEFINED 2984 index = fieldFromInstruction32(Insn, 7, 1); 2985 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2986 align = 8; 2987 if (fieldFromInstruction32(Insn, 6, 1)) 2988 inc = 2; 2989 break; 2990 } 2991 2992 if (Rm != 0xF) { // Writeback 2993 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2994 } 2995 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2996 Inst.addOperand(MCOperand::CreateImm(align)); 2997 if (Rm != 0xF) { 2998 if (Rm != 0xD) 2999 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3000 else 3001 Inst.addOperand(MCOperand::CreateReg(0)); 3002 } 3003 3004 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3005 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3006 Inst.addOperand(MCOperand::CreateImm(index)); 3007 3008 return S; 3009} 3010 3011 3012static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3013 uint64_t Address, const void *Decoder) { 3014 DecodeStatus S = Success; 3015 3016 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3017 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3018 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3019 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3020 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3021 3022 unsigned align = 0; 3023 unsigned index = 0; 3024 unsigned inc = 1; 3025 switch (size) { 3026 default: 3027 return Fail; 3028 case 0: 3029 if (fieldFromInstruction32(Insn, 4, 1)) 3030 return Fail; // UNDEFINED 3031 index = fieldFromInstruction32(Insn, 5, 3); 3032 break; 3033 case 1: 3034 if (fieldFromInstruction32(Insn, 4, 1)) 3035 return Fail; // UNDEFINED 3036 index = fieldFromInstruction32(Insn, 6, 2); 3037 if (fieldFromInstruction32(Insn, 5, 1)) 3038 inc = 2; 3039 break; 3040 case 2: 3041 if (fieldFromInstruction32(Insn, 4, 2)) 3042 return Fail; // UNDEFINED 3043 index = fieldFromInstruction32(Insn, 7, 1); 3044 if (fieldFromInstruction32(Insn, 6, 1)) 3045 inc = 2; 3046 break; 3047 } 3048 3049 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3050 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3051 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3052 3053 if (Rm != 0xF) { // Writeback 3054 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3055 } 3056 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3057 Inst.addOperand(MCOperand::CreateImm(align)); 3058 if (Rm != 0xF) { 3059 if (Rm != 0xD) 3060 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3061 else 3062 Inst.addOperand(MCOperand::CreateReg(0)); 3063 } 3064 3065 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3066 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3067 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3068 Inst.addOperand(MCOperand::CreateImm(index)); 3069 3070 return S; 3071} 3072 3073static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3074 uint64_t Address, const void *Decoder) { 3075 DecodeStatus S = Success; 3076 3077 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3078 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3079 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3080 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3081 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3082 3083 unsigned align = 0; 3084 unsigned index = 0; 3085 unsigned inc = 1; 3086 switch (size) { 3087 default: 3088 return Fail; 3089 case 0: 3090 if (fieldFromInstruction32(Insn, 4, 1)) 3091 return Fail; // UNDEFINED 3092 index = fieldFromInstruction32(Insn, 5, 3); 3093 break; 3094 case 1: 3095 if (fieldFromInstruction32(Insn, 4, 1)) 3096 return Fail; // UNDEFINED 3097 index = fieldFromInstruction32(Insn, 6, 2); 3098 if (fieldFromInstruction32(Insn, 5, 1)) 3099 inc = 2; 3100 break; 3101 case 2: 3102 if (fieldFromInstruction32(Insn, 4, 2)) 3103 return Fail; // UNDEFINED 3104 index = fieldFromInstruction32(Insn, 7, 1); 3105 if (fieldFromInstruction32(Insn, 6, 1)) 3106 inc = 2; 3107 break; 3108 } 3109 3110 if (Rm != 0xF) { // Writeback 3111 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3112 } 3113 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3114 Inst.addOperand(MCOperand::CreateImm(align)); 3115 if (Rm != 0xF) { 3116 if (Rm != 0xD) 3117 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3118 else 3119 Inst.addOperand(MCOperand::CreateReg(0)); 3120 } 3121 3122 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3123 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3124 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3125 Inst.addOperand(MCOperand::CreateImm(index)); 3126 3127 return S; 3128} 3129 3130 3131static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3132 uint64_t Address, const void *Decoder) { 3133 DecodeStatus S = Success; 3134 3135 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3136 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3137 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3138 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3139 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3140 3141 unsigned align = 0; 3142 unsigned index = 0; 3143 unsigned inc = 1; 3144 switch (size) { 3145 default: 3146 return Fail; 3147 case 0: 3148 if (fieldFromInstruction32(Insn, 4, 1)) 3149 align = 4; 3150 index = fieldFromInstruction32(Insn, 5, 3); 3151 break; 3152 case 1: 3153 if (fieldFromInstruction32(Insn, 4, 1)) 3154 align = 8; 3155 index = fieldFromInstruction32(Insn, 6, 2); 3156 if (fieldFromInstruction32(Insn, 5, 1)) 3157 inc = 2; 3158 break; 3159 case 2: 3160 if (fieldFromInstruction32(Insn, 4, 2)) 3161 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3162 index = fieldFromInstruction32(Insn, 7, 1); 3163 if (fieldFromInstruction32(Insn, 6, 1)) 3164 inc = 2; 3165 break; 3166 } 3167 3168 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3169 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3170 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3171 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3172 3173 if (Rm != 0xF) { // Writeback 3174 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3175 } 3176 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3177 Inst.addOperand(MCOperand::CreateImm(align)); 3178 if (Rm != 0xF) { 3179 if (Rm != 0xD) 3180 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3181 else 3182 Inst.addOperand(MCOperand::CreateReg(0)); 3183 } 3184 3185 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3186 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3187 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3188 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3189 Inst.addOperand(MCOperand::CreateImm(index)); 3190 3191 return S; 3192} 3193 3194static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3195 uint64_t Address, const void *Decoder) { 3196 DecodeStatus S = Success; 3197 3198 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3199 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3200 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3201 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3202 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3203 3204 unsigned align = 0; 3205 unsigned index = 0; 3206 unsigned inc = 1; 3207 switch (size) { 3208 default: 3209 return Fail; 3210 case 0: 3211 if (fieldFromInstruction32(Insn, 4, 1)) 3212 align = 4; 3213 index = fieldFromInstruction32(Insn, 5, 3); 3214 break; 3215 case 1: 3216 if (fieldFromInstruction32(Insn, 4, 1)) 3217 align = 8; 3218 index = fieldFromInstruction32(Insn, 6, 2); 3219 if (fieldFromInstruction32(Insn, 5, 1)) 3220 inc = 2; 3221 break; 3222 case 2: 3223 if (fieldFromInstruction32(Insn, 4, 2)) 3224 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3225 index = fieldFromInstruction32(Insn, 7, 1); 3226 if (fieldFromInstruction32(Insn, 6, 1)) 3227 inc = 2; 3228 break; 3229 } 3230 3231 if (Rm != 0xF) { // Writeback 3232 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3233 } 3234 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3235 Inst.addOperand(MCOperand::CreateImm(align)); 3236 if (Rm != 0xF) { 3237 if (Rm != 0xD) 3238 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3239 else 3240 Inst.addOperand(MCOperand::CreateReg(0)); 3241 } 3242 3243 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3244 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3245 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3246 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3247 Inst.addOperand(MCOperand::CreateImm(index)); 3248 3249 return S; 3250} 3251 3252static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3253 uint64_t Address, const void *Decoder) { 3254 DecodeStatus S = Success; 3255 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3256 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3257 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3258 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3259 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3260 3261 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3262 CHECK(S, Unpredictable); 3263 3264 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)); 3265 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)); 3266 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)); 3267 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)); 3268 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 3269 3270 return S; 3271} 3272 3273static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3274 uint64_t Address, const void *Decoder) { 3275 DecodeStatus S = Success; 3276 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3277 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3278 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3279 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3280 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3281 3282 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3283 CHECK(S, Unpredictable); 3284 3285 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)); 3286 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)); 3287 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)); 3288 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)); 3289 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 3290 3291 return S; 3292} 3293 3294static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond, 3295 uint64_t Address, const void *Decoder) { 3296 DecodeStatus S = Success; 3297 if (Cond == 0xF) { 3298 Cond = 0xE; 3299 CHECK(S, Unpredictable); 3300 } 3301 3302 Inst.addOperand(MCOperand::CreateImm(Cond)); 3303 return S; 3304} 3305 3306