131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===// 2a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 3a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// The LLVM Compiler Infrastructure 4a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 8a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 9a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 10a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// This file contains the ARM addressing mode implementation stuff. 11a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 12a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 13a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 14a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H 15a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 174ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach#include "llvm/ADT/APFloat.h" 184ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach#include "llvm/ADT/APInt.h" 19bc2198133a1836598b54b943420748e75d5dea94Craig Topper#include "llvm/Support/ErrorHandling.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/Support/MathExtras.h" 21a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <cassert> 22a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 23a8e2989ece6dc46df59b0768184028257f913843Evan Chengnamespace llvm { 24764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 25a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// ARM_AM - ARM Addressing Mode Stuff 26a8e2989ece6dc46df59b0768184028257f913843Evan Chengnamespace ARM_AM { 27a8e2989ece6dc46df59b0768184028257f913843Evan Cheng enum ShiftOpc { 28a8e2989ece6dc46df59b0768184028257f913843Evan Cheng no_shift = 0, 29a8e2989ece6dc46df59b0768184028257f913843Evan Cheng asr, 30a8e2989ece6dc46df59b0768184028257f913843Evan Cheng lsl, 31a8e2989ece6dc46df59b0768184028257f913843Evan Cheng lsr, 32a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ror, 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng rrx 34a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 35764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng enum AddrOpc { 377ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach sub = 0, 387ce057983ea7b8ad42d5cca1bb5d3f6941662269Jim Grosbach add 39a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 40764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 419e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen static inline const char *getAddrOpcStr(AddrOpc Op) { 429e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen return Op == sub ? "-" : ""; 439e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 449e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline const char *getShiftOpcStr(ShiftOpc Op) { 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Op) { 47bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unknown shift opc!"); 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::asr: return "asr"; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::lsl: return "lsl"; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::lsr: return "lsr"; 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::ror: return "ror"; 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::rrx: return "rrx"; 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 55764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 5642fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach static inline unsigned getShiftOpcEncoding(ShiftOpc Op) { 5742fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach switch (Op) { 58bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unknown shift opc!"); 5942fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach case ARM_AM::asr: return 2; 6042fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach case ARM_AM::lsl: return 0; 6142fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach case ARM_AM::lsr: return 1; 6242fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach case ARM_AM::ror: return 3; 6342fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach } 6442fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach } 6542fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng enum AMSubMode { 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bad_am_submode = 0, 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ia, 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ib, 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng da, 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng db 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline const char *getAMSubModeStr(AMSubMode Mode) { 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Mode) { 76bc2198133a1836598b54b943420748e75d5dea94Craig Topper default: llvm_unreachable("Unknown addressing sub-mode!"); 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::ia: return "ia"; 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::ib: return "ib"; 79a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::da: return "da"; 80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::db: return "db"; 81a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 82a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 83a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 84a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// 86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned rotr32(unsigned Val, unsigned Amt) { 87a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Amt < 32 && "Invalid rotate amount"); 88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (Val >> Amt) | (Val << ((32-Amt)&31)); 89a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 90764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 91a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned rotl32(unsigned Val, unsigned Amt) { 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Amt < 32 && "Invalid rotate amount"); 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (Val << Amt) | (Val >> ((32-Amt)&31)); 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 97764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Addressing Mode #1: shift_operand with registers 100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 101a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This 'addressing mode' is used for arithmetic instructions. It can 103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // represent things like: 104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg 105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg [asr|lsl|lsr|ror|rrx] reg 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg [asr|lsl|lsr|ror|rrx] imm 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 108a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This is stored three operands [rega, regb, opc]. The first is the base 109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg, the second is the shift amount (or reg0 if not present or imm). The 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // third operand encodes the shift opcode and the imm if a reg isn't present. 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ShOp | (Imm << 3); 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSORegOffset(unsigned Op) { 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return Op >> 3; 117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline ShiftOpc getSORegShOp(unsigned Op) { 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (ShiftOpc)(Op & 7); 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return 123a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// the 8-bit imm value. 124a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSOImmValImm(unsigned Imm) { 125a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return Imm & 0xFF; 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 127d83712ad678ae453f3342762c78142f851d3a2d3Bob Wilson /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// the rotate amount. 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSOImmValRot(unsigned Imm) { 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (Imm >> 8) * 2; 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 132764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 133a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, 134a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// computing the rotate amount to use. If this immediate value cannot be 135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// handled with a single shifter-op, determine a good rotate amount that will 136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// take a maximal chunk of bits out of the immediate. 137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSOImmValRotate(unsigned Imm) { 138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 8-bit (or less) immediates are trivially shifter_operands with a rotate 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of zero. 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((Imm & ~255U) == 0) return 0; 141764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use CTZ to compute the rotate amount. 143a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TZ = CountTrailingZeros_32(Imm); 144764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, 146a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // not 9. 147a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = TZ & ~1; 148764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we can handle this spread, return it. 150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((rotr32(Imm, RotAmt) & ~255U) == 0) 151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (32-RotAmt)&31; // HW rotates right, not left. 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1538a87ffb9252d6d66093dcd96f3b9a496dae4a439Johnny Chen // For values like 0xF000000F, we should ignore the low 6 bits, then 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // retry the hunt. 1558a87ffb9252d6d66093dcd96f3b9a496dae4a439Johnny Chen if (Imm & 63U) { 1568a87ffb9252d6d66093dcd96f3b9a496dae4a439Johnny Chen unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); 157b123b8bee0b2c3f5e296ef7ca067e20982a7dbc8Bob Wilson unsigned RotAmt2 = TZ2 & ~1; 158b123b8bee0b2c3f5e296ef7ca067e20982a7dbc8Bob Wilson if ((rotr32(Imm, RotAmt2) & ~255U) == 0) 159b123b8bee0b2c3f5e296ef7ca067e20982a7dbc8Bob Wilson return (32-RotAmt2)&31; // HW rotates right, not left. 160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 161764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we have no way to cover this span of bits with a single 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // shifter_op immediate. Return a chunk of bits that will be useful to 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // handle. 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (32-RotAmt)&31; // HW rotates right, not left. 166a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 168a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// into an shifter_operand immediate operand, return the 12-bit encoding for 170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// it. If not, return -1. 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline int getSOImmVal(unsigned Arg) { 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 8-bit (or less) immediates are trivially shifter_operands with a rotate 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of zero. 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((Arg & ~255U) == 0) return Arg; 175764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 176e6f83878bc7cc26ae2fcf3112e6a9fe687e8eba6Johnny Chen unsigned RotAmt = getSOImmValRotate(Arg); 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If this cannot be handled with a single shifter_op, bail out. 179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (rotr32(~255U, RotAmt) & Arg) 180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return -1; 181764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Encode this correctly. 183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 185764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// isSOImmTwoPartVal - Return true if the specified value can be obtained by 187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// or'ing together two SOImmVal's. 188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline bool isSOImmTwoPartVal(unsigned V) { 189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If this can be handled with a single shifter_op, bail out. 190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng V = rotr32(~255U, getSOImmValRotate(V)) & V; 191a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (V == 0) 192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 193764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If this can be handled with two shifter_op's, accept. 195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng V = rotr32(~255U, getSOImmValRotate(V)) & V; 196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return V == 0; 197a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 198764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, 200a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// return the first chunk of it. 201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSOImmTwoPartFirst(unsigned V) { 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return rotr32(255U, getSOImmValRotate(V)) & V; 203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, 206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// return the second chunk of it. 207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSOImmTwoPartSecond(unsigned V) { 208764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach // Mask out the first hunk. 209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng V = rotr32(~255U, getSOImmValRotate(V)) & V; 210764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Take what's left. 212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); 213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return V; 214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 215764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// by a left shift. Returns the shift amount to use. 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getThumbImmValShift(unsigned Imm) { 219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 8-bit (or less) immediates are trivially immediate operand with a shift 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of zero. 221a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((Imm & ~255U) == 0) return 0; 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use CTZ to compute the shift amount. 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return CountTrailingZeros_32(Imm); 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 226a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// isThumbImmShiftedVal - Return true if the specified value can be obtained 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// by left shifting a 8-bit immediate. 229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline bool isThumbImmShiftedVal(unsigned V) { 230764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach // If this can be handled with 231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng V = (~255U << getThumbImmValShift(V)) & V; 232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return V == 0; 233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 235f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed 236f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// by a left shift. Returns the shift amount to use. 237f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng static inline unsigned getThumbImm16ValShift(unsigned Imm) { 238f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // 16-bit (or less) immediates are trivially immediate operand with a shift 239f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // of zero. 240f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if ((Imm & ~65535U) == 0) return 0; 241f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 242f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // Use CTZ to compute the shift amount. 243f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return CountTrailingZeros_32(Imm); 244f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng } 245f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 246764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach /// isThumbImm16ShiftedVal - Return true if the specified value can be 247f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// obtained by left shifting a 16-bit immediate. 248f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng static inline bool isThumbImm16ShiftedVal(unsigned V) { 249764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach // If this can be handled with 250f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng V = (~65535U << getThumbImm16ValShift(V)) & V; 251f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return V == 0; 252f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng } 253f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getThumbImmNonShiftedVal - If V is a value that satisfies 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// isThumbImmShiftedVal, return the non-shiftd value. 256a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getThumbImmNonShiftedVal(unsigned V) { 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return V >> getThumbImmValShift(V); 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 2606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 261f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// getT2SOImmValSplat - Return the 12-bit encoded representation 262f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// if the specified value can be obtained by splatting the low 8 bits 263f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// into every other byte or every byte of a 32-bit value. i.e., 264f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// 00000000 00000000 00000000 abcdefgh control = 0 265f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// 00000000 abcdefgh 00000000 abcdefgh control = 1 266f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// abcdefgh 00000000 abcdefgh 00000000 control = 2 267f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 268f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// Return -1 if none of the above apply. 269f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// See ARM Reference Manual A6.3.2. 2706495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng static inline int getT2SOImmValSplatVal(unsigned V) { 271f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng unsigned u, Vs, Imm; 272f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // control = 0 273764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach if ((V & 0xffffff00) == 0) 274f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return V; 275764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 276f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // If the value is zeroes in the first byte, just shift those off 277f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng Vs = ((V & 0xff) == 0) ? V >> 8 : V; 278f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // Any passing value only has 8 bits of payload, splatted across the word 279f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng Imm = Vs & 0xff; 280f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // Likewise, any passing values have the payload splatted into the 3rd byte 281f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng u = Imm | (Imm << 16); 282f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 283f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // control = 1 or 2 284f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if (Vs == u) 285f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return (((Vs == V) ? 1 : 2) << 8) | Imm; 286f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 287f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // control = 3 288f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if (Vs == (u | (u << 8))) 289f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return (3 << 8) | Imm; 290f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 291f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return -1; 292f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng } 293f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 2946495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the 295f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// specified value is a rotated 8-bit value. Return -1 if no rotation 296f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// encoding is possible. 297f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// See ARM Reference Manual A6.3.2. 2986495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng static inline int getT2SOImmValRotateVal(unsigned V) { 299f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng unsigned RotAmt = CountLeadingZeros_32(V); 300f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if (RotAmt >= 24) 301f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return -1; 302f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 303f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // If 'Arg' can be handled with a single shifter_op return the value. 304f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if ((rotr32(0xff000000U, RotAmt) & V) == V) 305f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); 306f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 307f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return -1; 308f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng } 309f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 310f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit 311764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit 312f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// encoding for it. If not, return -1. 313f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// See ARM Reference Manual A6.3.2. 314f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng static inline int getT2SOImmVal(unsigned Arg) { 315f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // If 'Arg' is an 8-bit splat, then get the encoded value. 3166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int Splat = getT2SOImmValSplatVal(Arg); 317f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if (Splat != -1) 318f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return Splat; 319764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 320f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // If 'Arg' can be handled with a single shifter_op return the value. 3216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int Rot = getT2SOImmValRotateVal(Arg); 322f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if (Rot != -1) 323f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return Rot; 324f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 325f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return -1; 326f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng } 327764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 32865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach static inline unsigned getT2SOImmValRotate(unsigned V) { 32965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if ((V & ~255U) == 0) return 0; 33065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Use CTZ to compute the rotate amount. 33165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach unsigned RotAmt = CountTrailingZeros_32(V); 33265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return (32 - RotAmt) & 31; 33365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach } 33465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 33565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach static inline bool isT2SOImmTwoPartVal (unsigned Imm) { 33665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach unsigned V = Imm; 33765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Passing values can be any combination of splat values and shifter 33865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // values. If this can be handled with a single shifter or splat, bail 33965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // out. Those should be handled directly, not with a two-part val. 34065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmValSplatVal(V) != -1) 34165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return false; 34265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach V = rotr32 (~255U, getT2SOImmValRotate(V)) & V; 34365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (V == 0) 34465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return false; 34565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 34665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // If this can be handled as an immediate, accept. 34765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmVal(V) != -1) return true; 34865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 34965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Likewise, try masking out a splat value first. 35065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach V = Imm; 35165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) 35265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach V &= ~0xff00ff00U; 35365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) 35465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach V &= ~0x00ff00ffU; 35565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // If what's left can be handled as an immediate, accept. 35665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmVal(V) != -1) return true; 35765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 35865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Otherwise, do not accept. 35965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return false; 36065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach } 36165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 36265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) { 36365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach assert (isT2SOImmTwoPartVal(Imm) && 36465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach "Immedate cannot be encoded as two part immediate!"); 36565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Try a shifter operand as one part 36665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm; 36765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // If the rest is encodable as an immediate, then return it. 36865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmVal(V) != -1) return V; 36965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 37065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Try masking out a splat value first. 37165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) 37265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return Imm & 0xff00ff00U; 37365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 37465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // The other splat is all that's left as an option. 37565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1); 37665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return Imm & 0x00ff00ffU; 37765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach } 37865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 37965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) { 38065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Mask out the first hunk 38165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach Imm ^= getT2SOImmTwoPartFirst(Imm); 38265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Return what's left 38365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach assert (getT2SOImmVal(Imm) != -1 && 38465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach "Unable to encode second part of T2 two part SO immediate"); 38565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return Imm; 38665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach } 38765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 388f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 389a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 390a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Addressing Mode #2 391a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 392a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 393a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This is used for most simple load/store instructions. 394a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 395a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode2 := reg +/- reg shop imm 396a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode2 := reg +/- imm12 397a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // The first operand is always a Reg. The second operand is a reg if in 399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg/reg form, otherwise it's reg#0. The third field encodes the operation 400ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The 401ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // fourth operand 16-17 encodes the index mode. 402a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 403a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If this addressing mode is a frame index (before prolog/epilog insertion 404a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // and code rewriting), this operand will have the form: FI#, reg0, <offs> 405a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // with no shift amount for the frame offset. 406764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach // 407ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, 408ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes unsigned IdxMode = 0) { 409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Imm12 < (1 << 12) && "Imm too large!"); 410a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Opc == sub; 411ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ; 412a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 413a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getAM2Offset(unsigned AM2Opc) { 414a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return AM2Opc & ((1 << 12)-1); 415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 416a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline AddrOpc getAM2Op(unsigned AM2Opc) { 417a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((AM2Opc >> 12) & 1) ? sub : add; 418a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 419a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { 420ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return (ShiftOpc)((AM2Opc >> 13) & 7); 421ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 422ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes static inline unsigned getAM2IdxMode(unsigned AM2Opc) { 423ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return (AM2Opc >> 16); 424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 425764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 426764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 427a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Addressing Mode #3 429a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 431a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This is used for sign-extending loads, and load/store-pair instructions. 432a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 433a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode3 := reg +/- reg 434a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode3 := reg +/- imm8 435a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 436a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // The first operand is always a Reg. The second operand is a reg if in 437a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg/reg form, otherwise it's reg#0. The third field encodes the operation 438ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the 439ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // index mode. 440764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 441a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getAM3Opc - This function encodes the addrmode3 opc field. 442ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, 443ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes unsigned IdxMode = 0) { 444a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Opc == sub; 445ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return ((int)isSub << 8) | Offset | (IdxMode << 9); 446a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 447a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned char getAM3Offset(unsigned AM3Opc) { 448a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return AM3Opc & 0xFF; 449a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 450a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline AddrOpc getAM3Op(unsigned AM3Opc) { 451a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((AM3Opc >> 8) & 1) ? sub : add; 452a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 453ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes static inline unsigned getAM3IdxMode(unsigned AM3Opc) { 454ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return (AM3Opc >> 9); 455ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 456764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 457a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 458a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Addressing Mode #4 459a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 460a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 461a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This is used for load / store multiple instructions. 462a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 463a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode4 := reg, <mode> 464a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 465a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // The four modes are: 466a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // IA - Increment after 467a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // IB - Increment before 468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // DA - Decrement after 469a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // DB - Decrement before 470d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson // For VFP instructions, only the IA and DB modes are valid. 471a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 472a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline AMSubMode getAM4SubMode(unsigned Mode) { 473a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (AMSubMode)(Mode & 0x7); 474a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 475a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 476ab3460519e8013cdba33a416cefd55dfb418999cBob Wilson static inline unsigned getAM4ModeImm(AMSubMode SubMode) { 477ab3460519e8013cdba33a416cefd55dfb418999cBob Wilson return (int)SubMode; 478a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 479a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 481a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Addressing Mode #5 482a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 483a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 484a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This is used for coprocessor instructions, such as FP load/stores. 485a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 486a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode5 := reg +/- imm8*4 487a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 488d4d826e17081808fea81509a959a983ed5df1d36Bob Wilson // The first operand is always a Reg. The second operand encodes the 489d4d826e17081808fea81509a959a983ed5df1d36Bob Wilson // operation in bit 8 and the immediate in bits 0-7. 490764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 491a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getAM5Opc - This function encodes the addrmode5 opc field. 492a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) { 493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Opc == sub; 494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((int)isSub << 8) | Offset; 495a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 496a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned char getAM5Offset(unsigned AM5Opc) { 497a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return AM5Opc & 0xFF; 498a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 499a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline AddrOpc getAM5Op(unsigned AM5Opc) { 500a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((AM5Opc >> 8) & 1) ? sub : add; 501a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5038b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson //===--------------------------------------------------------------------===// 5048b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson // Addressing Mode #6 5058b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson //===--------------------------------------------------------------------===// 5068b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson // 5078b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson // This is used for NEON load / store instructions. 5088b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson // 509226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson // addrmode6 := reg with optional alignment 5108b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson // 511226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson // This is stored in two operands [regaddr, align]. The first is the 512226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson // address register. The second operand is the value of the alignment 513273ff31e134d48c8247e981d30e214e82568ff86Bob Wilson // specifier in bytes or zero if no explicit alignment. 514273ff31e134d48c8247e981d30e214e82568ff86Bob Wilson // Valid alignments depend on the specific instruction. 5158b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson 5166dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson //===--------------------------------------------------------------------===// 5176dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // NEON Modified Immediates 5186dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson //===--------------------------------------------------------------------===// 5196dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 5206dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // Several NEON instructions (e.g., VMOV) take a "modified immediate" 5216dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // vector operand, where a small immediate encoded in the instruction 5226dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // specifies a full NEON vector value. These modified immediates are 5236dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // represented here as encoded integers. The low 8 bits hold the immediate 5246dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold 5256dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // the "Cmode" field of the instruction. The interfaces below treat the 5266dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // Op and Cmode values as a single 5-bit value. 5276dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson 5286dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) { 5296dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson return (OpCmode << 8) | Val; 5306dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5316dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson static inline unsigned getNEONModImmOpCmode(unsigned ModImm) { 5326dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson return (ModImm >> 8) & 0x1f; 5336dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5346dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson static inline unsigned getNEONModImmVal(unsigned ModImm) { 5356dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson return ModImm & 0xff; 5366dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5376dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson 5386dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson /// decodeNEONModImm - Decode a NEON modified immediate value into the 5396dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson /// element value and the element size in bits. (If the element size is 5406dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson /// smaller than the vector, it is splatted into all the elements.) 5416dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson static inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) { 5426dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned OpCmode = getNEONModImmOpCmode(ModImm); 5436dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned Imm8 = getNEONModImmVal(ModImm); 5446dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson uint64_t Val = 0; 5456dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson 5466dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson if (OpCmode == 0xe) { 5476dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 8-bit vector elements 5486dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson Val = Imm8; 5496dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson EltBits = 8; 5506dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } else if ((OpCmode & 0xc) == 0x8) { 5516dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 16-bit vector elements 5526dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned ByteNum = (OpCmode & 0x6) >> 1; 5536dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson Val = Imm8 << (8 * ByteNum); 5546dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson EltBits = 16; 5556dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } else if ((OpCmode & 0x8) == 0) { 5566dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 32-bit vector elements, zero with one byte set 5576dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned ByteNum = (OpCmode & 0x6) >> 1; 5586dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson Val = Imm8 << (8 * ByteNum); 5596dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson EltBits = 32; 5606dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } else if ((OpCmode & 0xe) == 0xc) { 5616dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 32-bit vector elements, one byte with low bits set 5626dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned ByteNum = 1 + (OpCmode & 0x1); 5636dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); 5646dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson EltBits = 32; 5656dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } else if (OpCmode == 0x1e) { 5666dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 64-bit vector elements 5676dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) { 5686dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson if ((ModImm >> ByteNum) & 1) 5696dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson Val |= (uint64_t)0xff << (8 * ByteNum); 5706dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5716dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson EltBits = 64; 5726dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } else { 573bc2198133a1836598b54b943420748e75d5dea94Craig Topper llvm_unreachable("Unsupported NEON immediate"); 5746dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5756dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson return Val; 5766dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5776dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson 5782567eec4233d58a2a0cbdcafca9420452689b395Bill Wendling AMSubMode getLoadStoreMultipleSubMode(int Opcode); 5792567eec4233d58a2a0cbdcafca9420452689b395Bill Wendling 5804ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach //===--------------------------------------------------------------------===// 5814ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // Floating-point Immediates 5824ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // 5834ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach static inline float getFPImmFloat(unsigned Imm) { 5844ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // We expect an 8-bit binary encoding of a floating-point number here. 5854ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach union { 5864ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach uint32_t I; 5874ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach float F; 5884ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach } FPUnion; 5894ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 5904ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach uint8_t Sign = (Imm >> 7) & 0x1; 5914ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach uint8_t Exp = (Imm >> 4) & 0x7; 5924ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach uint8_t Mantissa = Imm & 0xf; 5934ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 5944ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // 8-bit FP iEEEE Float Encoding 5954ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // abcd efgh aBbbbbbc defgh000 00000000 00000000 5964ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // 5974ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // where B = NOT(b); 5984ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 5994ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach FPUnion.I = 0; 6004ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach FPUnion.I |= Sign << 31; 6014ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30; 6024ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25; 6034ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach FPUnion.I |= (Exp & 0x3) << 23; 6044ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach FPUnion.I |= Mantissa << 19; 6054ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return FPUnion.F; 6064ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach } 6074ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 6084ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit 6094ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach /// floating-point value. If the value cannot be represented as an 8-bit 6104ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach /// floating-point value, then return -1. 6114ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach static inline int getFP32Imm(const APInt &Imm) { 6124ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; 6134ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 6144ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits 6154ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 6164ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // We can handle 4 bits of mantissa. 6174ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // mantissa = (16+UInt(e:f:g:h))/16. 6184ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach if (Mantissa & 0x7ffff) 6194ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return -1; 6204ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach Mantissa >>= 19; 6214ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach if ((Mantissa & 0xf) != Mantissa) 6224ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return -1; 6234ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 6244ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 6254ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach if (Exp < -3 || Exp > 4) 6264ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return -1; 6274ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach Exp = ((Exp+3) & 0x7) ^ 4; 6284ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 6294ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return ((int)Sign << 7) | (Exp << 4) | Mantissa; 6304ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach } 6314ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 6324ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach static inline int getFP32Imm(const APFloat &FPImm) { 6334ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return getFP32Imm(FPImm.bitcastToAPInt()); 6344ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach } 6354ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 6364ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach /// getFP64Imm - Return an 8-bit floating-point version of the 64-bit 6374ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach /// floating-point value. If the value cannot be represented as an 8-bit 6384ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach /// floating-point value, then return -1. 6394ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach static inline int getFP64Imm(const APInt &Imm) { 6404ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; 6412a3f19d7e3f77d4d2f8e2b030d6ec1fa11b2abeaJim Grosbach int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 6424ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL; 6434ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 6444ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // We can handle 4 bits of mantissa. 6454ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // mantissa = (16+UInt(e:f:g:h))/16. 6464ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach if (Mantissa & 0xffffffffffffULL) 6474ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return -1; 6484ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach Mantissa >>= 48; 6494ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach if ((Mantissa & 0xf) != Mantissa) 6504ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return -1; 6514ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 6524ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 6534ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach if (Exp < -3 || Exp > 4) 6544ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return -1; 6554ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach Exp = ((Exp+3) & 0x7) ^ 4; 6564ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 6574ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return ((int)Sign << 7) | (Exp << 4) | Mantissa; 6584ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach } 6594ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 6604ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach static inline int getFP64Imm(const APFloat &FPImm) { 6614ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach return getFP64Imm(FPImm.bitcastToAPInt()); 6624ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach } 6634ebbf7b8a8e80532bd2ddf7209e62689c1698a96Jim Grosbach 664a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} // end namespace ARM_AM 665a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} // end namespace llvm 666a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 667a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#endif 668a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 669