Mips16InstrInfo.cpp revision d04a8d4b33ff316ca4cf961e06c9e312eff8e64f
10bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka//===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===// 20bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka// 30bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka// The LLVM Compiler Infrastructure 40bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka// 50bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka// This file is distributed under the University of Illinois Open Source 60bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka// License. See LICENSE.TXT for details. 70bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka// 80bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka//===----------------------------------------------------------------------===// 90bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka// 100bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka// This file contains the Mips16 implementation of the TargetInstrInfo class. 110bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka// 120bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka//===----------------------------------------------------------------------===// 130bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 140bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka#include "Mips16InstrInfo.h" 150bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka#include "InstPrinter/MipsInstPrinter.h" 16d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "MipsMachineFunction.h" 17d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "MipsTargetMachine.h" 18d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/STLExtras.h" 19d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/StringRef.h" 200bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka#include "llvm/CodeGen/MachineInstrBuilder.h" 210bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka#include "llvm/CodeGen/MachineRegisterInfo.h" 220bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka#include "llvm/Support/ErrorHandling.h" 230bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka#include "llvm/Support/TargetRegistry.h" 240bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 250bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakausing namespace llvm; 260bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 270bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira HatanakaMips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm) 2895a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler : MipsInstrInfo(tm, Mips::BimmX16), 299441125d636dee246acf9cb6c8f264edda92c335Reed Kotler RI(*tm.getSubtargetImpl(), *this) {} 308589010e3d1d5a902992a5039cffa9d4116982c5Akira Hatanaka 318589010e3d1d5a902992a5039cffa9d4116982c5Akira Hatanakaconst MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const { 328589010e3d1d5a902992a5039cffa9d4116982c5Akira Hatanaka return RI; 338589010e3d1d5a902992a5039cffa9d4116982c5Akira Hatanaka} 340bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 350bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// isLoadFromStackSlot - If the specified machine instruction is a direct 360bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// load from a stack slot, return the virtual or physical register number of 370bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// the destination along with the FrameIndex of the loaded stack slot. If 380bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// not, return 0. This predicate must return 0 if the instruction has 390bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// any side effects other than loading from the stack slot. 400bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakaunsigned Mips16InstrInfo:: 410bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira HatanakaisLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const 420bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka{ 430bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka return 0; 440bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka} 450bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 460bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// isStoreToStackSlot - If the specified machine instruction is a direct 470bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// store to a stack slot, return the virtual or physical register number of 480bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// the source reg along with the FrameIndex of the loaded stack slot. If 490bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// not, return 0. This predicate must return 0 if the instruction has 500bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// any side effects other than storing to the stack slot. 510bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakaunsigned Mips16InstrInfo:: 520bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira HatanakaisStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const 530bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka{ 540bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka return 0; 550bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka} 560bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 570bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakavoid Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 580bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka MachineBasicBlock::iterator I, DebugLoc DL, 590bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka unsigned DestReg, unsigned SrcReg, 600bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka bool KillSrc) const { 617d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler unsigned Opc = 0; 627d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler 637d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler if (Mips::CPU16RegsRegClass.contains(DestReg) && 647d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler Mips::CPURegsRegClass.contains(SrcReg)) 657d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler Opc = Mips::MoveR3216; 667d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler else if (Mips::CPURegsRegClass.contains(DestReg) && 677d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler Mips::CPU16RegsRegClass.contains(SrcReg)) 687d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler Opc = Mips::Move32R16; 697d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler else if ((SrcReg == Mips::HI) && 707d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler (Mips::CPU16RegsRegClass.contains(DestReg))) 717d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler Opc = Mips::Mfhi16, SrcReg = 0; 727d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler 737d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler else if ((SrcReg == Mips::LO) && 747d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler (Mips::CPU16RegsRegClass.contains(DestReg))) 757d90d4d709b9053f7214203c34b8be9dbd311aceReed Kotler Opc = Mips::Mflo16, SrcReg = 0; 760bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 770bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 780bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka assert(Opc && "Cannot copy registers"); 790bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 800bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 810bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 820bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka if (DestReg) 830bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka MIB.addReg(DestReg, RegState::Define); 840bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 850bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka if (SrcReg) 860bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka MIB.addReg(SrcReg, getKillRegState(KillSrc)); 870bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka} 880bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 890bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakavoid Mips16InstrInfo:: 900bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira HatanakastoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 910bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka unsigned SrcReg, bool isKill, int FI, 920bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka const TargetRegisterClass *RC, 930bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka const TargetRegisterInfo *TRI) const { 94c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler DebugLoc DL; 95c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler if (I != MBB.end()) DL = I->getDebugLoc(); 96c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 97c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler unsigned Opc = 0; 98c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) 99c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler Opc = Mips::SwRxSpImmX16; 100c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler assert(Opc && "Register class not handled!"); 101c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 102c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 1030bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka} 1040bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1050bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakavoid Mips16InstrInfo:: 1060bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira HatanakaloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 1070bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka unsigned DestReg, int FI, 1080bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka const TargetRegisterClass *RC, 1090bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka const TargetRegisterInfo *TRI) const { 110c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler DebugLoc DL; 111c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler if (I != MBB.end()) DL = I->getDebugLoc(); 112c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 113c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler unsigned Opc = 0; 114c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler 115c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) 116c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler Opc = Mips::LwRxSpImmX16; 117c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler assert(Opc && "Register class not handled!"); 118c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0) 119c94a38ff1732b960a551c7c1a4c50ede5c4737b4Reed Kotler .addMemOperand(MMO); 1200bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka} 1210bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1220bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakabool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 1230bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka MachineBasicBlock &MBB = *MI->getParent(); 1240bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1250bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka switch(MI->getDesc().getOpcode()) { 1260bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka default: 1270bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka return false; 1280bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka case Mips::RetRA16: 129c09856b5357af621fcb84a7b2b6bfbf630c244efReed Kotler ExpandRetRA16(MBB, MI, Mips::JrcRa16); 1300bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka break; 1310bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka } 1320bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1330bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka MBB.erase(MI); 1340bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka return true; 1350bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka} 1360bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1370bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// GetOppositeBranchOpc - Return the inverse of the specified 1380bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka/// opcode, e.g. turning BEQ to BNE. 1390bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakaunsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const { 14095a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler switch (Opc) { 14195a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler default: llvm_unreachable("Illegal opcode!"); 14295a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16; 14395a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16; 14495a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16; 14595a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16; 14695a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16; 14795a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BtnezX16: return Mips::BteqzX16; 14895a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16; 14995a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16; 15095a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16; 15195a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BteqzX16: return Mips::BtnezX16; 15295a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16; 15395a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16; 15495a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16; 15595a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16; 15695a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16; 15795a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16; 15895a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler } 1590bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka assert(false && "Implement this function."); 1600bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka return 0; 1610bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka} 1620bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1639441125d636dee246acf9cb6c8f264edda92c335Reed Kotler/// Adjust SP by Amount bytes. 1649441125d636dee246acf9cb6c8f264edda92c335Reed Kotlervoid Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 1659441125d636dee246acf9cb6c8f264edda92c335Reed Kotler MachineBasicBlock &MBB, 1669441125d636dee246acf9cb6c8f264edda92c335Reed Kotler MachineBasicBlock::iterator I) const { 1679441125d636dee246acf9cb6c8f264edda92c335Reed Kotler DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 1689441125d636dee246acf9cb6c8f264edda92c335Reed Kotler if (isInt<16>(Amount)) { 1699441125d636dee246acf9cb6c8f264edda92c335Reed Kotler if (Amount < 0) 1709441125d636dee246acf9cb6c8f264edda92c335Reed Kotler BuildMI(MBB, I, DL, get(Mips::SaveDecSpF16)). addImm(-Amount); 1719441125d636dee246acf9cb6c8f264edda92c335Reed Kotler else if (Amount > 0) 1729441125d636dee246acf9cb6c8f264edda92c335Reed Kotler BuildMI(MBB, I, DL, get(Mips::RestoreIncSpF16)).addImm(Amount); 1739441125d636dee246acf9cb6c8f264edda92c335Reed Kotler } 1749441125d636dee246acf9cb6c8f264edda92c335Reed Kotler else 1759441125d636dee246acf9cb6c8f264edda92c335Reed Kotler // not implemented for large values yet 1769441125d636dee246acf9cb6c8f264edda92c335Reed Kotler assert(false && "adjust stack pointer amount exceeded"); 1779441125d636dee246acf9cb6c8f264edda92c335Reed Kotler} 1789441125d636dee246acf9cb6c8f264edda92c335Reed Kotler 1790bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakaunsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const { 18095a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 || 18195a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 || 18295a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 || 18395a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 || 18495a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 || 18595a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 || 18695a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 || 18795a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 || 18895a2bb4cdf48fb927c1c7c640012118c455b6727Reed Kotler Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0; 1890bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka} 1900bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka 1910bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanakavoid Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB, 1920bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka MachineBasicBlock::iterator I, 1930bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka unsigned Opc) const { 1940bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); 1950bc1adbbc4fdc6d85a671ed70a1bbd345dba445dAkira Hatanaka} 196af2662606745bdebaa2cb43096274ce3d33b665fAkira Hatanaka 197af2662606745bdebaa2cb43096274ce3d33b665fAkira Hatanakaconst MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) { 198af2662606745bdebaa2cb43096274ce3d33b665fAkira Hatanaka return new Mips16InstrInfo(TM); 199af2662606745bdebaa2cb43096274ce3d33b665fAkira Hatanaka} 200