MipsInstrInfo.h revision 7b76da145be2b3b7518ca42b43a903eabd52e1b7 
1//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSINSTRUCTIONINFO_H
15#define MIPSINSTRUCTIONINFO_H
16
17#include "Mips.h"
18#include "llvm/Target/TargetInstrInfo.h"
19#include "MipsRegisterInfo.h"
20
21namespace llvm {
22
23namespace Mips {
24
25  // Mips Condition Codes
26  enum CondCode {
27    // To be used with float branch True
28    FCOND_F,
29    FCOND_UN,
30    FCOND_EQ,
31    FCOND_UEQ,
32    FCOND_OLT,
33    FCOND_ULT,
34    FCOND_OLE,
35    FCOND_ULE,
36    FCOND_SF,
37    FCOND_NGLE,
38    FCOND_SEQ,
39    FCOND_NGL,
40    FCOND_LT,
41    FCOND_NGE,
42    FCOND_LE,
43    FCOND_NGT,
44
45    // To be used with float branch False
46    // This conditions have the same mnemonic as the
47    // above ones, but are used with a branch False;
48    FCOND_T,
49    FCOND_OR,
50    FCOND_NEQ,
51    FCOND_OGL,
52    FCOND_UGE,
53    FCOND_OGE,
54    FCOND_UGT,
55    FCOND_OGT,
56    FCOND_ST,
57    FCOND_GLE,
58    FCOND_SNE,
59    FCOND_GL,
60    FCOND_NLT,
61    FCOND_GE,
62    FCOND_NLE,
63    FCOND_GT,
64
65    // Only integer conditions
66    COND_E,
67    COND_GZ,
68    COND_GEZ,
69    COND_LZ,
70    COND_LEZ,
71    COND_NE,
72    COND_INVALID
73  };
74
75  // Turn condition code into conditional branch opcode.
76  unsigned GetCondBranchFromCond(CondCode CC);
77
78  /// GetOppositeBranchCondition - Return the inverse of the specified cond,
79  /// e.g. turning COND_E to COND_NE.
80  CondCode GetOppositeBranchCondition(Mips::CondCode CC);
81
82  /// MipsCCToString - Map each FP condition code to its string
83  inline static const char *MipsFCCToString(Mips::CondCode CC)
84  {
85    switch (CC) {
86      default: assert(0 && "Unknown condition code");
87      case FCOND_F:
88      case FCOND_T:   return "f";
89      case FCOND_UN:
90      case FCOND_OR:  return "un";
91      case FCOND_EQ:
92      case FCOND_NEQ: return "eq";
93      case FCOND_UEQ:
94      case FCOND_OGL: return "ueq";
95      case FCOND_OLT:
96      case FCOND_UGE: return "olt";
97      case FCOND_ULT:
98      case FCOND_OGE: return "ult";
99      case FCOND_OLE:
100      case FCOND_UGT: return "ole";
101      case FCOND_ULE:
102      case FCOND_OGT: return "ule";
103      case FCOND_SF:
104      case FCOND_ST:  return "sf";
105      case FCOND_NGLE:
106      case FCOND_GLE: return "ngle";
107      case FCOND_SEQ:
108      case FCOND_SNE: return "seq";
109      case FCOND_NGL:
110      case FCOND_GL:  return "ngl";
111      case FCOND_LT:
112      case FCOND_NLT: return "lt";
113      case FCOND_NGE:
114      case FCOND_GE:  return "ge";
115      case FCOND_LE:
116      case FCOND_NLE: return "nle";
117      case FCOND_NGT:
118      case FCOND_GT:  return "gt";
119    }
120  }
121}
122
123class MipsInstrInfo : public TargetInstrInfoImpl {
124  MipsTargetMachine &TM;
125  const MipsRegisterInfo RI;
126public:
127  explicit MipsInstrInfo(MipsTargetMachine &TM);
128
129  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
130  /// such, whenever a client has an instance of instruction info, it should
131  /// always be able to get register info as well (through this method).
132  ///
133  virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
134
135  /// Return true if the instruction is a register to register move and
136  /// leave the source and dest operands in the passed parameters.
137  ///
138  virtual bool isMoveInstr(const MachineInstr &MI,
139                           unsigned &SrcReg, unsigned &DstReg) const;
140
141  /// isLoadFromStackSlot - If the specified machine instruction is a direct
142  /// load from a stack slot, return the virtual or physical register number of
143  /// the destination along with the FrameIndex of the loaded stack slot.  If
144  /// not, return 0.  This predicate must return 0 if the instruction has
145  /// any side effects other than loading from the stack slot.
146  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
147
148  /// isStoreToStackSlot - If the specified machine instruction is a direct
149  /// store to a stack slot, return the virtual or physical register number of
150  /// the source reg along with the FrameIndex of the loaded stack slot.  If
151  /// not, return 0.  This predicate must return 0 if the instruction has
152  /// any side effects other than storing to the stack slot.
153  virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
154
155  /// Branch Analysis
156  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
157                             MachineBasicBlock *&FBB,
158                             std::vector<MachineOperand> &Cond) const;
159  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
160  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
161                                MachineBasicBlock *FBB,
162                                const std::vector<MachineOperand> &Cond) const;
163  virtual void copyRegToReg(MachineBasicBlock &MBB,
164                            MachineBasicBlock::iterator I,
165                            unsigned DestReg, unsigned SrcReg,
166                            const TargetRegisterClass *DestRC,
167                            const TargetRegisterClass *SrcRC) const;
168  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
169                                   MachineBasicBlock::iterator MBBI,
170                                   unsigned SrcReg, bool isKill, int FrameIndex,
171                                   const TargetRegisterClass *RC) const;
172
173  virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
174                              SmallVectorImpl<MachineOperand> &Addr,
175                              const TargetRegisterClass *RC,
176                              SmallVectorImpl<MachineInstr*> &NewMIs) const;
177
178  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
179                                    MachineBasicBlock::iterator MBBI,
180                                    unsigned DestReg, int FrameIndex,
181                                    const TargetRegisterClass *RC) const;
182
183  virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
184                               SmallVectorImpl<MachineOperand> &Addr,
185                               const TargetRegisterClass *RC,
186                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
187
188  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
189                                          MachineInstr* MI,
190                                          SmallVectorImpl<unsigned> &Ops,
191                                          int FrameIndex) const;
192
193  virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
194                                          MachineInstr* MI,
195                                          SmallVectorImpl<unsigned> &Ops,
196                                          MachineInstr* LoadMI) const {
197    return 0;
198  }
199
200  virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
201  virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
202
203  /// Insert nop instruction when hazard condition is found
204  virtual void insertNoop(MachineBasicBlock &MBB,
205                          MachineBasicBlock::iterator MI) const;
206};
207
208}
209
210#endif
211