1//===-- MipsJITInfo.cpp - Implement the Mips JIT Interface ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the JIT interfaces for the Mips target. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "jit" 15#include "MipsJITInfo.h" 16#include "MipsInstrInfo.h" 17#include "MipsRelocations.h" 18#include "MipsSubtarget.h" 19#include "llvm/CodeGen/JITCodeEmitter.h" 20#include "llvm/IR/Function.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Support/ErrorHandling.h" 23#include "llvm/Support/Memory.h" 24#include "llvm/Support/raw_ostream.h" 25#include <cstdlib> 26using namespace llvm; 27 28 29void MipsJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { 30 unsigned NewAddr = (intptr_t)New; 31 unsigned OldAddr = (intptr_t)Old; 32 const unsigned NopInstr = 0x0; 33 34 // If the functions are in the same memory segment, insert PC-region branch. 35 if ((NewAddr & 0xF0000000) == ((OldAddr + 4) & 0xF0000000)) { 36 unsigned *OldInstruction = (unsigned *)Old; 37 *OldInstruction = 0x08000000; 38 unsigned JTargetAddr = NewAddr & 0x0FFFFFFC; 39 40 JTargetAddr >>= 2; 41 *OldInstruction |= JTargetAddr; 42 43 // Insert a NOP. 44 OldInstruction++; 45 *OldInstruction = NopInstr; 46 47 sys::Memory::InvalidateInstructionCache(Old, 2 * 4); 48 } else { 49 // We need to clear hint bits from the instruction, in case it is 'jr ra'. 50 const unsigned HintMask = 0xFFFFF83F, ReturnSequence = 0x03e00008; 51 unsigned* CurrentInstr = (unsigned*)Old; 52 unsigned CurrInstrHintClear = (*CurrentInstr) & HintMask; 53 unsigned* NextInstr = CurrentInstr + 1; 54 unsigned NextInstrHintClear = (*NextInstr) & HintMask; 55 56 // Do absolute jump if there are 2 or more instructions before return from 57 // the old function. 58 if ((CurrInstrHintClear != ReturnSequence) && 59 (NextInstrHintClear != ReturnSequence)) { 60 const unsigned LuiT0Instr = 0x3c080000, AddiuT0Instr = 0x25080000; 61 const unsigned JrT0Instr = 0x01000008; 62 // lui t0, high 16 bit of the NewAddr 63 (*(CurrentInstr++)) = LuiT0Instr | ((NewAddr & 0xffff0000) >> 16); 64 // addiu t0, t0, low 16 bit of the NewAddr 65 (*(CurrentInstr++)) = AddiuT0Instr | (NewAddr & 0x0000ffff); 66 // jr t0 67 (*(CurrentInstr++)) = JrT0Instr; 68 (*CurrentInstr) = NopInstr; 69 70 sys::Memory::InvalidateInstructionCache(Old, 4 * 4); 71 } else { 72 // Unsupported case 73 report_fatal_error("MipsJITInfo::replaceMachineCodeForFunction"); 74 } 75 } 76} 77 78/// JITCompilerFunction - This contains the address of the JIT function used to 79/// compile a function lazily. 80static TargetJITInfo::JITCompilerFn JITCompilerFunction; 81 82// Get the ASMPREFIX for the current host. This is often '_'. 83#ifndef __USER_LABEL_PREFIX__ 84#define __USER_LABEL_PREFIX__ 85#endif 86#define GETASMPREFIX2(X) #X 87#define GETASMPREFIX(X) GETASMPREFIX2(X) 88#define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__) 89 90// CompilationCallback stub - We can't use a C function with inline assembly in 91// it, because the prolog/epilog inserted by GCC won't work for us. Instead, 92// write our own wrapper, which does things our way, so we have complete control 93// over register saving and restoring. This code saves registers, calls 94// MipsCompilationCallbackC and restores registers. 95extern "C" { 96#if defined (__mips__) 97void MipsCompilationCallback(); 98 99 asm( 100 ".text\n" 101 ".align 2\n" 102 ".globl " ASMPREFIX "MipsCompilationCallback\n" 103 ASMPREFIX "MipsCompilationCallback:\n" 104 ".ent " ASMPREFIX "MipsCompilationCallback\n" 105 ".frame $sp, 32, $ra\n" 106 ".set noreorder\n" 107 ".cpload $t9\n" 108 109 "addiu $sp, $sp, -64\n" 110 ".cprestore 16\n" 111 112 // Save argument registers a0, a1, a2, a3, f12, f14 since they may contain 113 // stuff for the real target function right now. We have to act as if this 114 // whole compilation callback doesn't exist as far as the caller is 115 // concerned. We also need to save the ra register since it contains the 116 // original return address, and t8 register since it contains the address 117 // of the end of function stub. 118 "sw $a0, 20($sp)\n" 119 "sw $a1, 24($sp)\n" 120 "sw $a2, 28($sp)\n" 121 "sw $a3, 32($sp)\n" 122 "sw $ra, 36($sp)\n" 123 "sw $t8, 40($sp)\n" 124 "sdc1 $f12, 48($sp)\n" 125 "sdc1 $f14, 56($sp)\n" 126 127 // t8 points at the end of function stub. Pass the beginning of the stub 128 // to the MipsCompilationCallbackC. 129 "addiu $a0, $t8, -16\n" 130 "jal " ASMPREFIX "MipsCompilationCallbackC\n" 131 "nop\n" 132 133 // Restore registers. 134 "lw $a0, 20($sp)\n" 135 "lw $a1, 24($sp)\n" 136 "lw $a2, 28($sp)\n" 137 "lw $a3, 32($sp)\n" 138 "lw $ra, 36($sp)\n" 139 "lw $t8, 40($sp)\n" 140 "ldc1 $f12, 48($sp)\n" 141 "ldc1 $f14, 56($sp)\n" 142 "addiu $sp, $sp, 64\n" 143 144 // Jump to the (newly modified) stub to invoke the real function. 145 "addiu $t8, $t8, -16\n" 146 "jr $t8\n" 147 "nop\n" 148 149 ".set reorder\n" 150 ".end " ASMPREFIX "MipsCompilationCallback\n" 151 ); 152#else // host != Mips 153 void MipsCompilationCallback() { 154 llvm_unreachable( 155 "Cannot call MipsCompilationCallback() on a non-Mips arch!"); 156 } 157#endif 158} 159 160/// MipsCompilationCallbackC - This is the target-specific function invoked 161/// by the function stub when we did not know the real target of a call. 162/// This function must locate the start of the stub or call site and pass 163/// it into the JIT compiler function. 164extern "C" void MipsCompilationCallbackC(intptr_t StubAddr) { 165 // Get the address of the compiled code for this function. 166 intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr); 167 168 // Rewrite the function stub so that we don't end up here every time we 169 // execute the call. We're replacing the first four instructions of the 170 // stub with code that jumps to the compiled function: 171 // lui $t9, %hi(NewVal) 172 // addiu $t9, $t9, %lo(NewVal) 173 // jr $t9 174 // nop 175 176 int Hi = ((unsigned)NewVal & 0xffff0000) >> 16; 177 if ((NewVal & 0x8000) != 0) 178 Hi++; 179 int Lo = (int)(NewVal & 0xffff); 180 181 *(intptr_t *)(StubAddr) = 0xf << 26 | 25 << 16 | Hi; 182 *(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo; 183 *(intptr_t *)(StubAddr + 8) = 25 << 21 | 8; 184 *(intptr_t *)(StubAddr + 12) = 0; 185 186 sys::Memory::InvalidateInstructionCache((void*) StubAddr, 16); 187} 188 189TargetJITInfo::LazyResolverFn MipsJITInfo::getLazyResolverFunction( 190 JITCompilerFn F) { 191 JITCompilerFunction = F; 192 return MipsCompilationCallback; 193} 194 195TargetJITInfo::StubLayout MipsJITInfo::getStubLayout() { 196 // The stub contains 4 4-byte instructions, aligned at 4 bytes. See 197 // emitFunctionStub for details. 198 StubLayout Result = { 4*4, 4 }; 199 return Result; 200} 201 202void *MipsJITInfo::emitFunctionStub(const Function *F, void *Fn, 203 JITCodeEmitter &JCE) { 204 JCE.emitAlignment(4); 205 void *Addr = (void*) (JCE.getCurrentPCValue()); 206 if (!sys::Memory::setRangeWritable(Addr, 16)) 207 llvm_unreachable("ERROR: Unable to mark stub writable."); 208 209 intptr_t EmittedAddr; 210 if (Fn != (void*)(intptr_t)MipsCompilationCallback) 211 EmittedAddr = (intptr_t)Fn; 212 else 213 EmittedAddr = (intptr_t)MipsCompilationCallback; 214 215 216 int Hi = ((unsigned)EmittedAddr & 0xffff0000) >> 16; 217 if ((EmittedAddr & 0x8000) != 0) 218 Hi++; 219 int Lo = (int)(EmittedAddr & 0xffff); 220 221 // lui t9, %hi(EmittedAddr) 222 // addiu t9, t9, %lo(EmittedAddr) 223 // jalr t8, t9 224 // nop 225 if (IsLittleEndian) { 226 JCE.emitWordLE(0xf << 26 | 25 << 16 | Hi); 227 JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo); 228 JCE.emitWordLE(25 << 21 | 24 << 11 | 9); 229 JCE.emitWordLE(0); 230 } else { 231 JCE.emitWordBE(0xf << 26 | 25 << 16 | Hi); 232 JCE.emitWordBE(9 << 26 | 25 << 21 | 25 << 16 | Lo); 233 JCE.emitWordBE(25 << 21 | 24 << 11 | 9); 234 JCE.emitWordBE(0); 235 } 236 237 sys::Memory::InvalidateInstructionCache(Addr, 16); 238 if (!sys::Memory::setRangeExecutable(Addr, 16)) 239 llvm_unreachable("ERROR: Unable to mark stub executable."); 240 241 return Addr; 242} 243 244/// relocate - Before the JIT can run a block of code that has been emitted, 245/// it must rewrite the code to contain the actual addresses of any 246/// referenced global symbols. 247void MipsJITInfo::relocate(void *Function, MachineRelocation *MR, 248 unsigned NumRelocs, unsigned char *GOTBase) { 249 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { 250 251 void *RelocPos = (char*) Function + MR->getMachineCodeOffset(); 252 intptr_t ResultPtr = (intptr_t) MR->getResultPointer(); 253 254 switch ((Mips::RelocationType) MR->getRelocationType()) { 255 case Mips::reloc_mips_pc16: 256 ResultPtr = (((ResultPtr - (intptr_t) RelocPos) - 4) >> 2) & 0xffff; 257 *((unsigned*) RelocPos) |= (unsigned) ResultPtr; 258 break; 259 260 case Mips::reloc_mips_26: 261 ResultPtr = (ResultPtr & 0x0fffffff) >> 2; 262 *((unsigned*) RelocPos) |= (unsigned) ResultPtr; 263 break; 264 265 case Mips::reloc_mips_hi: 266 ResultPtr = ResultPtr >> 16; 267 if ((((intptr_t) (MR->getResultPointer()) & 0xffff) >> 15) == 1) { 268 ResultPtr += 1; 269 } 270 *((unsigned*) RelocPos) |= (unsigned) ResultPtr; 271 break; 272 273 case Mips::reloc_mips_lo: { 274 // Addend is needed for unaligned load/store instructions, where offset 275 // for the second load/store in the expanded instruction sequence must 276 // be modified by +1 or +3. Otherwise, Addend is 0. 277 int Addend = *((unsigned*) RelocPos) & 0xffff; 278 ResultPtr = (ResultPtr + Addend) & 0xffff; 279 *((unsigned*) RelocPos) &= 0xffff0000; 280 *((unsigned*) RelocPos) |= (unsigned) ResultPtr; 281 break; 282 } 283 } 284 } 285} 286