NVPTXISelDAGToDAG.h revision 49683f3c961379fbc088871a5d6304950f1f1cbc 
1//===-- NVPTXISelDAGToDAG.h - A dag to dag inst selector for NVPTX --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the NVPTX target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "nvptx-isel"
15
16#include "NVPTX.h"
17#include "NVPTXISelLowering.h"
18#include "NVPTXRegisterInfo.h"
19#include "NVPTXTargetMachine.h"
20#include "llvm/CodeGen/SelectionDAGISel.h"
21#include "llvm/Support/Compiler.h"
22#include "llvm/Intrinsics.h"
23using namespace llvm;
24
25namespace {
26
27class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
28
29  // If true, generate corresponding FPCONTRACT. This is
30  // language dependent (i.e. CUDA and OpenCL works differently).
31  bool doFMADF32;
32  bool doFMAF64;
33  bool doFMAF32;
34  bool doFMAF64AGG;
35  bool doFMAF32AGG;
36  bool allowFMA;
37
38  // 0: use div.approx
39  // 1: use div.full
40  // 2: For sm_20 and later, ieee-compliant div.rnd.f32 can be generated;
41  //    Otherwise, use div.full
42  int do_DIVF32_PREC;
43
44  // If true, add .ftz to f32 instructions.
45  // This is only meaningful for sm_20 and later, as the default
46  // is not ftz.
47  // For sm earlier than sm_20, f32 denorms are always ftz by the
48  // hardware.
49  // We always add the .ftz modifier regardless of the sm value
50  // when Use32FTZ is true.
51  bool UseF32FTZ;
52
53  // If true, generate mul.wide from sext and mul
54  bool doMulWide;
55
56public:
57  explicit NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
58                             CodeGenOpt::Level OptLevel);
59
60  // Pass Name
61  virtual const char *getPassName() const {
62    return "NVPTX DAG->DAG Pattern Instruction Selection";
63  }
64
65  const NVPTXSubtarget &Subtarget;
66
67  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
68                                            char ConstraintCode,
69                                            std::vector<SDValue> &OutOps);
70private:
71  // Include the pieces autogenerated from the target description.
72#include "NVPTXGenDAGISel.inc"
73
74  SDNode *Select(SDNode *N);
75  SDNode* SelectLoad(SDNode *N);
76  SDNode* SelectStore(SDNode *N);
77
78  inline SDValue getI32Imm(unsigned Imm) {
79    return CurDAG->getTargetConstant(Imm, MVT::i32);
80  }
81
82  // Match direct address complex pattern.
83  bool SelectDirectAddr(SDValue N, SDValue &Address);
84
85  bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
86                        SDValue &Offset, MVT mvt);
87  bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
88                    SDValue &Offset);
89  bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
90                      SDValue &Offset);
91
92  bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
93                        SDValue &Offset, MVT mvt);
94  bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
95                    SDValue &Offset);
96  bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
97                      SDValue &Offset);
98
99
100  bool ChkMemSDNodeAddressSpace(SDNode *N, unsigned int spN) const;
101
102  bool UndefOrImm(SDValue Op, SDValue N, SDValue &Retval);
103
104};
105}
106