PPCInstrInfo.cpp revision 6524287c53cf727a8ef33517403fcb1bbd7adff9 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCGenInstrInfo.inc"
16#include "PPC.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include <iostream>
19using namespace llvm;
20
21PPCInstrInfo::PPCInstrInfo()
22  : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])) {}
23
24bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
25                               unsigned& sourceReg,
26                               unsigned& destReg) const {
27  MachineOpCode oc = MI.getOpcode();
28  if (oc == PPC::OR4 || oc == PPC::OR8 ||
29      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
30    assert(MI.getNumOperands() == 3 &&
31           MI.getOperand(0).isRegister() &&
32           MI.getOperand(1).isRegister() &&
33           MI.getOperand(2).isRegister() &&
34           "invalid PPC OR instruction!");
35    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
36      sourceReg = MI.getOperand(1).getReg();
37      destReg = MI.getOperand(0).getReg();
38      return true;
39    }
40  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
41    assert(MI.getNumOperands() == 3 &&
42           MI.getOperand(0).isRegister() &&
43           MI.getOperand(2).isImmediate() &&
44           "invalid PPC ADDI instruction!");
45    if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
46      sourceReg = MI.getOperand(1).getReg();
47      destReg = MI.getOperand(0).getReg();
48      return true;
49    }
50  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
51    assert(MI.getNumOperands() == 3 &&
52           MI.getOperand(0).isRegister() &&
53           MI.getOperand(1).isRegister() &&
54           MI.getOperand(2).isImmediate() &&
55           "invalid PPC ORI instruction!");
56    if (MI.getOperand(2).getImmedValue()==0) {
57      sourceReg = MI.getOperand(1).getReg();
58      destReg = MI.getOperand(0).getReg();
59      return true;
60    }
61  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
62             oc == PPC::FMRSD) {      // fmr r1, r2
63    assert(MI.getNumOperands() == 2 &&
64           MI.getOperand(0).isRegister() &&
65           MI.getOperand(1).isRegister() &&
66           "invalid PPC FMR instruction");
67    sourceReg = MI.getOperand(1).getReg();
68    destReg = MI.getOperand(0).getReg();
69    return true;
70  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
71    assert(MI.getNumOperands() == 2 &&
72           MI.getOperand(0).isRegister() &&
73           MI.getOperand(1).isRegister() &&
74           "invalid PPC MCRF instruction");
75    sourceReg = MI.getOperand(1).getReg();
76    destReg = MI.getOperand(0).getReg();
77    return true;
78  }
79  return false;
80}
81
82unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
83                                              int &FrameIndex) const {
84  switch (MI->getOpcode()) {
85  default: break;
86  case PPC::LD:
87  case PPC::LWZ:
88  case PPC::LFS:
89  case PPC::LFD:
90    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
91        MI->getOperand(2).isFrameIndex()) {
92      FrameIndex = MI->getOperand(2).getFrameIndex();
93      return MI->getOperand(0).getReg();
94    }
95    break;
96  }
97  return 0;
98}
99
100unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
101                                          int &FrameIndex) const {
102  switch (MI->getOpcode()) {
103  default: break;
104  //case PPC::ST:  ?
105  case PPC::STW:
106  case PPC::STFS:
107  case PPC::STFD:
108    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
109        MI->getOperand(2).isFrameIndex()) {
110      FrameIndex = MI->getOperand(2).getFrameIndex();
111      return MI->getOperand(0).getReg();
112    }
113    break;
114  }
115  return 0;
116}
117
118// commuteInstruction - We can commute rlwimi instructions, but only if the
119// rotate amt is zero.  We also have to munge the immediates a bit.
120MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
121  // Normal instructions can be commuted the obvious way.
122  if (MI->getOpcode() != PPC::RLWIMI)
123    return TargetInstrInfo::commuteInstruction(MI);
124
125  // Cannot commute if it has a non-zero rotate count.
126  if (MI->getOperand(3).getImmedValue() != 0)
127    return 0;
128
129  // If we have a zero rotate count, we have:
130  //   M = mask(MB,ME)
131  //   Op0 = (Op1 & ~M) | (Op2 & M)
132  // Change this to:
133  //   M = mask((ME+1)&31, (MB-1)&31)
134  //   Op0 = (Op2 & ~M) | (Op1 & M)
135
136  // Swap op1/op2
137  unsigned Reg1 = MI->getOperand(1).getReg();
138  unsigned Reg2 = MI->getOperand(2).getReg();
139  MI->SetMachineOperandReg(2, Reg1);
140  MI->SetMachineOperandReg(1, Reg2);
141
142  // Swap the mask around.
143  unsigned MB = MI->getOperand(4).getImmedValue();
144  unsigned ME = MI->getOperand(5).getImmedValue();
145  MI->getOperand(4).setImmedValue((ME+1) & 31);
146  MI->getOperand(5).setImmedValue((MB-1) & 31);
147  return MI;
148}
149