PPCInstrInfo.cpp revision c7f3ace20c325521c68335a1689645b43b06ddf0 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
26#include "llvm/MC/MCAsmInfo.h"
27using namespace llvm;
28
29extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
30extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
31
32PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
33  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
34    RI(*TM.getSubtargetImpl(), *this) {}
35
36bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
37                               unsigned& sourceReg,
38                               unsigned& destReg,
39                               unsigned& sourceSubIdx,
40                               unsigned& destSubIdx) const {
41  sourceSubIdx = destSubIdx = 0; // No sub-registers.
42
43  unsigned oc = MI.getOpcode();
44  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
45      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
46    assert(MI.getNumOperands() >= 3 &&
47           MI.getOperand(0).isReg() &&
48           MI.getOperand(1).isReg() &&
49           MI.getOperand(2).isReg() &&
50           "invalid PPC OR instruction!");
51    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
52      sourceReg = MI.getOperand(1).getReg();
53      destReg = MI.getOperand(0).getReg();
54      return true;
55    }
56  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
57    assert(MI.getNumOperands() >= 3 &&
58           MI.getOperand(0).isReg() &&
59           MI.getOperand(2).isImm() &&
60           "invalid PPC ADDI instruction!");
61    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
62      sourceReg = MI.getOperand(1).getReg();
63      destReg = MI.getOperand(0).getReg();
64      return true;
65    }
66  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
67    assert(MI.getNumOperands() >= 3 &&
68           MI.getOperand(0).isReg() &&
69           MI.getOperand(1).isReg() &&
70           MI.getOperand(2).isImm() &&
71           "invalid PPC ORI instruction!");
72    if (MI.getOperand(2).getImm() == 0) {
73      sourceReg = MI.getOperand(1).getReg();
74      destReg = MI.getOperand(0).getReg();
75      return true;
76    }
77  } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2
78    assert(MI.getNumOperands() >= 2 &&
79           MI.getOperand(0).isReg() &&
80           MI.getOperand(1).isReg() &&
81           "invalid PPC FMR instruction");
82    sourceReg = MI.getOperand(1).getReg();
83    destReg = MI.getOperand(0).getReg();
84    return true;
85  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
86    assert(MI.getNumOperands() >= 2 &&
87           MI.getOperand(0).isReg() &&
88           MI.getOperand(1).isReg() &&
89           "invalid PPC MCRF instruction");
90    sourceReg = MI.getOperand(1).getReg();
91    destReg = MI.getOperand(0).getReg();
92    return true;
93  }
94  return false;
95}
96
97unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
98                                           int &FrameIndex) const {
99  switch (MI->getOpcode()) {
100  default: break;
101  case PPC::LD:
102  case PPC::LWZ:
103  case PPC::LFS:
104  case PPC::LFD:
105    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
106        MI->getOperand(2).isFI()) {
107      FrameIndex = MI->getOperand(2).getIndex();
108      return MI->getOperand(0).getReg();
109    }
110    break;
111  }
112  return 0;
113}
114
115unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
116                                          int &FrameIndex) const {
117  switch (MI->getOpcode()) {
118  default: break;
119  case PPC::STD:
120  case PPC::STW:
121  case PPC::STFS:
122  case PPC::STFD:
123    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
124        MI->getOperand(2).isFI()) {
125      FrameIndex = MI->getOperand(2).getIndex();
126      return MI->getOperand(0).getReg();
127    }
128    break;
129  }
130  return 0;
131}
132
133// commuteInstruction - We can commute rlwimi instructions, but only if the
134// rotate amt is zero.  We also have to munge the immediates a bit.
135MachineInstr *
136PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
137  MachineFunction &MF = *MI->getParent()->getParent();
138
139  // Normal instructions can be commuted the obvious way.
140  if (MI->getOpcode() != PPC::RLWIMI)
141    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
142
143  // Cannot commute if it has a non-zero rotate count.
144  if (MI->getOperand(3).getImm() != 0)
145    return 0;
146
147  // If we have a zero rotate count, we have:
148  //   M = mask(MB,ME)
149  //   Op0 = (Op1 & ~M) | (Op2 & M)
150  // Change this to:
151  //   M = mask((ME+1)&31, (MB-1)&31)
152  //   Op0 = (Op2 & ~M) | (Op1 & M)
153
154  // Swap op1/op2
155  unsigned Reg0 = MI->getOperand(0).getReg();
156  unsigned Reg1 = MI->getOperand(1).getReg();
157  unsigned Reg2 = MI->getOperand(2).getReg();
158  bool Reg1IsKill = MI->getOperand(1).isKill();
159  bool Reg2IsKill = MI->getOperand(2).isKill();
160  bool ChangeReg0 = false;
161  // If machine instrs are no longer in two-address forms, update
162  // destination register as well.
163  if (Reg0 == Reg1) {
164    // Must be two address instruction!
165    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
166           "Expecting a two-address instruction!");
167    Reg2IsKill = false;
168    ChangeReg0 = true;
169  }
170
171  // Masks.
172  unsigned MB = MI->getOperand(4).getImm();
173  unsigned ME = MI->getOperand(5).getImm();
174
175  if (NewMI) {
176    // Create a new instruction.
177    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
178    bool Reg0IsDead = MI->getOperand(0).isDead();
179    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
180      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
181      .addReg(Reg2, getKillRegState(Reg2IsKill))
182      .addReg(Reg1, getKillRegState(Reg1IsKill))
183      .addImm((ME+1) & 31)
184      .addImm((MB-1) & 31);
185  }
186
187  if (ChangeReg0)
188    MI->getOperand(0).setReg(Reg2);
189  MI->getOperand(2).setReg(Reg1);
190  MI->getOperand(1).setReg(Reg2);
191  MI->getOperand(2).setIsKill(Reg1IsKill);
192  MI->getOperand(1).setIsKill(Reg2IsKill);
193
194  // Swap the mask around.
195  MI->getOperand(4).setImm((ME+1) & 31);
196  MI->getOperand(5).setImm((MB-1) & 31);
197  return MI;
198}
199
200void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
201                              MachineBasicBlock::iterator MI) const {
202  DebugLoc DL;
203  if (MI != MBB.end()) DL = MI->getDebugLoc();
204
205  BuildMI(MBB, MI, DL, get(PPC::NOP));
206}
207
208
209// Branch analysis.
210bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
211                                 MachineBasicBlock *&FBB,
212                                 SmallVectorImpl<MachineOperand> &Cond,
213                                 bool AllowModify) const {
214  // If the block has no terminators, it just falls into the block after it.
215  MachineBasicBlock::iterator I = MBB.end();
216  if (I == MBB.begin())
217    return false;
218  --I;
219  while (I->isDebugValue()) {
220    if (I == MBB.begin())
221      return false;
222    --I;
223  }
224  if (!isUnpredicatedTerminator(I))
225    return false;
226
227  // Get the last instruction in the block.
228  MachineInstr *LastInst = I;
229
230  // If there is only one terminator instruction, process it.
231  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
232    if (LastInst->getOpcode() == PPC::B) {
233      if (!LastInst->getOperand(0).isMBB())
234        return true;
235      TBB = LastInst->getOperand(0).getMBB();
236      return false;
237    } else if (LastInst->getOpcode() == PPC::BCC) {
238      if (!LastInst->getOperand(2).isMBB())
239        return true;
240      // Block ends with fall-through condbranch.
241      TBB = LastInst->getOperand(2).getMBB();
242      Cond.push_back(LastInst->getOperand(0));
243      Cond.push_back(LastInst->getOperand(1));
244      return false;
245    }
246    // Otherwise, don't know what this is.
247    return true;
248  }
249
250  // Get the instruction before it if it's a terminator.
251  MachineInstr *SecondLastInst = I;
252
253  // If there are three terminators, we don't know what sort of block this is.
254  if (SecondLastInst && I != MBB.begin() &&
255      isUnpredicatedTerminator(--I))
256    return true;
257
258  // If the block ends with PPC::B and PPC:BCC, handle it.
259  if (SecondLastInst->getOpcode() == PPC::BCC &&
260      LastInst->getOpcode() == PPC::B) {
261    if (!SecondLastInst->getOperand(2).isMBB() ||
262        !LastInst->getOperand(0).isMBB())
263      return true;
264    TBB =  SecondLastInst->getOperand(2).getMBB();
265    Cond.push_back(SecondLastInst->getOperand(0));
266    Cond.push_back(SecondLastInst->getOperand(1));
267    FBB = LastInst->getOperand(0).getMBB();
268    return false;
269  }
270
271  // If the block ends with two PPC:Bs, handle it.  The second one is not
272  // executed, so remove it.
273  if (SecondLastInst->getOpcode() == PPC::B &&
274      LastInst->getOpcode() == PPC::B) {
275    if (!SecondLastInst->getOperand(0).isMBB())
276      return true;
277    TBB = SecondLastInst->getOperand(0).getMBB();
278    I = LastInst;
279    if (AllowModify)
280      I->eraseFromParent();
281    return false;
282  }
283
284  // Otherwise, can't handle this.
285  return true;
286}
287
288unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
289  MachineBasicBlock::iterator I = MBB.end();
290  if (I == MBB.begin()) return 0;
291  --I;
292  while (I->isDebugValue()) {
293    if (I == MBB.begin())
294      return 0;
295    --I;
296  }
297  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
298    return 0;
299
300  // Remove the branch.
301  I->eraseFromParent();
302
303  I = MBB.end();
304
305  if (I == MBB.begin()) return 1;
306  --I;
307  if (I->getOpcode() != PPC::BCC)
308    return 1;
309
310  // Remove the branch.
311  I->eraseFromParent();
312  return 2;
313}
314
315unsigned
316PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
317                           MachineBasicBlock *FBB,
318                           const SmallVectorImpl<MachineOperand> &Cond) const {
319  // FIXME this should probably have a DebugLoc argument
320  DebugLoc dl;
321  // Shouldn't be a fall through.
322  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
323  assert((Cond.size() == 2 || Cond.size() == 0) &&
324         "PPC branch conditions have two components!");
325
326  // One-way branch.
327  if (FBB == 0) {
328    if (Cond.empty())   // Unconditional branch
329      BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
330    else                // Conditional branch
331      BuildMI(&MBB, dl, get(PPC::BCC))
332        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
333    return 1;
334  }
335
336  // Two-way Conditional Branch.
337  BuildMI(&MBB, dl, get(PPC::BCC))
338    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
339  BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
340  return 2;
341}
342
343bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
344                                   MachineBasicBlock::iterator MI,
345                                   unsigned DestReg, unsigned SrcReg,
346                                   const TargetRegisterClass *DestRC,
347                                   const TargetRegisterClass *SrcRC) const {
348  if (DestRC != SrcRC) {
349    // Not yet supported!
350    return false;
351  }
352
353  DebugLoc DL;
354  if (MI != MBB.end()) DL = MI->getDebugLoc();
355
356  if (DestRC == PPC::GPRCRegisterClass) {
357    BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
358  } else if (DestRC == PPC::G8RCRegisterClass) {
359    BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
360  } else if (DestRC == PPC::F4RCRegisterClass ||
361             DestRC == PPC::F8RCRegisterClass) {
362    BuildMI(MBB, MI, DL, get(PPC::FMR), DestReg).addReg(SrcReg);
363  } else if (DestRC == PPC::CRRCRegisterClass) {
364    BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
365  } else if (DestRC == PPC::VRRCRegisterClass) {
366    BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
367  } else if (DestRC == PPC::CRBITRCRegisterClass) {
368    BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
369  } else {
370    // Attempt to copy register that is not GPR or FPR
371    return false;
372  }
373
374  return true;
375}
376
377bool
378PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
379                                  unsigned SrcReg, bool isKill,
380                                  int FrameIdx,
381                                  const TargetRegisterClass *RC,
382                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
383  DebugLoc DL;
384  if (RC == PPC::GPRCRegisterClass) {
385    if (SrcReg != PPC::LR) {
386      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
387                                         .addReg(SrcReg,
388                                                 getKillRegState(isKill)),
389                                         FrameIdx));
390    } else {
391      // FIXME: this spills LR immediately to memory in one step.  To do this,
392      // we use R11, which we know cannot be used in the prolog/epilog.  This is
393      // a hack.
394      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
395      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
396                                         .addReg(PPC::R11,
397                                                 getKillRegState(isKill)),
398                                         FrameIdx));
399    }
400  } else if (RC == PPC::G8RCRegisterClass) {
401    if (SrcReg != PPC::LR8) {
402      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
403                                         .addReg(SrcReg,
404                                                 getKillRegState(isKill)),
405                                         FrameIdx));
406    } else {
407      // FIXME: this spills LR immediately to memory in one step.  To do this,
408      // we use R11, which we know cannot be used in the prolog/epilog.  This is
409      // a hack.
410      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
411      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
412                                         .addReg(PPC::X11,
413                                                 getKillRegState(isKill)),
414                                         FrameIdx));
415    }
416  } else if (RC == PPC::F8RCRegisterClass) {
417    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
418                                       .addReg(SrcReg,
419                                               getKillRegState(isKill)),
420                                       FrameIdx));
421  } else if (RC == PPC::F4RCRegisterClass) {
422    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
423                                       .addReg(SrcReg,
424                                               getKillRegState(isKill)),
425                                       FrameIdx));
426  } else if (RC == PPC::CRRCRegisterClass) {
427    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
428        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
429      // FIXME (64-bit): Enable
430      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
431                                         .addReg(SrcReg,
432                                                 getKillRegState(isKill)),
433                                         FrameIdx));
434      return true;
435    } else {
436      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
437      // it's possible for the stack frame to be so big the save location is
438      // out of range of immediate offsets, necessitating another register.
439      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
440      // at the moment.
441
442      // We need to store the CR in the low 4-bits of the saved value.  First,
443      // issue a MFCR to save all of the CRBits.
444      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
445                                                           PPC::R2 : PPC::R0;
446      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), ScratchReg));
447
448      // If the saved register wasn't CR0, shift the bits left so that they are
449      // in CR0's slot.
450      if (SrcReg != PPC::CR0) {
451        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
452        // rlwinm scratch, scratch, ShiftBits, 0, 31.
453        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
454                       .addReg(ScratchReg).addImm(ShiftBits)
455                       .addImm(0).addImm(31));
456      }
457
458      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
459                                         .addReg(ScratchReg,
460                                                 getKillRegState(isKill)),
461                                         FrameIdx));
462    }
463  } else if (RC == PPC::CRBITRCRegisterClass) {
464    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
465    // backend currently only uses CR1EQ as an individual bit, this should
466    // not cause any bug. If we need other uses of CR bits, the following
467    // code may be invalid.
468    unsigned Reg = 0;
469    if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
470        SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
471      Reg = PPC::CR0;
472    else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
473             SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
474      Reg = PPC::CR1;
475    else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
476             SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
477      Reg = PPC::CR2;
478    else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
479             SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
480      Reg = PPC::CR3;
481    else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
482             SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
483      Reg = PPC::CR4;
484    else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
485             SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
486      Reg = PPC::CR5;
487    else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
488             SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
489      Reg = PPC::CR6;
490    else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
491             SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
492      Reg = PPC::CR7;
493
494    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
495                               PPC::CRRCRegisterClass, NewMIs);
496
497  } else if (RC == PPC::VRRCRegisterClass) {
498    // We don't have indexed addressing for vector loads.  Emit:
499    // R0 = ADDI FI#
500    // STVX VAL, 0, R0
501    //
502    // FIXME: We use R0 here, because it isn't available for RA.
503    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
504                                       FrameIdx, 0, 0));
505    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
506                     .addReg(SrcReg, getKillRegState(isKill))
507                     .addReg(PPC::R0)
508                     .addReg(PPC::R0));
509  } else {
510    llvm_unreachable("Unknown regclass!");
511  }
512
513  return false;
514}
515
516void
517PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
518                                  MachineBasicBlock::iterator MI,
519                                  unsigned SrcReg, bool isKill, int FrameIdx,
520                                  const TargetRegisterClass *RC) const {
521  MachineFunction &MF = *MBB.getParent();
522  SmallVector<MachineInstr*, 4> NewMIs;
523
524  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
525    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
526    FuncInfo->setSpillsCR();
527  }
528
529  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
530    MBB.insert(MI, NewMIs[i]);
531}
532
533void
534PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
535                                   unsigned DestReg, int FrameIdx,
536                                   const TargetRegisterClass *RC,
537                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
538  if (RC == PPC::GPRCRegisterClass) {
539    if (DestReg != PPC::LR) {
540      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
541                                                 DestReg), FrameIdx));
542    } else {
543      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
544                                                 PPC::R11), FrameIdx));
545      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
546    }
547  } else if (RC == PPC::G8RCRegisterClass) {
548    if (DestReg != PPC::LR8) {
549      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
550                                         FrameIdx));
551    } else {
552      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
553                                                 PPC::R11), FrameIdx));
554      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
555    }
556  } else if (RC == PPC::F8RCRegisterClass) {
557    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
558                                       FrameIdx));
559  } else if (RC == PPC::F4RCRegisterClass) {
560    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
561                                       FrameIdx));
562  } else if (RC == PPC::CRRCRegisterClass) {
563    // FIXME: We need a scatch reg here.  The trouble with using R0 is that
564    // it's possible for the stack frame to be so big the save location is
565    // out of range of immediate offsets, necessitating another register.
566    // We hack this on Darwin by reserving R2.  It's probably broken on Linux
567    // at the moment.
568    unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
569                                                          PPC::R2 : PPC::R0;
570    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
571                                       ScratchReg), FrameIdx));
572
573    // If the reloaded register isn't CR0, shift the bits right so that they are
574    // in the right CR's slot.
575    if (DestReg != PPC::CR0) {
576      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
577      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
578      NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
579                    .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
580                    .addImm(31));
581    }
582
583    NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
584                     .addReg(ScratchReg));
585  } else if (RC == PPC::CRBITRCRegisterClass) {
586
587    unsigned Reg = 0;
588    if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
589        DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
590      Reg = PPC::CR0;
591    else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
592             DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
593      Reg = PPC::CR1;
594    else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
595             DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
596      Reg = PPC::CR2;
597    else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
598             DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
599      Reg = PPC::CR3;
600    else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
601             DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
602      Reg = PPC::CR4;
603    else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
604             DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
605      Reg = PPC::CR5;
606    else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
607             DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
608      Reg = PPC::CR6;
609    else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
610             DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
611      Reg = PPC::CR7;
612
613    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
614                                PPC::CRRCRegisterClass, NewMIs);
615
616  } else if (RC == PPC::VRRCRegisterClass) {
617    // We don't have indexed addressing for vector loads.  Emit:
618    // R0 = ADDI FI#
619    // Dest = LVX 0, R0
620    //
621    // FIXME: We use R0 here, because it isn't available for RA.
622    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
623                                       FrameIdx, 0, 0));
624    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
625                     .addReg(PPC::R0));
626  } else {
627    llvm_unreachable("Unknown regclass!");
628  }
629}
630
631void
632PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
633                                   MachineBasicBlock::iterator MI,
634                                   unsigned DestReg, int FrameIdx,
635                                   const TargetRegisterClass *RC) const {
636  MachineFunction &MF = *MBB.getParent();
637  SmallVector<MachineInstr*, 4> NewMIs;
638  DebugLoc DL;
639  if (MI != MBB.end()) DL = MI->getDebugLoc();
640  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
641  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
642    MBB.insert(MI, NewMIs[i]);
643}
644
645/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
646/// copy instructions, turning them into load/store instructions.
647MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
648                                                  MachineInstr *MI,
649                                           const SmallVectorImpl<unsigned> &Ops,
650                                                  int FrameIndex) const {
651  if (Ops.size() != 1) return NULL;
652
653  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
654  // it takes more than one instruction to store it.
655  unsigned Opc = MI->getOpcode();
656  unsigned OpNum = Ops[0];
657
658  MachineInstr *NewMI = NULL;
659  if ((Opc == PPC::OR &&
660       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
661    if (OpNum == 0) {  // move -> store
662      unsigned InReg = MI->getOperand(1).getReg();
663      bool isKill = MI->getOperand(1).isKill();
664      bool isUndef = MI->getOperand(1).isUndef();
665      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
666                                .addReg(InReg,
667                                        getKillRegState(isKill) |
668                                        getUndefRegState(isUndef)),
669                                FrameIndex);
670    } else {           // move -> load
671      unsigned OutReg = MI->getOperand(0).getReg();
672      bool isDead = MI->getOperand(0).isDead();
673      bool isUndef = MI->getOperand(0).isUndef();
674      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
675                                .addReg(OutReg,
676                                        RegState::Define |
677                                        getDeadRegState(isDead) |
678                                        getUndefRegState(isUndef)),
679                                FrameIndex);
680    }
681  } else if ((Opc == PPC::OR8 &&
682              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
683    if (OpNum == 0) {  // move -> store
684      unsigned InReg = MI->getOperand(1).getReg();
685      bool isKill = MI->getOperand(1).isKill();
686      bool isUndef = MI->getOperand(1).isUndef();
687      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
688                                .addReg(InReg,
689                                        getKillRegState(isKill) |
690                                        getUndefRegState(isUndef)),
691                                FrameIndex);
692    } else {           // move -> load
693      unsigned OutReg = MI->getOperand(0).getReg();
694      bool isDead = MI->getOperand(0).isDead();
695      bool isUndef = MI->getOperand(0).isUndef();
696      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
697                                .addReg(OutReg,
698                                        RegState::Define |
699                                        getDeadRegState(isDead) |
700                                        getUndefRegState(isUndef)),
701                                FrameIndex);
702    }
703  } else if (Opc == PPC::FMR || Opc == PPC::FMRSD) {
704    // The register may be F4RC or F8RC, and that determines the memory op.
705    unsigned OrigReg = MI->getOperand(OpNum).getReg();
706    // We cannot tell the register class from a physreg alone.
707    if (TargetRegisterInfo::isPhysicalRegister(OrigReg))
708      return NULL;
709    const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(OrigReg);
710    const bool is64 = RC == PPC::F8RCRegisterClass;
711
712    if (OpNum == 0) {  // move -> store
713      unsigned InReg = MI->getOperand(1).getReg();
714      bool isKill = MI->getOperand(1).isKill();
715      bool isUndef = MI->getOperand(1).isUndef();
716      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
717                                        get(is64 ? PPC::STFD : PPC::STFS))
718                                .addReg(InReg,
719                                        getKillRegState(isKill) |
720                                        getUndefRegState(isUndef)),
721                                FrameIndex);
722    } else {           // move -> load
723      unsigned OutReg = MI->getOperand(0).getReg();
724      bool isDead = MI->getOperand(0).isDead();
725      bool isUndef = MI->getOperand(0).isUndef();
726      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
727                                        get(is64 ? PPC::LFD : PPC::LFS))
728                                .addReg(OutReg,
729                                        RegState::Define |
730                                        getDeadRegState(isDead) |
731                                        getUndefRegState(isUndef)),
732                                FrameIndex);
733    }
734  }
735
736  return NewMI;
737}
738
739bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
740                                  const SmallVectorImpl<unsigned> &Ops) const {
741  if (Ops.size() != 1) return false;
742
743  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
744  // it takes more than one instruction to store it.
745  unsigned Opc = MI->getOpcode();
746
747  if ((Opc == PPC::OR &&
748       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
749    return true;
750  else if ((Opc == PPC::OR8 &&
751              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
752    return true;
753  else if (Opc == PPC::FMR || Opc == PPC::FMRSD)
754    return true;
755
756  return false;
757}
758
759
760bool PPCInstrInfo::
761ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
762  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
763  // Leave the CR# the same, but invert the condition.
764  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
765  return false;
766}
767
768/// GetInstSize - Return the number of bytes of code the specified
769/// instruction may be.  This returns the maximum number of bytes.
770///
771unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
772  switch (MI->getOpcode()) {
773  case PPC::INLINEASM: {       // Inline Asm: Variable size.
774    const MachineFunction *MF = MI->getParent()->getParent();
775    const char *AsmStr = MI->getOperand(0).getSymbolName();
776    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
777  }
778  case PPC::DBG_LABEL:
779  case PPC::EH_LABEL:
780  case PPC::GC_LABEL:
781    return 0;
782  default:
783    return 4; // PowerPC instructions are all 4 bytes
784  }
785}
786