1f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===// 2f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 3f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// The LLVM Compiler Infrastructure 4f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 5f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// This file is distributed under the University of Illinois Open Source 6f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// License. See LICENSE.TXT for details. 7f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 8f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 9f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 10f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \file 11f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \brief SI implementation of the TargetRegisterInfo class. 12f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// 13f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===// 14f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 15f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 16f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "SIRegisterInfo.h" 17f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUTargetMachine.h" 18f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 19f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardusing namespace llvm; 20f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 21f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardSIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm, 22f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard const TargetInstrInfo &tii) 23f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard: AMDGPURegisterInfo(tm, tii), 24f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard TM(tm), 25f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard TII(tii) 26f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard { } 27f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 28f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardBitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 29f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard BitVector Reserved(getNumRegs()); 30f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return Reserved; 31f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 32f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 33f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardconst TargetRegisterClass * 34f98f2ce29e6e2996fa58f38979143eceaa818335Tom StellardSIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const { 35f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard switch (rc->getID()) { 36f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case AMDGPU::GPRF32RegClassID: 37f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard return &AMDGPU::VReg_32RegClass; 38f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard default: return rc; 39f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 40f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 41f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard 42f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardconst TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass( 43f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard MVT VT) const { 44f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard switch(VT.SimpleTy) { 45f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard default: 46f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard case MVT::i32: return &AMDGPU::VReg_32RegClass; 47f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard } 48f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} 49