SparcInstrInfo.cpp revision 9a1ceaedc282f0cae31f2723f4d6c00c7b88fe90
17c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// The LLVM Compiler Infrastructure 4e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke//===----------------------------------------------------------------------===// 9e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 107c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner// This file contains the Sparc implementation of the TargetInstrInfo class. 11e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 12e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke//===----------------------------------------------------------------------===// 13e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 147c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "SparcInstrInfo.h" 157c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "Sparc.h" 16718cb665ca6ce2bc4d8e8479f46a45db91b49f86Owen Anderson#include "llvm/ADT/STLExtras.h" 17e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke#include "llvm/CodeGen/MachineInstrBuilder.h" 187c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "SparcGenInstrInfo.inc" 191ddf475b6a3d748427546ab8f65a712c8eea3a0fChris Lattnerusing namespace llvm; 20e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 217c90f73a1b06040d971a3dd95a491031ae6238d5Chris LattnerSparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 22718cb665ca6ce2bc4d8e8479f46a45db91b49f86Owen Anderson : TargetInstrInfo(SparcInsts, array_lengthof(SparcInsts)), 237ce45783531cfa81bfd7be561ea7e4738e8c6ca8Evan Cheng RI(ST, *this) { 24e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke} 25e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 2669d39091fe2af94d1ceebca526eabede98831a65Chris Lattnerstatic bool isZeroImm(const MachineOperand &op) { 279a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner return op.isImmediate() && op.getImm() == 0; 284658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke} 294658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke 301d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// Return true if the instruction is a register to register move and 311d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// leave the source and dest operands in the passed parameters. 321d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// 337c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattnerbool SparcInstrInfo::isMoveInstr(const MachineInstr &MI, 347c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner unsigned &SrcReg, unsigned &DstReg) const { 354658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // We look for 3 kinds of patterns here: 364658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // or with G0 or 0 374658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // add with G0 or 0 384658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // fmovs or FpMOVD (pseudo double move). 397c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) { 407c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI.getOperand(1).getReg() == SP::G0) { 414658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke DstReg = MI.getOperand(0).getReg(); 424658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke SrcReg = MI.getOperand(2).getReg(); 434658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke return true; 447c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if (MI.getOperand(2).getReg() == SP::G0) { 454658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke DstReg = MI.getOperand(0).getReg(); 464658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke SrcReg = MI.getOperand(1).getReg(); 474658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke return true; 484658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke } 497c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) && 5069d39091fe2af94d1ceebca526eabede98831a65Chris Lattner isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) { 5169d39091fe2af94d1ceebca526eabede98831a65Chris Lattner DstReg = MI.getOperand(0).getReg(); 5269d39091fe2af94d1ceebca526eabede98831a65Chris Lattner SrcReg = MI.getOperand(1).getReg(); 5369d39091fe2af94d1ceebca526eabede98831a65Chris Lattner return true; 547c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD || 557c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI.getOpcode() == SP::FMOVD) { 561d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner SrcReg = MI.getOperand(1).getReg(); 571d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner DstReg = MI.getOperand(0).getReg(); 581d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner return true; 591d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner } 601d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner return false; 611d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner} 625ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner 635ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// isLoadFromStackSlot - If the specified machine instruction is a direct 645ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// load from a stack slot, return the virtual or physical register number of 655ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// the destination along with the FrameIndex of the loaded stack slot. If 665ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// not, return 0. This predicate must return 0 if the instruction has 675ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// any side effects other than loading from the stack slot. 687c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattnerunsigned SparcInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 697c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner int &FrameIndex) const { 707c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI->getOpcode() == SP::LDri || 717c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::LDFri || 727c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::LDDFri) { 735ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && 749a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(2).getImm() == 0) { 755ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner FrameIndex = MI->getOperand(1).getFrameIndex(); 765ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return MI->getOperand(0).getReg(); 775ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 785ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 795ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return 0; 805ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner} 815ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner 825ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// isStoreToStackSlot - If the specified machine instruction is a direct 835ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// store to a stack slot, return the virtual or physical register number of 845ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// the source reg along with the FrameIndex of the loaded stack slot. If 855ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// not, return 0. This predicate must return 0 if the instruction has 865ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// any side effects other than storing to the stack slot. 877c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattnerunsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI, 887c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner int &FrameIndex) const { 897c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI->getOpcode() == SP::STri || 907c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::STFri || 917c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::STDFri) { 925ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() && 939a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(1).getImm() == 0) { 945ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner FrameIndex = MI->getOperand(0).getFrameIndex(); 955ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return MI->getOperand(2).getReg(); 965ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 975ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 985ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return 0; 995ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner} 100e87146ace88464be4ea4f8869830642c40178f1fChris Lattner 1016ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Chengunsigned 1026ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan ChengSparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 1036ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng MachineBasicBlock *FBB, 1046ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng const std::vector<MachineOperand> &Cond)const{ 105e87146ace88464be4ea4f8869830642c40178f1fChris Lattner // Can only insert uncond branches so far. 106e87146ace88464be4ea4f8869830642c40178f1fChris Lattner assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); 107c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(&MBB, get(SP::BA)).addMBB(TBB); 1086ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng return 1; 1093d7d39ab1549f5ab7a929ec18a3e6481862cf247Rafael Espindola} 110