X86MCTargetDesc.h revision 536a88ad5bf160232205192a7ce72e50bfadbded
1//===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides X86 specific target descriptions. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef X86MCTARGETDESC_H 15#define X86MCTARGETDESC_H 16 17#include "llvm/Support/DataTypes.h" 18#include <string> 19 20namespace llvm { 21class MCAsmBackend; 22class MCCodeEmitter; 23class MCContext; 24class MCInstrInfo; 25class MCObjectWriter; 26class MCRegisterInfo; 27class MCSubtargetInfo; 28class Target; 29class StringRef; 30class raw_ostream; 31 32extern Target TheX86_32Target, TheX86_64Target; 33 34/// DWARFFlavour - Flavour of dwarf regnumbers 35/// 36namespace DWARFFlavour { 37 enum { 38 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 39 }; 40} 41 42/// N86 namespace - Native X86 register numbers 43/// 44namespace N86 { 45 enum { 46 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 47 }; 48} 49 50namespace X86_MC { 51 std::string ParseX86Triple(StringRef TT); 52 53 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in 54 /// the specified arguments. If we can't run cpuid on the host, return true. 55 bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, 56 unsigned *rEBX, unsigned *rECX, unsigned *rEDX); 57 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 58 /// the 4 values in the specified arguments. If we can't run cpuid on the 59 /// host, return true. 60 bool GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX, 61 unsigned *rEBX, unsigned *rECX, unsigned *rEDX); 62 63 void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); 64 65 unsigned getDwarfRegFlavour(StringRef TT, bool isEH); 66 67 unsigned getX86RegNum(unsigned RegNo); 68 69 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); 70 71 /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance. 72 /// This is exposed so Asm parser, etc. do not need to go through 73 /// TargetRegistry. 74 MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, 75 StringRef FS); 76} 77 78MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, 79 const MCRegisterInfo &MRI, 80 const MCSubtargetInfo &STI, 81 MCContext &Ctx); 82 83MCAsmBackend *createX86_32AsmBackend(const Target &T, StringRef TT, StringRef CPU); 84MCAsmBackend *createX86_64AsmBackend(const Target &T, StringRef TT, StringRef CPU); 85 86/// createX86MachObjectWriter - Construct an X86 Mach-O object writer. 87MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS, 88 bool Is64Bit, 89 uint32_t CPUType, 90 uint32_t CPUSubtype); 91 92/// createX86ELFObjectWriter - Construct an X86 ELF object writer. 93MCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS, 94 bool Is64Bit, 95 uint8_t OSABI); 96/// createX86WinCOFFObjectWriter - Construct an X86 Win COFF object writer. 97MCObjectWriter *createX86WinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit); 98} // End llvm namespace 99 100 101// Defines symbolic names for X86 registers. This defines a mapping from 102// register name to register number. 103// 104#define GET_REGINFO_ENUM 105#include "X86GenRegisterInfo.inc" 106 107// Defines symbolic names for the X86 instructions. 108// 109#define GET_INSTRINFO_ENUM 110#include "X86GenInstrInfo.inc" 111 112#define GET_SUBTARGETINFO_ENUM 113#include "X86GenSubtargetInfo.inc" 114 115#endif 116