X86InstrInfo.cpp revision 0e0a7a45d3d0a8c865a078459d2e1c6d8967a100 
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "X86GenInstrInfo.inc"
19using namespace llvm;
20
21X86InstrInfo::X86InstrInfo()
22  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
23}
24
25
26bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
27                               unsigned& sourceReg,
28                               unsigned& destReg) const {
29  MachineOpCode oc = MI.getOpcode();
30  if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
31      oc == X86::FpMOV) {
32      assert(MI.getNumOperands() == 2 &&
33             MI.getOperand(0).isRegister() &&
34             MI.getOperand(1).isRegister() &&
35             "invalid register-register move instruction");
36      sourceReg = MI.getOperand(1).getReg();
37      destReg = MI.getOperand(0).getReg();
38      return true;
39  }
40  return false;
41}
42
43/// convertToThreeAddress - This method must be implemented by targets that
44/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
45/// may be able to convert a two-address instruction into a true
46/// three-address instruction on demand.  This allows the X86 target (for
47/// example) to convert ADD and SHL instructions into LEA instructions if they
48/// would require register copies due to two-addressness.
49///
50/// This method returns a null pointer if the transformation cannot be
51/// performed, otherwise it returns the new instruction.
52///
53MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
54  // All instructions input are two-addr instructions.  Get the known operands.
55  unsigned Dest = MI->getOperand(0).getReg();
56  unsigned Src = MI->getOperand(1).getReg();
57
58  // FIXME: None of these instructions are promotable to LEAs without
59  // additional information.  In particular, LEA doesn't set the flags that
60  // add and inc do.  :(
61  return 0;
62
63  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
64  // we have subtarget support, enable the 16-bit LEA generation here.
65  bool DisableLEA16 = true;
66
67  switch (MI->getOpcode()) {
68  case X86::INC32r:
69    assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
70    return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
71  case X86::INC16r:
72    if (DisableLEA16) return 0;
73    assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
74    return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
75  case X86::DEC32r:
76    assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
77    return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
78  case X86::DEC16r:
79    if (DisableLEA16) return 0;
80    assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
81    return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
82  case X86::ADD32rr:
83    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
84    return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
85                     MI->getOperand(2).getReg());
86  case X86::ADD16rr:
87    if (DisableLEA16) return 0;
88    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
89    return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
90                     MI->getOperand(2).getReg());
91  case X86::ADD32ri:
92    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
93    if (MI->getOperand(2).isImmediate())
94      return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
95                          MI->getOperand(2).getImmedValue());
96    return 0;
97  case X86::ADD16ri:
98    if (DisableLEA16) return 0;
99    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
100    if (MI->getOperand(2).isImmediate())
101      return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
102                          MI->getOperand(2).getImmedValue());
103    break;
104
105  case X86::SHL16ri:
106    if (DisableLEA16) return 0;
107  case X86::SHL32ri:
108    assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
109           "Unknown shl instruction!");
110    unsigned ShAmt = MI->getOperand(2).getImmedValue();
111    if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
112      X86AddressMode AM;
113      AM.Scale = 1 << ShAmt;
114      AM.IndexReg = Src;
115      unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
116      return addFullAddress(BuildMI(Opc, 5, Dest), AM);
117    }
118    break;
119  }
120
121  return 0;
122}
123
124/// commuteInstruction - We have a few instructions that must be hacked on to
125/// commute them.
126///
127MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
128  switch (MI->getOpcode()) {
129  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
130  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
131  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
132  case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
133    unsigned Opc;
134    unsigned Size;
135    switch (MI->getOpcode()) {
136    default: assert(0 && "Unreachable!");
137    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
138    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
139    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
140    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
141    }
142    unsigned Amt = MI->getOperand(3).getImmedValue();
143    unsigned A = MI->getOperand(0).getReg();
144    unsigned B = MI->getOperand(1).getReg();
145    unsigned C = MI->getOperand(2).getReg();
146    return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
147  }
148  default:
149    return TargetInstrInfo::commuteInstruction(MI);
150  }
151}
152
153
154void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
155                              MachineBasicBlock& TMBB) const {
156  BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
157}
158
159MachineBasicBlock::iterator
160X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
161  unsigned Opcode = MI->getOpcode();
162  assert(isBranch(Opcode) && "MachineInstr must be a branch");
163  unsigned ROpcode;
164  switch (Opcode) {
165  default: assert(0 && "Cannot reverse unconditional branches!");
166  case X86::JB:  ROpcode = X86::JAE; break;
167  case X86::JAE: ROpcode = X86::JB;  break;
168  case X86::JE:  ROpcode = X86::JNE; break;
169  case X86::JNE: ROpcode = X86::JE;  break;
170  case X86::JBE: ROpcode = X86::JA;  break;
171  case X86::JA:  ROpcode = X86::JBE; break;
172  case X86::JS:  ROpcode = X86::JNS; break;
173  case X86::JNS: ROpcode = X86::JS;  break;
174  case X86::JP:  ROpcode = X86::JNP; break;
175  case X86::JNP: ROpcode = X86::JP;  break;
176  case X86::JL:  ROpcode = X86::JGE; break;
177  case X86::JGE: ROpcode = X86::JL;  break;
178  case X86::JLE: ROpcode = X86::JG;  break;
179  case X86::JG:  ROpcode = X86::JLE; break;
180  }
181  MachineBasicBlock* MBB = MI->getParent();
182  MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
183  return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
184}
185
186