X86InstrInfo.cpp revision 0edd83bfff5b29a6d08718a0abc13aa7197c372d 
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/LLVMContext.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/CodeGen/MachineConstantPool.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/LiveVariables.h"
28#include "llvm/MC/MCInst.h"
29#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/Debug.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/raw_ostream.h"
33#include "llvm/Target/TargetOptions.h"
34#include "llvm/MC/MCAsmInfo.h"
35#include <limits>
36
37#define GET_INSTRINFO_CTOR
38#include "X86GenInstrInfo.inc"
39
40using namespace llvm;
41
42static cl::opt<bool>
43NoFusing("disable-spill-fusing",
44         cl::desc("Disable fusing of spill code into instructions"));
45static cl::opt<bool>
46PrintFailedFusing("print-failed-fuse-candidates",
47                  cl::desc("Print instructions that the allocator wants to"
48                           " fuse, but the X86 backend currently can't"),
49                  cl::Hidden);
50static cl::opt<bool>
51ReMatPICStubLoad("remat-pic-stub-load",
52                 cl::desc("Re-materialize load from stub in PIC mode"),
53                 cl::init(false), cl::Hidden);
54
55enum {
56  // Select which memory operand is being unfolded.
57  // (stored in bits 0 - 7)
58  TB_INDEX_0    = 0,
59  TB_INDEX_1    = 1,
60  TB_INDEX_2    = 2,
61  TB_INDEX_MASK = 0xff,
62
63  // Minimum alignment required for load/store.
64  // Used for RegOp->MemOp conversion.
65  // (stored in bits 8 - 15)
66  TB_ALIGN_SHIFT = 8,
67  TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
68  TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
69  TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
70  TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT,
71
72  // Do not insert the reverse map (MemOp -> RegOp) into the table.
73  // This may be needed because there is a many -> one mapping.
74  TB_NO_REVERSE   = 1 << 16,
75
76  // Do not insert the forward map (RegOp -> MemOp) into the table.
77  // This is needed for Native Client, which prohibits branch
78  // instructions from using a memory operand.
79  TB_NO_FORWARD   = 1 << 17,
80
81  TB_FOLDED_LOAD  = 1 << 18,
82  TB_FOLDED_STORE = 1 << 19
83};
84
85X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
86  : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
87                     ? X86::ADJCALLSTACKDOWN64
88                     : X86::ADJCALLSTACKDOWN32),
89                    (tm.getSubtarget<X86Subtarget>().is64Bit()
90                     ? X86::ADJCALLSTACKUP64
91                     : X86::ADJCALLSTACKUP32)),
92    TM(tm), RI(tm, *this) {
93
94  static const unsigned OpTbl2Addr[][3] = {
95    { X86::ADC32ri,     X86::ADC32mi,    0 },
96    { X86::ADC32ri8,    X86::ADC32mi8,   0 },
97    { X86::ADC32rr,     X86::ADC32mr,    0 },
98    { X86::ADC64ri32,   X86::ADC64mi32,  0 },
99    { X86::ADC64ri8,    X86::ADC64mi8,   0 },
100    { X86::ADC64rr,     X86::ADC64mr,    0 },
101    { X86::ADD16ri,     X86::ADD16mi,    0 },
102    { X86::ADD16ri8,    X86::ADD16mi8,   0 },
103    { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
104    { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
105    { X86::ADD16rr,     X86::ADD16mr,    0 },
106    { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
107    { X86::ADD32ri,     X86::ADD32mi,    0 },
108    { X86::ADD32ri8,    X86::ADD32mi8,   0 },
109    { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
110    { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
111    { X86::ADD32rr,     X86::ADD32mr,    0 },
112    { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
113    { X86::ADD64ri32,   X86::ADD64mi32,  0 },
114    { X86::ADD64ri8,    X86::ADD64mi8,   0 },
115    { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
116    { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
117    { X86::ADD64rr,     X86::ADD64mr,    0 },
118    { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
119    { X86::ADD8ri,      X86::ADD8mi,     0 },
120    { X86::ADD8rr,      X86::ADD8mr,     0 },
121    { X86::AND16ri,     X86::AND16mi,    0 },
122    { X86::AND16ri8,    X86::AND16mi8,   0 },
123    { X86::AND16rr,     X86::AND16mr,    0 },
124    { X86::AND32ri,     X86::AND32mi,    0 },
125    { X86::AND32ri8,    X86::AND32mi8,   0 },
126    { X86::AND32rr,     X86::AND32mr,    0 },
127    { X86::AND64ri32,   X86::AND64mi32,  0 },
128    { X86::AND64ri8,    X86::AND64mi8,   0 },
129    { X86::AND64rr,     X86::AND64mr,    0 },
130    { X86::AND8ri,      X86::AND8mi,     0 },
131    { X86::AND8rr,      X86::AND8mr,     0 },
132    { X86::DEC16r,      X86::DEC16m,     0 },
133    { X86::DEC32r,      X86::DEC32m,     0 },
134    { X86::DEC64_16r,   X86::DEC64_16m,  0 },
135    { X86::DEC64_32r,   X86::DEC64_32m,  0 },
136    { X86::DEC64r,      X86::DEC64m,     0 },
137    { X86::DEC8r,       X86::DEC8m,      0 },
138    { X86::INC16r,      X86::INC16m,     0 },
139    { X86::INC32r,      X86::INC32m,     0 },
140    { X86::INC64_16r,   X86::INC64_16m,  0 },
141    { X86::INC64_32r,   X86::INC64_32m,  0 },
142    { X86::INC64r,      X86::INC64m,     0 },
143    { X86::INC8r,       X86::INC8m,      0 },
144    { X86::NEG16r,      X86::NEG16m,     0 },
145    { X86::NEG32r,      X86::NEG32m,     0 },
146    { X86::NEG64r,      X86::NEG64m,     0 },
147    { X86::NEG8r,       X86::NEG8m,      0 },
148    { X86::NOT16r,      X86::NOT16m,     0 },
149    { X86::NOT32r,      X86::NOT32m,     0 },
150    { X86::NOT64r,      X86::NOT64m,     0 },
151    { X86::NOT8r,       X86::NOT8m,      0 },
152    { X86::OR16ri,      X86::OR16mi,     0 },
153    { X86::OR16ri8,     X86::OR16mi8,    0 },
154    { X86::OR16rr,      X86::OR16mr,     0 },
155    { X86::OR32ri,      X86::OR32mi,     0 },
156    { X86::OR32ri8,     X86::OR32mi8,    0 },
157    { X86::OR32rr,      X86::OR32mr,     0 },
158    { X86::OR64ri32,    X86::OR64mi32,   0 },
159    { X86::OR64ri8,     X86::OR64mi8,    0 },
160    { X86::OR64rr,      X86::OR64mr,     0 },
161    { X86::OR8ri,       X86::OR8mi,      0 },
162    { X86::OR8rr,       X86::OR8mr,      0 },
163    { X86::ROL16r1,     X86::ROL16m1,    0 },
164    { X86::ROL16rCL,    X86::ROL16mCL,   0 },
165    { X86::ROL16ri,     X86::ROL16mi,    0 },
166    { X86::ROL32r1,     X86::ROL32m1,    0 },
167    { X86::ROL32rCL,    X86::ROL32mCL,   0 },
168    { X86::ROL32ri,     X86::ROL32mi,    0 },
169    { X86::ROL64r1,     X86::ROL64m1,    0 },
170    { X86::ROL64rCL,    X86::ROL64mCL,   0 },
171    { X86::ROL64ri,     X86::ROL64mi,    0 },
172    { X86::ROL8r1,      X86::ROL8m1,     0 },
173    { X86::ROL8rCL,     X86::ROL8mCL,    0 },
174    { X86::ROL8ri,      X86::ROL8mi,     0 },
175    { X86::ROR16r1,     X86::ROR16m1,    0 },
176    { X86::ROR16rCL,    X86::ROR16mCL,   0 },
177    { X86::ROR16ri,     X86::ROR16mi,    0 },
178    { X86::ROR32r1,     X86::ROR32m1,    0 },
179    { X86::ROR32rCL,    X86::ROR32mCL,   0 },
180    { X86::ROR32ri,     X86::ROR32mi,    0 },
181    { X86::ROR64r1,     X86::ROR64m1,    0 },
182    { X86::ROR64rCL,    X86::ROR64mCL,   0 },
183    { X86::ROR64ri,     X86::ROR64mi,    0 },
184    { X86::ROR8r1,      X86::ROR8m1,     0 },
185    { X86::ROR8rCL,     X86::ROR8mCL,    0 },
186    { X86::ROR8ri,      X86::ROR8mi,     0 },
187    { X86::SAR16r1,     X86::SAR16m1,    0 },
188    { X86::SAR16rCL,    X86::SAR16mCL,   0 },
189    { X86::SAR16ri,     X86::SAR16mi,    0 },
190    { X86::SAR32r1,     X86::SAR32m1,    0 },
191    { X86::SAR32rCL,    X86::SAR32mCL,   0 },
192    { X86::SAR32ri,     X86::SAR32mi,    0 },
193    { X86::SAR64r1,     X86::SAR64m1,    0 },
194    { X86::SAR64rCL,    X86::SAR64mCL,   0 },
195    { X86::SAR64ri,     X86::SAR64mi,    0 },
196    { X86::SAR8r1,      X86::SAR8m1,     0 },
197    { X86::SAR8rCL,     X86::SAR8mCL,    0 },
198    { X86::SAR8ri,      X86::SAR8mi,     0 },
199    { X86::SBB32ri,     X86::SBB32mi,    0 },
200    { X86::SBB32ri8,    X86::SBB32mi8,   0 },
201    { X86::SBB32rr,     X86::SBB32mr,    0 },
202    { X86::SBB64ri32,   X86::SBB64mi32,  0 },
203    { X86::SBB64ri8,    X86::SBB64mi8,   0 },
204    { X86::SBB64rr,     X86::SBB64mr,    0 },
205    { X86::SHL16rCL,    X86::SHL16mCL,   0 },
206    { X86::SHL16ri,     X86::SHL16mi,    0 },
207    { X86::SHL32rCL,    X86::SHL32mCL,   0 },
208    { X86::SHL32ri,     X86::SHL32mi,    0 },
209    { X86::SHL64rCL,    X86::SHL64mCL,   0 },
210    { X86::SHL64ri,     X86::SHL64mi,    0 },
211    { X86::SHL8rCL,     X86::SHL8mCL,    0 },
212    { X86::SHL8ri,      X86::SHL8mi,     0 },
213    { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
214    { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
215    { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
216    { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
217    { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
218    { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
219    { X86::SHR16r1,     X86::SHR16m1,    0 },
220    { X86::SHR16rCL,    X86::SHR16mCL,   0 },
221    { X86::SHR16ri,     X86::SHR16mi,    0 },
222    { X86::SHR32r1,     X86::SHR32m1,    0 },
223    { X86::SHR32rCL,    X86::SHR32mCL,   0 },
224    { X86::SHR32ri,     X86::SHR32mi,    0 },
225    { X86::SHR64r1,     X86::SHR64m1,    0 },
226    { X86::SHR64rCL,    X86::SHR64mCL,   0 },
227    { X86::SHR64ri,     X86::SHR64mi,    0 },
228    { X86::SHR8r1,      X86::SHR8m1,     0 },
229    { X86::SHR8rCL,     X86::SHR8mCL,    0 },
230    { X86::SHR8ri,      X86::SHR8mi,     0 },
231    { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
232    { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
233    { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
234    { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
235    { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
236    { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
237    { X86::SUB16ri,     X86::SUB16mi,    0 },
238    { X86::SUB16ri8,    X86::SUB16mi8,   0 },
239    { X86::SUB16rr,     X86::SUB16mr,    0 },
240    { X86::SUB32ri,     X86::SUB32mi,    0 },
241    { X86::SUB32ri8,    X86::SUB32mi8,   0 },
242    { X86::SUB32rr,     X86::SUB32mr,    0 },
243    { X86::SUB64ri32,   X86::SUB64mi32,  0 },
244    { X86::SUB64ri8,    X86::SUB64mi8,   0 },
245    { X86::SUB64rr,     X86::SUB64mr,    0 },
246    { X86::SUB8ri,      X86::SUB8mi,     0 },
247    { X86::SUB8rr,      X86::SUB8mr,     0 },
248    { X86::XOR16ri,     X86::XOR16mi,    0 },
249    { X86::XOR16ri8,    X86::XOR16mi8,   0 },
250    { X86::XOR16rr,     X86::XOR16mr,    0 },
251    { X86::XOR32ri,     X86::XOR32mi,    0 },
252    { X86::XOR32ri8,    X86::XOR32mi8,   0 },
253    { X86::XOR32rr,     X86::XOR32mr,    0 },
254    { X86::XOR64ri32,   X86::XOR64mi32,  0 },
255    { X86::XOR64ri8,    X86::XOR64mi8,   0 },
256    { X86::XOR64rr,     X86::XOR64mr,    0 },
257    { X86::XOR8ri,      X86::XOR8mi,     0 },
258    { X86::XOR8rr,      X86::XOR8mr,     0 }
259  };
260
261  for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
262    unsigned RegOp = OpTbl2Addr[i][0];
263    unsigned MemOp = OpTbl2Addr[i][1];
264    unsigned Flags = OpTbl2Addr[i][2];
265    AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
266                  RegOp, MemOp,
267                  // Index 0, folded load and store, no alignment requirement.
268                  Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
269  }
270
271  static const unsigned OpTbl0[][3] = {
272    { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
273    { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
274    { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
275    { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
276    { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
277    { X86::WINCALL64r,  X86::WINCALL64m,    TB_FOLDED_LOAD },
278    { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
279    { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
280    { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
281    { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
282    { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
283    { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
284    { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
285    { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
286    { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
287    { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
288    { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
289    { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
290    { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
291    { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
292    { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
293    { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE | TB_ALIGN_16 },
294    { X86::FsMOVAPDrr,  X86::MOVSDmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
295    { X86::FsMOVAPSrr,  X86::MOVSSmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
296    { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
297    { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
298    { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
299    { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
300    { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
301    { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
302    { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
303    { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
304    { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
305    { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
306    { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
307    { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
308    { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
309    { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
310    { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
311    { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
312    { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
313    { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
314    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
315    { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
316    { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
317    { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
318    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
319    { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
320    { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
321    { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
322    { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
323    { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
324    { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
325    { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
326    { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
327    { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
328    { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
329    { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
330    { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
331    { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
332    { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
333    { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
334    { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
335    { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
336    { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
337    { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
338    { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
339    { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
340    { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
341    { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
342    { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
343    { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
344    { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
345    { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
346    { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
347    { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
348    { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
349    { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
350    // AVX 128-bit versions of foldable instructions
351    { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE | TB_ALIGN_16 },
352    { X86::FsVMOVAPDrr, X86::VMOVSDmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
353    { X86::FsVMOVAPSrr, X86::VMOVSSmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
354    { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
355    { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
356    { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
357    { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
358    { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
359    { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
360    { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
361    { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
362    { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
363    // AVX 256-bit foldable instructions
364    { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
365    { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
366    { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
367    { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
368    { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE }
369  };
370
371  for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
372    unsigned RegOp      = OpTbl0[i][0];
373    unsigned MemOp      = OpTbl0[i][1];
374    unsigned Flags      = OpTbl0[i][2];
375    AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
376                  RegOp, MemOp, TB_INDEX_0 | Flags);
377  }
378
379  static const unsigned OpTbl1[][3] = {
380    { X86::CMP16rr,         X86::CMP16rm,             0 },
381    { X86::CMP32rr,         X86::CMP32rm,             0 },
382    { X86::CMP64rr,         X86::CMP64rm,             0 },
383    { X86::CMP8rr,          X86::CMP8rm,              0 },
384    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
385    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
386    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
387    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
388    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
389    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
390    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
391    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
392    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
393    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
394    { X86::FsMOVAPDrr,      X86::MOVSDrm,             TB_NO_REVERSE },
395    { X86::FsMOVAPSrr,      X86::MOVSSrm,             TB_NO_REVERSE },
396    { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
397    { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
398    { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
399    { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
400    { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
401    { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
402    { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
403    { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
404    { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm,      TB_ALIGN_16 },
405    { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm,      TB_ALIGN_16 },
406    { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm,      TB_ALIGN_16 },
407    { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm,      TB_ALIGN_16 },
408    { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm,      TB_ALIGN_16 },
409    { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm,      0 },
410    { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
411    { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
412    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
413    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
414    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
415    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
416    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
417    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
418    { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
419    { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
420    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
421    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
422    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
423    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
424    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
425    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
426    { X86::MOV16rr,         X86::MOV16rm,             0 },
427    { X86::MOV32rr,         X86::MOV32rm,             0 },
428    { X86::MOV64rr,         X86::MOV64rm,             0 },
429    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
430    { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
431    { X86::MOV8rr,          X86::MOV8rm,              0 },
432    { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
433    { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
434    { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
435    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
436    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
437    { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
438    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
439    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
440    { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
441    { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
442    { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
443    { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
444    { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
445    { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
446    { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
447    { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
448    { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm,        0 },
449    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
450    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
451    { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
452    { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
453    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
454    { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
455    { X86::MOVZX64rr16,     X86::MOVZX64rm16,         0 },
456    { X86::MOVZX64rr32,     X86::MOVZX64rm32,         0 },
457    { X86::MOVZX64rr8,      X86::MOVZX64rm8,          0 },
458    { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
459    { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
460    { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
461    { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
462    { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
463    { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
464    { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
465    { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
466    { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
467    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
468    { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
469    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
470    { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
471    { X86::SQRTPDr_Int,     X86::SQRTPDm_Int,         TB_ALIGN_16 },
472    { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
473    { X86::SQRTPSr_Int,     X86::SQRTPSm_Int,         TB_ALIGN_16 },
474    { X86::SQRTSDr,         X86::SQRTSDm,             0 },
475    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
476    { X86::SQRTSSr,         X86::SQRTSSm,             0 },
477    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
478    { X86::TEST16rr,        X86::TEST16rm,            0 },
479    { X86::TEST32rr,        X86::TEST32rm,            0 },
480    { X86::TEST64rr,        X86::TEST64rm,            0 },
481    { X86::TEST8rr,         X86::TEST8rm,             0 },
482    // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
483    { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
484    { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
485    // AVX 128-bit versions of foldable instructions
486    { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
487    { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
488    { X86::Int_VCVTDQ2PDrr, X86::Int_VCVTDQ2PDrm,     TB_ALIGN_16 },
489    { X86::Int_VCVTDQ2PSrr, X86::Int_VCVTDQ2PSrm,     TB_ALIGN_16 },
490    { X86::Int_VCVTPD2DQrr, X86::Int_VCVTPD2DQrm,     TB_ALIGN_16 },
491    { X86::Int_VCVTPD2PSrr, X86::Int_VCVTPD2PSrm,     TB_ALIGN_16 },
492    { X86::Int_VCVTPS2DQrr, X86::Int_VCVTPS2DQrm,     TB_ALIGN_16 },
493    { X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm,     0 },
494    { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
495    { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
496    { X86::FsVMOVAPDrr,     X86::VMOVSDrm,            TB_NO_REVERSE },
497    { X86::FsVMOVAPSrr,     X86::VMOVSSrm,            TB_NO_REVERSE },
498    { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
499    { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
500    { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
501    { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
502    { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
503    { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
504    { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
505    { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
506    { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
507    { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
508    { X86::VMOVUPDrr,       X86::VMOVUPDrm,           TB_ALIGN_16 },
509    { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
510    { X86::VMOVZDI2PDIrr,   X86::VMOVZDI2PDIrm,       0 },
511    { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
512    { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
513    { X86::VPABSBrr128,     X86::VPABSBrm128,         TB_ALIGN_16 },
514    { X86::VPABSDrr128,     X86::VPABSDrm128,         TB_ALIGN_16 },
515    { X86::VPABSWrr128,     X86::VPABSWrm128,         TB_ALIGN_16 },
516    { X86::VPSHUFDri,       X86::VPSHUFDmi,           TB_ALIGN_16 },
517    { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          TB_ALIGN_16 },
518    { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          TB_ALIGN_16 },
519    { X86::VRCPPSr,         X86::VRCPPSm,             TB_ALIGN_16 },
520    { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         TB_ALIGN_16 },
521    { X86::VRSQRTPSr,       X86::VRSQRTPSm,           TB_ALIGN_16 },
522    { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       TB_ALIGN_16 },
523    { X86::VSQRTPDr,        X86::VSQRTPDm,            TB_ALIGN_16 },
524    { X86::VSQRTPDr_Int,    X86::VSQRTPDm_Int,        TB_ALIGN_16 },
525    { X86::VSQRTPSr,        X86::VSQRTPSm,            TB_ALIGN_16 },
526    { X86::VSQRTPSr_Int,    X86::VSQRTPSm_Int,        TB_ALIGN_16 },
527    { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
528    { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
529    // AVX 256-bit foldable instructions
530    { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
531    { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
532    { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_16 },
533    { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
534    { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
535    // AVX2 foldable instructions
536    { X86::VPABSBrr256,     X86::VPABSBrm256,         TB_ALIGN_16 },
537    { X86::VPABSDrr256,     X86::VPABSDrm256,         TB_ALIGN_16 },
538    { X86::VPABSWrr256,     X86::VPABSWrm256,         TB_ALIGN_16 },
539    { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          TB_ALIGN_16 },
540    { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         TB_ALIGN_16 },
541    { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         TB_ALIGN_16 }
542  };
543
544  for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
545    unsigned RegOp = OpTbl1[i][0];
546    unsigned MemOp = OpTbl1[i][1];
547    unsigned Flags = OpTbl1[i][2];
548    AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
549                  RegOp, MemOp,
550                  // Index 1, folded load
551                  Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
552  }
553
554  static const unsigned OpTbl2[][3] = {
555    { X86::ADC32rr,         X86::ADC32rm,       0 },
556    { X86::ADC64rr,         X86::ADC64rm,       0 },
557    { X86::ADD16rr,         X86::ADD16rm,       0 },
558    { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
559    { X86::ADD32rr,         X86::ADD32rm,       0 },
560    { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
561    { X86::ADD64rr,         X86::ADD64rm,       0 },
562    { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
563    { X86::ADD8rr,          X86::ADD8rm,        0 },
564    { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
565    { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
566    { X86::ADDSDrr,         X86::ADDSDrm,       0 },
567    { X86::ADDSSrr,         X86::ADDSSrm,       0 },
568    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
569    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
570    { X86::AND16rr,         X86::AND16rm,       0 },
571    { X86::AND32rr,         X86::AND32rm,       0 },
572    { X86::AND64rr,         X86::AND64rm,       0 },
573    { X86::AND8rr,          X86::AND8rm,        0 },
574    { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
575    { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
576    { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
577    { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
578    { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
579    { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
580    { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
581    { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
582    { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
583    { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
584    { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
585    { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
586    { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
587    { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
588    { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
589    { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
590    { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
591    { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
592    { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
593    { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
594    { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
595    { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
596    { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
597    { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
598    { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
599    { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
600    { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
601    { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
602    { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
603    { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
604    { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
605    { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
606    { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
607    { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
608    { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
609    { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
610    { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
611    { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
612    { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
613    { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
614    { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
615    { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
616    { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
617    { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
618    { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
619    { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
620    { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
621    { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
622    { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
623    { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
624    { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
625    { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
626    { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
627    { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
628    { X86::CMPSDrr,         X86::CMPSDrm,       0 },
629    { X86::CMPSSrr,         X86::CMPSSrm,       0 },
630    { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
631    { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
632    { X86::DIVSDrr,         X86::DIVSDrm,       0 },
633    { X86::DIVSSrr,         X86::DIVSSrm,       0 },
634    { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
635    { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
636    { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
637    { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
638    { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
639    { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
640    { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
641    { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
642    { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
643    { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
644    { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
645    { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
646    { X86::IMUL16rr,        X86::IMUL16rm,      0 },
647    { X86::IMUL32rr,        X86::IMUL32rm,      0 },
648    { X86::IMUL64rr,        X86::IMUL64rm,      0 },
649    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
650    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
651    { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
652    { X86::MAXPDrr_Int,     X86::MAXPDrm_Int,   TB_ALIGN_16 },
653    { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
654    { X86::MAXPSrr_Int,     X86::MAXPSrm_Int,   TB_ALIGN_16 },
655    { X86::MAXSDrr,         X86::MAXSDrm,       0 },
656    { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
657    { X86::MAXSSrr,         X86::MAXSSrm,       0 },
658    { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
659    { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
660    { X86::MINPDrr_Int,     X86::MINPDrm_Int,   TB_ALIGN_16 },
661    { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
662    { X86::MINPSrr_Int,     X86::MINPSrm_Int,   TB_ALIGN_16 },
663    { X86::MINSDrr,         X86::MINSDrm,       0 },
664    { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
665    { X86::MINSSrr,         X86::MINSSrm,       0 },
666    { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
667    { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
668    { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
669    { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
670    { X86::MULSDrr,         X86::MULSDrm,       0 },
671    { X86::MULSSrr,         X86::MULSSrm,       0 },
672    { X86::OR16rr,          X86::OR16rm,        0 },
673    { X86::OR32rr,          X86::OR32rm,        0 },
674    { X86::OR64rr,          X86::OR64rm,        0 },
675    { X86::OR8rr,           X86::OR8rm,         0 },
676    { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
677    { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
678    { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
679    { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
680    { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
681    { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
682    { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
683    { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
684    { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
685    { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
686    { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
687    { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
688    { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
689    { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
690    { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
691    { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
692    { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
693    { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
694    { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
695    { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
696    { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
697    { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
698    { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
699    { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
700    { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
701    { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
702    { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
703    { X86::PHADDDrr128,     X86::PHADDDrm128,   TB_ALIGN_16 },
704    { X86::PHADDWrr128,     X86::PHADDWrm128,   TB_ALIGN_16 },
705    { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
706    { X86::PHSUBDrr128,     X86::PHSUBDrm128,   TB_ALIGN_16 },
707    { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
708    { X86::PHSUBWrr128,     X86::PHSUBWrm128,   TB_ALIGN_16 },
709    { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
710    { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
711    { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
712    { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
713    { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
714    { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
715    { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
716    { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
717    { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
718    { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
719    { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
720    { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
721    { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
722    { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
723    { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
724    { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
725    { X86::PSHUFBrr128,     X86::PSHUFBrm128,   TB_ALIGN_16 },
726    { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
727    { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
728    { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
729    { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
730    { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
731    { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
732    { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
733    { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
734    { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
735    { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
736    { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
737    { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
738    { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
739    { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
740    { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
741    { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
742    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
743    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
744    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
745    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
746    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
747    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
748    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
749    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
750    { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
751    { X86::SBB32rr,         X86::SBB32rm,       0 },
752    { X86::SBB64rr,         X86::SBB64rm,       0 },
753    { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
754    { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
755    { X86::SUB16rr,         X86::SUB16rm,       0 },
756    { X86::SUB32rr,         X86::SUB32rm,       0 },
757    { X86::SUB64rr,         X86::SUB64rm,       0 },
758    { X86::SUB8rr,          X86::SUB8rm,        0 },
759    { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
760    { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
761    { X86::SUBSDrr,         X86::SUBSDrm,       0 },
762    { X86::SUBSSrr,         X86::SUBSSrm,       0 },
763    // FIXME: TEST*rr -> swapped operand of TEST*mr.
764    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
765    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
766    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
767    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
768    { X86::XOR16rr,         X86::XOR16rm,       0 },
769    { X86::XOR32rr,         X86::XOR32rm,       0 },
770    { X86::XOR64rr,         X86::XOR64rm,       0 },
771    { X86::XOR8rr,          X86::XOR8rm,        0 },
772    { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
773    { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
774    // AVX 128-bit versions of foldable instructions
775    { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
776    { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
777    { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
778    { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
779    { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
780    { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
781    { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
782    { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
783    { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
784    { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
785    { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
786    { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
787    { X86::VCVTTSD2SI64rr,    X86::VCVTTSD2SI64rm,     0 },
788    { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm, 0 },
789    { X86::VCVTTSD2SIrr,      X86::VCVTTSD2SIrm,       0 },
790    { X86::Int_VCVTTSD2SIrr,  X86::Int_VCVTTSD2SIrm,   0 },
791    { X86::VCVTTSS2SI64rr,    X86::VCVTTSS2SI64rm,     0 },
792    { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm, 0 },
793    { X86::VCVTTSS2SIrr,      X86::VCVTTSS2SIrm,       0 },
794    { X86::Int_VCVTTSS2SIrr,  X86::Int_VCVTTSS2SIrm,   0 },
795    { X86::VCVTSD2SI64rr,     X86::VCVTSD2SI64rm,      0 },
796    { X86::VCVTSD2SIrr,       X86::VCVTSD2SIrm,        0 },
797    { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQrm,       TB_ALIGN_16 },
798    { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       TB_ALIGN_16 },
799    { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
800    { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
801    { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
802    { X86::VADDPDrr,          X86::VADDPDrm,           TB_ALIGN_16 },
803    { X86::VADDPSrr,          X86::VADDPSrm,           TB_ALIGN_16 },
804    { X86::VADDSDrr,          X86::VADDSDrm,           0 },
805    { X86::VADDSSrr,          X86::VADDSSrm,           0 },
806    { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        TB_ALIGN_16 },
807    { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        TB_ALIGN_16 },
808    { X86::VANDNPDrr,         X86::VANDNPDrm,          TB_ALIGN_16 },
809    { X86::VANDNPSrr,         X86::VANDNPSrm,          TB_ALIGN_16 },
810    { X86::VANDPDrr,          X86::VANDPDrm,           TB_ALIGN_16 },
811    { X86::VANDPSrr,          X86::VANDPSrm,           TB_ALIGN_16 },
812    { X86::VCMPPDrri,         X86::VCMPPDrmi,          TB_ALIGN_16 },
813    { X86::VCMPPSrri,         X86::VCMPPSrmi,          TB_ALIGN_16 },
814    { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
815    { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
816    { X86::VDIVPDrr,          X86::VDIVPDrm,           TB_ALIGN_16 },
817    { X86::VDIVPSrr,          X86::VDIVPSrm,           TB_ALIGN_16 },
818    { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
819    { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
820    { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
821    { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
822    { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
823    { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
824    { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
825    { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
826    { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
827    { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
828    { X86::VHADDPDrr,         X86::VHADDPDrm,          TB_ALIGN_16 },
829    { X86::VHADDPSrr,         X86::VHADDPSrm,          TB_ALIGN_16 },
830    { X86::VHSUBPDrr,         X86::VHSUBPDrm,          TB_ALIGN_16 },
831    { X86::VHSUBPSrr,         X86::VHSUBPSrm,          TB_ALIGN_16 },
832    { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
833    { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
834    { X86::VMAXPDrr,          X86::VMAXPDrm,           TB_ALIGN_16 },
835    { X86::VMAXPDrr_Int,      X86::VMAXPDrm_Int,       TB_ALIGN_16 },
836    { X86::VMAXPSrr,          X86::VMAXPSrm,           TB_ALIGN_16 },
837    { X86::VMAXPSrr_Int,      X86::VMAXPSrm_Int,       TB_ALIGN_16 },
838    { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
839    { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
840    { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
841    { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
842    { X86::VMINPDrr,          X86::VMINPDrm,           TB_ALIGN_16 },
843    { X86::VMINPDrr_Int,      X86::VMINPDrm_Int,       TB_ALIGN_16 },
844    { X86::VMINPSrr,          X86::VMINPSrm,           TB_ALIGN_16 },
845    { X86::VMINPSrr_Int,      X86::VMINPSrm_Int,       TB_ALIGN_16 },
846    { X86::VMINSDrr,          X86::VMINSDrm,           0 },
847    { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
848    { X86::VMINSSrr,          X86::VMINSSrm,           0 },
849    { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
850    { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        TB_ALIGN_16 },
851    { X86::VMULPDrr,          X86::VMULPDrm,           TB_ALIGN_16 },
852    { X86::VMULPSrr,          X86::VMULPSrm,           TB_ALIGN_16 },
853    { X86::VMULSDrr,          X86::VMULSDrm,           0 },
854    { X86::VMULSSrr,          X86::VMULSSrm,           0 },
855    { X86::VORPDrr,           X86::VORPDrm,            TB_ALIGN_16 },
856    { X86::VORPSrr,           X86::VORPSrm,            TB_ALIGN_16 },
857    { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        TB_ALIGN_16 },
858    { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        TB_ALIGN_16 },
859    { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        TB_ALIGN_16 },
860    { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        TB_ALIGN_16 },
861    { X86::VPADDBrr,          X86::VPADDBrm,           TB_ALIGN_16 },
862    { X86::VPADDDrr,          X86::VPADDDrm,           TB_ALIGN_16 },
863    { X86::VPADDQrr,          X86::VPADDQrm,           TB_ALIGN_16 },
864    { X86::VPADDSBrr,         X86::VPADDSBrm,          TB_ALIGN_16 },
865    { X86::VPADDSWrr,         X86::VPADDSWrm,          TB_ALIGN_16 },
866    { X86::VPADDUSBrr,        X86::VPADDUSBrm,         TB_ALIGN_16 },
867    { X86::VPADDUSWrr,        X86::VPADDUSWrm,         TB_ALIGN_16 },
868    { X86::VPADDWrr,          X86::VPADDWrm,           TB_ALIGN_16 },
869    { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      TB_ALIGN_16 },
870    { X86::VPANDNrr,          X86::VPANDNrm,           TB_ALIGN_16 },
871    { X86::VPANDrr,           X86::VPANDrm,            TB_ALIGN_16 },
872    { X86::VPAVGBrr,          X86::VPAVGBrm,           TB_ALIGN_16 },
873    { X86::VPAVGWrr,          X86::VPAVGWrm,           TB_ALIGN_16 },
874    { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         TB_ALIGN_16 },
875    { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         TB_ALIGN_16 },
876    { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         TB_ALIGN_16 },
877    { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         TB_ALIGN_16 },
878    { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         TB_ALIGN_16 },
879    { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         TB_ALIGN_16 },
880    { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         TB_ALIGN_16 },
881    { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         TB_ALIGN_16 },
882    { X86::VPHADDDrr128,      X86::VPHADDDrm128,       TB_ALIGN_16 },
883    { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      TB_ALIGN_16 },
884    { X86::VPHADDWrr128,      X86::VPHADDWrm128,       TB_ALIGN_16 },
885    { X86::VPHSUBDrr128,      X86::VPHSUBDrm128,       TB_ALIGN_16 },
886    { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      TB_ALIGN_16 },
887    { X86::VPHSUBWrr128,      X86::VPHSUBWrm128,       TB_ALIGN_16 },
888    { X86::VPINSRWrri,        X86::VPINSRWrmi,         TB_ALIGN_16 },
889    { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    TB_ALIGN_16 },
890    { X86::VPMADDWDrr,        X86::VPMADDWDrm,         TB_ALIGN_16 },
891    { X86::VPMAXSWrr,         X86::VPMAXSWrm,          TB_ALIGN_16 },
892    { X86::VPMAXUBrr,         X86::VPMAXUBrm,          TB_ALIGN_16 },
893    { X86::VPMINSWrr,         X86::VPMINSWrm,          TB_ALIGN_16 },
894    { X86::VPMINUBrr,         X86::VPMINUBrm,          TB_ALIGN_16 },
895    { X86::VPMULDQrr,         X86::VPMULDQrm,          TB_ALIGN_16 },
896    { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     TB_ALIGN_16 },
897    { X86::VPMULHUWrr,        X86::VPMULHUWrm,         TB_ALIGN_16 },
898    { X86::VPMULHWrr,         X86::VPMULHWrm,          TB_ALIGN_16 },
899    { X86::VPMULLDrr,         X86::VPMULLDrm,          TB_ALIGN_16 },
900    { X86::VPMULLWrr,         X86::VPMULLWrm,          TB_ALIGN_16 },
901    { X86::VPMULUDQrr,        X86::VPMULUDQrm,         TB_ALIGN_16 },
902    { X86::VPORrr,            X86::VPORrm,             TB_ALIGN_16 },
903    { X86::VPSADBWrr,         X86::VPSADBWrm,          TB_ALIGN_16 },
904    { X86::VPSHUFBrr128,      X86::VPSHUFBrm128,       TB_ALIGN_16 },
905    { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       TB_ALIGN_16 },
906    { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       TB_ALIGN_16 },
907    { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       TB_ALIGN_16 },
908    { X86::VPSLLDrr,          X86::VPSLLDrm,           TB_ALIGN_16 },
909    { X86::VPSLLQrr,          X86::VPSLLQrm,           TB_ALIGN_16 },
910    { X86::VPSLLWrr,          X86::VPSLLWrm,           TB_ALIGN_16 },
911    { X86::VPSRADrr,          X86::VPSRADrm,           TB_ALIGN_16 },
912    { X86::VPSRAWrr,          X86::VPSRAWrm,           TB_ALIGN_16 },
913    { X86::VPSRLDrr,          X86::VPSRLDrm,           TB_ALIGN_16 },
914    { X86::VPSRLQrr,          X86::VPSRLQrm,           TB_ALIGN_16 },
915    { X86::VPSRLWrr,          X86::VPSRLWrm,           TB_ALIGN_16 },
916    { X86::VPSUBBrr,          X86::VPSUBBrm,           TB_ALIGN_16 },
917    { X86::VPSUBDrr,          X86::VPSUBDrm,           TB_ALIGN_16 },
918    { X86::VPSUBSBrr,         X86::VPSUBSBrm,          TB_ALIGN_16 },
919    { X86::VPSUBSWrr,         X86::VPSUBSWrm,          TB_ALIGN_16 },
920    { X86::VPSUBWrr,          X86::VPSUBWrm,           TB_ALIGN_16 },
921    { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       TB_ALIGN_16 },
922    { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       TB_ALIGN_16 },
923    { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      TB_ALIGN_16 },
924    { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       TB_ALIGN_16 },
925    { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       TB_ALIGN_16 },
926    { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       TB_ALIGN_16 },
927    { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      TB_ALIGN_16 },
928    { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       TB_ALIGN_16 },
929    { X86::VPXORrr,           X86::VPXORrm,            TB_ALIGN_16 },
930    { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         TB_ALIGN_16 },
931    { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         TB_ALIGN_16 },
932    { X86::VSUBPDrr,          X86::VSUBPDrm,           TB_ALIGN_16 },
933    { X86::VSUBPSrr,          X86::VSUBPSrm,           TB_ALIGN_16 },
934    { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
935    { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
936    { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        TB_ALIGN_16 },
937    { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        TB_ALIGN_16 },
938    { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        TB_ALIGN_16 },
939    { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        TB_ALIGN_16 },
940    { X86::VXORPDrr,          X86::VXORPDrm,           TB_ALIGN_16 },
941    { X86::VXORPSrr,          X86::VXORPSrm,           TB_ALIGN_16 },
942    // AVX2 foldable instructions
943    { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       TB_ALIGN_16 },
944    { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       TB_ALIGN_16 },
945    { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       TB_ALIGN_16 },
946    { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       TB_ALIGN_16 },
947    { X86::VPADDBYrr,         X86::VPADDBYrm,          TB_ALIGN_16 },
948    { X86::VPADDDYrr,         X86::VPADDDYrm,          TB_ALIGN_16 },
949    { X86::VPADDQYrr,         X86::VPADDQYrm,          TB_ALIGN_16 },
950    { X86::VPADDSBYrr,        X86::VPADDSBYrm,         TB_ALIGN_16 },
951    { X86::VPADDSWYrr,        X86::VPADDSWYrm,         TB_ALIGN_16 },
952    { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        TB_ALIGN_16 },
953    { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        TB_ALIGN_16 },
954    { X86::VPADDWYrr,         X86::VPADDWYrm,          TB_ALIGN_16 },
955    { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      TB_ALIGN_16 },
956    { X86::VPANDNYrr,         X86::VPANDNYrm,          TB_ALIGN_16 },
957    { X86::VPANDYrr,          X86::VPANDYrm,           TB_ALIGN_16 },
958    { X86::VPAVGBYrr,         X86::VPAVGBYrm,          TB_ALIGN_16 },
959    { X86::VPAVGWYrr,         X86::VPAVGWYrm,          TB_ALIGN_16 },
960    { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        TB_ALIGN_16 },
961    { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        TB_ALIGN_16 },
962    { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        TB_ALIGN_16 },
963    { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        TB_ALIGN_16 },
964    { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        TB_ALIGN_16 },
965    { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        TB_ALIGN_16 },
966    { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        TB_ALIGN_16 },
967    { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        TB_ALIGN_16 },
968    { X86::VPHADDDrr256,      X86::VPHADDDrm256,       TB_ALIGN_16 },
969    { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      TB_ALIGN_16 },
970    { X86::VPHADDWrr256,      X86::VPHADDWrm256,       TB_ALIGN_16 },
971    { X86::VPHSUBDrr256,      X86::VPHSUBDrm256,       TB_ALIGN_16 },
972    { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      TB_ALIGN_16 },
973    { X86::VPHSUBWrr256,      X86::VPHSUBWrm256,       TB_ALIGN_16 },
974    { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    TB_ALIGN_16 },
975    { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        TB_ALIGN_16 },
976    { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         TB_ALIGN_16 },
977    { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         TB_ALIGN_16 },
978    { X86::VPMINSWYrr,        X86::VPMINSWYrm,         TB_ALIGN_16 },
979    { X86::VPMINUBYrr,        X86::VPMINUBYrm,         TB_ALIGN_16 },
980    { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       TB_ALIGN_16 },
981    { X86::VPMULDQYrr,        X86::VPMULDQYrm,         TB_ALIGN_16 },
982    { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     TB_ALIGN_16 },
983    { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        TB_ALIGN_16 },
984    { X86::VPMULHWYrr,        X86::VPMULHWYrm,         TB_ALIGN_16 },
985    { X86::VPMULLDYrr,        X86::VPMULLDYrm,         TB_ALIGN_16 },
986    { X86::VPMULLWYrr,        X86::VPMULLWYrm,         TB_ALIGN_16 },
987    { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        TB_ALIGN_16 },
988    { X86::VPORYrr,           X86::VPORYrm,            TB_ALIGN_16 },
989    { X86::VPSADBWYrr,        X86::VPSADBWYrm,         TB_ALIGN_16 },
990    { X86::VPSHUFBrr256,      X86::VPSHUFBrm256,       TB_ALIGN_16 },
991    { X86::VPSIGNBrr256,      X86::VPSIGNBrm256,       TB_ALIGN_16 },
992    { X86::VPSIGNWrr256,      X86::VPSIGNWrm256,       TB_ALIGN_16 },
993    { X86::VPSIGNDrr256,      X86::VPSIGNDrm256,       TB_ALIGN_16 },
994    { X86::VPSLLDYrr,         X86::VPSLLDYrm,          TB_ALIGN_16 },
995    { X86::VPSLLQYrr,         X86::VPSLLQYrm,          TB_ALIGN_16 },
996    { X86::VPSLLWYrr,         X86::VPSLLWYrm,          TB_ALIGN_16 },
997    { X86::VPSLLVDrr,         X86::VPSLLVDrm,          TB_ALIGN_16 },
998    { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         TB_ALIGN_16 },
999    { X86::VPSLLVQrr,         X86::VPSLLVQrm,          TB_ALIGN_16 },
1000    { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         TB_ALIGN_16 },
1001    { X86::VPSRADYrr,         X86::VPSRADYrm,          TB_ALIGN_16 },
1002    { X86::VPSRAWYrr,         X86::VPSRAWYrm,          TB_ALIGN_16 },
1003    { X86::VPSRAVDrr,         X86::VPSRAVDrm,          TB_ALIGN_16 },
1004    { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         TB_ALIGN_16 },
1005    { X86::VPSRLDYrr,         X86::VPSRLDYrm,          TB_ALIGN_16 },
1006    { X86::VPSRLQYrr,         X86::VPSRLQYrm,          TB_ALIGN_16 },
1007    { X86::VPSRLWYrr,         X86::VPSRLWYrm,          TB_ALIGN_16 },
1008    { X86::VPSRLVDrr,         X86::VPSRLVDrm,          TB_ALIGN_16 },
1009    { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         TB_ALIGN_16 },
1010    { X86::VPSRLVQrr,         X86::VPSRLVQrm,          TB_ALIGN_16 },
1011    { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         TB_ALIGN_16 },
1012    { X86::VPSUBBYrr,         X86::VPSUBBYrm,          TB_ALIGN_16 },
1013    { X86::VPSUBDYrr,         X86::VPSUBDYrm,          TB_ALIGN_16 },
1014    { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         TB_ALIGN_16 },
1015    { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         TB_ALIGN_16 },
1016    { X86::VPSUBWYrr,         X86::VPSUBWYrm,          TB_ALIGN_16 },
1017    { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      TB_ALIGN_16 },
1018    { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      TB_ALIGN_16 },
1019    { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     TB_ALIGN_16 },
1020    { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      TB_ALIGN_16 },
1021    { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      TB_ALIGN_16 },
1022    { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      TB_ALIGN_16 },
1023    { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     TB_ALIGN_16 },
1024    { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      TB_ALIGN_16 },
1025    { X86::VPXORYrr,          X86::VPXORYrm,           TB_ALIGN_16 },
1026    // FIXME: add AVX 256-bit foldable instructions
1027  };
1028
1029  for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1030    unsigned RegOp = OpTbl2[i][0];
1031    unsigned MemOp = OpTbl2[i][1];
1032    unsigned Flags = OpTbl2[i][2];
1033    AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1034                  RegOp, MemOp,
1035                  // Index 2, folded load
1036                  Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1037  }
1038}
1039
1040void
1041X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1042                            MemOp2RegOpTableType &M2RTable,
1043                            unsigned RegOp, unsigned MemOp, unsigned Flags) {
1044    if ((Flags & TB_NO_FORWARD) == 0) {
1045      assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1046      R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1047    }
1048    if ((Flags & TB_NO_REVERSE) == 0) {
1049      assert(!M2RTable.count(MemOp) &&
1050           "Duplicated entries in unfolding maps?");
1051      M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1052    }
1053}
1054
1055bool
1056X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1057                                    unsigned &SrcReg, unsigned &DstReg,
1058                                    unsigned &SubIdx) const {
1059  switch (MI.getOpcode()) {
1060  default: break;
1061  case X86::MOVSX16rr8:
1062  case X86::MOVZX16rr8:
1063  case X86::MOVSX32rr8:
1064  case X86::MOVZX32rr8:
1065  case X86::MOVSX64rr8:
1066  case X86::MOVZX64rr8:
1067    if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1068      // It's not always legal to reference the low 8-bit of the larger
1069      // register in 32-bit mode.
1070      return false;
1071  case X86::MOVSX32rr16:
1072  case X86::MOVZX32rr16:
1073  case X86::MOVSX64rr16:
1074  case X86::MOVZX64rr16:
1075  case X86::MOVSX64rr32:
1076  case X86::MOVZX64rr32: {
1077    if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1078      // Be conservative.
1079      return false;
1080    SrcReg = MI.getOperand(1).getReg();
1081    DstReg = MI.getOperand(0).getReg();
1082    switch (MI.getOpcode()) {
1083    default:
1084      llvm_unreachable(0);
1085      break;
1086    case X86::MOVSX16rr8:
1087    case X86::MOVZX16rr8:
1088    case X86::MOVSX32rr8:
1089    case X86::MOVZX32rr8:
1090    case X86::MOVSX64rr8:
1091    case X86::MOVZX64rr8:
1092      SubIdx = X86::sub_8bit;
1093      break;
1094    case X86::MOVSX32rr16:
1095    case X86::MOVZX32rr16:
1096    case X86::MOVSX64rr16:
1097    case X86::MOVZX64rr16:
1098      SubIdx = X86::sub_16bit;
1099      break;
1100    case X86::MOVSX64rr32:
1101    case X86::MOVZX64rr32:
1102      SubIdx = X86::sub_32bit;
1103      break;
1104    }
1105    return true;
1106  }
1107  }
1108  return false;
1109}
1110
1111/// isFrameOperand - Return true and the FrameIndex if the specified
1112/// operand and follow operands form a reference to the stack frame.
1113bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1114                                  int &FrameIndex) const {
1115  if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1116      MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1117      MI->getOperand(Op+1).getImm() == 1 &&
1118      MI->getOperand(Op+2).getReg() == 0 &&
1119      MI->getOperand(Op+3).getImm() == 0) {
1120    FrameIndex = MI->getOperand(Op).getIndex();
1121    return true;
1122  }
1123  return false;
1124}
1125
1126static bool isFrameLoadOpcode(int Opcode) {
1127  switch (Opcode) {
1128  default: break;
1129  case X86::MOV8rm:
1130  case X86::MOV16rm:
1131  case X86::MOV32rm:
1132  case X86::MOV64rm:
1133  case X86::LD_Fp64m:
1134  case X86::MOVSSrm:
1135  case X86::MOVSDrm:
1136  case X86::MOVAPSrm:
1137  case X86::MOVAPDrm:
1138  case X86::MOVDQArm:
1139  case X86::VMOVSSrm:
1140  case X86::VMOVSDrm:
1141  case X86::VMOVAPSrm:
1142  case X86::VMOVAPDrm:
1143  case X86::VMOVDQArm:
1144  case X86::VMOVAPSYrm:
1145  case X86::VMOVAPDYrm:
1146  case X86::VMOVDQAYrm:
1147  case X86::MMX_MOVD64rm:
1148  case X86::MMX_MOVQ64rm:
1149    return true;
1150    break;
1151  }
1152  return false;
1153}
1154
1155static bool isFrameStoreOpcode(int Opcode) {
1156  switch (Opcode) {
1157  default: break;
1158  case X86::MOV8mr:
1159  case X86::MOV16mr:
1160  case X86::MOV32mr:
1161  case X86::MOV64mr:
1162  case X86::ST_FpP64m:
1163  case X86::MOVSSmr:
1164  case X86::MOVSDmr:
1165  case X86::MOVAPSmr:
1166  case X86::MOVAPDmr:
1167  case X86::MOVDQAmr:
1168  case X86::VMOVSSmr:
1169  case X86::VMOVSDmr:
1170  case X86::VMOVAPSmr:
1171  case X86::VMOVAPDmr:
1172  case X86::VMOVDQAmr:
1173  case X86::VMOVAPSYmr:
1174  case X86::VMOVAPDYmr:
1175  case X86::VMOVDQAYmr:
1176  case X86::MMX_MOVD64mr:
1177  case X86::MMX_MOVQ64mr:
1178  case X86::MMX_MOVNTQmr:
1179    return true;
1180  }
1181  return false;
1182}
1183
1184unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1185                                           int &FrameIndex) const {
1186  if (isFrameLoadOpcode(MI->getOpcode()))
1187    if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1188      return MI->getOperand(0).getReg();
1189  return 0;
1190}
1191
1192unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1193                                                 int &FrameIndex) const {
1194  if (isFrameLoadOpcode(MI->getOpcode())) {
1195    unsigned Reg;
1196    if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1197      return Reg;
1198    // Check for post-frame index elimination operations
1199    const MachineMemOperand *Dummy;
1200    return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1201  }
1202  return 0;
1203}
1204
1205unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1206                                          int &FrameIndex) const {
1207  if (isFrameStoreOpcode(MI->getOpcode()))
1208    if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1209        isFrameOperand(MI, 0, FrameIndex))
1210      return MI->getOperand(X86::AddrNumOperands).getReg();
1211  return 0;
1212}
1213
1214unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1215                                                int &FrameIndex) const {
1216  if (isFrameStoreOpcode(MI->getOpcode())) {
1217    unsigned Reg;
1218    if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1219      return Reg;
1220    // Check for post-frame index elimination operations
1221    const MachineMemOperand *Dummy;
1222    return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1223  }
1224  return 0;
1225}
1226
1227/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1228/// X86::MOVPC32r.
1229static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1230  bool isPICBase = false;
1231  for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1232         E = MRI.def_end(); I != E; ++I) {
1233    MachineInstr *DefMI = I.getOperand().getParent();
1234    if (DefMI->getOpcode() != X86::MOVPC32r)
1235      return false;
1236    assert(!isPICBase && "More than one PIC base?");
1237    isPICBase = true;
1238  }
1239  return isPICBase;
1240}
1241
1242bool
1243X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1244                                                AliasAnalysis *AA) const {
1245  switch (MI->getOpcode()) {
1246  default: break;
1247    case X86::MOV8rm:
1248    case X86::MOV16rm:
1249    case X86::MOV32rm:
1250    case X86::MOV64rm:
1251    case X86::LD_Fp64m:
1252    case X86::MOVSSrm:
1253    case X86::MOVSDrm:
1254    case X86::MOVAPSrm:
1255    case X86::MOVUPSrm:
1256    case X86::MOVAPDrm:
1257    case X86::MOVDQArm:
1258    case X86::VMOVSSrm:
1259    case X86::VMOVSDrm:
1260    case X86::VMOVAPSrm:
1261    case X86::VMOVUPSrm:
1262    case X86::VMOVAPDrm:
1263    case X86::VMOVDQArm:
1264    case X86::VMOVAPSYrm:
1265    case X86::VMOVUPSYrm:
1266    case X86::VMOVAPDYrm:
1267    case X86::VMOVDQAYrm:
1268    case X86::MMX_MOVD64rm:
1269    case X86::MMX_MOVQ64rm:
1270    case X86::FsVMOVAPSrm:
1271    case X86::FsVMOVAPDrm:
1272    case X86::FsMOVAPSrm:
1273    case X86::FsMOVAPDrm: {
1274      // Loads from constant pools are trivially rematerializable.
1275      if (MI->getOperand(1).isReg() &&
1276          MI->getOperand(2).isImm() &&
1277          MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1278          MI->isInvariantLoad(AA)) {
1279        unsigned BaseReg = MI->getOperand(1).getReg();
1280        if (BaseReg == 0 || BaseReg == X86::RIP)
1281          return true;
1282        // Allow re-materialization of PIC load.
1283        if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1284          return false;
1285        const MachineFunction &MF = *MI->getParent()->getParent();
1286        const MachineRegisterInfo &MRI = MF.getRegInfo();
1287        bool isPICBase = false;
1288        for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1289               E = MRI.def_end(); I != E; ++I) {
1290          MachineInstr *DefMI = I.getOperand().getParent();
1291          if (DefMI->getOpcode() != X86::MOVPC32r)
1292            return false;
1293          assert(!isPICBase && "More than one PIC base?");
1294          isPICBase = true;
1295        }
1296        return isPICBase;
1297      }
1298      return false;
1299    }
1300
1301     case X86::LEA32r:
1302     case X86::LEA64r: {
1303       if (MI->getOperand(2).isImm() &&
1304           MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1305           !MI->getOperand(4).isReg()) {
1306         // lea fi#, lea GV, etc. are all rematerializable.
1307         if (!MI->getOperand(1).isReg())
1308           return true;
1309         unsigned BaseReg = MI->getOperand(1).getReg();
1310         if (BaseReg == 0)
1311           return true;
1312         // Allow re-materialization of lea PICBase + x.
1313         const MachineFunction &MF = *MI->getParent()->getParent();
1314         const MachineRegisterInfo &MRI = MF.getRegInfo();
1315         return regIsPICBase(BaseReg, MRI);
1316       }
1317       return false;
1318     }
1319  }
1320
1321  // All other instructions marked M_REMATERIALIZABLE are always trivially
1322  // rematerializable.
1323  return true;
1324}
1325
1326/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1327/// would clobber the EFLAGS condition register. Note the result may be
1328/// conservative. If it cannot definitely determine the safety after visiting
1329/// a few instructions in each direction it assumes it's not safe.
1330static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1331                                  MachineBasicBlock::iterator I) {
1332  MachineBasicBlock::iterator E = MBB.end();
1333
1334  // For compile time consideration, if we are not able to determine the
1335  // safety after visiting 4 instructions in each direction, we will assume
1336  // it's not safe.
1337  MachineBasicBlock::iterator Iter = I;
1338  for (unsigned i = 0; Iter != E && i < 4; ++i) {
1339    bool SeenDef = false;
1340    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1341      MachineOperand &MO = Iter->getOperand(j);
1342      if (!MO.isReg())
1343        continue;
1344      if (MO.getReg() == X86::EFLAGS) {
1345        if (MO.isUse())
1346          return false;
1347        SeenDef = true;
1348      }
1349    }
1350
1351    if (SeenDef)
1352      // This instruction defines EFLAGS, no need to look any further.
1353      return true;
1354    ++Iter;
1355    // Skip over DBG_VALUE.
1356    while (Iter != E && Iter->isDebugValue())
1357      ++Iter;
1358  }
1359
1360  // It is safe to clobber EFLAGS at the end of a block of no successor has it
1361  // live in.
1362  if (Iter == E) {
1363    for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1364           SE = MBB.succ_end(); SI != SE; ++SI)
1365      if ((*SI)->isLiveIn(X86::EFLAGS))
1366        return false;
1367    return true;
1368  }
1369
1370  MachineBasicBlock::iterator B = MBB.begin();
1371  Iter = I;
1372  for (unsigned i = 0; i < 4; ++i) {
1373    // If we make it to the beginning of the block, it's safe to clobber
1374    // EFLAGS iff EFLAGS is not live-in.
1375    if (Iter == B)
1376      return !MBB.isLiveIn(X86::EFLAGS);
1377
1378    --Iter;
1379    // Skip over DBG_VALUE.
1380    while (Iter != B && Iter->isDebugValue())
1381      --Iter;
1382
1383    bool SawKill = false;
1384    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1385      MachineOperand &MO = Iter->getOperand(j);
1386      if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1387        if (MO.isDef()) return MO.isDead();
1388        if (MO.isKill()) SawKill = true;
1389      }
1390    }
1391
1392    if (SawKill)
1393      // This instruction kills EFLAGS and doesn't redefine it, so
1394      // there's no need to look further.
1395      return true;
1396  }
1397
1398  // Conservative answer.
1399  return false;
1400}
1401
1402void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1403                                 MachineBasicBlock::iterator I,
1404                                 unsigned DestReg, unsigned SubIdx,
1405                                 const MachineInstr *Orig,
1406                                 const TargetRegisterInfo &TRI) const {
1407  DebugLoc DL = Orig->getDebugLoc();
1408
1409  // MOV32r0 etc. are implemented with xor which clobbers condition code.
1410  // Re-materialize them as movri instructions to avoid side effects.
1411  bool Clone = true;
1412  unsigned Opc = Orig->getOpcode();
1413  switch (Opc) {
1414  default: break;
1415  case X86::MOV8r0:
1416  case X86::MOV16r0:
1417  case X86::MOV32r0:
1418  case X86::MOV64r0: {
1419    if (!isSafeToClobberEFLAGS(MBB, I)) {
1420      switch (Opc) {
1421      default: break;
1422      case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
1423      case X86::MOV16r0: Opc = X86::MOV16ri; break;
1424      case X86::MOV32r0: Opc = X86::MOV32ri; break;
1425      case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1426      }
1427      Clone = false;
1428    }
1429    break;
1430  }
1431  }
1432
1433  if (Clone) {
1434    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1435    MBB.insert(I, MI);
1436  } else {
1437    BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1438  }
1439
1440  MachineInstr *NewMI = prior(I);
1441  NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1442}
1443
1444/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1445/// is not marked dead.
1446static bool hasLiveCondCodeDef(MachineInstr *MI) {
1447  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1448    MachineOperand &MO = MI->getOperand(i);
1449    if (MO.isReg() && MO.isDef() &&
1450        MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1451      return true;
1452    }
1453  }
1454  return false;
1455}
1456
1457/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1458/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1459/// to a 32-bit superregister and then truncating back down to a 16-bit
1460/// subregister.
1461MachineInstr *
1462X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1463                                           MachineFunction::iterator &MFI,
1464                                           MachineBasicBlock::iterator &MBBI,
1465                                           LiveVariables *LV) const {
1466  MachineInstr *MI = MBBI;
1467  unsigned Dest = MI->getOperand(0).getReg();
1468  unsigned Src = MI->getOperand(1).getReg();
1469  bool isDead = MI->getOperand(0).isDead();
1470  bool isKill = MI->getOperand(1).isKill();
1471
1472  unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1473    ? X86::LEA64_32r : X86::LEA32r;
1474  MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1475  unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1476  unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1477
1478  // Build and insert into an implicit UNDEF value. This is OK because
1479  // well be shifting and then extracting the lower 16-bits.
1480  // This has the potential to cause partial register stall. e.g.
1481  //   movw    (%rbp,%rcx,2), %dx
1482  //   leal    -65(%rdx), %esi
1483  // But testing has shown this *does* help performance in 64-bit mode (at
1484  // least on modern x86 machines).
1485  BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1486  MachineInstr *InsMI =
1487    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1488    .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1489    .addReg(Src, getKillRegState(isKill));
1490
1491  MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1492                                    get(Opc), leaOutReg);
1493  switch (MIOpc) {
1494  default:
1495    llvm_unreachable(0);
1496    break;
1497  case X86::SHL16ri: {
1498    unsigned ShAmt = MI->getOperand(2).getImm();
1499    MIB.addReg(0).addImm(1 << ShAmt)
1500       .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1501    break;
1502  }
1503  case X86::INC16r:
1504  case X86::INC64_16r:
1505    addRegOffset(MIB, leaInReg, true, 1);
1506    break;
1507  case X86::DEC16r:
1508  case X86::DEC64_16r:
1509    addRegOffset(MIB, leaInReg, true, -1);
1510    break;
1511  case X86::ADD16ri:
1512  case X86::ADD16ri8:
1513  case X86::ADD16ri_DB:
1514  case X86::ADD16ri8_DB:
1515    addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1516    break;
1517  case X86::ADD16rr:
1518  case X86::ADD16rr_DB: {
1519    unsigned Src2 = MI->getOperand(2).getReg();
1520    bool isKill2 = MI->getOperand(2).isKill();
1521    unsigned leaInReg2 = 0;
1522    MachineInstr *InsMI2 = 0;
1523    if (Src == Src2) {
1524      // ADD16rr %reg1028<kill>, %reg1028
1525      // just a single insert_subreg.
1526      addRegReg(MIB, leaInReg, true, leaInReg, false);
1527    } else {
1528      leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1529      // Build and insert into an implicit UNDEF value. This is OK because
1530      // well be shifting and then extracting the lower 16-bits.
1531      BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1532      InsMI2 =
1533        BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1534        .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1535        .addReg(Src2, getKillRegState(isKill2));
1536      addRegReg(MIB, leaInReg, true, leaInReg2, true);
1537    }
1538    if (LV && isKill2 && InsMI2)
1539      LV->replaceKillInstruction(Src2, MI, InsMI2);
1540    break;
1541  }
1542  }
1543
1544  MachineInstr *NewMI = MIB;
1545  MachineInstr *ExtMI =
1546    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1547    .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1548    .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1549
1550  if (LV) {
1551    // Update live variables
1552    LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1553    LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1554    if (isKill)
1555      LV->replaceKillInstruction(Src, MI, InsMI);
1556    if (isDead)
1557      LV->replaceKillInstruction(Dest, MI, ExtMI);
1558  }
1559
1560  return ExtMI;
1561}
1562
1563/// convertToThreeAddress - This method must be implemented by targets that
1564/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1565/// may be able to convert a two-address instruction into a true
1566/// three-address instruction on demand.  This allows the X86 target (for
1567/// example) to convert ADD and SHL instructions into LEA instructions if they
1568/// would require register copies due to two-addressness.
1569///
1570/// This method returns a null pointer if the transformation cannot be
1571/// performed, otherwise it returns the new instruction.
1572///
1573MachineInstr *
1574X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1575                                    MachineBasicBlock::iterator &MBBI,
1576                                    LiveVariables *LV) const {
1577  MachineInstr *MI = MBBI;
1578  MachineFunction &MF = *MI->getParent()->getParent();
1579  // All instructions input are two-addr instructions.  Get the known operands.
1580  unsigned Dest = MI->getOperand(0).getReg();
1581  unsigned Src = MI->getOperand(1).getReg();
1582  bool isDead = MI->getOperand(0).isDead();
1583  bool isKill = MI->getOperand(1).isKill();
1584
1585  MachineInstr *NewMI = NULL;
1586  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
1587  // we have better subtarget support, enable the 16-bit LEA generation here.
1588  // 16-bit LEA is also slow on Core2.
1589  bool DisableLEA16 = true;
1590  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1591
1592  unsigned MIOpc = MI->getOpcode();
1593  switch (MIOpc) {
1594  case X86::SHUFPSrri: {
1595    assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1596    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1597
1598    unsigned B = MI->getOperand(1).getReg();
1599    unsigned C = MI->getOperand(2).getReg();
1600    if (B != C) return 0;
1601    unsigned A = MI->getOperand(0).getReg();
1602    unsigned M = MI->getOperand(3).getImm();
1603    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1604      .addReg(A, RegState::Define | getDeadRegState(isDead))
1605      .addReg(B, getKillRegState(isKill)).addImm(M);
1606    break;
1607  }
1608  case X86::SHL64ri: {
1609    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1610    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1611    // the flags produced by a shift yet, so this is safe.
1612    unsigned ShAmt = MI->getOperand(2).getImm();
1613    if (ShAmt == 0 || ShAmt >= 4) return 0;
1614
1615    // LEA can't handle RSP.
1616    if (TargetRegisterInfo::isVirtualRegister(Src) &&
1617        !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1618      return 0;
1619
1620    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1621      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1622      .addReg(0).addImm(1 << ShAmt)
1623      .addReg(Src, getKillRegState(isKill))
1624      .addImm(0).addReg(0);
1625    break;
1626  }
1627  case X86::SHL32ri: {
1628    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1629    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1630    // the flags produced by a shift yet, so this is safe.
1631    unsigned ShAmt = MI->getOperand(2).getImm();
1632    if (ShAmt == 0 || ShAmt >= 4) return 0;
1633
1634    // LEA can't handle ESP.
1635    if (TargetRegisterInfo::isVirtualRegister(Src) &&
1636        !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1637      return 0;
1638
1639    unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1640    NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1641      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1642      .addReg(0).addImm(1 << ShAmt)
1643      .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1644    break;
1645  }
1646  case X86::SHL16ri: {
1647    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1648    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1649    // the flags produced by a shift yet, so this is safe.
1650    unsigned ShAmt = MI->getOperand(2).getImm();
1651    if (ShAmt == 0 || ShAmt >= 4) return 0;
1652
1653    if (DisableLEA16)
1654      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1655    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1656      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1657      .addReg(0).addImm(1 << ShAmt)
1658      .addReg(Src, getKillRegState(isKill))
1659      .addImm(0).addReg(0);
1660    break;
1661  }
1662  default: {
1663    // The following opcodes also sets the condition code register(s). Only
1664    // convert them to equivalent lea if the condition code register def's
1665    // are dead!
1666    if (hasLiveCondCodeDef(MI))
1667      return 0;
1668
1669    switch (MIOpc) {
1670    default: return 0;
1671    case X86::INC64r:
1672    case X86::INC32r:
1673    case X86::INC64_32r: {
1674      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1675      unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1676        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1677
1678      // LEA can't handle RSP.
1679      if (TargetRegisterInfo::isVirtualRegister(Src) &&
1680          !MF.getRegInfo().constrainRegClass(Src,
1681                            MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass :
1682                                                   X86::GR32_NOSPRegisterClass))
1683        return 0;
1684
1685      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1686                              .addReg(Dest, RegState::Define |
1687                                      getDeadRegState(isDead)),
1688                              Src, isKill, 1);
1689      break;
1690    }
1691    case X86::INC16r:
1692    case X86::INC64_16r:
1693      if (DisableLEA16)
1694        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1695      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1696      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1697                           .addReg(Dest, RegState::Define |
1698                                   getDeadRegState(isDead)),
1699                           Src, isKill, 1);
1700      break;
1701    case X86::DEC64r:
1702    case X86::DEC32r:
1703    case X86::DEC64_32r: {
1704      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1705      unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1706        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1707      // LEA can't handle RSP.
1708      if (TargetRegisterInfo::isVirtualRegister(Src) &&
1709          !MF.getRegInfo().constrainRegClass(Src,
1710                            MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass :
1711                                                   X86::GR32_NOSPRegisterClass))
1712        return 0;
1713
1714      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1715                              .addReg(Dest, RegState::Define |
1716                                      getDeadRegState(isDead)),
1717                              Src, isKill, -1);
1718      break;
1719    }
1720    case X86::DEC16r:
1721    case X86::DEC64_16r:
1722      if (DisableLEA16)
1723        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1724      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1725      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1726                           .addReg(Dest, RegState::Define |
1727                                   getDeadRegState(isDead)),
1728                           Src, isKill, -1);
1729      break;
1730    case X86::ADD64rr:
1731    case X86::ADD64rr_DB:
1732    case X86::ADD32rr:
1733    case X86::ADD32rr_DB: {
1734      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1735      unsigned Opc;
1736      TargetRegisterClass *RC;
1737      if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1738        Opc = X86::LEA64r;
1739        RC = X86::GR64_NOSPRegisterClass;
1740      } else {
1741        Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1742        RC = X86::GR32_NOSPRegisterClass;
1743      }
1744
1745
1746      unsigned Src2 = MI->getOperand(2).getReg();
1747      bool isKill2 = MI->getOperand(2).isKill();
1748
1749      // LEA can't handle RSP.
1750      if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1751          !MF.getRegInfo().constrainRegClass(Src2, RC))
1752        return 0;
1753
1754      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1755                        .addReg(Dest, RegState::Define |
1756                                getDeadRegState(isDead)),
1757                        Src, isKill, Src2, isKill2);
1758      if (LV && isKill2)
1759        LV->replaceKillInstruction(Src2, MI, NewMI);
1760      break;
1761    }
1762    case X86::ADD16rr:
1763    case X86::ADD16rr_DB: {
1764      if (DisableLEA16)
1765        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1766      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1767      unsigned Src2 = MI->getOperand(2).getReg();
1768      bool isKill2 = MI->getOperand(2).isKill();
1769      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1770                        .addReg(Dest, RegState::Define |
1771                                getDeadRegState(isDead)),
1772                        Src, isKill, Src2, isKill2);
1773      if (LV && isKill2)
1774        LV->replaceKillInstruction(Src2, MI, NewMI);
1775      break;
1776    }
1777    case X86::ADD64ri32:
1778    case X86::ADD64ri8:
1779    case X86::ADD64ri32_DB:
1780    case X86::ADD64ri8_DB:
1781      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1782      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1783                              .addReg(Dest, RegState::Define |
1784                                      getDeadRegState(isDead)),
1785                              Src, isKill, MI->getOperand(2).getImm());
1786      break;
1787    case X86::ADD32ri:
1788    case X86::ADD32ri8:
1789    case X86::ADD32ri_DB:
1790    case X86::ADD32ri8_DB: {
1791      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1792      unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1793      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1794                              .addReg(Dest, RegState::Define |
1795                                      getDeadRegState(isDead)),
1796                                Src, isKill, MI->getOperand(2).getImm());
1797      break;
1798    }
1799    case X86::ADD16ri:
1800    case X86::ADD16ri8:
1801    case X86::ADD16ri_DB:
1802    case X86::ADD16ri8_DB:
1803      if (DisableLEA16)
1804        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1805      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1806      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1807                              .addReg(Dest, RegState::Define |
1808                                      getDeadRegState(isDead)),
1809                              Src, isKill, MI->getOperand(2).getImm());
1810      break;
1811    }
1812  }
1813  }
1814
1815  if (!NewMI) return 0;
1816
1817  if (LV) {  // Update live variables
1818    if (isKill)
1819      LV->replaceKillInstruction(Src, MI, NewMI);
1820    if (isDead)
1821      LV->replaceKillInstruction(Dest, MI, NewMI);
1822  }
1823
1824  MFI->insert(MBBI, NewMI);          // Insert the new inst
1825  return NewMI;
1826}
1827
1828/// commuteInstruction - We have a few instructions that must be hacked on to
1829/// commute them.
1830///
1831MachineInstr *
1832X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1833  switch (MI->getOpcode()) {
1834  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1835  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1836  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1837  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1838  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1839  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1840    unsigned Opc;
1841    unsigned Size;
1842    switch (MI->getOpcode()) {
1843    default: llvm_unreachable("Unreachable!");
1844    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1845    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1846    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1847    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1848    case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1849    case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1850    }
1851    unsigned Amt = MI->getOperand(3).getImm();
1852    if (NewMI) {
1853      MachineFunction &MF = *MI->getParent()->getParent();
1854      MI = MF.CloneMachineInstr(MI);
1855      NewMI = false;
1856    }
1857    MI->setDesc(get(Opc));
1858    MI->getOperand(3).setImm(Size-Amt);
1859    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1860  }
1861  case X86::CMOVB16rr:
1862  case X86::CMOVB32rr:
1863  case X86::CMOVB64rr:
1864  case X86::CMOVAE16rr:
1865  case X86::CMOVAE32rr:
1866  case X86::CMOVAE64rr:
1867  case X86::CMOVE16rr:
1868  case X86::CMOVE32rr:
1869  case X86::CMOVE64rr:
1870  case X86::CMOVNE16rr:
1871  case X86::CMOVNE32rr:
1872  case X86::CMOVNE64rr:
1873  case X86::CMOVBE16rr:
1874  case X86::CMOVBE32rr:
1875  case X86::CMOVBE64rr:
1876  case X86::CMOVA16rr:
1877  case X86::CMOVA32rr:
1878  case X86::CMOVA64rr:
1879  case X86::CMOVL16rr:
1880  case X86::CMOVL32rr:
1881  case X86::CMOVL64rr:
1882  case X86::CMOVGE16rr:
1883  case X86::CMOVGE32rr:
1884  case X86::CMOVGE64rr:
1885  case X86::CMOVLE16rr:
1886  case X86::CMOVLE32rr:
1887  case X86::CMOVLE64rr:
1888  case X86::CMOVG16rr:
1889  case X86::CMOVG32rr:
1890  case X86::CMOVG64rr:
1891  case X86::CMOVS16rr:
1892  case X86::CMOVS32rr:
1893  case X86::CMOVS64rr:
1894  case X86::CMOVNS16rr:
1895  case X86::CMOVNS32rr:
1896  case X86::CMOVNS64rr:
1897  case X86::CMOVP16rr:
1898  case X86::CMOVP32rr:
1899  case X86::CMOVP64rr:
1900  case X86::CMOVNP16rr:
1901  case X86::CMOVNP32rr:
1902  case X86::CMOVNP64rr:
1903  case X86::CMOVO16rr:
1904  case X86::CMOVO32rr:
1905  case X86::CMOVO64rr:
1906  case X86::CMOVNO16rr:
1907  case X86::CMOVNO32rr:
1908  case X86::CMOVNO64rr: {
1909    unsigned Opc = 0;
1910    switch (MI->getOpcode()) {
1911    default: break;
1912    case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
1913    case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
1914    case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
1915    case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1916    case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1917    case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1918    case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
1919    case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
1920    case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
1921    case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1922    case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1923    case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1924    case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1925    case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1926    case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1927    case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
1928    case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
1929    case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
1930    case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
1931    case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
1932    case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
1933    case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1934    case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1935    case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1936    case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1937    case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1938    case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1939    case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
1940    case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
1941    case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
1942    case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
1943    case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
1944    case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
1945    case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1946    case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1947    case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1948    case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
1949    case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
1950    case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
1951    case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1952    case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1953    case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1954    case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
1955    case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
1956    case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
1957    case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1958    case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1959    case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1960    }
1961    if (NewMI) {
1962      MachineFunction &MF = *MI->getParent()->getParent();
1963      MI = MF.CloneMachineInstr(MI);
1964      NewMI = false;
1965    }
1966    MI->setDesc(get(Opc));
1967    // Fallthrough intended.
1968  }
1969  default:
1970    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1971  }
1972}
1973
1974static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1975  switch (BrOpc) {
1976  default: return X86::COND_INVALID;
1977  case X86::JE_4:  return X86::COND_E;
1978  case X86::JNE_4: return X86::COND_NE;
1979  case X86::JL_4:  return X86::COND_L;
1980  case X86::JLE_4: return X86::COND_LE;
1981  case X86::JG_4:  return X86::COND_G;
1982  case X86::JGE_4: return X86::COND_GE;
1983  case X86::JB_4:  return X86::COND_B;
1984  case X86::JBE_4: return X86::COND_BE;
1985  case X86::JA_4:  return X86::COND_A;
1986  case X86::JAE_4: return X86::COND_AE;
1987  case X86::JS_4:  return X86::COND_S;
1988  case X86::JNS_4: return X86::COND_NS;
1989  case X86::JP_4:  return X86::COND_P;
1990  case X86::JNP_4: return X86::COND_NP;
1991  case X86::JO_4:  return X86::COND_O;
1992  case X86::JNO_4: return X86::COND_NO;
1993  }
1994}
1995
1996unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1997  switch (CC) {
1998  default: llvm_unreachable("Illegal condition code!");
1999  case X86::COND_E:  return X86::JE_4;
2000  case X86::COND_NE: return X86::JNE_4;
2001  case X86::COND_L:  return X86::JL_4;
2002  case X86::COND_LE: return X86::JLE_4;
2003  case X86::COND_G:  return X86::JG_4;
2004  case X86::COND_GE: return X86::JGE_4;
2005  case X86::COND_B:  return X86::JB_4;
2006  case X86::COND_BE: return X86::JBE_4;
2007  case X86::COND_A:  return X86::JA_4;
2008  case X86::COND_AE: return X86::JAE_4;
2009  case X86::COND_S:  return X86::JS_4;
2010  case X86::COND_NS: return X86::JNS_4;
2011  case X86::COND_P:  return X86::JP_4;
2012  case X86::COND_NP: return X86::JNP_4;
2013  case X86::COND_O:  return X86::JO_4;
2014  case X86::COND_NO: return X86::JNO_4;
2015  }
2016}
2017
2018/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2019/// e.g. turning COND_E to COND_NE.
2020X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2021  switch (CC) {
2022  default: llvm_unreachable("Illegal condition code!");
2023  case X86::COND_E:  return X86::COND_NE;
2024  case X86::COND_NE: return X86::COND_E;
2025  case X86::COND_L:  return X86::COND_GE;
2026  case X86::COND_LE: return X86::COND_G;
2027  case X86::COND_G:  return X86::COND_LE;
2028  case X86::COND_GE: return X86::COND_L;
2029  case X86::COND_B:  return X86::COND_AE;
2030  case X86::COND_BE: return X86::COND_A;
2031  case X86::COND_A:  return X86::COND_BE;
2032  case X86::COND_AE: return X86::COND_B;
2033  case X86::COND_S:  return X86::COND_NS;
2034  case X86::COND_NS: return X86::COND_S;
2035  case X86::COND_P:  return X86::COND_NP;
2036  case X86::COND_NP: return X86::COND_P;
2037  case X86::COND_O:  return X86::COND_NO;
2038  case X86::COND_NO: return X86::COND_O;
2039  }
2040}
2041
2042bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2043  const MCInstrDesc &MCID = MI->getDesc();
2044  if (!MCID.isTerminator()) return false;
2045
2046  // Conditional branch is a special case.
2047  if (MCID.isBranch() && !MCID.isBarrier())
2048    return true;
2049  if (!MCID.isPredicable())
2050    return true;
2051  return !isPredicated(MI);
2052}
2053
2054bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2055                                 MachineBasicBlock *&TBB,
2056                                 MachineBasicBlock *&FBB,
2057                                 SmallVectorImpl<MachineOperand> &Cond,
2058                                 bool AllowModify) const {
2059  // Start from the bottom of the block and work up, examining the
2060  // terminator instructions.
2061  MachineBasicBlock::iterator I = MBB.end();
2062  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2063  while (I != MBB.begin()) {
2064    --I;
2065    if (I->isDebugValue())
2066      continue;
2067
2068    // Working from the bottom, when we see a non-terminator instruction, we're
2069    // done.
2070    if (!isUnpredicatedTerminator(I))
2071      break;
2072
2073    // A terminator that isn't a branch can't easily be handled by this
2074    // analysis.
2075    if (!I->getDesc().isBranch())
2076      return true;
2077
2078    // Handle unconditional branches.
2079    if (I->getOpcode() == X86::JMP_4) {
2080      UnCondBrIter = I;
2081
2082      if (!AllowModify) {
2083        TBB = I->getOperand(0).getMBB();
2084        continue;
2085      }
2086
2087      // If the block has any instructions after a JMP, delete them.
2088      while (llvm::next(I) != MBB.end())
2089        llvm::next(I)->eraseFromParent();
2090
2091      Cond.clear();
2092      FBB = 0;
2093
2094      // Delete the JMP if it's equivalent to a fall-through.
2095      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2096        TBB = 0;
2097        I->eraseFromParent();
2098        I = MBB.end();
2099        UnCondBrIter = MBB.end();
2100        continue;
2101      }
2102
2103      // TBB is used to indicate the unconditional destination.
2104      TBB = I->getOperand(0).getMBB();
2105      continue;
2106    }
2107
2108    // Handle conditional branches.
2109    X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
2110    if (BranchCode == X86::COND_INVALID)
2111      return true;  // Can't handle indirect branch.
2112
2113    // Working from the bottom, handle the first conditional branch.
2114    if (Cond.empty()) {
2115      MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2116      if (AllowModify && UnCondBrIter != MBB.end() &&
2117          MBB.isLayoutSuccessor(TargetBB)) {
2118        // If we can modify the code and it ends in something like:
2119        //
2120        //     jCC L1
2121        //     jmp L2
2122        //   L1:
2123        //     ...
2124        //   L2:
2125        //
2126        // Then we can change this to:
2127        //
2128        //     jnCC L2
2129        //   L1:
2130        //     ...
2131        //   L2:
2132        //
2133        // Which is a bit more efficient.
2134        // We conditionally jump to the fall-through block.
2135        BranchCode = GetOppositeBranchCondition(BranchCode);
2136        unsigned JNCC = GetCondBranchFromCond(BranchCode);
2137        MachineBasicBlock::iterator OldInst = I;
2138
2139        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2140          .addMBB(UnCondBrIter->getOperand(0).getMBB());
2141        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2142          .addMBB(TargetBB);
2143
2144        OldInst->eraseFromParent();
2145        UnCondBrIter->eraseFromParent();
2146
2147        // Restart the analysis.
2148        UnCondBrIter = MBB.end();
2149        I = MBB.end();
2150        continue;
2151      }
2152
2153      FBB = TBB;
2154      TBB = I->getOperand(0).getMBB();
2155      Cond.push_back(MachineOperand::CreateImm(BranchCode));
2156      continue;
2157    }
2158
2159    // Handle subsequent conditional branches. Only handle the case where all
2160    // conditional branches branch to the same destination and their condition
2161    // opcodes fit one of the special multi-branch idioms.
2162    assert(Cond.size() == 1);
2163    assert(TBB);
2164
2165    // Only handle the case where all conditional branches branch to the same
2166    // destination.
2167    if (TBB != I->getOperand(0).getMBB())
2168      return true;
2169
2170    // If the conditions are the same, we can leave them alone.
2171    X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2172    if (OldBranchCode == BranchCode)
2173      continue;
2174
2175    // If they differ, see if they fit one of the known patterns. Theoretically,
2176    // we could handle more patterns here, but we shouldn't expect to see them
2177    // if instruction selection has done a reasonable job.
2178    if ((OldBranchCode == X86::COND_NP &&
2179         BranchCode == X86::COND_E) ||
2180        (OldBranchCode == X86::COND_E &&
2181         BranchCode == X86::COND_NP))
2182      BranchCode = X86::COND_NP_OR_E;
2183    else if ((OldBranchCode == X86::COND_P &&
2184              BranchCode == X86::COND_NE) ||
2185             (OldBranchCode == X86::COND_NE &&
2186              BranchCode == X86::COND_P))
2187      BranchCode = X86::COND_NE_OR_P;
2188    else
2189      return true;
2190
2191    // Update the MachineOperand.
2192    Cond[0].setImm(BranchCode);
2193  }
2194
2195  return false;
2196}
2197
2198unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2199  MachineBasicBlock::iterator I = MBB.end();
2200  unsigned Count = 0;
2201
2202  while (I != MBB.begin()) {
2203    --I;
2204    if (I->isDebugValue())
2205      continue;
2206    if (I->getOpcode() != X86::JMP_4 &&
2207        GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2208      break;
2209    // Remove the branch.
2210    I->eraseFromParent();
2211    I = MBB.end();
2212    ++Count;
2213  }
2214
2215  return Count;
2216}
2217
2218unsigned
2219X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2220                           MachineBasicBlock *FBB,
2221                           const SmallVectorImpl<MachineOperand> &Cond,
2222                           DebugLoc DL) const {
2223  // Shouldn't be a fall through.
2224  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2225  assert((Cond.size() == 1 || Cond.size() == 0) &&
2226         "X86 branch conditions have one component!");
2227
2228  if (Cond.empty()) {
2229    // Unconditional branch?
2230    assert(!FBB && "Unconditional branch with multiple successors!");
2231    BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2232    return 1;
2233  }
2234
2235  // Conditional branch.
2236  unsigned Count = 0;
2237  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2238  switch (CC) {
2239  case X86::COND_NP_OR_E:
2240    // Synthesize NP_OR_E with two branches.
2241    BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2242    ++Count;
2243    BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2244    ++Count;
2245    break;
2246  case X86::COND_NE_OR_P:
2247    // Synthesize NE_OR_P with two branches.
2248    BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2249    ++Count;
2250    BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2251    ++Count;
2252    break;
2253  default: {
2254    unsigned Opc = GetCondBranchFromCond(CC);
2255    BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2256    ++Count;
2257  }
2258  }
2259  if (FBB) {
2260    // Two-way Conditional branch. Insert the second branch.
2261    BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2262    ++Count;
2263  }
2264  return Count;
2265}
2266
2267/// isHReg - Test if the given register is a physical h register.
2268static bool isHReg(unsigned Reg) {
2269  return X86::GR8_ABCD_HRegClass.contains(Reg);
2270}
2271
2272// Try and copy between VR128/VR64 and GR64 registers.
2273static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2274                                        bool HasAVX) {
2275  // SrcReg(VR128) -> DestReg(GR64)
2276  // SrcReg(VR64)  -> DestReg(GR64)
2277  // SrcReg(GR64)  -> DestReg(VR128)
2278  // SrcReg(GR64)  -> DestReg(VR64)
2279
2280  if (X86::GR64RegClass.contains(DestReg)) {
2281    if (X86::VR128RegClass.contains(SrcReg)) {
2282      // Copy from a VR128 register to a GR64 register.
2283      return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2284    } else if (X86::VR64RegClass.contains(SrcReg)) {
2285      // Copy from a VR64 register to a GR64 register.
2286      return X86::MOVSDto64rr;
2287    }
2288  } else if (X86::GR64RegClass.contains(SrcReg)) {
2289    // Copy from a GR64 register to a VR128 register.
2290    if (X86::VR128RegClass.contains(DestReg))
2291      return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2292    // Copy from a GR64 register to a VR64 register.
2293    else if (X86::VR64RegClass.contains(DestReg))
2294      return X86::MOV64toSDrr;
2295  }
2296
2297  // SrcReg(FR32) -> DestReg(GR32)
2298  // SrcReg(GR32) -> DestReg(FR32)
2299
2300  if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2301      // Copy from a FR32 register to a GR32 register.
2302      return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2303
2304  if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2305      // Copy from a GR32 register to a FR32 register.
2306      return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2307
2308  return 0;
2309}
2310
2311void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2312                               MachineBasicBlock::iterator MI, DebugLoc DL,
2313                               unsigned DestReg, unsigned SrcReg,
2314                               bool KillSrc) const {
2315  // First deal with the normal symmetric copies.
2316  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2317  unsigned Opc = 0;
2318  if (X86::GR64RegClass.contains(DestReg, SrcReg))
2319    Opc = X86::MOV64rr;
2320  else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2321    Opc = X86::MOV32rr;
2322  else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2323    Opc = X86::MOV16rr;
2324  else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2325    // Copying to or from a physical H register on x86-64 requires a NOREX
2326    // move.  Otherwise use a normal move.
2327    if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2328        TM.getSubtarget<X86Subtarget>().is64Bit()) {
2329      Opc = X86::MOV8rr_NOREX;
2330      // Both operands must be encodable without an REX prefix.
2331      assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2332             "8-bit H register can not be copied outside GR8_NOREX");
2333    } else
2334      Opc = X86::MOV8rr;
2335  } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2336    Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2337  else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2338    Opc = X86::VMOVAPSYrr;
2339  else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2340    Opc = X86::MMX_MOVQ64rr;
2341  else
2342    Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2343
2344  if (Opc) {
2345    BuildMI(MBB, MI, DL, get(Opc), DestReg)
2346      .addReg(SrcReg, getKillRegState(KillSrc));
2347    return;
2348  }
2349
2350  // Moving EFLAGS to / from another register requires a push and a pop.
2351  if (SrcReg == X86::EFLAGS) {
2352    if (X86::GR64RegClass.contains(DestReg)) {
2353      BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2354      BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2355      return;
2356    } else if (X86::GR32RegClass.contains(DestReg)) {
2357      BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2358      BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2359      return;
2360    }
2361  }
2362  if (DestReg == X86::EFLAGS) {
2363    if (X86::GR64RegClass.contains(SrcReg)) {
2364      BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2365        .addReg(SrcReg, getKillRegState(KillSrc));
2366      BuildMI(MBB, MI, DL, get(X86::POPF64));
2367      return;
2368    } else if (X86::GR32RegClass.contains(SrcReg)) {
2369      BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2370        .addReg(SrcReg, getKillRegState(KillSrc));
2371      BuildMI(MBB, MI, DL, get(X86::POPF32));
2372      return;
2373    }
2374  }
2375
2376  DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2377               << " to " << RI.getName(DestReg) << '\n');
2378  llvm_unreachable("Cannot emit physreg copy instruction");
2379}
2380
2381static unsigned getLoadStoreRegOpcode(unsigned Reg,
2382                                      const TargetRegisterClass *RC,
2383                                      bool isStackAligned,
2384                                      const TargetMachine &TM,
2385                                      bool load) {
2386  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2387  switch (RC->getSize()) {
2388  default:
2389    llvm_unreachable("Unknown spill size");
2390  case 1:
2391    assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2392    if (TM.getSubtarget<X86Subtarget>().is64Bit())
2393      // Copying to or from a physical H register on x86-64 requires a NOREX
2394      // move.  Otherwise use a normal move.
2395      if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2396        return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2397    return load ? X86::MOV8rm : X86::MOV8mr;
2398  case 2:
2399    assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2400    return load ? X86::MOV16rm : X86::MOV16mr;
2401  case 4:
2402    if (X86::GR32RegClass.hasSubClassEq(RC))
2403      return load ? X86::MOV32rm : X86::MOV32mr;
2404    if (X86::FR32RegClass.hasSubClassEq(RC))
2405      return load ?
2406        (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2407        (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2408    if (X86::RFP32RegClass.hasSubClassEq(RC))
2409      return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2410    llvm_unreachable("Unknown 4-byte regclass");
2411  case 8:
2412    if (X86::GR64RegClass.hasSubClassEq(RC))
2413      return load ? X86::MOV64rm : X86::MOV64mr;
2414    if (X86::FR64RegClass.hasSubClassEq(RC))
2415      return load ?
2416        (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2417        (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2418    if (X86::VR64RegClass.hasSubClassEq(RC))
2419      return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2420    if (X86::RFP64RegClass.hasSubClassEq(RC))
2421      return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2422    llvm_unreachable("Unknown 8-byte regclass");
2423  case 10:
2424    assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2425    return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2426  case 16: {
2427    assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2428    // If stack is realigned we can use aligned stores.
2429    if (isStackAligned)
2430      return load ?
2431        (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2432        (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2433    else
2434      return load ?
2435        (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2436        (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2437  }
2438  case 32:
2439    assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2440    // If stack is realigned we can use aligned stores.
2441    if (isStackAligned)
2442      return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2443    else
2444      return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2445  }
2446}
2447
2448static unsigned getStoreRegOpcode(unsigned SrcReg,
2449                                  const TargetRegisterClass *RC,
2450                                  bool isStackAligned,
2451                                  TargetMachine &TM) {
2452  return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2453}
2454
2455
2456static unsigned getLoadRegOpcode(unsigned DestReg,
2457                                 const TargetRegisterClass *RC,
2458                                 bool isStackAligned,
2459                                 const TargetMachine &TM) {
2460  return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2461}
2462
2463void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2464                                       MachineBasicBlock::iterator MI,
2465                                       unsigned SrcReg, bool isKill, int FrameIdx,
2466                                       const TargetRegisterClass *RC,
2467                                       const TargetRegisterInfo *TRI) const {
2468  const MachineFunction &MF = *MBB.getParent();
2469  assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2470         "Stack slot too small for store");
2471  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2472  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2473    RI.canRealignStack(MF);
2474  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2475  DebugLoc DL = MBB.findDebugLoc(MI);
2476  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2477    .addReg(SrcReg, getKillRegState(isKill));
2478}
2479
2480void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2481                                  bool isKill,
2482                                  SmallVectorImpl<MachineOperand> &Addr,
2483                                  const TargetRegisterClass *RC,
2484                                  MachineInstr::mmo_iterator MMOBegin,
2485                                  MachineInstr::mmo_iterator MMOEnd,
2486                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
2487  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2488  bool isAligned = MMOBegin != MMOEnd &&
2489                   (*MMOBegin)->getAlignment() >= Alignment;
2490  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2491  DebugLoc DL;
2492  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2493  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2494    MIB.addOperand(Addr[i]);
2495  MIB.addReg(SrcReg, getKillRegState(isKill));
2496  (*MIB).setMemRefs(MMOBegin, MMOEnd);
2497  NewMIs.push_back(MIB);
2498}
2499
2500
2501void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2502                                        MachineBasicBlock::iterator MI,
2503                                        unsigned DestReg, int FrameIdx,
2504                                        const TargetRegisterClass *RC,
2505                                        const TargetRegisterInfo *TRI) const {
2506  const MachineFunction &MF = *MBB.getParent();
2507  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2508  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2509    RI.canRealignStack(MF);
2510  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2511  DebugLoc DL = MBB.findDebugLoc(MI);
2512  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2513}
2514
2515void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2516                                 SmallVectorImpl<MachineOperand> &Addr,
2517                                 const TargetRegisterClass *RC,
2518                                 MachineInstr::mmo_iterator MMOBegin,
2519                                 MachineInstr::mmo_iterator MMOEnd,
2520                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2521  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2522  bool isAligned = MMOBegin != MMOEnd &&
2523                   (*MMOBegin)->getAlignment() >= Alignment;
2524  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2525  DebugLoc DL;
2526  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2527  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2528    MIB.addOperand(Addr[i]);
2529  (*MIB).setMemRefs(MMOBegin, MMOEnd);
2530  NewMIs.push_back(MIB);
2531}
2532
2533/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
2534/// instruction with two undef reads of the register being defined.  This is
2535/// used for mapping:
2536///   %xmm4 = V_SET0
2537/// to:
2538///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
2539///
2540static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
2541  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
2542  unsigned Reg = MI->getOperand(0).getReg();
2543  MI->setDesc(Desc);
2544
2545  // MachineInstr::addOperand() will insert explicit operands before any
2546  // implicit operands.
2547  MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
2548                         .addReg(Reg, RegState::Undef);
2549  // But we don't trust that.
2550  assert(MI->getOperand(1).getReg() == Reg &&
2551         MI->getOperand(2).getReg() == Reg && "Misplaced operand");
2552  return true;
2553}
2554
2555bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
2556  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2557  switch (MI->getOpcode()) {
2558  case X86::V_SET0:
2559  case X86::FsFLD0SS:
2560  case X86::FsFLD0SD:
2561    return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
2562  case X86::TEST8ri_NOREX:
2563    MI->setDesc(get(X86::TEST8ri));
2564    return true;
2565  }
2566  return false;
2567}
2568
2569MachineInstr*
2570X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2571                                       int FrameIx, uint64_t Offset,
2572                                       const MDNode *MDPtr,
2573                                       DebugLoc DL) const {
2574  X86AddressMode AM;
2575  AM.BaseType = X86AddressMode::FrameIndexBase;
2576  AM.Base.FrameIndex = FrameIx;
2577  MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2578  addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2579  return &*MIB;
2580}
2581
2582static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2583                                     const SmallVectorImpl<MachineOperand> &MOs,
2584                                     MachineInstr *MI,
2585                                     const TargetInstrInfo &TII) {
2586  // Create the base instruction with the memory operand as the first part.
2587  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2588                                              MI->getDebugLoc(), true);
2589  MachineInstrBuilder MIB(NewMI);
2590  unsigned NumAddrOps = MOs.size();
2591  for (unsigned i = 0; i != NumAddrOps; ++i)
2592    MIB.addOperand(MOs[i]);
2593  if (NumAddrOps < 4)  // FrameIndex only
2594    addOffset(MIB, 0);
2595
2596  // Loop over the rest of the ri operands, converting them over.
2597  unsigned NumOps = MI->getDesc().getNumOperands()-2;
2598  for (unsigned i = 0; i != NumOps; ++i) {
2599    MachineOperand &MO = MI->getOperand(i+2);
2600    MIB.addOperand(MO);
2601  }
2602  for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2603    MachineOperand &MO = MI->getOperand(i);
2604    MIB.addOperand(MO);
2605  }
2606  return MIB;
2607}
2608
2609static MachineInstr *FuseInst(MachineFunction &MF,
2610                              unsigned Opcode, unsigned OpNo,
2611                              const SmallVectorImpl<MachineOperand> &MOs,
2612                              MachineInstr *MI, const TargetInstrInfo &TII) {
2613  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2614                                              MI->getDebugLoc(), true);
2615  MachineInstrBuilder MIB(NewMI);
2616
2617  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2618    MachineOperand &MO = MI->getOperand(i);
2619    if (i == OpNo) {
2620      assert(MO.isReg() && "Expected to fold into reg operand!");
2621      unsigned NumAddrOps = MOs.size();
2622      for (unsigned i = 0; i != NumAddrOps; ++i)
2623        MIB.addOperand(MOs[i]);
2624      if (NumAddrOps < 4)  // FrameIndex only
2625        addOffset(MIB, 0);
2626    } else {
2627      MIB.addOperand(MO);
2628    }
2629  }
2630  return MIB;
2631}
2632
2633static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2634                                const SmallVectorImpl<MachineOperand> &MOs,
2635                                MachineInstr *MI) {
2636  MachineFunction &MF = *MI->getParent()->getParent();
2637  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2638
2639  unsigned NumAddrOps = MOs.size();
2640  for (unsigned i = 0; i != NumAddrOps; ++i)
2641    MIB.addOperand(MOs[i]);
2642  if (NumAddrOps < 4)  // FrameIndex only
2643    addOffset(MIB, 0);
2644  return MIB.addImm(0);
2645}
2646
2647MachineInstr*
2648X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2649                                    MachineInstr *MI, unsigned i,
2650                                    const SmallVectorImpl<MachineOperand> &MOs,
2651                                    unsigned Size, unsigned Align) const {
2652  const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2653  bool isTwoAddrFold = false;
2654  unsigned NumOps = MI->getDesc().getNumOperands();
2655  bool isTwoAddr = NumOps > 1 &&
2656    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2657
2658  // FIXME: AsmPrinter doesn't know how to handle
2659  // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2660  if (MI->getOpcode() == X86::ADD32ri &&
2661      MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2662    return NULL;
2663
2664  MachineInstr *NewMI = NULL;
2665  // Folding a memory location into the two-address part of a two-address
2666  // instruction is different than folding it other places.  It requires
2667  // replacing the *two* registers with the memory location.
2668  if (isTwoAddr && NumOps >= 2 && i < 2 &&
2669      MI->getOperand(0).isReg() &&
2670      MI->getOperand(1).isReg() &&
2671      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2672    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2673    isTwoAddrFold = true;
2674  } else if (i == 0) { // If operand 0
2675    if (MI->getOpcode() == X86::MOV64r0)
2676      NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2677    else if (MI->getOpcode() == X86::MOV32r0)
2678      NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2679    else if (MI->getOpcode() == X86::MOV16r0)
2680      NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2681    else if (MI->getOpcode() == X86::MOV8r0)
2682      NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2683    if (NewMI)
2684      return NewMI;
2685
2686    OpcodeTablePtr = &RegOp2MemOpTable0;
2687  } else if (i == 1) {
2688    OpcodeTablePtr = &RegOp2MemOpTable1;
2689  } else if (i == 2) {
2690    OpcodeTablePtr = &RegOp2MemOpTable2;
2691  }
2692
2693  // If table selected...
2694  if (OpcodeTablePtr) {
2695    // Find the Opcode to fuse
2696    DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2697      OpcodeTablePtr->find(MI->getOpcode());
2698    if (I != OpcodeTablePtr->end()) {
2699      unsigned Opcode = I->second.first;
2700      unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
2701      if (Align < MinAlign)
2702        return NULL;
2703      bool NarrowToMOV32rm = false;
2704      if (Size) {
2705        unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
2706        if (Size < RCSize) {
2707          // Check if it's safe to fold the load. If the size of the object is
2708          // narrower than the load width, then it's not.
2709          if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2710            return NULL;
2711          // If this is a 64-bit load, but the spill slot is 32, then we can do
2712          // a 32-bit load which is implicitly zero-extended. This likely is due
2713          // to liveintervalanalysis remat'ing a load from stack slot.
2714          if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2715            return NULL;
2716          Opcode = X86::MOV32rm;
2717          NarrowToMOV32rm = true;
2718        }
2719      }
2720
2721      if (isTwoAddrFold)
2722        NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2723      else
2724        NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2725
2726      if (NarrowToMOV32rm) {
2727        // If this is the special case where we use a MOV32rm to load a 32-bit
2728        // value and zero-extend the top bits. Change the destination register
2729        // to a 32-bit one.
2730        unsigned DstReg = NewMI->getOperand(0).getReg();
2731        if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2732          NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2733                                                   X86::sub_32bit));
2734        else
2735          NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2736      }
2737      return NewMI;
2738    }
2739  }
2740
2741  // No fusion
2742  if (PrintFailedFusing && !MI->isCopy())
2743    dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2744  return NULL;
2745}
2746
2747/// hasPartialRegUpdate - Return true for all instructions that only update
2748/// the first 32 or 64-bits of the destination register and leave the rest
2749/// unmodified. This can be used to avoid folding loads if the instructions
2750/// only update part of the destination register, and the non-updated part is
2751/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
2752/// instructions breaks the partial register dependency and it can improve
2753/// performance. e.g.:
2754///
2755///   movss (%rdi), %xmm0
2756///   cvtss2sd %xmm0, %xmm0
2757///
2758/// Instead of
2759///   cvtss2sd (%rdi), %xmm0
2760///
2761/// FIXME: This should be turned into a TSFlags.
2762///
2763static bool hasPartialRegUpdate(unsigned Opcode) {
2764  switch (Opcode) {
2765  case X86::CVTSI2SSrr:
2766  case X86::CVTSI2SS64rr:
2767  case X86::CVTSI2SDrr:
2768  case X86::CVTSI2SD64rr:
2769  case X86::CVTSD2SSrr:
2770  case X86::Int_CVTSD2SSrr:
2771  case X86::CVTSS2SDrr:
2772  case X86::Int_CVTSS2SDrr:
2773  case X86::RCPSSr:
2774  case X86::RCPSSr_Int:
2775  case X86::ROUNDSDr:
2776  case X86::ROUNDSSr:
2777  case X86::RSQRTSSr:
2778  case X86::RSQRTSSr_Int:
2779  case X86::SQRTSSr:
2780  case X86::SQRTSSr_Int:
2781  // AVX encoded versions
2782  case X86::VCVTSD2SSrr:
2783  case X86::Int_VCVTSD2SSrr:
2784  case X86::VCVTSS2SDrr:
2785  case X86::Int_VCVTSS2SDrr:
2786  case X86::VRCPSSr:
2787  case X86::VROUNDSDr:
2788  case X86::VROUNDSSr:
2789  case X86::VRSQRTSSr:
2790  case X86::VSQRTSSr:
2791    return true;
2792  }
2793
2794  return false;
2795}
2796
2797/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
2798/// instructions we would like before a partial register update.
2799unsigned X86InstrInfo::
2800getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
2801                             const TargetRegisterInfo *TRI) const {
2802  if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
2803    return 0;
2804
2805  // If MI is marked as reading Reg, the partial register update is wanted.
2806  const MachineOperand &MO = MI->getOperand(0);
2807  unsigned Reg = MO.getReg();
2808  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2809    if (MO.readsReg() || MI->readsVirtualRegister(Reg))
2810      return 0;
2811  } else {
2812    if (MI->readsRegister(Reg, TRI))
2813      return 0;
2814  }
2815
2816  // If any of the preceding 16 instructions are reading Reg, insert a
2817  // dependency breaking instruction.  The magic number is based on a few
2818  // Nehalem experiments.
2819  return 16;
2820}
2821
2822void X86InstrInfo::
2823breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
2824                          const TargetRegisterInfo *TRI) const {
2825  unsigned Reg = MI->getOperand(OpNum).getReg();
2826  if (X86::VR128RegClass.contains(Reg)) {
2827    // These instructions are all floating point domain, so xorps is the best
2828    // choice.
2829    bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2830    unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
2831    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
2832      .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
2833  } else if (X86::VR256RegClass.contains(Reg)) {
2834    // Use vxorps to clear the full ymm register.
2835    // It wants to read and write the xmm sub-register.
2836    unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
2837    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
2838      .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
2839      .addReg(Reg, RegState::ImplicitDefine);
2840  } else
2841    return;
2842  MI->addRegisterKilled(Reg, TRI, true);
2843}
2844
2845MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2846                                                  MachineInstr *MI,
2847                                           const SmallVectorImpl<unsigned> &Ops,
2848                                                  int FrameIndex) const {
2849  // Check switch flag
2850  if (NoFusing) return NULL;
2851
2852  // Unless optimizing for size, don't fold to avoid partial
2853  // register update stalls
2854  if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2855      hasPartialRegUpdate(MI->getOpcode()))
2856    return 0;
2857
2858  const MachineFrameInfo *MFI = MF.getFrameInfo();
2859  unsigned Size = MFI->getObjectSize(FrameIndex);
2860  unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2861  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2862    unsigned NewOpc = 0;
2863    unsigned RCSize = 0;
2864    switch (MI->getOpcode()) {
2865    default: return NULL;
2866    case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
2867    case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2868    case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2869    case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2870    }
2871    // Check if it's safe to fold the load. If the size of the object is
2872    // narrower than the load width, then it's not.
2873    if (Size < RCSize)
2874      return NULL;
2875    // Change to CMPXXri r, 0 first.
2876    MI->setDesc(get(NewOpc));
2877    MI->getOperand(1).ChangeToImmediate(0);
2878  } else if (Ops.size() != 1)
2879    return NULL;
2880
2881  SmallVector<MachineOperand,4> MOs;
2882  MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2883  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2884}
2885
2886MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2887                                                  MachineInstr *MI,
2888                                           const SmallVectorImpl<unsigned> &Ops,
2889                                                  MachineInstr *LoadMI) const {
2890  // Check switch flag
2891  if (NoFusing) return NULL;
2892
2893  // Unless optimizing for size, don't fold to avoid partial
2894  // register update stalls
2895  if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
2896      hasPartialRegUpdate(MI->getOpcode()))
2897    return 0;
2898
2899  // Determine the alignment of the load.
2900  unsigned Alignment = 0;
2901  if (LoadMI->hasOneMemOperand())
2902    Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2903  else
2904    switch (LoadMI->getOpcode()) {
2905    case X86::AVX_SET0PSY:
2906    case X86::AVX_SET0PDY:
2907    case X86::AVX2_SETALLONES:
2908      Alignment = 32;
2909      break;
2910    case X86::V_SET0:
2911    case X86::V_SETALLONES:
2912    case X86::AVX_SETALLONES:
2913      Alignment = 16;
2914      break;
2915    case X86::FsFLD0SD:
2916      Alignment = 8;
2917      break;
2918    case X86::FsFLD0SS:
2919      Alignment = 4;
2920      break;
2921    default:
2922      return 0;
2923    }
2924  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2925    unsigned NewOpc = 0;
2926    switch (MI->getOpcode()) {
2927    default: return NULL;
2928    case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
2929    case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
2930    case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
2931    case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
2932    }
2933    // Change to CMPXXri r, 0 first.
2934    MI->setDesc(get(NewOpc));
2935    MI->getOperand(1).ChangeToImmediate(0);
2936  } else if (Ops.size() != 1)
2937    return NULL;
2938
2939  // Make sure the subregisters match.
2940  // Otherwise we risk changing the size of the load.
2941  if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
2942    return NULL;
2943
2944  SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
2945  switch (LoadMI->getOpcode()) {
2946  case X86::V_SET0:
2947  case X86::V_SETALLONES:
2948  case X86::AVX_SET0PSY:
2949  case X86::AVX_SET0PDY:
2950  case X86::AVX_SETALLONES:
2951  case X86::AVX2_SETALLONES:
2952  case X86::FsFLD0SD:
2953  case X86::FsFLD0SS: {
2954    // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2955    // Create a constant-pool entry and operands to load from it.
2956
2957    // Medium and large mode can't fold loads this way.
2958    if (TM.getCodeModel() != CodeModel::Small &&
2959        TM.getCodeModel() != CodeModel::Kernel)
2960      return NULL;
2961
2962    // x86-32 PIC requires a PIC base register for constant pools.
2963    unsigned PICBase = 0;
2964    if (TM.getRelocationModel() == Reloc::PIC_) {
2965      if (TM.getSubtarget<X86Subtarget>().is64Bit())
2966        PICBase = X86::RIP;
2967      else
2968        // FIXME: PICBase = getGlobalBaseReg(&MF);
2969        // This doesn't work for several reasons.
2970        // 1. GlobalBaseReg may have been spilled.
2971        // 2. It may not be live at MI.
2972        return NULL;
2973    }
2974
2975    // Create a constant-pool entry.
2976    MachineConstantPool &MCP = *MF.getConstantPool();
2977    Type *Ty;
2978    unsigned Opc = LoadMI->getOpcode();
2979    if (Opc == X86::FsFLD0SS)
2980      Ty = Type::getFloatTy(MF.getFunction()->getContext());
2981    else if (Opc == X86::FsFLD0SD)
2982      Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2983    else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
2984      Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
2985    else
2986      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2987
2988    bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES ||
2989                      Opc == X86::AVX2_SETALLONES);
2990    const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
2991                                    Constant::getNullValue(Ty);
2992    unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2993
2994    // Create operands to load from the constant pool entry.
2995    MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2996    MOs.push_back(MachineOperand::CreateImm(1));
2997    MOs.push_back(MachineOperand::CreateReg(0, false));
2998    MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2999    MOs.push_back(MachineOperand::CreateReg(0, false));
3000    break;
3001  }
3002  default: {
3003    // Folding a normal load. Just copy the load's address operands.
3004    unsigned NumOps = LoadMI->getDesc().getNumOperands();
3005    for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
3006      MOs.push_back(LoadMI->getOperand(i));
3007    break;
3008  }
3009  }
3010  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
3011}
3012
3013
3014bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
3015                                  const SmallVectorImpl<unsigned> &Ops) const {
3016  // Check switch flag
3017  if (NoFusing) return 0;
3018
3019  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3020    switch (MI->getOpcode()) {
3021    default: return false;
3022    case X86::TEST8rr:
3023    case X86::TEST16rr:
3024    case X86::TEST32rr:
3025    case X86::TEST64rr:
3026      return true;
3027    case X86::ADD32ri:
3028      // FIXME: AsmPrinter doesn't know how to handle
3029      // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3030      if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3031        return false;
3032      break;
3033    }
3034  }
3035
3036  if (Ops.size() != 1)
3037    return false;
3038
3039  unsigned OpNum = Ops[0];
3040  unsigned Opc = MI->getOpcode();
3041  unsigned NumOps = MI->getDesc().getNumOperands();
3042  bool isTwoAddr = NumOps > 1 &&
3043    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3044
3045  // Folding a memory location into the two-address part of a two-address
3046  // instruction is different than folding it other places.  It requires
3047  // replacing the *two* registers with the memory location.
3048  const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3049  if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
3050    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3051  } else if (OpNum == 0) { // If operand 0
3052    switch (Opc) {
3053    case X86::MOV8r0:
3054    case X86::MOV16r0:
3055    case X86::MOV32r0:
3056    case X86::MOV64r0: return true;
3057    default: break;
3058    }
3059    OpcodeTablePtr = &RegOp2MemOpTable0;
3060  } else if (OpNum == 1) {
3061    OpcodeTablePtr = &RegOp2MemOpTable1;
3062  } else if (OpNum == 2) {
3063    OpcodeTablePtr = &RegOp2MemOpTable2;
3064  }
3065
3066  if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
3067    return true;
3068  return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
3069}
3070
3071bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
3072                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
3073                                SmallVectorImpl<MachineInstr*> &NewMIs) const {
3074  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3075    MemOp2RegOpTable.find(MI->getOpcode());
3076  if (I == MemOp2RegOpTable.end())
3077    return false;
3078  unsigned Opc = I->second.first;
3079  unsigned Index = I->second.second & TB_INDEX_MASK;
3080  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3081  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3082  if (UnfoldLoad && !FoldedLoad)
3083    return false;
3084  UnfoldLoad &= FoldedLoad;
3085  if (UnfoldStore && !FoldedStore)
3086    return false;
3087  UnfoldStore &= FoldedStore;
3088
3089  const MCInstrDesc &MCID = get(Opc);
3090  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3091  if (!MI->hasOneMemOperand() &&
3092      RC == &X86::VR128RegClass &&
3093      !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3094    // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
3095    // conservatively assume the address is unaligned. That's bad for
3096    // performance.
3097    return false;
3098  SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
3099  SmallVector<MachineOperand,2> BeforeOps;
3100  SmallVector<MachineOperand,2> AfterOps;
3101  SmallVector<MachineOperand,4> ImpOps;
3102  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3103    MachineOperand &Op = MI->getOperand(i);
3104    if (i >= Index && i < Index + X86::AddrNumOperands)
3105      AddrOps.push_back(Op);
3106    else if (Op.isReg() && Op.isImplicit())
3107      ImpOps.push_back(Op);
3108    else if (i < Index)
3109      BeforeOps.push_back(Op);
3110    else if (i > Index)
3111      AfterOps.push_back(Op);
3112  }
3113
3114  // Emit the load instruction.
3115  if (UnfoldLoad) {
3116    std::pair<MachineInstr::mmo_iterator,
3117              MachineInstr::mmo_iterator> MMOs =
3118      MF.extractLoadMemRefs(MI->memoperands_begin(),
3119                            MI->memoperands_end());
3120    loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
3121    if (UnfoldStore) {
3122      // Address operands cannot be marked isKill.
3123      for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
3124        MachineOperand &MO = NewMIs[0]->getOperand(i);
3125        if (MO.isReg())
3126          MO.setIsKill(false);
3127      }
3128    }
3129  }
3130
3131  // Emit the data processing instruction.
3132  MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
3133  MachineInstrBuilder MIB(DataMI);
3134
3135  if (FoldedStore)
3136    MIB.addReg(Reg, RegState::Define);
3137  for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
3138    MIB.addOperand(BeforeOps[i]);
3139  if (FoldedLoad)
3140    MIB.addReg(Reg);
3141  for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
3142    MIB.addOperand(AfterOps[i]);
3143  for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
3144    MachineOperand &MO = ImpOps[i];
3145    MIB.addReg(MO.getReg(),
3146               getDefRegState(MO.isDef()) |
3147               RegState::Implicit |
3148               getKillRegState(MO.isKill()) |
3149               getDeadRegState(MO.isDead()) |
3150               getUndefRegState(MO.isUndef()));
3151  }
3152  // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
3153  unsigned NewOpc = 0;
3154  switch (DataMI->getOpcode()) {
3155  default: break;
3156  case X86::CMP64ri32:
3157  case X86::CMP64ri8:
3158  case X86::CMP32ri:
3159  case X86::CMP32ri8:
3160  case X86::CMP16ri:
3161  case X86::CMP16ri8:
3162  case X86::CMP8ri: {
3163    MachineOperand &MO0 = DataMI->getOperand(0);
3164    MachineOperand &MO1 = DataMI->getOperand(1);
3165    if (MO1.getImm() == 0) {
3166      switch (DataMI->getOpcode()) {
3167      default: break;
3168      case X86::CMP64ri8:
3169      case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
3170      case X86::CMP32ri8:
3171      case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
3172      case X86::CMP16ri8:
3173      case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
3174      case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
3175      }
3176      DataMI->setDesc(get(NewOpc));
3177      MO1.ChangeToRegister(MO0.getReg(), false);
3178    }
3179  }
3180  }
3181  NewMIs.push_back(DataMI);
3182
3183  // Emit the store instruction.
3184  if (UnfoldStore) {
3185    const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI);
3186    std::pair<MachineInstr::mmo_iterator,
3187              MachineInstr::mmo_iterator> MMOs =
3188      MF.extractStoreMemRefs(MI->memoperands_begin(),
3189                             MI->memoperands_end());
3190    storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
3191  }
3192
3193  return true;
3194}
3195
3196bool
3197X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
3198                                  SmallVectorImpl<SDNode*> &NewNodes) const {
3199  if (!N->isMachineOpcode())
3200    return false;
3201
3202  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3203    MemOp2RegOpTable.find(N->getMachineOpcode());
3204  if (I == MemOp2RegOpTable.end())
3205    return false;
3206  unsigned Opc = I->second.first;
3207  unsigned Index = I->second.second & TB_INDEX_MASK;
3208  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3209  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3210  const MCInstrDesc &MCID = get(Opc);
3211  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI);
3212  unsigned NumDefs = MCID.NumDefs;
3213  std::vector<SDValue> AddrOps;
3214  std::vector<SDValue> BeforeOps;
3215  std::vector<SDValue> AfterOps;
3216  DebugLoc dl = N->getDebugLoc();
3217  unsigned NumOps = N->getNumOperands();
3218  for (unsigned i = 0; i != NumOps-1; ++i) {
3219    SDValue Op = N->getOperand(i);
3220    if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
3221      AddrOps.push_back(Op);
3222    else if (i < Index-NumDefs)
3223      BeforeOps.push_back(Op);
3224    else if (i > Index-NumDefs)
3225      AfterOps.push_back(Op);
3226  }
3227  SDValue Chain = N->getOperand(NumOps-1);
3228  AddrOps.push_back(Chain);
3229
3230  // Emit the load instruction.
3231  SDNode *Load = 0;
3232  MachineFunction &MF = DAG.getMachineFunction();
3233  if (FoldedLoad) {
3234    EVT VT = *RC->vt_begin();
3235    std::pair<MachineInstr::mmo_iterator,
3236              MachineInstr::mmo_iterator> MMOs =
3237      MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3238                            cast<MachineSDNode>(N)->memoperands_end());
3239    if (!(*MMOs.first) &&
3240        RC == &X86::VR128RegClass &&
3241        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3242      // Do not introduce a slow unaligned load.
3243      return false;
3244    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3245    bool isAligned = (*MMOs.first) &&
3246                     (*MMOs.first)->getAlignment() >= Alignment;
3247    Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3248                              VT, MVT::Other, &AddrOps[0], AddrOps.size());
3249    NewNodes.push_back(Load);
3250
3251    // Preserve memory reference information.
3252    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3253  }
3254
3255  // Emit the data processing instruction.
3256  std::vector<EVT> VTs;
3257  const TargetRegisterClass *DstRC = 0;
3258  if (MCID.getNumDefs() > 0) {
3259    DstRC = getRegClass(MCID, 0, &RI);
3260    VTs.push_back(*DstRC->vt_begin());
3261  }
3262  for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
3263    EVT VT = N->getValueType(i);
3264    if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
3265      VTs.push_back(VT);
3266  }
3267  if (Load)
3268    BeforeOps.push_back(SDValue(Load, 0));
3269  std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
3270  SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
3271                                      BeforeOps.size());
3272  NewNodes.push_back(NewNode);
3273
3274  // Emit the store instruction.
3275  if (FoldedStore) {
3276    AddrOps.pop_back();
3277    AddrOps.push_back(SDValue(NewNode, 0));
3278    AddrOps.push_back(Chain);
3279    std::pair<MachineInstr::mmo_iterator,
3280              MachineInstr::mmo_iterator> MMOs =
3281      MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3282                             cast<MachineSDNode>(N)->memoperands_end());
3283    if (!(*MMOs.first) &&
3284        RC == &X86::VR128RegClass &&
3285        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3286      // Do not introduce a slow unaligned store.
3287      return false;
3288    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3289    bool isAligned = (*MMOs.first) &&
3290                     (*MMOs.first)->getAlignment() >= Alignment;
3291    SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
3292                                                         isAligned, TM),
3293                                       dl, MVT::Other,
3294                                       &AddrOps[0], AddrOps.size());
3295    NewNodes.push_back(Store);
3296
3297    // Preserve memory reference information.
3298    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3299  }
3300
3301  return true;
3302}
3303
3304unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
3305                                      bool UnfoldLoad, bool UnfoldStore,
3306                                      unsigned *LoadRegIndex) const {
3307  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3308    MemOp2RegOpTable.find(Opc);
3309  if (I == MemOp2RegOpTable.end())
3310    return 0;
3311  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3312  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3313  if (UnfoldLoad && !FoldedLoad)
3314    return 0;
3315  if (UnfoldStore && !FoldedStore)
3316    return 0;
3317  if (LoadRegIndex)
3318    *LoadRegIndex = I->second.second & TB_INDEX_MASK;
3319  return I->second.first;
3320}
3321
3322bool
3323X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
3324                                     int64_t &Offset1, int64_t &Offset2) const {
3325  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
3326    return false;
3327  unsigned Opc1 = Load1->getMachineOpcode();
3328  unsigned Opc2 = Load2->getMachineOpcode();
3329  switch (Opc1) {
3330  default: return false;
3331  case X86::MOV8rm:
3332  case X86::MOV16rm:
3333  case X86::MOV32rm:
3334  case X86::MOV64rm:
3335  case X86::LD_Fp32m:
3336  case X86::LD_Fp64m:
3337  case X86::LD_Fp80m:
3338  case X86::MOVSSrm:
3339  case X86::MOVSDrm:
3340  case X86::MMX_MOVD64rm:
3341  case X86::MMX_MOVQ64rm:
3342  case X86::FsMOVAPSrm:
3343  case X86::FsMOVAPDrm:
3344  case X86::MOVAPSrm:
3345  case X86::MOVUPSrm:
3346  case X86::MOVAPDrm:
3347  case X86::MOVDQArm:
3348  case X86::MOVDQUrm:
3349  // AVX load instructions
3350  case X86::VMOVSSrm:
3351  case X86::VMOVSDrm:
3352  case X86::FsVMOVAPSrm:
3353  case X86::FsVMOVAPDrm:
3354  case X86::VMOVAPSrm:
3355  case X86::VMOVUPSrm:
3356  case X86::VMOVAPDrm:
3357  case X86::VMOVDQArm:
3358  case X86::VMOVDQUrm:
3359  case X86::VMOVAPSYrm:
3360  case X86::VMOVUPSYrm:
3361  case X86::VMOVAPDYrm:
3362  case X86::VMOVDQAYrm:
3363  case X86::VMOVDQUYrm:
3364    break;
3365  }
3366  switch (Opc2) {
3367  default: return false;
3368  case X86::MOV8rm:
3369  case X86::MOV16rm:
3370  case X86::MOV32rm:
3371  case X86::MOV64rm:
3372  case X86::LD_Fp32m:
3373  case X86::LD_Fp64m:
3374  case X86::LD_Fp80m:
3375  case X86::MOVSSrm:
3376  case X86::MOVSDrm:
3377  case X86::MMX_MOVD64rm:
3378  case X86::MMX_MOVQ64rm:
3379  case X86::FsMOVAPSrm:
3380  case X86::FsMOVAPDrm:
3381  case X86::MOVAPSrm:
3382  case X86::MOVUPSrm:
3383  case X86::MOVAPDrm:
3384  case X86::MOVDQArm:
3385  case X86::MOVDQUrm:
3386  // AVX load instructions
3387  case X86::VMOVSSrm:
3388  case X86::VMOVSDrm:
3389  case X86::FsVMOVAPSrm:
3390  case X86::FsVMOVAPDrm:
3391  case X86::VMOVAPSrm:
3392  case X86::VMOVUPSrm:
3393  case X86::VMOVAPDrm:
3394  case X86::VMOVDQArm:
3395  case X86::VMOVDQUrm:
3396  case X86::VMOVAPSYrm:
3397  case X86::VMOVUPSYrm:
3398  case X86::VMOVAPDYrm:
3399  case X86::VMOVDQAYrm:
3400  case X86::VMOVDQUYrm:
3401    break;
3402  }
3403
3404  // Check if chain operands and base addresses match.
3405  if (Load1->getOperand(0) != Load2->getOperand(0) ||
3406      Load1->getOperand(5) != Load2->getOperand(5))
3407    return false;
3408  // Segment operands should match as well.
3409  if (Load1->getOperand(4) != Load2->getOperand(4))
3410    return false;
3411  // Scale should be 1, Index should be Reg0.
3412  if (Load1->getOperand(1) == Load2->getOperand(1) &&
3413      Load1->getOperand(2) == Load2->getOperand(2)) {
3414    if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3415      return false;
3416
3417    // Now let's examine the displacements.
3418    if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3419        isa<ConstantSDNode>(Load2->getOperand(3))) {
3420      Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3421      Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3422      return true;
3423    }
3424  }
3425  return false;
3426}
3427
3428bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3429                                           int64_t Offset1, int64_t Offset2,
3430                                           unsigned NumLoads) const {
3431  assert(Offset2 > Offset1);
3432  if ((Offset2 - Offset1) / 8 > 64)
3433    return false;
3434
3435  unsigned Opc1 = Load1->getMachineOpcode();
3436  unsigned Opc2 = Load2->getMachineOpcode();
3437  if (Opc1 != Opc2)
3438    return false;  // FIXME: overly conservative?
3439
3440  switch (Opc1) {
3441  default: break;
3442  case X86::LD_Fp32m:
3443  case X86::LD_Fp64m:
3444  case X86::LD_Fp80m:
3445  case X86::MMX_MOVD64rm:
3446  case X86::MMX_MOVQ64rm:
3447    return false;
3448  }
3449
3450  EVT VT = Load1->getValueType(0);
3451  switch (VT.getSimpleVT().SimpleTy) {
3452  default:
3453    // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3454    // have 16 of them to play with.
3455    if (TM.getSubtargetImpl()->is64Bit()) {
3456      if (NumLoads >= 3)
3457        return false;
3458    } else if (NumLoads) {
3459      return false;
3460    }
3461    break;
3462  case MVT::i8:
3463  case MVT::i16:
3464  case MVT::i32:
3465  case MVT::i64:
3466  case MVT::f32:
3467  case MVT::f64:
3468    if (NumLoads)
3469      return false;
3470    break;
3471  }
3472
3473  return true;
3474}
3475
3476
3477bool X86InstrInfo::
3478ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3479  assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3480  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3481  if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3482    return true;
3483  Cond[0].setImm(GetOppositeBranchCondition(CC));
3484  return false;
3485}
3486
3487bool X86InstrInfo::
3488isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3489  // FIXME: Return false for x87 stack register classes for now. We can't
3490  // allow any loads of these registers before FpGet_ST0_80.
3491  return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3492           RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3493}
3494
3495/// getGlobalBaseReg - Return a virtual register initialized with the
3496/// the global base register value. Output instructions required to
3497/// initialize the register in the function entry block, if necessary.
3498///
3499/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3500///
3501unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3502  assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3503         "X86-64 PIC uses RIP relative addressing");
3504
3505  X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3506  unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3507  if (GlobalBaseReg != 0)
3508    return GlobalBaseReg;
3509
3510  // Create the register. The code to initialize it is inserted
3511  // later, by the CGBR pass (below).
3512  MachineRegisterInfo &RegInfo = MF->getRegInfo();
3513  GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3514  X86FI->setGlobalBaseReg(GlobalBaseReg);
3515  return GlobalBaseReg;
3516}
3517
3518// These are the replaceable SSE instructions. Some of these have Int variants
3519// that we don't include here. We don't want to replace instructions selected
3520// by intrinsics.
3521static const unsigned ReplaceableInstrs[][3] = {
3522  //PackedSingle     PackedDouble    PackedInt
3523  { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
3524  { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
3525  { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
3526  { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
3527  { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
3528  { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
3529  { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
3530  { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
3531  { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
3532  { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
3533  { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
3534  { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
3535  { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
3536  { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
3537  // AVX 128-bit support
3538  { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
3539  { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
3540  { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
3541  { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
3542  { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
3543  { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3544  { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
3545  { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
3546  { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
3547  { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
3548  { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
3549  { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
3550  { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
3551  { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
3552  // AVX 256-bit support
3553  { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
3554  { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
3555  { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
3556  { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
3557  { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
3558  { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
3559};
3560
3561static const unsigned ReplaceableInstrsAVX2[][3] = {
3562  //PackedSingle       PackedDouble       PackedInt
3563  { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
3564  { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
3565  { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
3566  { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
3567  { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
3568  { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
3569  { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
3570  { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
3571  { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
3572  { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
3573  { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
3574  { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
3575  { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
3576  { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr }
3577};
3578
3579// FIXME: Some shuffle and unpack instructions have equivalents in different
3580// domains, but they require a bit more work than just switching opcodes.
3581
3582static const unsigned *lookup(unsigned opcode, unsigned domain) {
3583  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3584    if (ReplaceableInstrs[i][domain-1] == opcode)
3585      return ReplaceableInstrs[i];
3586  return 0;
3587}
3588
3589static const unsigned *lookupAVX2(unsigned opcode, unsigned domain) {
3590  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
3591    if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
3592      return ReplaceableInstrsAVX2[i];
3593  return 0;
3594}
3595
3596std::pair<uint16_t, uint16_t>
3597X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3598  uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3599  bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
3600  uint16_t validDomains = 0;
3601  if (domain && lookup(MI->getOpcode(), domain))
3602    validDomains = 0xe;
3603  else if (domain && lookupAVX2(MI->getOpcode(), domain))
3604    validDomains = hasAVX2 ? 0xe : 0x6;
3605  return std::make_pair(domain, validDomains);
3606}
3607
3608void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3609  assert(Domain>0 && Domain<4 && "Invalid execution domain");
3610  uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3611  assert(dom && "Not an SSE instruction");
3612  const unsigned *table = lookup(MI->getOpcode(), dom);
3613  if (!table) { // try the other table
3614    assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
3615           "256-bit vector operations only available in AVX2");
3616    table = lookupAVX2(MI->getOpcode(), dom);
3617  }
3618  assert(table && "Cannot change domain");
3619  MI->setDesc(get(table[Domain-1]));
3620}
3621
3622/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3623void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3624  NopInst.setOpcode(X86::NOOP);
3625}
3626
3627bool X86InstrInfo::isHighLatencyDef(int opc) const {
3628  switch (opc) {
3629  default: return false;
3630  case X86::DIVSDrm:
3631  case X86::DIVSDrm_Int:
3632  case X86::DIVSDrr:
3633  case X86::DIVSDrr_Int:
3634  case X86::DIVSSrm:
3635  case X86::DIVSSrm_Int:
3636  case X86::DIVSSrr:
3637  case X86::DIVSSrr_Int:
3638  case X86::SQRTPDm:
3639  case X86::SQRTPDm_Int:
3640  case X86::SQRTPDr:
3641  case X86::SQRTPDr_Int:
3642  case X86::SQRTPSm:
3643  case X86::SQRTPSm_Int:
3644  case X86::SQRTPSr:
3645  case X86::SQRTPSr_Int:
3646  case X86::SQRTSDm:
3647  case X86::SQRTSDm_Int:
3648  case X86::SQRTSDr:
3649  case X86::SQRTSDr_Int:
3650  case X86::SQRTSSm:
3651  case X86::SQRTSSm_Int:
3652  case X86::SQRTSSr:
3653  case X86::SQRTSSr_Int:
3654  // AVX instructions with high latency
3655  case X86::VDIVSDrm:
3656  case X86::VDIVSDrm_Int:
3657  case X86::VDIVSDrr:
3658  case X86::VDIVSDrr_Int:
3659  case X86::VDIVSSrm:
3660  case X86::VDIVSSrm_Int:
3661  case X86::VDIVSSrr:
3662  case X86::VDIVSSrr_Int:
3663  case X86::VSQRTPDm:
3664  case X86::VSQRTPDm_Int:
3665  case X86::VSQRTPDr:
3666  case X86::VSQRTPDr_Int:
3667  case X86::VSQRTPSm:
3668  case X86::VSQRTPSm_Int:
3669  case X86::VSQRTPSr:
3670  case X86::VSQRTPSr_Int:
3671  case X86::VSQRTSDm:
3672  case X86::VSQRTSDm_Int:
3673  case X86::VSQRTSDr:
3674  case X86::VSQRTSSm:
3675  case X86::VSQRTSSm_Int:
3676  case X86::VSQRTSSr:
3677    return true;
3678  }
3679}
3680
3681bool X86InstrInfo::
3682hasHighOperandLatency(const InstrItineraryData *ItinData,
3683                      const MachineRegisterInfo *MRI,
3684                      const MachineInstr *DefMI, unsigned DefIdx,
3685                      const MachineInstr *UseMI, unsigned UseIdx) const {
3686  return isHighLatencyDef(DefMI->getOpcode());
3687}
3688
3689namespace {
3690  /// CGBR - Create Global Base Reg pass. This initializes the PIC
3691  /// global base register for x86-32.
3692  struct CGBR : public MachineFunctionPass {
3693    static char ID;
3694    CGBR() : MachineFunctionPass(ID) {}
3695
3696    virtual bool runOnMachineFunction(MachineFunction &MF) {
3697      const X86TargetMachine *TM =
3698        static_cast<const X86TargetMachine *>(&MF.getTarget());
3699
3700      assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3701             "X86-64 PIC uses RIP relative addressing");
3702
3703      // Only emit a global base reg in PIC mode.
3704      if (TM->getRelocationModel() != Reloc::PIC_)
3705        return false;
3706
3707      X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3708      unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3709
3710      // If we didn't need a GlobalBaseReg, don't insert code.
3711      if (GlobalBaseReg == 0)
3712        return false;
3713
3714      // Insert the set of GlobalBaseReg into the first MBB of the function
3715      MachineBasicBlock &FirstMBB = MF.front();
3716      MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3717      DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3718      MachineRegisterInfo &RegInfo = MF.getRegInfo();
3719      const X86InstrInfo *TII = TM->getInstrInfo();
3720
3721      unsigned PC;
3722      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3723        PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3724      else
3725        PC = GlobalBaseReg;
3726
3727      // Operand of MovePCtoStack is completely ignored by asm printer. It's
3728      // only used in JIT code emission as displacement to pc.
3729      BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3730
3731      // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3732      // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3733      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3734        // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3735        BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3736          .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3737                                        X86II::MO_GOT_ABSOLUTE_ADDRESS);
3738      }
3739
3740      return true;
3741    }
3742
3743    virtual const char *getPassName() const {
3744      return "X86 PIC Global Base Reg Initialization";
3745    }
3746
3747    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3748      AU.setPreservesCFG();
3749      MachineFunctionPass::getAnalysisUsage(AU);
3750    }
3751  };
3752}
3753
3754char CGBR::ID = 0;
3755FunctionPass*
3756llvm::createGlobalBaseRegPass() { return new CGBR(); }
3757