X86InstrInfo.cpp revision 11e15b38e965731e5bfff6c73d8d269196e5048c 
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "X86GenInstrInfo.inc"
19using namespace llvm;
20
21X86InstrInfo::X86InstrInfo()
22  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
23}
24
25
26bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
27                               unsigned& sourceReg,
28                               unsigned& destReg) const {
29  MachineOpCode oc = MI.getOpcode();
30  if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
31      oc == X86::FpMOV  || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
32      oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
33      oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
34      oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
35      oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
36      oc == X86::MOVDI2PDIrr || oc == X86::MOVQI2PQIrr ||
37      oc == X86::MOVPDI2DIrr) {
38      assert(MI.getNumOperands() == 2 &&
39             MI.getOperand(0).isRegister() &&
40             MI.getOperand(1).isRegister() &&
41             "invalid register-register move instruction");
42      sourceReg = MI.getOperand(1).getReg();
43      destReg = MI.getOperand(0).getReg();
44      return true;
45  }
46  return false;
47}
48
49unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
50                                           int &FrameIndex) const {
51  switch (MI->getOpcode()) {
52  default: break;
53  case X86::MOV8rm:
54  case X86::MOV16rm:
55  case X86::MOV32rm:
56  case X86::FpLD64m:
57  case X86::MOVSSrm:
58  case X86::MOVSDrm:
59    if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
60        MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
61        MI->getOperand(2).getImmedValue() == 1 &&
62        MI->getOperand(3).getReg() == 0 &&
63        MI->getOperand(4).getImmedValue() == 0) {
64      FrameIndex = MI->getOperand(1).getFrameIndex();
65      return MI->getOperand(0).getReg();
66    }
67    break;
68  }
69  return 0;
70}
71
72unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
73                                          int &FrameIndex) const {
74  switch (MI->getOpcode()) {
75  default: break;
76  case X86::MOV8mr:
77  case X86::MOV16mr:
78  case X86::MOV32mr:
79  case X86::FpSTP64m:
80  case X86::MOVSSmr:
81  case X86::MOVSDmr:
82    if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
83        MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
84        MI->getOperand(1).getImmedValue() == 1 &&
85        MI->getOperand(2).getReg() == 0 &&
86        MI->getOperand(3).getImmedValue() == 0) {
87      FrameIndex = MI->getOperand(0).getFrameIndex();
88      return MI->getOperand(4).getReg();
89    }
90    break;
91  }
92  return 0;
93}
94
95
96
97/// convertToThreeAddress - This method must be implemented by targets that
98/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
99/// may be able to convert a two-address instruction into a true
100/// three-address instruction on demand.  This allows the X86 target (for
101/// example) to convert ADD and SHL instructions into LEA instructions if they
102/// would require register copies due to two-addressness.
103///
104/// This method returns a null pointer if the transformation cannot be
105/// performed, otherwise it returns the new instruction.
106///
107MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
108  // All instructions input are two-addr instructions.  Get the known operands.
109  unsigned Dest = MI->getOperand(0).getReg();
110  unsigned Src = MI->getOperand(1).getReg();
111
112  // FIXME: None of these instructions are promotable to LEAs without
113  // additional information.  In particular, LEA doesn't set the flags that
114  // add and inc do.  :(
115  return 0;
116
117  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
118  // we have subtarget support, enable the 16-bit LEA generation here.
119  bool DisableLEA16 = true;
120
121  switch (MI->getOpcode()) {
122  case X86::INC32r:
123    assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
124    return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
125  case X86::INC16r:
126    if (DisableLEA16) return 0;
127    assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
128    return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
129  case X86::DEC32r:
130    assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
131    return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
132  case X86::DEC16r:
133    if (DisableLEA16) return 0;
134    assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
135    return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
136  case X86::ADD32rr:
137    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
138    return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
139                     MI->getOperand(2).getReg());
140  case X86::ADD16rr:
141    if (DisableLEA16) return 0;
142    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
143    return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
144                     MI->getOperand(2).getReg());
145  case X86::ADD32ri:
146    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
147    if (MI->getOperand(2).isImmediate())
148      return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
149                          MI->getOperand(2).getImmedValue());
150    return 0;
151  case X86::ADD16ri:
152    if (DisableLEA16) return 0;
153    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
154    if (MI->getOperand(2).isImmediate())
155      return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
156                          MI->getOperand(2).getImmedValue());
157    break;
158
159  case X86::SHL16ri:
160    if (DisableLEA16) return 0;
161  case X86::SHL32ri:
162    assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
163           "Unknown shl instruction!");
164    unsigned ShAmt = MI->getOperand(2).getImmedValue();
165    if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
166      X86AddressMode AM;
167      AM.Scale = 1 << ShAmt;
168      AM.IndexReg = Src;
169      unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
170      return addFullAddress(BuildMI(Opc, 5, Dest), AM);
171    }
172    break;
173  }
174
175  return 0;
176}
177
178/// commuteInstruction - We have a few instructions that must be hacked on to
179/// commute them.
180///
181MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
182  switch (MI->getOpcode()) {
183  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
184  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
185  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
186  case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
187    unsigned Opc;
188    unsigned Size;
189    switch (MI->getOpcode()) {
190    default: assert(0 && "Unreachable!");
191    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
192    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
193    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
194    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
195    }
196    unsigned Amt = MI->getOperand(3).getImmedValue();
197    unsigned A = MI->getOperand(0).getReg();
198    unsigned B = MI->getOperand(1).getReg();
199    unsigned C = MI->getOperand(2).getReg();
200    return BuildMI(Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt);
201  }
202  default:
203    return TargetInstrInfo::commuteInstruction(MI);
204  }
205}
206
207
208void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
209                              MachineBasicBlock& TMBB) const {
210  BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
211}
212
213MachineBasicBlock::iterator
214X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
215  unsigned Opcode = MI->getOpcode();
216  assert(isBranch(Opcode) && "MachineInstr must be a branch");
217  unsigned ROpcode;
218  switch (Opcode) {
219  default: assert(0 && "Cannot reverse unconditional branches!");
220  case X86::JB:  ROpcode = X86::JAE; break;
221  case X86::JAE: ROpcode = X86::JB;  break;
222  case X86::JE:  ROpcode = X86::JNE; break;
223  case X86::JNE: ROpcode = X86::JE;  break;
224  case X86::JBE: ROpcode = X86::JA;  break;
225  case X86::JA:  ROpcode = X86::JBE; break;
226  case X86::JS:  ROpcode = X86::JNS; break;
227  case X86::JNS: ROpcode = X86::JS;  break;
228  case X86::JP:  ROpcode = X86::JNP; break;
229  case X86::JNP: ROpcode = X86::JP;  break;
230  case X86::JL:  ROpcode = X86::JGE; break;
231  case X86::JGE: ROpcode = X86::JL;  break;
232  case X86::JLE: ROpcode = X86::JG;  break;
233  case X86::JG:  ROpcode = X86::JLE; break;
234  }
235  MachineBasicBlock* MBB = MI->getParent();
236  MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
237  return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
238}
239
240