X86InstrInfo.cpp revision 1ee29257428960fede862fcfdbe80d5d007927e9
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86Subtarget.h" 19#include "X86TargetMachine.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/LiveVariables.h" 22using namespace llvm; 23 24X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 25 : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])), 26 TM(tm), RI(tm, *this) { 27} 28 29bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, 30 unsigned& sourceReg, 31 unsigned& destReg) const { 32 MachineOpCode oc = MI.getOpcode(); 33 if (oc == X86::MOV8rr || oc == X86::MOV16rr || 34 oc == X86::MOV32rr || oc == X86::MOV64rr || 35 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ || 36 oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr || 37 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || 38 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || 39 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || 40 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr) { 41 assert(MI.getNumOperands() == 2 && 42 MI.getOperand(0).isRegister() && 43 MI.getOperand(1).isRegister() && 44 "invalid register-register move instruction"); 45 sourceReg = MI.getOperand(1).getReg(); 46 destReg = MI.getOperand(0).getReg(); 47 return true; 48 } 49 return false; 50} 51 52unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, 53 int &FrameIndex) const { 54 switch (MI->getOpcode()) { 55 default: break; 56 case X86::MOV8rm: 57 case X86::MOV16rm: 58 case X86::MOV16_rm: 59 case X86::MOV32rm: 60 case X86::MOV32_rm: 61 case X86::MOV64rm: 62 case X86::FpLD64m: 63 case X86::MOVSSrm: 64 case X86::MOVSDrm: 65 case X86::MOVAPSrm: 66 case X86::MOVAPDrm: 67 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && 68 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() && 69 MI->getOperand(2).getImmedValue() == 1 && 70 MI->getOperand(3).getReg() == 0 && 71 MI->getOperand(4).getImmedValue() == 0) { 72 FrameIndex = MI->getOperand(1).getFrameIndex(); 73 return MI->getOperand(0).getReg(); 74 } 75 break; 76 } 77 return 0; 78} 79 80unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, 81 int &FrameIndex) const { 82 switch (MI->getOpcode()) { 83 default: break; 84 case X86::MOV8mr: 85 case X86::MOV16mr: 86 case X86::MOV16_mr: 87 case X86::MOV32mr: 88 case X86::MOV32_mr: 89 case X86::MOV64mr: 90 case X86::FpSTP64m: 91 case X86::MOVSSmr: 92 case X86::MOVSDmr: 93 case X86::MOVAPSmr: 94 case X86::MOVAPDmr: 95 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() && 96 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() && 97 MI->getOperand(1).getImmedValue() == 1 && 98 MI->getOperand(2).getReg() == 0 && 99 MI->getOperand(3).getImmedValue() == 0) { 100 FrameIndex = MI->getOperand(0).getFrameIndex(); 101 return MI->getOperand(4).getReg(); 102 } 103 break; 104 } 105 return 0; 106} 107 108 109/// convertToThreeAddress - This method must be implemented by targets that 110/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 111/// may be able to convert a two-address instruction into a true 112/// three-address instruction on demand. This allows the X86 target (for 113/// example) to convert ADD and SHL instructions into LEA instructions if they 114/// would require register copies due to two-addressness. 115/// 116/// This method returns a null pointer if the transformation cannot be 117/// performed, otherwise it returns the new instruction. 118/// 119MachineInstr * 120X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 121 MachineBasicBlock::iterator &MBBI, 122 LiveVariables &LV) const { 123 MachineInstr *MI = MBBI; 124 // All instructions input are two-addr instructions. Get the known operands. 125 unsigned Dest = MI->getOperand(0).getReg(); 126 unsigned Src = MI->getOperand(1).getReg(); 127 128 MachineInstr *NewMI = NULL; 129 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 130 // we have subtarget support, enable the 16-bit LEA generation here. 131 bool DisableLEA16 = true; 132 133 switch (MI->getOpcode()) { 134 default: break; 135 case X86::SHUFPSrri: { 136 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 137 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 138 unsigned A = MI->getOperand(0).getReg(); 139 unsigned B = MI->getOperand(1).getReg(); 140 unsigned C = MI->getOperand(2).getReg(); 141 unsigned M = MI->getOperand(3).getImmedValue(); 142 if (!Subtarget->hasSSE2() || B != C) return 0; 143 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M); 144 goto Done; 145 } 146 } 147 148 // FIXME: None of these instructions are promotable to LEAs without 149 // additional information. In particular, LEA doesn't set the flags that 150 // add and inc do. :( 151 return 0; 152 153 switch (MI->getOpcode()) { 154 case X86::INC32r: 155 case X86::INC64_32r: 156 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); 157 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 1); 158 break; 159 case X86::INC16r: 160 case X86::INC64_16r: 161 if (DisableLEA16) return 0; 162 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); 163 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1); 164 break; 165 case X86::DEC32r: 166 case X86::DEC64_32r: 167 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); 168 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, -1); 169 break; 170 case X86::DEC16r: 171 case X86::DEC64_16r: 172 if (DisableLEA16) return 0; 173 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); 174 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1); 175 break; 176 case X86::ADD32rr: 177 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 178 NewMI = addRegReg(BuildMI(get(X86::LEA32r), Dest), Src, 179 MI->getOperand(2).getReg()); 180 break; 181 case X86::ADD16rr: 182 if (DisableLEA16) return 0; 183 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 184 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src, 185 MI->getOperand(2).getReg()); 186 break; 187 case X86::ADD32ri: 188 case X86::ADD32ri8: 189 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 190 if (MI->getOperand(2).isImmediate()) 191 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 192 MI->getOperand(2).getImmedValue()); 193 break; 194 case X86::ADD16ri: 195 case X86::ADD16ri8: 196 if (DisableLEA16) return 0; 197 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 198 if (MI->getOperand(2).isImmediate()) 199 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 200 MI->getOperand(2).getImmedValue()); 201 break; 202 case X86::SHL16ri: 203 if (DisableLEA16) return 0; 204 case X86::SHL32ri: 205 assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() && 206 "Unknown shl instruction!"); 207 unsigned ShAmt = MI->getOperand(2).getImmedValue(); 208 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { 209 X86AddressMode AM; 210 AM.Scale = 1 << ShAmt; 211 AM.IndexReg = Src; 212 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r; 213 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM); 214 } 215 break; 216 } 217 218Done: 219 if (NewMI) { 220 NewMI->copyKillDeadInfo(MI); 221 LV.instructionChanged(MI, NewMI); // Update live variables 222 MFI->insert(MBBI, NewMI); // Insert the new inst 223 } 224 return NewMI; 225} 226 227/// commuteInstruction - We have a few instructions that must be hacked on to 228/// commute them. 229/// 230MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { 231 // FIXME: Can commute cmoves by changing the condition! 232 switch (MI->getOpcode()) { 233 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 234 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 235 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 236 case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 237 unsigned Opc; 238 unsigned Size; 239 switch (MI->getOpcode()) { 240 default: assert(0 && "Unreachable!"); 241 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 242 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 243 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 244 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 245 } 246 unsigned Amt = MI->getOperand(3).getImmedValue(); 247 unsigned A = MI->getOperand(0).getReg(); 248 unsigned B = MI->getOperand(1).getReg(); 249 unsigned C = MI->getOperand(2).getReg(); 250 bool BisKill = MI->getOperand(1).isKill(); 251 bool CisKill = MI->getOperand(2).isKill(); 252 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill) 253 .addReg(B, false, false, BisKill).addImm(Size-Amt); 254 } 255 default: 256 return TargetInstrInfo::commuteInstruction(MI); 257 } 258} 259 260static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 261 switch (BrOpc) { 262 default: return X86::COND_INVALID; 263 case X86::JE: return X86::COND_E; 264 case X86::JNE: return X86::COND_NE; 265 case X86::JL: return X86::COND_L; 266 case X86::JLE: return X86::COND_LE; 267 case X86::JG: return X86::COND_G; 268 case X86::JGE: return X86::COND_GE; 269 case X86::JB: return X86::COND_B; 270 case X86::JBE: return X86::COND_BE; 271 case X86::JA: return X86::COND_A; 272 case X86::JAE: return X86::COND_AE; 273 case X86::JS: return X86::COND_S; 274 case X86::JNS: return X86::COND_NS; 275 case X86::JP: return X86::COND_P; 276 case X86::JNP: return X86::COND_NP; 277 case X86::JO: return X86::COND_O; 278 case X86::JNO: return X86::COND_NO; 279 } 280} 281 282unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 283 switch (CC) { 284 default: assert(0 && "Illegal condition code!"); 285 case X86::COND_E: return X86::JE; 286 case X86::COND_NE: return X86::JNE; 287 case X86::COND_L: return X86::JL; 288 case X86::COND_LE: return X86::JLE; 289 case X86::COND_G: return X86::JG; 290 case X86::COND_GE: return X86::JGE; 291 case X86::COND_B: return X86::JB; 292 case X86::COND_BE: return X86::JBE; 293 case X86::COND_A: return X86::JA; 294 case X86::COND_AE: return X86::JAE; 295 case X86::COND_S: return X86::JS; 296 case X86::COND_NS: return X86::JNS; 297 case X86::COND_P: return X86::JP; 298 case X86::COND_NP: return X86::JNP; 299 case X86::COND_O: return X86::JO; 300 case X86::COND_NO: return X86::JNO; 301 } 302} 303 304/// GetOppositeBranchCondition - Return the inverse of the specified condition, 305/// e.g. turning COND_E to COND_NE. 306X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 307 switch (CC) { 308 default: assert(0 && "Illegal condition code!"); 309 case X86::COND_E: return X86::COND_NE; 310 case X86::COND_NE: return X86::COND_E; 311 case X86::COND_L: return X86::COND_GE; 312 case X86::COND_LE: return X86::COND_G; 313 case X86::COND_G: return X86::COND_LE; 314 case X86::COND_GE: return X86::COND_L; 315 case X86::COND_B: return X86::COND_AE; 316 case X86::COND_BE: return X86::COND_A; 317 case X86::COND_A: return X86::COND_BE; 318 case X86::COND_AE: return X86::COND_B; 319 case X86::COND_S: return X86::COND_NS; 320 case X86::COND_NS: return X86::COND_S; 321 case X86::COND_P: return X86::COND_NP; 322 case X86::COND_NP: return X86::COND_P; 323 case X86::COND_O: return X86::COND_NO; 324 case X86::COND_NO: return X86::COND_O; 325 } 326} 327 328 329bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 330 MachineBasicBlock *&TBB, 331 MachineBasicBlock *&FBB, 332 std::vector<MachineOperand> &Cond) const { 333 // TODO: If FP_REG_KILL is around, ignore it. 334 335 // If the block has no terminators, it just falls into the block after it. 336 MachineBasicBlock::iterator I = MBB.end(); 337 if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) 338 return false; 339 340 // Get the last instruction in the block. 341 MachineInstr *LastInst = I; 342 343 // If there is only one terminator instruction, process it. 344 if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) { 345 if (!isBranch(LastInst->getOpcode())) 346 return true; 347 348 // If the block ends with a branch there are 3 possibilities: 349 // it's an unconditional, conditional, or indirect branch. 350 351 if (LastInst->getOpcode() == X86::JMP) { 352 TBB = LastInst->getOperand(0).getMachineBasicBlock(); 353 return false; 354 } 355 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 356 if (BranchCode == X86::COND_INVALID) 357 return true; // Can't handle indirect branch. 358 359 // Otherwise, block ends with fall-through condbranch. 360 TBB = LastInst->getOperand(0).getMachineBasicBlock(); 361 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 362 return false; 363 } 364 365 // Get the instruction before it if it's a terminator. 366 MachineInstr *SecondLastInst = I; 367 368 // If there are three terminators, we don't know what sort of block this is. 369 if (SecondLastInst && I != MBB.begin() && 370 isTerminatorInstr((--I)->getOpcode())) 371 return true; 372 373 // If the block ends with X86::JMP and a conditional branch, handle it. 374 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode()); 375 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) { 376 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock(); 377 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 378 FBB = LastInst->getOperand(0).getMachineBasicBlock(); 379 return false; 380 } 381 382 // Otherwise, can't handle this. 383 return true; 384} 385 386void X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 387 MachineBasicBlock::iterator I = MBB.end(); 388 if (I == MBB.begin()) return; 389 --I; 390 if (I->getOpcode() != X86::JMP && 391 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 392 return; 393 394 // Remove the branch. 395 I->eraseFromParent(); 396 397 I = MBB.end(); 398 399 if (I == MBB.begin()) return; 400 --I; 401 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 402 return; 403 404 // Remove the branch. 405 I->eraseFromParent(); 406} 407 408void X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 409 MachineBasicBlock *FBB, 410 const std::vector<MachineOperand> &Cond) const { 411 // Shouldn't be a fall through. 412 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 413 assert((Cond.size() == 1 || Cond.size() == 0) && 414 "X86 branch conditions have one component!"); 415 416 if (FBB == 0) { // One way branch. 417 if (Cond.empty()) { 418 // Unconditional branch? 419 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB); 420 } else { 421 // Conditional branch. 422 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); 423 BuildMI(&MBB, get(Opc)).addMBB(TBB); 424 } 425 return; 426 } 427 428 // Two-way Conditional branch. 429 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); 430 BuildMI(&MBB, get(Opc)).addMBB(TBB); 431 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB); 432} 433 434bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 435 if (MBB.empty()) return false; 436 437 switch (MBB.back().getOpcode()) { 438 case X86::JMP: // Uncond branch. 439 case X86::JMP32r: // Indirect branch. 440 case X86::JMP32m: // Indirect branch through mem. 441 return true; 442 default: return false; 443 } 444} 445 446bool X86InstrInfo:: 447ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 448 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 449 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm())); 450 return false; 451} 452 453const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const { 454 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 455 if (Subtarget->is64Bit()) 456 return &X86::GR64RegClass; 457 else 458 return &X86::GR32RegClass; 459} 460