X86InstrInfo.cpp revision 31e2c7b4c13c2f31774614b1124533628958d0cd 
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86GenInstrInfo.inc"
17#include "X86InstrBuilder.h"
18#include "X86MachineFunctionInfo.h"
19#include "X86Subtarget.h"
20#include "X86TargetMachine.h"
21#include "llvm/GlobalVariable.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/LLVMContext.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/LiveVariables.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/raw_ostream.h"
33#include "llvm/Target/TargetOptions.h"
34#include "llvm/MC/MCAsmInfo.h"
35using namespace llvm;
36
37static cl::opt<bool>
38NoFusing("disable-spill-fusing",
39         cl::desc("Disable fusing of spill code into instructions"));
40static cl::opt<bool>
41PrintFailedFusing("print-failed-fuse-candidates",
42                  cl::desc("Print instructions that the allocator wants to"
43                           " fuse, but the X86 backend currently can't"),
44                  cl::Hidden);
45static cl::opt<bool>
46ReMatPICStubLoad("remat-pic-stub-load",
47                 cl::desc("Re-materialize load from stub in PIC mode"),
48                 cl::init(false), cl::Hidden);
49
50X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
51  : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
52    TM(tm), RI(tm, *this) {
53  SmallVector<unsigned,16> AmbEntries;
54  static const unsigned OpTbl2Addr[][2] = {
55    { X86::ADC32ri,     X86::ADC32mi },
56    { X86::ADC32ri8,    X86::ADC32mi8 },
57    { X86::ADC32rr,     X86::ADC32mr },
58    { X86::ADC64ri32,   X86::ADC64mi32 },
59    { X86::ADC64ri8,    X86::ADC64mi8 },
60    { X86::ADC64rr,     X86::ADC64mr },
61    { X86::ADD16ri,     X86::ADD16mi },
62    { X86::ADD16ri8,    X86::ADD16mi8 },
63    { X86::ADD16rr,     X86::ADD16mr },
64    { X86::ADD32ri,     X86::ADD32mi },
65    { X86::ADD32ri8,    X86::ADD32mi8 },
66    { X86::ADD32rr,     X86::ADD32mr },
67    { X86::ADD64ri32,   X86::ADD64mi32 },
68    { X86::ADD64ri8,    X86::ADD64mi8 },
69    { X86::ADD64rr,     X86::ADD64mr },
70    { X86::ADD8ri,      X86::ADD8mi },
71    { X86::ADD8rr,      X86::ADD8mr },
72    { X86::AND16ri,     X86::AND16mi },
73    { X86::AND16ri8,    X86::AND16mi8 },
74    { X86::AND16rr,     X86::AND16mr },
75    { X86::AND32ri,     X86::AND32mi },
76    { X86::AND32ri8,    X86::AND32mi8 },
77    { X86::AND32rr,     X86::AND32mr },
78    { X86::AND64ri32,   X86::AND64mi32 },
79    { X86::AND64ri8,    X86::AND64mi8 },
80    { X86::AND64rr,     X86::AND64mr },
81    { X86::AND8ri,      X86::AND8mi },
82    { X86::AND8rr,      X86::AND8mr },
83    { X86::DEC16r,      X86::DEC16m },
84    { X86::DEC32r,      X86::DEC32m },
85    { X86::DEC64_16r,   X86::DEC64_16m },
86    { X86::DEC64_32r,   X86::DEC64_32m },
87    { X86::DEC64r,      X86::DEC64m },
88    { X86::DEC8r,       X86::DEC8m },
89    { X86::INC16r,      X86::INC16m },
90    { X86::INC32r,      X86::INC32m },
91    { X86::INC64_16r,   X86::INC64_16m },
92    { X86::INC64_32r,   X86::INC64_32m },
93    { X86::INC64r,      X86::INC64m },
94    { X86::INC8r,       X86::INC8m },
95    { X86::NEG16r,      X86::NEG16m },
96    { X86::NEG32r,      X86::NEG32m },
97    { X86::NEG64r,      X86::NEG64m },
98    { X86::NEG8r,       X86::NEG8m },
99    { X86::NOT16r,      X86::NOT16m },
100    { X86::NOT32r,      X86::NOT32m },
101    { X86::NOT64r,      X86::NOT64m },
102    { X86::NOT8r,       X86::NOT8m },
103    { X86::OR16ri,      X86::OR16mi },
104    { X86::OR16ri8,     X86::OR16mi8 },
105    { X86::OR16rr,      X86::OR16mr },
106    { X86::OR32ri,      X86::OR32mi },
107    { X86::OR32ri8,     X86::OR32mi8 },
108    { X86::OR32rr,      X86::OR32mr },
109    { X86::OR64ri32,    X86::OR64mi32 },
110    { X86::OR64ri8,     X86::OR64mi8 },
111    { X86::OR64rr,      X86::OR64mr },
112    { X86::OR8ri,       X86::OR8mi },
113    { X86::OR8rr,       X86::OR8mr },
114    { X86::ROL16r1,     X86::ROL16m1 },
115    { X86::ROL16rCL,    X86::ROL16mCL },
116    { X86::ROL16ri,     X86::ROL16mi },
117    { X86::ROL32r1,     X86::ROL32m1 },
118    { X86::ROL32rCL,    X86::ROL32mCL },
119    { X86::ROL32ri,     X86::ROL32mi },
120    { X86::ROL64r1,     X86::ROL64m1 },
121    { X86::ROL64rCL,    X86::ROL64mCL },
122    { X86::ROL64ri,     X86::ROL64mi },
123    { X86::ROL8r1,      X86::ROL8m1 },
124    { X86::ROL8rCL,     X86::ROL8mCL },
125    { X86::ROL8ri,      X86::ROL8mi },
126    { X86::ROR16r1,     X86::ROR16m1 },
127    { X86::ROR16rCL,    X86::ROR16mCL },
128    { X86::ROR16ri,     X86::ROR16mi },
129    { X86::ROR32r1,     X86::ROR32m1 },
130    { X86::ROR32rCL,    X86::ROR32mCL },
131    { X86::ROR32ri,     X86::ROR32mi },
132    { X86::ROR64r1,     X86::ROR64m1 },
133    { X86::ROR64rCL,    X86::ROR64mCL },
134    { X86::ROR64ri,     X86::ROR64mi },
135    { X86::ROR8r1,      X86::ROR8m1 },
136    { X86::ROR8rCL,     X86::ROR8mCL },
137    { X86::ROR8ri,      X86::ROR8mi },
138    { X86::SAR16r1,     X86::SAR16m1 },
139    { X86::SAR16rCL,    X86::SAR16mCL },
140    { X86::SAR16ri,     X86::SAR16mi },
141    { X86::SAR32r1,     X86::SAR32m1 },
142    { X86::SAR32rCL,    X86::SAR32mCL },
143    { X86::SAR32ri,     X86::SAR32mi },
144    { X86::SAR64r1,     X86::SAR64m1 },
145    { X86::SAR64rCL,    X86::SAR64mCL },
146    { X86::SAR64ri,     X86::SAR64mi },
147    { X86::SAR8r1,      X86::SAR8m1 },
148    { X86::SAR8rCL,     X86::SAR8mCL },
149    { X86::SAR8ri,      X86::SAR8mi },
150    { X86::SBB32ri,     X86::SBB32mi },
151    { X86::SBB32ri8,    X86::SBB32mi8 },
152    { X86::SBB32rr,     X86::SBB32mr },
153    { X86::SBB64ri32,   X86::SBB64mi32 },
154    { X86::SBB64ri8,    X86::SBB64mi8 },
155    { X86::SBB64rr,     X86::SBB64mr },
156    { X86::SHL16rCL,    X86::SHL16mCL },
157    { X86::SHL16ri,     X86::SHL16mi },
158    { X86::SHL32rCL,    X86::SHL32mCL },
159    { X86::SHL32ri,     X86::SHL32mi },
160    { X86::SHL64rCL,    X86::SHL64mCL },
161    { X86::SHL64ri,     X86::SHL64mi },
162    { X86::SHL8rCL,     X86::SHL8mCL },
163    { X86::SHL8ri,      X86::SHL8mi },
164    { X86::SHLD16rrCL,  X86::SHLD16mrCL },
165    { X86::SHLD16rri8,  X86::SHLD16mri8 },
166    { X86::SHLD32rrCL,  X86::SHLD32mrCL },
167    { X86::SHLD32rri8,  X86::SHLD32mri8 },
168    { X86::SHLD64rrCL,  X86::SHLD64mrCL },
169    { X86::SHLD64rri8,  X86::SHLD64mri8 },
170    { X86::SHR16r1,     X86::SHR16m1 },
171    { X86::SHR16rCL,    X86::SHR16mCL },
172    { X86::SHR16ri,     X86::SHR16mi },
173    { X86::SHR32r1,     X86::SHR32m1 },
174    { X86::SHR32rCL,    X86::SHR32mCL },
175    { X86::SHR32ri,     X86::SHR32mi },
176    { X86::SHR64r1,     X86::SHR64m1 },
177    { X86::SHR64rCL,    X86::SHR64mCL },
178    { X86::SHR64ri,     X86::SHR64mi },
179    { X86::SHR8r1,      X86::SHR8m1 },
180    { X86::SHR8rCL,     X86::SHR8mCL },
181    { X86::SHR8ri,      X86::SHR8mi },
182    { X86::SHRD16rrCL,  X86::SHRD16mrCL },
183    { X86::SHRD16rri8,  X86::SHRD16mri8 },
184    { X86::SHRD32rrCL,  X86::SHRD32mrCL },
185    { X86::SHRD32rri8,  X86::SHRD32mri8 },
186    { X86::SHRD64rrCL,  X86::SHRD64mrCL },
187    { X86::SHRD64rri8,  X86::SHRD64mri8 },
188    { X86::SUB16ri,     X86::SUB16mi },
189    { X86::SUB16ri8,    X86::SUB16mi8 },
190    { X86::SUB16rr,     X86::SUB16mr },
191    { X86::SUB32ri,     X86::SUB32mi },
192    { X86::SUB32ri8,    X86::SUB32mi8 },
193    { X86::SUB32rr,     X86::SUB32mr },
194    { X86::SUB64ri32,   X86::SUB64mi32 },
195    { X86::SUB64ri8,    X86::SUB64mi8 },
196    { X86::SUB64rr,     X86::SUB64mr },
197    { X86::SUB8ri,      X86::SUB8mi },
198    { X86::SUB8rr,      X86::SUB8mr },
199    { X86::XOR16ri,     X86::XOR16mi },
200    { X86::XOR16ri8,    X86::XOR16mi8 },
201    { X86::XOR16rr,     X86::XOR16mr },
202    { X86::XOR32ri,     X86::XOR32mi },
203    { X86::XOR32ri8,    X86::XOR32mi8 },
204    { X86::XOR32rr,     X86::XOR32mr },
205    { X86::XOR64ri32,   X86::XOR64mi32 },
206    { X86::XOR64ri8,    X86::XOR64mi8 },
207    { X86::XOR64rr,     X86::XOR64mr },
208    { X86::XOR8ri,      X86::XOR8mi },
209    { X86::XOR8rr,      X86::XOR8mr }
210  };
211
212  for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
213    unsigned RegOp = OpTbl2Addr[i][0];
214    unsigned MemOp = OpTbl2Addr[i][1];
215    if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
216                                               std::make_pair(MemOp,0))).second)
217      assert(false && "Duplicated entries?");
218    // Index 0, folded load and store, no alignment requirement.
219    unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
220    if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
221                                                std::make_pair(RegOp,
222                                                              AuxInfo))).second)
223      AmbEntries.push_back(MemOp);
224  }
225
226  // If the third value is 1, then it's folding either a load or a store.
227  static const unsigned OpTbl0[][4] = {
228    { X86::BT16ri8,     X86::BT16mi8, 1, 0 },
229    { X86::BT32ri8,     X86::BT32mi8, 1, 0 },
230    { X86::BT64ri8,     X86::BT64mi8, 1, 0 },
231    { X86::CALL32r,     X86::CALL32m, 1, 0 },
232    { X86::CALL64r,     X86::CALL64m, 1, 0 },
233    { X86::CMP16ri,     X86::CMP16mi, 1, 0 },
234    { X86::CMP16ri8,    X86::CMP16mi8, 1, 0 },
235    { X86::CMP16rr,     X86::CMP16mr, 1, 0 },
236    { X86::CMP32ri,     X86::CMP32mi, 1, 0 },
237    { X86::CMP32ri8,    X86::CMP32mi8, 1, 0 },
238    { X86::CMP32rr,     X86::CMP32mr, 1, 0 },
239    { X86::CMP64ri32,   X86::CMP64mi32, 1, 0 },
240    { X86::CMP64ri8,    X86::CMP64mi8, 1, 0 },
241    { X86::CMP64rr,     X86::CMP64mr, 1, 0 },
242    { X86::CMP8ri,      X86::CMP8mi, 1, 0 },
243    { X86::CMP8rr,      X86::CMP8mr, 1, 0 },
244    { X86::DIV16r,      X86::DIV16m, 1, 0 },
245    { X86::DIV32r,      X86::DIV32m, 1, 0 },
246    { X86::DIV64r,      X86::DIV64m, 1, 0 },
247    { X86::DIV8r,       X86::DIV8m, 1, 0 },
248    { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
249    { X86::FsMOVAPDrr,  X86::MOVSDmr, 0, 0 },
250    { X86::FsMOVAPSrr,  X86::MOVSSmr, 0, 0 },
251    { X86::IDIV16r,     X86::IDIV16m, 1, 0 },
252    { X86::IDIV32r,     X86::IDIV32m, 1, 0 },
253    { X86::IDIV64r,     X86::IDIV64m, 1, 0 },
254    { X86::IDIV8r,      X86::IDIV8m, 1, 0 },
255    { X86::IMUL16r,     X86::IMUL16m, 1, 0 },
256    { X86::IMUL32r,     X86::IMUL32m, 1, 0 },
257    { X86::IMUL64r,     X86::IMUL64m, 1, 0 },
258    { X86::IMUL8r,      X86::IMUL8m, 1, 0 },
259    { X86::JMP32r,      X86::JMP32m, 1, 0 },
260    { X86::JMP64r,      X86::JMP64m, 1, 0 },
261    { X86::MOV16ri,     X86::MOV16mi, 0, 0 },
262    { X86::MOV16rr,     X86::MOV16mr, 0, 0 },
263    { X86::MOV32ri,     X86::MOV32mi, 0, 0 },
264    { X86::MOV32rr,     X86::MOV32mr, 0, 0 },
265    { X86::MOV64ri32,   X86::MOV64mi32, 0, 0 },
266    { X86::MOV64rr,     X86::MOV64mr, 0, 0 },
267    { X86::MOV8ri,      X86::MOV8mi, 0, 0 },
268    { X86::MOV8rr,      X86::MOV8mr, 0, 0 },
269    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
270    { X86::MOVAPDrr,    X86::MOVAPDmr, 0, 16 },
271    { X86::MOVAPSrr,    X86::MOVAPSmr, 0, 16 },
272    { X86::MOVDQArr,    X86::MOVDQAmr, 0, 16 },
273    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
274    { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
275    { X86::MOVPS2SSrr,  X86::MOVPS2SSmr, 0, 0 },
276    { X86::MOVSDrr,     X86::MOVSDmr, 0, 0 },
277    { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
278    { X86::MOVSS2DIrr,  X86::MOVSS2DImr, 0, 0 },
279    { X86::MOVSSrr,     X86::MOVSSmr, 0, 0 },
280    { X86::MOVUPDrr,    X86::MOVUPDmr, 0, 0 },
281    { X86::MOVUPSrr,    X86::MOVUPSmr, 0, 0 },
282    { X86::MUL16r,      X86::MUL16m, 1, 0 },
283    { X86::MUL32r,      X86::MUL32m, 1, 0 },
284    { X86::MUL64r,      X86::MUL64m, 1, 0 },
285    { X86::MUL8r,       X86::MUL8m, 1, 0 },
286    { X86::SETAEr,      X86::SETAEm, 0, 0 },
287    { X86::SETAr,       X86::SETAm, 0, 0 },
288    { X86::SETBEr,      X86::SETBEm, 0, 0 },
289    { X86::SETBr,       X86::SETBm, 0, 0 },
290    { X86::SETEr,       X86::SETEm, 0, 0 },
291    { X86::SETGEr,      X86::SETGEm, 0, 0 },
292    { X86::SETGr,       X86::SETGm, 0, 0 },
293    { X86::SETLEr,      X86::SETLEm, 0, 0 },
294    { X86::SETLr,       X86::SETLm, 0, 0 },
295    { X86::SETNEr,      X86::SETNEm, 0, 0 },
296    { X86::SETNOr,      X86::SETNOm, 0, 0 },
297    { X86::SETNPr,      X86::SETNPm, 0, 0 },
298    { X86::SETNSr,      X86::SETNSm, 0, 0 },
299    { X86::SETOr,       X86::SETOm, 0, 0 },
300    { X86::SETPr,       X86::SETPm, 0, 0 },
301    { X86::SETSr,       X86::SETSm, 0, 0 },
302    { X86::TAILJMPr,    X86::TAILJMPm, 1, 0 },
303    { X86::TEST16ri,    X86::TEST16mi, 1, 0 },
304    { X86::TEST32ri,    X86::TEST32mi, 1, 0 },
305    { X86::TEST64ri32,  X86::TEST64mi32, 1, 0 },
306    { X86::TEST8ri,     X86::TEST8mi, 1, 0 }
307  };
308
309  for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
310    unsigned RegOp = OpTbl0[i][0];
311    unsigned MemOp = OpTbl0[i][1];
312    unsigned Align = OpTbl0[i][3];
313    if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
314                                           std::make_pair(MemOp,Align))).second)
315      assert(false && "Duplicated entries?");
316    unsigned FoldedLoad = OpTbl0[i][2];
317    // Index 0, folded load or store.
318    unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
319    if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
320      if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
321                                     std::make_pair(RegOp, AuxInfo))).second)
322        AmbEntries.push_back(MemOp);
323  }
324
325  static const unsigned OpTbl1[][3] = {
326    { X86::CMP16rr,         X86::CMP16rm, 0 },
327    { X86::CMP32rr,         X86::CMP32rm, 0 },
328    { X86::CMP64rr,         X86::CMP64rm, 0 },
329    { X86::CMP8rr,          X86::CMP8rm, 0 },
330    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm, 0 },
331    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm, 0 },
332    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm, 0 },
333    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm, 0 },
334    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm, 0 },
335    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm, 0 },
336    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm, 0 },
337    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm, 0 },
338    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm, 0 },
339    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm, 0 },
340    { X86::FsMOVAPDrr,      X86::MOVSDrm, 0 },
341    { X86::FsMOVAPSrr,      X86::MOVSSrm, 0 },
342    { X86::IMUL16rri,       X86::IMUL16rmi, 0 },
343    { X86::IMUL16rri8,      X86::IMUL16rmi8, 0 },
344    { X86::IMUL32rri,       X86::IMUL32rmi, 0 },
345    { X86::IMUL32rri8,      X86::IMUL32rmi8, 0 },
346    { X86::IMUL64rri32,     X86::IMUL64rmi32, 0 },
347    { X86::IMUL64rri8,      X86::IMUL64rmi8, 0 },
348    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm, 0 },
349    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm, 0 },
350    { X86::Int_COMISDrr,    X86::Int_COMISDrm, 0 },
351    { X86::Int_COMISSrr,    X86::Int_COMISSrm, 0 },
352    { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm, 16 },
353    { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm, 16 },
354    { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm, 16 },
355    { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm, 16 },
356    { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm, 16 },
357    { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm, 0 },
358    { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
359    { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm, 0 },
360    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm, 0 },
361    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
362    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm, 0 },
363    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
364    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm, 0 },
365    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm, 0 },
366    { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
367    { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm, 0 },
368    { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
369    { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
370    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
371    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
372    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
373    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
374    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm, 0 },
375    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm, 0 },
376    { X86::MOV16rr,         X86::MOV16rm, 0 },
377    { X86::MOV32rr,         X86::MOV32rm, 0 },
378    { X86::MOV64rr,         X86::MOV64rm, 0 },
379    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm, 0 },
380    { X86::MOV64toSDrr,     X86::MOV64toSDrm, 0 },
381    { X86::MOV8rr,          X86::MOV8rm, 0 },
382    { X86::MOVAPDrr,        X86::MOVAPDrm, 16 },
383    { X86::MOVAPSrr,        X86::MOVAPSrm, 16 },
384    { X86::MOVDDUPrr,       X86::MOVDDUPrm, 0 },
385    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm, 0 },
386    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm, 0 },
387    { X86::MOVDQArr,        X86::MOVDQArm, 16 },
388    { X86::MOVSD2PDrr,      X86::MOVSD2PDrm, 0 },
389    { X86::MOVSDrr,         X86::MOVSDrm, 0 },
390    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm, 16 },
391    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm, 16 },
392    { X86::MOVSS2PSrr,      X86::MOVSS2PSrm, 0 },
393    { X86::MOVSSrr,         X86::MOVSSrm, 0 },
394    { X86::MOVSX16rr8,      X86::MOVSX16rm8, 0 },
395    { X86::MOVSX32rr16,     X86::MOVSX32rm16, 0 },
396    { X86::MOVSX32rr8,      X86::MOVSX32rm8, 0 },
397    { X86::MOVSX64rr16,     X86::MOVSX64rm16, 0 },
398    { X86::MOVSX64rr32,     X86::MOVSX64rm32, 0 },
399    { X86::MOVSX64rr8,      X86::MOVSX64rm8, 0 },
400    { X86::MOVUPDrr,        X86::MOVUPDrm, 16 },
401    { X86::MOVUPSrr,        X86::MOVUPSrm, 16 },
402    { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm, 0 },
403    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm, 0 },
404    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
405    { X86::MOVZX16rr8,      X86::MOVZX16rm8, 0 },
406    { X86::MOVZX32rr16,     X86::MOVZX32rm16, 0 },
407    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
408    { X86::MOVZX32rr8,      X86::MOVZX32rm8, 0 },
409    { X86::MOVZX64rr16,     X86::MOVZX64rm16, 0 },
410    { X86::MOVZX64rr32,     X86::MOVZX64rm32, 0 },
411    { X86::MOVZX64rr8,      X86::MOVZX64rm8, 0 },
412    { X86::PSHUFDri,        X86::PSHUFDmi, 16 },
413    { X86::PSHUFHWri,       X86::PSHUFHWmi, 16 },
414    { X86::PSHUFLWri,       X86::PSHUFLWmi, 16 },
415    { X86::RCPPSr,          X86::RCPPSm, 16 },
416    { X86::RCPPSr_Int,      X86::RCPPSm_Int, 16 },
417    { X86::RSQRTPSr,        X86::RSQRTPSm, 16 },
418    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int, 16 },
419    { X86::RSQRTSSr,        X86::RSQRTSSm, 0 },
420    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int, 0 },
421    { X86::SQRTPDr,         X86::SQRTPDm, 16 },
422    { X86::SQRTPDr_Int,     X86::SQRTPDm_Int, 16 },
423    { X86::SQRTPSr,         X86::SQRTPSm, 16 },
424    { X86::SQRTPSr_Int,     X86::SQRTPSm_Int, 16 },
425    { X86::SQRTSDr,         X86::SQRTSDm, 0 },
426    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int, 0 },
427    { X86::SQRTSSr,         X86::SQRTSSm, 0 },
428    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int, 0 },
429    { X86::TEST16rr,        X86::TEST16rm, 0 },
430    { X86::TEST32rr,        X86::TEST32rm, 0 },
431    { X86::TEST64rr,        X86::TEST64rm, 0 },
432    { X86::TEST8rr,         X86::TEST8rm, 0 },
433    // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
434    { X86::UCOMISDrr,       X86::UCOMISDrm, 0 },
435    { X86::UCOMISSrr,       X86::UCOMISSrm, 0 }
436  };
437
438  for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
439    unsigned RegOp = OpTbl1[i][0];
440    unsigned MemOp = OpTbl1[i][1];
441    unsigned Align = OpTbl1[i][2];
442    if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
443                                           std::make_pair(MemOp,Align))).second)
444      assert(false && "Duplicated entries?");
445    // Index 1, folded load
446    unsigned AuxInfo = 1 | (1 << 4);
447    if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
448      if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
449                                     std::make_pair(RegOp, AuxInfo))).second)
450        AmbEntries.push_back(MemOp);
451  }
452
453  static const unsigned OpTbl2[][3] = {
454    { X86::ADC32rr,         X86::ADC32rm, 0 },
455    { X86::ADC64rr,         X86::ADC64rm, 0 },
456    { X86::ADD16rr,         X86::ADD16rm, 0 },
457    { X86::ADD32rr,         X86::ADD32rm, 0 },
458    { X86::ADD64rr,         X86::ADD64rm, 0 },
459    { X86::ADD8rr,          X86::ADD8rm, 0 },
460    { X86::ADDPDrr,         X86::ADDPDrm, 16 },
461    { X86::ADDPSrr,         X86::ADDPSrm, 16 },
462    { X86::ADDSDrr,         X86::ADDSDrm, 0 },
463    { X86::ADDSSrr,         X86::ADDSSrm, 0 },
464    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm, 16 },
465    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm, 16 },
466    { X86::AND16rr,         X86::AND16rm, 0 },
467    { X86::AND32rr,         X86::AND32rm, 0 },
468    { X86::AND64rr,         X86::AND64rm, 0 },
469    { X86::AND8rr,          X86::AND8rm, 0 },
470    { X86::ANDNPDrr,        X86::ANDNPDrm, 16 },
471    { X86::ANDNPSrr,        X86::ANDNPSrm, 16 },
472    { X86::ANDPDrr,         X86::ANDPDrm, 16 },
473    { X86::ANDPSrr,         X86::ANDPSrm, 16 },
474    { X86::CMOVA16rr,       X86::CMOVA16rm, 0 },
475    { X86::CMOVA32rr,       X86::CMOVA32rm, 0 },
476    { X86::CMOVA64rr,       X86::CMOVA64rm, 0 },
477    { X86::CMOVAE16rr,      X86::CMOVAE16rm, 0 },
478    { X86::CMOVAE32rr,      X86::CMOVAE32rm, 0 },
479    { X86::CMOVAE64rr,      X86::CMOVAE64rm, 0 },
480    { X86::CMOVB16rr,       X86::CMOVB16rm, 0 },
481    { X86::CMOVB32rr,       X86::CMOVB32rm, 0 },
482    { X86::CMOVB64rr,       X86::CMOVB64rm, 0 },
483    { X86::CMOVBE16rr,      X86::CMOVBE16rm, 0 },
484    { X86::CMOVBE32rr,      X86::CMOVBE32rm, 0 },
485    { X86::CMOVBE64rr,      X86::CMOVBE64rm, 0 },
486    { X86::CMOVE16rr,       X86::CMOVE16rm, 0 },
487    { X86::CMOVE32rr,       X86::CMOVE32rm, 0 },
488    { X86::CMOVE64rr,       X86::CMOVE64rm, 0 },
489    { X86::CMOVG16rr,       X86::CMOVG16rm, 0 },
490    { X86::CMOVG32rr,       X86::CMOVG32rm, 0 },
491    { X86::CMOVG64rr,       X86::CMOVG64rm, 0 },
492    { X86::CMOVGE16rr,      X86::CMOVGE16rm, 0 },
493    { X86::CMOVGE32rr,      X86::CMOVGE32rm, 0 },
494    { X86::CMOVGE64rr,      X86::CMOVGE64rm, 0 },
495    { X86::CMOVL16rr,       X86::CMOVL16rm, 0 },
496    { X86::CMOVL32rr,       X86::CMOVL32rm, 0 },
497    { X86::CMOVL64rr,       X86::CMOVL64rm, 0 },
498    { X86::CMOVLE16rr,      X86::CMOVLE16rm, 0 },
499    { X86::CMOVLE32rr,      X86::CMOVLE32rm, 0 },
500    { X86::CMOVLE64rr,      X86::CMOVLE64rm, 0 },
501    { X86::CMOVNE16rr,      X86::CMOVNE16rm, 0 },
502    { X86::CMOVNE32rr,      X86::CMOVNE32rm, 0 },
503    { X86::CMOVNE64rr,      X86::CMOVNE64rm, 0 },
504    { X86::CMOVNO16rr,      X86::CMOVNO16rm, 0 },
505    { X86::CMOVNO32rr,      X86::CMOVNO32rm, 0 },
506    { X86::CMOVNO64rr,      X86::CMOVNO64rm, 0 },
507    { X86::CMOVNP16rr,      X86::CMOVNP16rm, 0 },
508    { X86::CMOVNP32rr,      X86::CMOVNP32rm, 0 },
509    { X86::CMOVNP64rr,      X86::CMOVNP64rm, 0 },
510    { X86::CMOVNS16rr,      X86::CMOVNS16rm, 0 },
511    { X86::CMOVNS32rr,      X86::CMOVNS32rm, 0 },
512    { X86::CMOVNS64rr,      X86::CMOVNS64rm, 0 },
513    { X86::CMOVO16rr,       X86::CMOVO16rm, 0 },
514    { X86::CMOVO32rr,       X86::CMOVO32rm, 0 },
515    { X86::CMOVO64rr,       X86::CMOVO64rm, 0 },
516    { X86::CMOVP16rr,       X86::CMOVP16rm, 0 },
517    { X86::CMOVP32rr,       X86::CMOVP32rm, 0 },
518    { X86::CMOVP64rr,       X86::CMOVP64rm, 0 },
519    { X86::CMOVS16rr,       X86::CMOVS16rm, 0 },
520    { X86::CMOVS32rr,       X86::CMOVS32rm, 0 },
521    { X86::CMOVS64rr,       X86::CMOVS64rm, 0 },
522    { X86::CMPPDrri,        X86::CMPPDrmi, 16 },
523    { X86::CMPPSrri,        X86::CMPPSrmi, 16 },
524    { X86::CMPSDrr,         X86::CMPSDrm, 0 },
525    { X86::CMPSSrr,         X86::CMPSSrm, 0 },
526    { X86::DIVPDrr,         X86::DIVPDrm, 16 },
527    { X86::DIVPSrr,         X86::DIVPSrm, 16 },
528    { X86::DIVSDrr,         X86::DIVSDrm, 0 },
529    { X86::DIVSSrr,         X86::DIVSSrm, 0 },
530    { X86::FsANDNPDrr,      X86::FsANDNPDrm, 16 },
531    { X86::FsANDNPSrr,      X86::FsANDNPSrm, 16 },
532    { X86::FsANDPDrr,       X86::FsANDPDrm, 16 },
533    { X86::FsANDPSrr,       X86::FsANDPSrm, 16 },
534    { X86::FsORPDrr,        X86::FsORPDrm, 16 },
535    { X86::FsORPSrr,        X86::FsORPSrm, 16 },
536    { X86::FsXORPDrr,       X86::FsXORPDrm, 16 },
537    { X86::FsXORPSrr,       X86::FsXORPSrm, 16 },
538    { X86::HADDPDrr,        X86::HADDPDrm, 16 },
539    { X86::HADDPSrr,        X86::HADDPSrm, 16 },
540    { X86::HSUBPDrr,        X86::HSUBPDrm, 16 },
541    { X86::HSUBPSrr,        X86::HSUBPSrm, 16 },
542    { X86::IMUL16rr,        X86::IMUL16rm, 0 },
543    { X86::IMUL32rr,        X86::IMUL32rm, 0 },
544    { X86::IMUL64rr,        X86::IMUL64rm, 0 },
545    { X86::MAXPDrr,         X86::MAXPDrm, 16 },
546    { X86::MAXPDrr_Int,     X86::MAXPDrm_Int, 16 },
547    { X86::MAXPSrr,         X86::MAXPSrm, 16 },
548    { X86::MAXPSrr_Int,     X86::MAXPSrm_Int, 16 },
549    { X86::MAXSDrr,         X86::MAXSDrm, 0 },
550    { X86::MAXSDrr_Int,     X86::MAXSDrm_Int, 0 },
551    { X86::MAXSSrr,         X86::MAXSSrm, 0 },
552    { X86::MAXSSrr_Int,     X86::MAXSSrm_Int, 0 },
553    { X86::MINPDrr,         X86::MINPDrm, 16 },
554    { X86::MINPDrr_Int,     X86::MINPDrm_Int, 16 },
555    { X86::MINPSrr,         X86::MINPSrm, 16 },
556    { X86::MINPSrr_Int,     X86::MINPSrm_Int, 16 },
557    { X86::MINSDrr,         X86::MINSDrm, 0 },
558    { X86::MINSDrr_Int,     X86::MINSDrm_Int, 0 },
559    { X86::MINSSrr,         X86::MINSSrm, 0 },
560    { X86::MINSSrr_Int,     X86::MINSSrm_Int, 0 },
561    { X86::MULPDrr,         X86::MULPDrm, 16 },
562    { X86::MULPSrr,         X86::MULPSrm, 16 },
563    { X86::MULSDrr,         X86::MULSDrm, 0 },
564    { X86::MULSSrr,         X86::MULSSrm, 0 },
565    { X86::OR16rr,          X86::OR16rm, 0 },
566    { X86::OR32rr,          X86::OR32rm, 0 },
567    { X86::OR64rr,          X86::OR64rm, 0 },
568    { X86::OR8rr,           X86::OR8rm, 0 },
569    { X86::ORPDrr,          X86::ORPDrm, 16 },
570    { X86::ORPSrr,          X86::ORPSrm, 16 },
571    { X86::PACKSSDWrr,      X86::PACKSSDWrm, 16 },
572    { X86::PACKSSWBrr,      X86::PACKSSWBrm, 16 },
573    { X86::PACKUSWBrr,      X86::PACKUSWBrm, 16 },
574    { X86::PADDBrr,         X86::PADDBrm, 16 },
575    { X86::PADDDrr,         X86::PADDDrm, 16 },
576    { X86::PADDQrr,         X86::PADDQrm, 16 },
577    { X86::PADDSBrr,        X86::PADDSBrm, 16 },
578    { X86::PADDSWrr,        X86::PADDSWrm, 16 },
579    { X86::PADDWrr,         X86::PADDWrm, 16 },
580    { X86::PANDNrr,         X86::PANDNrm, 16 },
581    { X86::PANDrr,          X86::PANDrm, 16 },
582    { X86::PAVGBrr,         X86::PAVGBrm, 16 },
583    { X86::PAVGWrr,         X86::PAVGWrm, 16 },
584    { X86::PCMPEQBrr,       X86::PCMPEQBrm, 16 },
585    { X86::PCMPEQDrr,       X86::PCMPEQDrm, 16 },
586    { X86::PCMPEQWrr,       X86::PCMPEQWrm, 16 },
587    { X86::PCMPGTBrr,       X86::PCMPGTBrm, 16 },
588    { X86::PCMPGTDrr,       X86::PCMPGTDrm, 16 },
589    { X86::PCMPGTWrr,       X86::PCMPGTWrm, 16 },
590    { X86::PINSRWrri,       X86::PINSRWrmi, 16 },
591    { X86::PMADDWDrr,       X86::PMADDWDrm, 16 },
592    { X86::PMAXSWrr,        X86::PMAXSWrm, 16 },
593    { X86::PMAXUBrr,        X86::PMAXUBrm, 16 },
594    { X86::PMINSWrr,        X86::PMINSWrm, 16 },
595    { X86::PMINUBrr,        X86::PMINUBrm, 16 },
596    { X86::PMULDQrr,        X86::PMULDQrm, 16 },
597    { X86::PMULHUWrr,       X86::PMULHUWrm, 16 },
598    { X86::PMULHWrr,        X86::PMULHWrm, 16 },
599    { X86::PMULLDrr,        X86::PMULLDrm, 16 },
600    { X86::PMULLDrr_int,    X86::PMULLDrm_int, 16 },
601    { X86::PMULLWrr,        X86::PMULLWrm, 16 },
602    { X86::PMULUDQrr,       X86::PMULUDQrm, 16 },
603    { X86::PORrr,           X86::PORrm, 16 },
604    { X86::PSADBWrr,        X86::PSADBWrm, 16 },
605    { X86::PSLLDrr,         X86::PSLLDrm, 16 },
606    { X86::PSLLQrr,         X86::PSLLQrm, 16 },
607    { X86::PSLLWrr,         X86::PSLLWrm, 16 },
608    { X86::PSRADrr,         X86::PSRADrm, 16 },
609    { X86::PSRAWrr,         X86::PSRAWrm, 16 },
610    { X86::PSRLDrr,         X86::PSRLDrm, 16 },
611    { X86::PSRLQrr,         X86::PSRLQrm, 16 },
612    { X86::PSRLWrr,         X86::PSRLWrm, 16 },
613    { X86::PSUBBrr,         X86::PSUBBrm, 16 },
614    { X86::PSUBDrr,         X86::PSUBDrm, 16 },
615    { X86::PSUBSBrr,        X86::PSUBSBrm, 16 },
616    { X86::PSUBSWrr,        X86::PSUBSWrm, 16 },
617    { X86::PSUBWrr,         X86::PSUBWrm, 16 },
618    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm, 16 },
619    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm, 16 },
620    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm, 16 },
621    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm, 16 },
622    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm, 16 },
623    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm, 16 },
624    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm, 16 },
625    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm, 16 },
626    { X86::PXORrr,          X86::PXORrm, 16 },
627    { X86::SBB32rr,         X86::SBB32rm, 0 },
628    { X86::SBB64rr,         X86::SBB64rm, 0 },
629    { X86::SHUFPDrri,       X86::SHUFPDrmi, 16 },
630    { X86::SHUFPSrri,       X86::SHUFPSrmi, 16 },
631    { X86::SUB16rr,         X86::SUB16rm, 0 },
632    { X86::SUB32rr,         X86::SUB32rm, 0 },
633    { X86::SUB64rr,         X86::SUB64rm, 0 },
634    { X86::SUB8rr,          X86::SUB8rm, 0 },
635    { X86::SUBPDrr,         X86::SUBPDrm, 16 },
636    { X86::SUBPSrr,         X86::SUBPSrm, 16 },
637    { X86::SUBSDrr,         X86::SUBSDrm, 0 },
638    { X86::SUBSSrr,         X86::SUBSSrm, 0 },
639    // FIXME: TEST*rr -> swapped operand of TEST*mr.
640    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm, 16 },
641    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm, 16 },
642    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm, 16 },
643    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm, 16 },
644    { X86::XOR16rr,         X86::XOR16rm, 0 },
645    { X86::XOR32rr,         X86::XOR32rm, 0 },
646    { X86::XOR64rr,         X86::XOR64rm, 0 },
647    { X86::XOR8rr,          X86::XOR8rm, 0 },
648    { X86::XORPDrr,         X86::XORPDrm, 16 },
649    { X86::XORPSrr,         X86::XORPSrm, 16 }
650  };
651
652  for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
653    unsigned RegOp = OpTbl2[i][0];
654    unsigned MemOp = OpTbl2[i][1];
655    unsigned Align = OpTbl2[i][2];
656    if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
657                                           std::make_pair(MemOp,Align))).second)
658      assert(false && "Duplicated entries?");
659    // Index 2, folded load
660    unsigned AuxInfo = 2 | (1 << 4);
661    if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
662                                   std::make_pair(RegOp, AuxInfo))).second)
663      AmbEntries.push_back(MemOp);
664  }
665
666  // Remove ambiguous entries.
667  assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
668}
669
670bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
671                               unsigned &SrcReg, unsigned &DstReg,
672                               unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
673  switch (MI.getOpcode()) {
674  default:
675    return false;
676  case X86::MOV8rr:
677  case X86::MOV8rr_NOREX:
678  case X86::MOV16rr:
679  case X86::MOV32rr:
680  case X86::MOV64rr:
681  case X86::MOVSSrr:
682  case X86::MOVSDrr:
683
684  // FP Stack register class copies
685  case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
686  case X86::MOV_Fp3264: case X86::MOV_Fp3280:
687  case X86::MOV_Fp6432: case X86::MOV_Fp8032:
688
689  case X86::FsMOVAPSrr:
690  case X86::FsMOVAPDrr:
691  case X86::MOVAPSrr:
692  case X86::MOVAPDrr:
693  case X86::MOVDQArr:
694  case X86::MOVSS2PSrr:
695  case X86::MOVSD2PDrr:
696  case X86::MOVPS2SSrr:
697  case X86::MOVPD2SDrr:
698  case X86::MMX_MOVQ64rr:
699    assert(MI.getNumOperands() >= 2 &&
700           MI.getOperand(0).isReg() &&
701           MI.getOperand(1).isReg() &&
702           "invalid register-register move instruction");
703    SrcReg = MI.getOperand(1).getReg();
704    DstReg = MI.getOperand(0).getReg();
705    SrcSubIdx = MI.getOperand(1).getSubReg();
706    DstSubIdx = MI.getOperand(0).getSubReg();
707    return true;
708  }
709}
710
711unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
712                                           int &FrameIndex) const {
713  switch (MI->getOpcode()) {
714  default: break;
715  case X86::MOV8rm:
716  case X86::MOV16rm:
717  case X86::MOV32rm:
718  case X86::MOV64rm:
719  case X86::LD_Fp64m:
720  case X86::MOVSSrm:
721  case X86::MOVSDrm:
722  case X86::MOVAPSrm:
723  case X86::MOVAPDrm:
724  case X86::MOVDQArm:
725  case X86::MMX_MOVD64rm:
726  case X86::MMX_MOVQ64rm:
727    if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
728        MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
729        MI->getOperand(2).getImm() == 1 &&
730        MI->getOperand(3).getReg() == 0 &&
731        MI->getOperand(4).getImm() == 0) {
732      FrameIndex = MI->getOperand(1).getIndex();
733      return MI->getOperand(0).getReg();
734    }
735    break;
736  }
737  return 0;
738}
739
740unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
741                                          int &FrameIndex) const {
742  switch (MI->getOpcode()) {
743  default: break;
744  case X86::MOV8mr:
745  case X86::MOV16mr:
746  case X86::MOV32mr:
747  case X86::MOV64mr:
748  case X86::ST_FpP64m:
749  case X86::MOVSSmr:
750  case X86::MOVSDmr:
751  case X86::MOVAPSmr:
752  case X86::MOVAPDmr:
753  case X86::MOVDQAmr:
754  case X86::MMX_MOVD64mr:
755  case X86::MMX_MOVQ64mr:
756  case X86::MMX_MOVNTQmr:
757    if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
758        MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
759        MI->getOperand(1).getImm() == 1 &&
760        MI->getOperand(2).getReg() == 0 &&
761        MI->getOperand(3).getImm() == 0) {
762      FrameIndex = MI->getOperand(0).getIndex();
763      return MI->getOperand(X86AddrNumOperands).getReg();
764    }
765    break;
766  }
767  return 0;
768}
769
770/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
771/// X86::MOVPC32r.
772static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
773  bool isPICBase = false;
774  for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
775         E = MRI.def_end(); I != E; ++I) {
776    MachineInstr *DefMI = I.getOperand().getParent();
777    if (DefMI->getOpcode() != X86::MOVPC32r)
778      return false;
779    assert(!isPICBase && "More than one PIC base?");
780    isPICBase = true;
781  }
782  return isPICBase;
783}
784
785/// CanRematLoadWithDispOperand - Return true if a load with the specified
786/// operand is a candidate for remat: for this to be true we need to know that
787/// the load will always return the same value, even if moved.
788static bool CanRematLoadWithDispOperand(const MachineOperand &MO,
789                                        X86TargetMachine &TM) {
790  // Loads from constant pool entries can be remat'd.
791  if (MO.isCPI()) return true;
792
793  // We can remat globals in some cases.
794  if (MO.isGlobal()) {
795    // If this is a load of a stub, not of the global, we can remat it.  This
796    // access will always return the address of the global.
797    if (isGlobalStubReference(MO.getTargetFlags()))
798      return true;
799
800    // If the global itself is constant, we can remat the load.
801    if (GlobalVariable *GV = dyn_cast<GlobalVariable>(MO.getGlobal()))
802      if (GV->isConstant())
803        return true;
804  }
805  return false;
806}
807
808bool
809X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
810  switch (MI->getOpcode()) {
811  default: break;
812    case X86::MOV8rm:
813    case X86::MOV16rm:
814    case X86::MOV32rm:
815    case X86::MOV64rm:
816    case X86::LD_Fp64m:
817    case X86::MOVSSrm:
818    case X86::MOVSDrm:
819    case X86::MOVAPSrm:
820    case X86::MOVAPDrm:
821    case X86::MOVDQArm:
822    case X86::MMX_MOVD64rm:
823    case X86::MMX_MOVQ64rm: {
824      // Loads from constant pools are trivially rematerializable.
825      if (MI->getOperand(1).isReg() &&
826          MI->getOperand(2).isImm() &&
827          MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
828          CanRematLoadWithDispOperand(MI->getOperand(4), TM)) {
829        unsigned BaseReg = MI->getOperand(1).getReg();
830        if (BaseReg == 0 || BaseReg == X86::RIP)
831          return true;
832        // Allow re-materialization of PIC load.
833        if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
834          return false;
835        const MachineFunction &MF = *MI->getParent()->getParent();
836        const MachineRegisterInfo &MRI = MF.getRegInfo();
837        bool isPICBase = false;
838        for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
839               E = MRI.def_end(); I != E; ++I) {
840          MachineInstr *DefMI = I.getOperand().getParent();
841          if (DefMI->getOpcode() != X86::MOVPC32r)
842            return false;
843          assert(!isPICBase && "More than one PIC base?");
844          isPICBase = true;
845        }
846        return isPICBase;
847      }
848      return false;
849    }
850
851     case X86::LEA32r:
852     case X86::LEA64r: {
853       if (MI->getOperand(2).isImm() &&
854           MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
855           !MI->getOperand(4).isReg()) {
856         // lea fi#, lea GV, etc. are all rematerializable.
857         if (!MI->getOperand(1).isReg())
858           return true;
859         unsigned BaseReg = MI->getOperand(1).getReg();
860         if (BaseReg == 0)
861           return true;
862         // Allow re-materialization of lea PICBase + x.
863         const MachineFunction &MF = *MI->getParent()->getParent();
864         const MachineRegisterInfo &MRI = MF.getRegInfo();
865         return regIsPICBase(BaseReg, MRI);
866       }
867       return false;
868     }
869  }
870
871  // All other instructions marked M_REMATERIALIZABLE are always trivially
872  // rematerializable.
873  return true;
874}
875
876/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
877/// would clobber the EFLAGS condition register. Note the result may be
878/// conservative. If it cannot definitely determine the safety after visiting
879/// two instructions it assumes it's not safe.
880static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
881                                  MachineBasicBlock::iterator I) {
882  // It's always safe to clobber EFLAGS at the end of a block.
883  if (I == MBB.end())
884    return true;
885
886  // For compile time consideration, if we are not able to determine the
887  // safety after visiting 2 instructions, we will assume it's not safe.
888  for (unsigned i = 0; i < 2; ++i) {
889    bool SeenDef = false;
890    for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
891      MachineOperand &MO = I->getOperand(j);
892      if (!MO.isReg())
893        continue;
894      if (MO.getReg() == X86::EFLAGS) {
895        if (MO.isUse())
896          return false;
897        SeenDef = true;
898      }
899    }
900
901    if (SeenDef)
902      // This instruction defines EFLAGS, no need to look any further.
903      return true;
904    ++I;
905
906    // If we make it to the end of the block, it's safe to clobber EFLAGS.
907    if (I == MBB.end())
908      return true;
909  }
910
911  // Conservative answer.
912  return false;
913}
914
915void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
916                                 MachineBasicBlock::iterator I,
917                                 unsigned DestReg, unsigned SubIdx,
918                                 const MachineInstr *Orig) const {
919  DebugLoc DL = DebugLoc::getUnknownLoc();
920  if (I != MBB.end()) DL = I->getDebugLoc();
921
922  if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
923    DestReg = RI.getSubReg(DestReg, SubIdx);
924    SubIdx = 0;
925  }
926
927  // MOV32r0 etc. are implemented with xor which clobbers condition code.
928  // Re-materialize them as movri instructions to avoid side effects.
929  bool Clone = true;
930  unsigned Opc = Orig->getOpcode();
931  switch (Opc) {
932  default: break;
933  case X86::MOV8r0:
934  case X86::MOV16r0:
935  case X86::MOV32r0: {
936    if (!isSafeToClobberEFLAGS(MBB, I)) {
937      switch (Opc) {
938      default: break;
939      case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
940      case X86::MOV16r0: Opc = X86::MOV16ri; break;
941      case X86::MOV32r0: Opc = X86::MOV32ri; break;
942      }
943      Clone = false;
944    }
945    break;
946  }
947  }
948
949  if (Clone) {
950    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
951    MI->getOperand(0).setReg(DestReg);
952    MBB.insert(I, MI);
953  } else {
954    BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
955  }
956
957  MachineInstr *NewMI = prior(I);
958  NewMI->getOperand(0).setSubReg(SubIdx);
959}
960
961/// isInvariantLoad - Return true if the specified instruction (which is marked
962/// mayLoad) is loading from a location whose value is invariant across the
963/// function.  For example, loading a value from the constant pool or from
964/// from the argument area of a function if it does not change.  This should
965/// only return true of *all* loads the instruction does are invariant (if it
966/// does multiple loads).
967bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const {
968  // This code cares about loads from three cases: constant pool entries,
969  // invariant argument slots, and global stubs.  In order to handle these cases
970  // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
971  // operand and base our analysis on it.  This is safe because the address of
972  // none of these three cases is ever used as anything other than a load base
973  // and X86 doesn't have any instructions that load from multiple places.
974
975  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
976    const MachineOperand &MO = MI->getOperand(i);
977    // Loads from constant pools are trivially invariant.
978    if (MO.isCPI())
979      return true;
980
981    if (MO.isGlobal())
982      return isGlobalStubReference(MO.getTargetFlags());
983
984    // If this is a load from an invariant stack slot, the load is a constant.
985    if (MO.isFI()) {
986      const MachineFrameInfo &MFI =
987        *MI->getParent()->getParent()->getFrameInfo();
988      int Idx = MO.getIndex();
989      return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
990    }
991  }
992
993  // All other instances of these instructions are presumed to have other
994  // issues.
995  return false;
996}
997
998/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
999/// is not marked dead.
1000static bool hasLiveCondCodeDef(MachineInstr *MI) {
1001  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1002    MachineOperand &MO = MI->getOperand(i);
1003    if (MO.isReg() && MO.isDef() &&
1004        MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1005      return true;
1006    }
1007  }
1008  return false;
1009}
1010
1011/// convertToThreeAddress - This method must be implemented by targets that
1012/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1013/// may be able to convert a two-address instruction into a true
1014/// three-address instruction on demand.  This allows the X86 target (for
1015/// example) to convert ADD and SHL instructions into LEA instructions if they
1016/// would require register copies due to two-addressness.
1017///
1018/// This method returns a null pointer if the transformation cannot be
1019/// performed, otherwise it returns the new instruction.
1020///
1021MachineInstr *
1022X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1023                                    MachineBasicBlock::iterator &MBBI,
1024                                    LiveVariables *LV) const {
1025  MachineInstr *MI = MBBI;
1026  MachineFunction &MF = *MI->getParent()->getParent();
1027  // All instructions input are two-addr instructions.  Get the known operands.
1028  unsigned Dest = MI->getOperand(0).getReg();
1029  unsigned Src = MI->getOperand(1).getReg();
1030  bool isDead = MI->getOperand(0).isDead();
1031  bool isKill = MI->getOperand(1).isKill();
1032
1033  MachineInstr *NewMI = NULL;
1034  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
1035  // we have better subtarget support, enable the 16-bit LEA generation here.
1036  bool DisableLEA16 = true;
1037
1038  unsigned MIOpc = MI->getOpcode();
1039  switch (MIOpc) {
1040  case X86::SHUFPSrri: {
1041    assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1042    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1043
1044    unsigned B = MI->getOperand(1).getReg();
1045    unsigned C = MI->getOperand(2).getReg();
1046    if (B != C) return 0;
1047    unsigned A = MI->getOperand(0).getReg();
1048    unsigned M = MI->getOperand(3).getImm();
1049    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1050      .addReg(A, RegState::Define | getDeadRegState(isDead))
1051      .addReg(B, getKillRegState(isKill)).addImm(M);
1052    break;
1053  }
1054  case X86::SHL64ri: {
1055    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1056    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1057    // the flags produced by a shift yet, so this is safe.
1058    unsigned ShAmt = MI->getOperand(2).getImm();
1059    if (ShAmt == 0 || ShAmt >= 4) return 0;
1060
1061    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1062      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1063      .addReg(0).addImm(1 << ShAmt)
1064      .addReg(Src, getKillRegState(isKill))
1065      .addImm(0);
1066    break;
1067  }
1068  case X86::SHL32ri: {
1069    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1070    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1071    // the flags produced by a shift yet, so this is safe.
1072    unsigned ShAmt = MI->getOperand(2).getImm();
1073    if (ShAmt == 0 || ShAmt >= 4) return 0;
1074
1075    unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1076      X86::LEA64_32r : X86::LEA32r;
1077    NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1078      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1079      .addReg(0).addImm(1 << ShAmt)
1080      .addReg(Src, getKillRegState(isKill)).addImm(0);
1081    break;
1082  }
1083  case X86::SHL16ri: {
1084    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1085    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1086    // the flags produced by a shift yet, so this is safe.
1087    unsigned ShAmt = MI->getOperand(2).getImm();
1088    if (ShAmt == 0 || ShAmt >= 4) return 0;
1089
1090    if (DisableLEA16) {
1091      // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1092      MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1093      unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1094        ? X86::LEA64_32r : X86::LEA32r;
1095      unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1096      unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1097
1098      // Build and insert into an implicit UNDEF value. This is OK because
1099      // well be shifting and then extracting the lower 16-bits.
1100      BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1101      MachineInstr *InsMI =
1102        BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1103        .addReg(leaInReg)
1104        .addReg(Src, getKillRegState(isKill))
1105        .addImm(X86::SUBREG_16BIT);
1106
1107      NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1108        .addReg(0).addImm(1 << ShAmt)
1109        .addReg(leaInReg, RegState::Kill)
1110        .addImm(0);
1111
1112      MachineInstr *ExtMI =
1113        BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1114        .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1115        .addReg(leaOutReg, RegState::Kill)
1116        .addImm(X86::SUBREG_16BIT);
1117
1118      if (LV) {
1119        // Update live variables
1120        LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1121        LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1122        if (isKill)
1123          LV->replaceKillInstruction(Src, MI, InsMI);
1124        if (isDead)
1125          LV->replaceKillInstruction(Dest, MI, ExtMI);
1126      }
1127      return ExtMI;
1128    } else {
1129      NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1130        .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1131        .addReg(0).addImm(1 << ShAmt)
1132        .addReg(Src, getKillRegState(isKill))
1133        .addImm(0);
1134    }
1135    break;
1136  }
1137  default: {
1138    // The following opcodes also sets the condition code register(s). Only
1139    // convert them to equivalent lea if the condition code register def's
1140    // are dead!
1141    if (hasLiveCondCodeDef(MI))
1142      return 0;
1143
1144    bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1145    switch (MIOpc) {
1146    default: return 0;
1147    case X86::INC64r:
1148    case X86::INC32r:
1149    case X86::INC64_32r: {
1150      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1151      unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1152        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1153      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1154                              .addReg(Dest, RegState::Define |
1155                                      getDeadRegState(isDead)),
1156                              Src, isKill, 1);
1157      break;
1158    }
1159    case X86::INC16r:
1160    case X86::INC64_16r:
1161      if (DisableLEA16) return 0;
1162      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1163      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1164                           .addReg(Dest, RegState::Define |
1165                                   getDeadRegState(isDead)),
1166                           Src, isKill, 1);
1167      break;
1168    case X86::DEC64r:
1169    case X86::DEC32r:
1170    case X86::DEC64_32r: {
1171      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1172      unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1173        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1174      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1175                              .addReg(Dest, RegState::Define |
1176                                      getDeadRegState(isDead)),
1177                              Src, isKill, -1);
1178      break;
1179    }
1180    case X86::DEC16r:
1181    case X86::DEC64_16r:
1182      if (DisableLEA16) return 0;
1183      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1184      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1185                           .addReg(Dest, RegState::Define |
1186                                   getDeadRegState(isDead)),
1187                           Src, isKill, -1);
1188      break;
1189    case X86::ADD64rr:
1190    case X86::ADD32rr: {
1191      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1192      unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1193        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1194      unsigned Src2 = MI->getOperand(2).getReg();
1195      bool isKill2 = MI->getOperand(2).isKill();
1196      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1197                        .addReg(Dest, RegState::Define |
1198                                getDeadRegState(isDead)),
1199                        Src, isKill, Src2, isKill2);
1200      if (LV && isKill2)
1201        LV->replaceKillInstruction(Src2, MI, NewMI);
1202      break;
1203    }
1204    case X86::ADD16rr: {
1205      if (DisableLEA16) return 0;
1206      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1207      unsigned Src2 = MI->getOperand(2).getReg();
1208      bool isKill2 = MI->getOperand(2).isKill();
1209      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1210                        .addReg(Dest, RegState::Define |
1211                                getDeadRegState(isDead)),
1212                        Src, isKill, Src2, isKill2);
1213      if (LV && isKill2)
1214        LV->replaceKillInstruction(Src2, MI, NewMI);
1215      break;
1216    }
1217    case X86::ADD64ri32:
1218    case X86::ADD64ri8:
1219      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1220      if (MI->getOperand(2).isImm())
1221        NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1222                                .addReg(Dest, RegState::Define |
1223                                        getDeadRegState(isDead)),
1224                                Src, isKill, MI->getOperand(2).getImm());
1225      break;
1226    case X86::ADD32ri:
1227    case X86::ADD32ri8:
1228      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1229      if (MI->getOperand(2).isImm()) {
1230        unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1231        NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1232                                .addReg(Dest, RegState::Define |
1233                                        getDeadRegState(isDead)),
1234                                Src, isKill, MI->getOperand(2).getImm());
1235      }
1236      break;
1237    case X86::ADD16ri:
1238    case X86::ADD16ri8:
1239      if (DisableLEA16) return 0;
1240      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1241      if (MI->getOperand(2).isImm())
1242        NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1243                             .addReg(Dest, RegState::Define |
1244                                     getDeadRegState(isDead)),
1245                             Src, isKill, MI->getOperand(2).getImm());
1246      break;
1247    case X86::SHL16ri:
1248      if (DisableLEA16) return 0;
1249    case X86::SHL32ri:
1250    case X86::SHL64ri: {
1251      assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1252             "Unknown shl instruction!");
1253      unsigned ShAmt = MI->getOperand(2).getImm();
1254      if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1255        X86AddressMode AM;
1256        AM.Scale = 1 << ShAmt;
1257        AM.IndexReg = Src;
1258        unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1259          : (MIOpc == X86::SHL32ri
1260             ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1261        NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1262                               .addReg(Dest, RegState::Define |
1263                                       getDeadRegState(isDead)), AM);
1264        if (isKill)
1265          NewMI->getOperand(3).setIsKill(true);
1266      }
1267      break;
1268    }
1269    }
1270  }
1271  }
1272
1273  if (!NewMI) return 0;
1274
1275  if (LV) {  // Update live variables
1276    if (isKill)
1277      LV->replaceKillInstruction(Src, MI, NewMI);
1278    if (isDead)
1279      LV->replaceKillInstruction(Dest, MI, NewMI);
1280  }
1281
1282  MFI->insert(MBBI, NewMI);          // Insert the new inst
1283  return NewMI;
1284}
1285
1286/// commuteInstruction - We have a few instructions that must be hacked on to
1287/// commute them.
1288///
1289MachineInstr *
1290X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1291  switch (MI->getOpcode()) {
1292  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1293  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1294  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1295  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1296  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1297  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1298    unsigned Opc;
1299    unsigned Size;
1300    switch (MI->getOpcode()) {
1301    default: llvm_unreachable("Unreachable!");
1302    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1303    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1304    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1305    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1306    case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1307    case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1308    }
1309    unsigned Amt = MI->getOperand(3).getImm();
1310    if (NewMI) {
1311      MachineFunction &MF = *MI->getParent()->getParent();
1312      MI = MF.CloneMachineInstr(MI);
1313      NewMI = false;
1314    }
1315    MI->setDesc(get(Opc));
1316    MI->getOperand(3).setImm(Size-Amt);
1317    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1318  }
1319  case X86::CMOVB16rr:
1320  case X86::CMOVB32rr:
1321  case X86::CMOVB64rr:
1322  case X86::CMOVAE16rr:
1323  case X86::CMOVAE32rr:
1324  case X86::CMOVAE64rr:
1325  case X86::CMOVE16rr:
1326  case X86::CMOVE32rr:
1327  case X86::CMOVE64rr:
1328  case X86::CMOVNE16rr:
1329  case X86::CMOVNE32rr:
1330  case X86::CMOVNE64rr:
1331  case X86::CMOVBE16rr:
1332  case X86::CMOVBE32rr:
1333  case X86::CMOVBE64rr:
1334  case X86::CMOVA16rr:
1335  case X86::CMOVA32rr:
1336  case X86::CMOVA64rr:
1337  case X86::CMOVL16rr:
1338  case X86::CMOVL32rr:
1339  case X86::CMOVL64rr:
1340  case X86::CMOVGE16rr:
1341  case X86::CMOVGE32rr:
1342  case X86::CMOVGE64rr:
1343  case X86::CMOVLE16rr:
1344  case X86::CMOVLE32rr:
1345  case X86::CMOVLE64rr:
1346  case X86::CMOVG16rr:
1347  case X86::CMOVG32rr:
1348  case X86::CMOVG64rr:
1349  case X86::CMOVS16rr:
1350  case X86::CMOVS32rr:
1351  case X86::CMOVS64rr:
1352  case X86::CMOVNS16rr:
1353  case X86::CMOVNS32rr:
1354  case X86::CMOVNS64rr:
1355  case X86::CMOVP16rr:
1356  case X86::CMOVP32rr:
1357  case X86::CMOVP64rr:
1358  case X86::CMOVNP16rr:
1359  case X86::CMOVNP32rr:
1360  case X86::CMOVNP64rr:
1361  case X86::CMOVO16rr:
1362  case X86::CMOVO32rr:
1363  case X86::CMOVO64rr:
1364  case X86::CMOVNO16rr:
1365  case X86::CMOVNO32rr:
1366  case X86::CMOVNO64rr: {
1367    unsigned Opc = 0;
1368    switch (MI->getOpcode()) {
1369    default: break;
1370    case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
1371    case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
1372    case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
1373    case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1374    case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1375    case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1376    case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
1377    case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
1378    case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
1379    case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1380    case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1381    case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1382    case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1383    case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1384    case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1385    case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
1386    case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
1387    case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
1388    case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
1389    case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
1390    case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
1391    case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1392    case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1393    case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1394    case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1395    case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1396    case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1397    case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
1398    case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
1399    case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
1400    case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
1401    case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
1402    case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
1403    case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1404    case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1405    case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1406    case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
1407    case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
1408    case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
1409    case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1410    case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1411    case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1412    case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
1413    case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
1414    case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
1415    case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1416    case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1417    case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1418    }
1419    if (NewMI) {
1420      MachineFunction &MF = *MI->getParent()->getParent();
1421      MI = MF.CloneMachineInstr(MI);
1422      NewMI = false;
1423    }
1424    MI->setDesc(get(Opc));
1425    // Fallthrough intended.
1426  }
1427  default:
1428    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1429  }
1430}
1431
1432static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1433  switch (BrOpc) {
1434  default: return X86::COND_INVALID;
1435  case X86::JE:  return X86::COND_E;
1436  case X86::JNE: return X86::COND_NE;
1437  case X86::JL:  return X86::COND_L;
1438  case X86::JLE: return X86::COND_LE;
1439  case X86::JG:  return X86::COND_G;
1440  case X86::JGE: return X86::COND_GE;
1441  case X86::JB:  return X86::COND_B;
1442  case X86::JBE: return X86::COND_BE;
1443  case X86::JA:  return X86::COND_A;
1444  case X86::JAE: return X86::COND_AE;
1445  case X86::JS:  return X86::COND_S;
1446  case X86::JNS: return X86::COND_NS;
1447  case X86::JP:  return X86::COND_P;
1448  case X86::JNP: return X86::COND_NP;
1449  case X86::JO:  return X86::COND_O;
1450  case X86::JNO: return X86::COND_NO;
1451  }
1452}
1453
1454unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1455  switch (CC) {
1456  default: llvm_unreachable("Illegal condition code!");
1457  case X86::COND_E:  return X86::JE;
1458  case X86::COND_NE: return X86::JNE;
1459  case X86::COND_L:  return X86::JL;
1460  case X86::COND_LE: return X86::JLE;
1461  case X86::COND_G:  return X86::JG;
1462  case X86::COND_GE: return X86::JGE;
1463  case X86::COND_B:  return X86::JB;
1464  case X86::COND_BE: return X86::JBE;
1465  case X86::COND_A:  return X86::JA;
1466  case X86::COND_AE: return X86::JAE;
1467  case X86::COND_S:  return X86::JS;
1468  case X86::COND_NS: return X86::JNS;
1469  case X86::COND_P:  return X86::JP;
1470  case X86::COND_NP: return X86::JNP;
1471  case X86::COND_O:  return X86::JO;
1472  case X86::COND_NO: return X86::JNO;
1473  }
1474}
1475
1476/// GetOppositeBranchCondition - Return the inverse of the specified condition,
1477/// e.g. turning COND_E to COND_NE.
1478X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1479  switch (CC) {
1480  default: llvm_unreachable("Illegal condition code!");
1481  case X86::COND_E:  return X86::COND_NE;
1482  case X86::COND_NE: return X86::COND_E;
1483  case X86::COND_L:  return X86::COND_GE;
1484  case X86::COND_LE: return X86::COND_G;
1485  case X86::COND_G:  return X86::COND_LE;
1486  case X86::COND_GE: return X86::COND_L;
1487  case X86::COND_B:  return X86::COND_AE;
1488  case X86::COND_BE: return X86::COND_A;
1489  case X86::COND_A:  return X86::COND_BE;
1490  case X86::COND_AE: return X86::COND_B;
1491  case X86::COND_S:  return X86::COND_NS;
1492  case X86::COND_NS: return X86::COND_S;
1493  case X86::COND_P:  return X86::COND_NP;
1494  case X86::COND_NP: return X86::COND_P;
1495  case X86::COND_O:  return X86::COND_NO;
1496  case X86::COND_NO: return X86::COND_O;
1497  }
1498}
1499
1500bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1501  const TargetInstrDesc &TID = MI->getDesc();
1502  if (!TID.isTerminator()) return false;
1503
1504  // Conditional branch is a special case.
1505  if (TID.isBranch() && !TID.isBarrier())
1506    return true;
1507  if (!TID.isPredicable())
1508    return true;
1509  return !isPredicated(MI);
1510}
1511
1512// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1513static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1514                                               const X86InstrInfo &TII) {
1515  if (MI->getOpcode() == X86::FP_REG_KILL)
1516    return false;
1517  return TII.isUnpredicatedTerminator(MI);
1518}
1519
1520bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1521                                 MachineBasicBlock *&TBB,
1522                                 MachineBasicBlock *&FBB,
1523                                 SmallVectorImpl<MachineOperand> &Cond,
1524                                 bool AllowModify) const {
1525  // Start from the bottom of the block and work up, examining the
1526  // terminator instructions.
1527  MachineBasicBlock::iterator I = MBB.end();
1528  while (I != MBB.begin()) {
1529    --I;
1530    // Working from the bottom, when we see a non-terminator
1531    // instruction, we're done.
1532    if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1533      break;
1534    // A terminator that isn't a branch can't easily be handled
1535    // by this analysis.
1536    if (!I->getDesc().isBranch())
1537      return true;
1538    // Handle unconditional branches.
1539    if (I->getOpcode() == X86::JMP) {
1540      if (!AllowModify) {
1541        TBB = I->getOperand(0).getMBB();
1542        continue;
1543      }
1544
1545      // If the block has any instructions after a JMP, delete them.
1546      while (next(I) != MBB.end())
1547        next(I)->eraseFromParent();
1548      Cond.clear();
1549      FBB = 0;
1550      // Delete the JMP if it's equivalent to a fall-through.
1551      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1552        TBB = 0;
1553        I->eraseFromParent();
1554        I = MBB.end();
1555        continue;
1556      }
1557      // TBB is used to indicate the unconditinal destination.
1558      TBB = I->getOperand(0).getMBB();
1559      continue;
1560    }
1561    // Handle conditional branches.
1562    X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1563    if (BranchCode == X86::COND_INVALID)
1564      return true;  // Can't handle indirect branch.
1565    // Working from the bottom, handle the first conditional branch.
1566    if (Cond.empty()) {
1567      FBB = TBB;
1568      TBB = I->getOperand(0).getMBB();
1569      Cond.push_back(MachineOperand::CreateImm(BranchCode));
1570      continue;
1571    }
1572    // Handle subsequent conditional branches. Only handle the case
1573    // where all conditional branches branch to the same destination
1574    // and their condition opcodes fit one of the special
1575    // multi-branch idioms.
1576    assert(Cond.size() == 1);
1577    assert(TBB);
1578    // Only handle the case where all conditional branches branch to
1579    // the same destination.
1580    if (TBB != I->getOperand(0).getMBB())
1581      return true;
1582    X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1583    // If the conditions are the same, we can leave them alone.
1584    if (OldBranchCode == BranchCode)
1585      continue;
1586    // If they differ, see if they fit one of the known patterns.
1587    // Theoretically we could handle more patterns here, but
1588    // we shouldn't expect to see them if instruction selection
1589    // has done a reasonable job.
1590    if ((OldBranchCode == X86::COND_NP &&
1591         BranchCode == X86::COND_E) ||
1592        (OldBranchCode == X86::COND_E &&
1593         BranchCode == X86::COND_NP))
1594      BranchCode = X86::COND_NP_OR_E;
1595    else if ((OldBranchCode == X86::COND_P &&
1596              BranchCode == X86::COND_NE) ||
1597             (OldBranchCode == X86::COND_NE &&
1598              BranchCode == X86::COND_P))
1599      BranchCode = X86::COND_NE_OR_P;
1600    else
1601      return true;
1602    // Update the MachineOperand.
1603    Cond[0].setImm(BranchCode);
1604  }
1605
1606  return false;
1607}
1608
1609unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1610  MachineBasicBlock::iterator I = MBB.end();
1611  unsigned Count = 0;
1612
1613  while (I != MBB.begin()) {
1614    --I;
1615    if (I->getOpcode() != X86::JMP &&
1616        GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1617      break;
1618    // Remove the branch.
1619    I->eraseFromParent();
1620    I = MBB.end();
1621    ++Count;
1622  }
1623
1624  return Count;
1625}
1626
1627unsigned
1628X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1629                           MachineBasicBlock *FBB,
1630                           const SmallVectorImpl<MachineOperand> &Cond) const {
1631  // FIXME this should probably have a DebugLoc operand
1632  DebugLoc dl = DebugLoc::getUnknownLoc();
1633  // Shouldn't be a fall through.
1634  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1635  assert((Cond.size() == 1 || Cond.size() == 0) &&
1636         "X86 branch conditions have one component!");
1637
1638  if (Cond.empty()) {
1639    // Unconditional branch?
1640    assert(!FBB && "Unconditional branch with multiple successors!");
1641    BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1642    return 1;
1643  }
1644
1645  // Conditional branch.
1646  unsigned Count = 0;
1647  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1648  switch (CC) {
1649  case X86::COND_NP_OR_E:
1650    // Synthesize NP_OR_E with two branches.
1651    BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1652    ++Count;
1653    BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1654    ++Count;
1655    break;
1656  case X86::COND_NE_OR_P:
1657    // Synthesize NE_OR_P with two branches.
1658    BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1659    ++Count;
1660    BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1661    ++Count;
1662    break;
1663  default: {
1664    unsigned Opc = GetCondBranchFromCond(CC);
1665    BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1666    ++Count;
1667  }
1668  }
1669  if (FBB) {
1670    // Two-way Conditional branch. Insert the second branch.
1671    BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1672    ++Count;
1673  }
1674  return Count;
1675}
1676
1677/// isHReg - Test if the given register is a physical h register.
1678static bool isHReg(unsigned Reg) {
1679  return X86::GR8_ABCD_HRegClass.contains(Reg);
1680}
1681
1682bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1683                                MachineBasicBlock::iterator MI,
1684                                unsigned DestReg, unsigned SrcReg,
1685                                const TargetRegisterClass *DestRC,
1686                                const TargetRegisterClass *SrcRC) const {
1687  DebugLoc DL = DebugLoc::getUnknownLoc();
1688  if (MI != MBB.end()) DL = MI->getDebugLoc();
1689
1690  // Determine if DstRC and SrcRC have a common superclass in common.
1691  const TargetRegisterClass *CommonRC = DestRC;
1692  if (DestRC == SrcRC)
1693    /* Source and destination have the same register class. */;
1694  else if (CommonRC->hasSuperClass(SrcRC))
1695    CommonRC = SrcRC;
1696  else if (!DestRC->hasSubClass(SrcRC)) {
1697    // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1698    // but we want to copy then as GR64. Similarly, for GR32_NOREX and
1699    // GR32_NOSP, copy as GR32.
1700    if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1701        DestRC->hasSuperClass(&X86::GR64RegClass))
1702      CommonRC = &X86::GR64RegClass;
1703    else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1704             DestRC->hasSuperClass(&X86::GR32RegClass))
1705      CommonRC = &X86::GR32RegClass;
1706    else
1707      CommonRC = 0;
1708  }
1709
1710  if (CommonRC) {
1711    unsigned Opc;
1712    if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1713      Opc = X86::MOV64rr;
1714    } else if (CommonRC == &X86::GR32RegClass ||
1715               CommonRC == &X86::GR32_NOSPRegClass) {
1716      Opc = X86::MOV32rr;
1717    } else if (CommonRC == &X86::GR16RegClass) {
1718      Opc = X86::MOV16rr;
1719    } else if (CommonRC == &X86::GR8RegClass) {
1720      // Copying to or from a physical H register on x86-64 requires a NOREX
1721      // move.  Otherwise use a normal move.
1722      if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1723          TM.getSubtarget<X86Subtarget>().is64Bit())
1724        Opc = X86::MOV8rr_NOREX;
1725      else
1726        Opc = X86::MOV8rr;
1727    } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1728      Opc = X86::MOV64rr;
1729    } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1730      Opc = X86::MOV32rr;
1731    } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1732      Opc = X86::MOV16rr;
1733    } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1734      Opc = X86::MOV8rr;
1735    } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1736      if (TM.getSubtarget<X86Subtarget>().is64Bit())
1737        Opc = X86::MOV8rr_NOREX;
1738      else
1739        Opc = X86::MOV8rr;
1740    } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1741               CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1742      Opc = X86::MOV64rr;
1743    } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1744      Opc = X86::MOV32rr;
1745    } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1746      Opc = X86::MOV16rr;
1747    } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1748      Opc = X86::MOV8rr;
1749    } else if (CommonRC == &X86::RFP32RegClass) {
1750      Opc = X86::MOV_Fp3232;
1751    } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1752      Opc = X86::MOV_Fp6464;
1753    } else if (CommonRC == &X86::RFP80RegClass) {
1754      Opc = X86::MOV_Fp8080;
1755    } else if (CommonRC == &X86::FR32RegClass) {
1756      Opc = X86::FsMOVAPSrr;
1757    } else if (CommonRC == &X86::FR64RegClass) {
1758      Opc = X86::FsMOVAPDrr;
1759    } else if (CommonRC == &X86::VR128RegClass) {
1760      Opc = X86::MOVAPSrr;
1761    } else if (CommonRC == &X86::VR64RegClass) {
1762      Opc = X86::MMX_MOVQ64rr;
1763    } else {
1764      return false;
1765    }
1766    BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1767    return true;
1768  }
1769
1770  // Moving EFLAGS to / from another register requires a push and a pop.
1771  if (SrcRC == &X86::CCRRegClass) {
1772    if (SrcReg != X86::EFLAGS)
1773      return false;
1774    if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1775      BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1776      BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1777      return true;
1778    } else if (DestRC == &X86::GR32RegClass ||
1779               DestRC == &X86::GR32_NOSPRegClass) {
1780      BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1781      BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1782      return true;
1783    }
1784  } else if (DestRC == &X86::CCRRegClass) {
1785    if (DestReg != X86::EFLAGS)
1786      return false;
1787    if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1788      BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1789      BuildMI(MBB, MI, DL, get(X86::POPFQ));
1790      return true;
1791    } else if (SrcRC == &X86::GR32RegClass ||
1792               DestRC == &X86::GR32_NOSPRegClass) {
1793      BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1794      BuildMI(MBB, MI, DL, get(X86::POPFD));
1795      return true;
1796    }
1797  }
1798
1799  // Moving from ST(0) turns into FpGET_ST0_32 etc.
1800  if (SrcRC == &X86::RSTRegClass) {
1801    // Copying from ST(0)/ST(1).
1802    if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1803      // Can only copy from ST(0)/ST(1) right now
1804      return false;
1805    bool isST0 = SrcReg == X86::ST0;
1806    unsigned Opc;
1807    if (DestRC == &X86::RFP32RegClass)
1808      Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1809    else if (DestRC == &X86::RFP64RegClass)
1810      Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1811    else {
1812      if (DestRC != &X86::RFP80RegClass)
1813        return false;
1814      Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1815    }
1816    BuildMI(MBB, MI, DL, get(Opc), DestReg);
1817    return true;
1818  }
1819
1820  // Moving to ST(0) turns into FpSET_ST0_32 etc.
1821  if (DestRC == &X86::RSTRegClass) {
1822    // Copying to ST(0) / ST(1).
1823    if (DestReg != X86::ST0 && DestReg != X86::ST1)
1824      // Can only copy to TOS right now
1825      return false;
1826    bool isST0 = DestReg == X86::ST0;
1827    unsigned Opc;
1828    if (SrcRC == &X86::RFP32RegClass)
1829      Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1830    else if (SrcRC == &X86::RFP64RegClass)
1831      Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1832    else {
1833      if (SrcRC != &X86::RFP80RegClass)
1834        return false;
1835      Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1836    }
1837    BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1838    return true;
1839  }
1840
1841  // Not yet supported!
1842  return false;
1843}
1844
1845static unsigned getStoreRegOpcode(unsigned SrcReg,
1846                                  const TargetRegisterClass *RC,
1847                                  bool isStackAligned,
1848                                  TargetMachine &TM) {
1849  unsigned Opc = 0;
1850  if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1851    Opc = X86::MOV64mr;
1852  } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1853    Opc = X86::MOV32mr;
1854  } else if (RC == &X86::GR16RegClass) {
1855    Opc = X86::MOV16mr;
1856  } else if (RC == &X86::GR8RegClass) {
1857    // Copying to or from a physical H register on x86-64 requires a NOREX
1858    // move.  Otherwise use a normal move.
1859    if (isHReg(SrcReg) &&
1860        TM.getSubtarget<X86Subtarget>().is64Bit())
1861      Opc = X86::MOV8mr_NOREX;
1862    else
1863      Opc = X86::MOV8mr;
1864  } else if (RC == &X86::GR64_ABCDRegClass) {
1865    Opc = X86::MOV64mr;
1866  } else if (RC == &X86::GR32_ABCDRegClass) {
1867    Opc = X86::MOV32mr;
1868  } else if (RC == &X86::GR16_ABCDRegClass) {
1869    Opc = X86::MOV16mr;
1870  } else if (RC == &X86::GR8_ABCD_LRegClass) {
1871    Opc = X86::MOV8mr;
1872  } else if (RC == &X86::GR8_ABCD_HRegClass) {
1873    if (TM.getSubtarget<X86Subtarget>().is64Bit())
1874      Opc = X86::MOV8mr_NOREX;
1875    else
1876      Opc = X86::MOV8mr;
1877  } else if (RC == &X86::GR64_NOREXRegClass ||
1878             RC == &X86::GR64_NOREX_NOSPRegClass) {
1879    Opc = X86::MOV64mr;
1880  } else if (RC == &X86::GR32_NOREXRegClass) {
1881    Opc = X86::MOV32mr;
1882  } else if (RC == &X86::GR16_NOREXRegClass) {
1883    Opc = X86::MOV16mr;
1884  } else if (RC == &X86::GR8_NOREXRegClass) {
1885    Opc = X86::MOV8mr;
1886  } else if (RC == &X86::RFP80RegClass) {
1887    Opc = X86::ST_FpP80m;   // pops
1888  } else if (RC == &X86::RFP64RegClass) {
1889    Opc = X86::ST_Fp64m;
1890  } else if (RC == &X86::RFP32RegClass) {
1891    Opc = X86::ST_Fp32m;
1892  } else if (RC == &X86::FR32RegClass) {
1893    Opc = X86::MOVSSmr;
1894  } else if (RC == &X86::FR64RegClass) {
1895    Opc = X86::MOVSDmr;
1896  } else if (RC == &X86::VR128RegClass) {
1897    // If stack is realigned we can use aligned stores.
1898    Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1899  } else if (RC == &X86::VR64RegClass) {
1900    Opc = X86::MMX_MOVQ64mr;
1901  } else {
1902    llvm_unreachable("Unknown regclass");
1903  }
1904
1905  return Opc;
1906}
1907
1908void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1909                                       MachineBasicBlock::iterator MI,
1910                                       unsigned SrcReg, bool isKill, int FrameIdx,
1911                                       const TargetRegisterClass *RC) const {
1912  const MachineFunction &MF = *MBB.getParent();
1913  bool isAligned = (RI.getStackAlignment() >= 16) ||
1914    RI.needsStackRealignment(MF);
1915  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1916  DebugLoc DL = DebugLoc::getUnknownLoc();
1917  if (MI != MBB.end()) DL = MI->getDebugLoc();
1918  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1919    .addReg(SrcReg, getKillRegState(isKill));
1920}
1921
1922void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1923                                  bool isKill,
1924                                  SmallVectorImpl<MachineOperand> &Addr,
1925                                  const TargetRegisterClass *RC,
1926                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
1927  bool isAligned = (RI.getStackAlignment() >= 16) ||
1928    RI.needsStackRealignment(MF);
1929  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1930  DebugLoc DL = DebugLoc::getUnknownLoc();
1931  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1932  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1933    MIB.addOperand(Addr[i]);
1934  MIB.addReg(SrcReg, getKillRegState(isKill));
1935  NewMIs.push_back(MIB);
1936}
1937
1938static unsigned getLoadRegOpcode(unsigned DestReg,
1939                                 const TargetRegisterClass *RC,
1940                                 bool isStackAligned,
1941                                 const TargetMachine &TM) {
1942  unsigned Opc = 0;
1943  if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1944    Opc = X86::MOV64rm;
1945  } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1946    Opc = X86::MOV32rm;
1947  } else if (RC == &X86::GR16RegClass) {
1948    Opc = X86::MOV16rm;
1949  } else if (RC == &X86::GR8RegClass) {
1950    // Copying to or from a physical H register on x86-64 requires a NOREX
1951    // move.  Otherwise use a normal move.
1952    if (isHReg(DestReg) &&
1953        TM.getSubtarget<X86Subtarget>().is64Bit())
1954      Opc = X86::MOV8rm_NOREX;
1955    else
1956      Opc = X86::MOV8rm;
1957  } else if (RC == &X86::GR64_ABCDRegClass) {
1958    Opc = X86::MOV64rm;
1959  } else if (RC == &X86::GR32_ABCDRegClass) {
1960    Opc = X86::MOV32rm;
1961  } else if (RC == &X86::GR16_ABCDRegClass) {
1962    Opc = X86::MOV16rm;
1963  } else if (RC == &X86::GR8_ABCD_LRegClass) {
1964    Opc = X86::MOV8rm;
1965  } else if (RC == &X86::GR8_ABCD_HRegClass) {
1966    if (TM.getSubtarget<X86Subtarget>().is64Bit())
1967      Opc = X86::MOV8rm_NOREX;
1968    else
1969      Opc = X86::MOV8rm;
1970  } else if (RC == &X86::GR64_NOREXRegClass ||
1971             RC == &X86::GR64_NOREX_NOSPRegClass) {
1972    Opc = X86::MOV64rm;
1973  } else if (RC == &X86::GR32_NOREXRegClass) {
1974    Opc = X86::MOV32rm;
1975  } else if (RC == &X86::GR16_NOREXRegClass) {
1976    Opc = X86::MOV16rm;
1977  } else if (RC == &X86::GR8_NOREXRegClass) {
1978    Opc = X86::MOV8rm;
1979  } else if (RC == &X86::RFP80RegClass) {
1980    Opc = X86::LD_Fp80m;
1981  } else if (RC == &X86::RFP64RegClass) {
1982    Opc = X86::LD_Fp64m;
1983  } else if (RC == &X86::RFP32RegClass) {
1984    Opc = X86::LD_Fp32m;
1985  } else if (RC == &X86::FR32RegClass) {
1986    Opc = X86::MOVSSrm;
1987  } else if (RC == &X86::FR64RegClass) {
1988    Opc = X86::MOVSDrm;
1989  } else if (RC == &X86::VR128RegClass) {
1990    // If stack is realigned we can use aligned loads.
1991    Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1992  } else if (RC == &X86::VR64RegClass) {
1993    Opc = X86::MMX_MOVQ64rm;
1994  } else {
1995    llvm_unreachable("Unknown regclass");
1996  }
1997
1998  return Opc;
1999}
2000
2001void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2002                                        MachineBasicBlock::iterator MI,
2003                                        unsigned DestReg, int FrameIdx,
2004                                        const TargetRegisterClass *RC) const{
2005  const MachineFunction &MF = *MBB.getParent();
2006  bool isAligned = (RI.getStackAlignment() >= 16) ||
2007    RI.needsStackRealignment(MF);
2008  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2009  DebugLoc DL = DebugLoc::getUnknownLoc();
2010  if (MI != MBB.end()) DL = MI->getDebugLoc();
2011  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2012}
2013
2014void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2015                                 SmallVectorImpl<MachineOperand> &Addr,
2016                                 const TargetRegisterClass *RC,
2017                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2018  bool isAligned = (RI.getStackAlignment() >= 16) ||
2019    RI.needsStackRealignment(MF);
2020  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2021  DebugLoc DL = DebugLoc::getUnknownLoc();
2022  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2023  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2024    MIB.addOperand(Addr[i]);
2025  NewMIs.push_back(MIB);
2026}
2027
2028bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2029                                             MachineBasicBlock::iterator MI,
2030                                const std::vector<CalleeSavedInfo> &CSI) const {
2031  if (CSI.empty())
2032    return false;
2033
2034  DebugLoc DL = DebugLoc::getUnknownLoc();
2035  if (MI != MBB.end()) DL = MI->getDebugLoc();
2036
2037  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2038  bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2039  unsigned SlotSize = is64Bit ? 8 : 4;
2040
2041  MachineFunction &MF = *MBB.getParent();
2042  unsigned FPReg = RI.getFrameRegister(MF);
2043  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2044  unsigned CalleeFrameSize = 0;
2045
2046  unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2047  for (unsigned i = CSI.size(); i != 0; --i) {
2048    unsigned Reg = CSI[i-1].getReg();
2049    const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2050    // Add the callee-saved register as live-in. It's killed at the spill.
2051    MBB.addLiveIn(Reg);
2052    if (Reg == FPReg)
2053      // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2054      continue;
2055    if (RegClass != &X86::VR128RegClass && !isWin64) {
2056      CalleeFrameSize += SlotSize;
2057      BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2058    } else {
2059      storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2060    }
2061  }
2062
2063  X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2064  return true;
2065}
2066
2067bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2068                                               MachineBasicBlock::iterator MI,
2069                                const std::vector<CalleeSavedInfo> &CSI) const {
2070  if (CSI.empty())
2071    return false;
2072
2073  DebugLoc DL = DebugLoc::getUnknownLoc();
2074  if (MI != MBB.end()) DL = MI->getDebugLoc();
2075
2076  MachineFunction &MF = *MBB.getParent();
2077  unsigned FPReg = RI.getFrameRegister(MF);
2078  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2079  bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2080  unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2081  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2082    unsigned Reg = CSI[i].getReg();
2083    if (Reg == FPReg)
2084      // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2085      continue;
2086    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2087    if (RegClass != &X86::VR128RegClass && !isWin64) {
2088      BuildMI(MBB, MI, DL, get(Opc), Reg);
2089    } else {
2090      loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2091    }
2092  }
2093  return true;
2094}
2095
2096static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2097                                     const SmallVectorImpl<MachineOperand> &MOs,
2098                                     MachineInstr *MI,
2099                                     const TargetInstrInfo &TII) {
2100  // Create the base instruction with the memory operand as the first part.
2101  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2102                                              MI->getDebugLoc(), true);
2103  MachineInstrBuilder MIB(NewMI);
2104  unsigned NumAddrOps = MOs.size();
2105  for (unsigned i = 0; i != NumAddrOps; ++i)
2106    MIB.addOperand(MOs[i]);
2107  if (NumAddrOps < 4)  // FrameIndex only
2108    addOffset(MIB, 0);
2109
2110  // Loop over the rest of the ri operands, converting them over.
2111  unsigned NumOps = MI->getDesc().getNumOperands()-2;
2112  for (unsigned i = 0; i != NumOps; ++i) {
2113    MachineOperand &MO = MI->getOperand(i+2);
2114    MIB.addOperand(MO);
2115  }
2116  for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2117    MachineOperand &MO = MI->getOperand(i);
2118    MIB.addOperand(MO);
2119  }
2120  return MIB;
2121}
2122
2123static MachineInstr *FuseInst(MachineFunction &MF,
2124                              unsigned Opcode, unsigned OpNo,
2125                              const SmallVectorImpl<MachineOperand> &MOs,
2126                              MachineInstr *MI, const TargetInstrInfo &TII) {
2127  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2128                                              MI->getDebugLoc(), true);
2129  MachineInstrBuilder MIB(NewMI);
2130
2131  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2132    MachineOperand &MO = MI->getOperand(i);
2133    if (i == OpNo) {
2134      assert(MO.isReg() && "Expected to fold into reg operand!");
2135      unsigned NumAddrOps = MOs.size();
2136      for (unsigned i = 0; i != NumAddrOps; ++i)
2137        MIB.addOperand(MOs[i]);
2138      if (NumAddrOps < 4)  // FrameIndex only
2139        addOffset(MIB, 0);
2140    } else {
2141      MIB.addOperand(MO);
2142    }
2143  }
2144  return MIB;
2145}
2146
2147static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2148                                const SmallVectorImpl<MachineOperand> &MOs,
2149                                MachineInstr *MI) {
2150  MachineFunction &MF = *MI->getParent()->getParent();
2151  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2152
2153  unsigned NumAddrOps = MOs.size();
2154  for (unsigned i = 0; i != NumAddrOps; ++i)
2155    MIB.addOperand(MOs[i]);
2156  if (NumAddrOps < 4)  // FrameIndex only
2157    addOffset(MIB, 0);
2158  return MIB.addImm(0);
2159}
2160
2161MachineInstr*
2162X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2163                                    MachineInstr *MI, unsigned i,
2164                                    const SmallVectorImpl<MachineOperand> &MOs,
2165                                    unsigned Align) const {
2166  const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2167  bool isTwoAddrFold = false;
2168  unsigned NumOps = MI->getDesc().getNumOperands();
2169  bool isTwoAddr = NumOps > 1 &&
2170    MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2171
2172  MachineInstr *NewMI = NULL;
2173  // Folding a memory location into the two-address part of a two-address
2174  // instruction is different than folding it other places.  It requires
2175  // replacing the *two* registers with the memory location.
2176  if (isTwoAddr && NumOps >= 2 && i < 2 &&
2177      MI->getOperand(0).isReg() &&
2178      MI->getOperand(1).isReg() &&
2179      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2180    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2181    isTwoAddrFold = true;
2182  } else if (i == 0) { // If operand 0
2183    if (MI->getOpcode() == X86::MOV16r0)
2184      NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2185    else if (MI->getOpcode() == X86::MOV32r0)
2186      NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2187    else if (MI->getOpcode() == X86::MOV8r0)
2188      NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2189    if (NewMI)
2190      return NewMI;
2191
2192    OpcodeTablePtr = &RegOp2MemOpTable0;
2193  } else if (i == 1) {
2194    OpcodeTablePtr = &RegOp2MemOpTable1;
2195  } else if (i == 2) {
2196    OpcodeTablePtr = &RegOp2MemOpTable2;
2197  }
2198
2199  // If table selected...
2200  if (OpcodeTablePtr) {
2201    // Find the Opcode to fuse
2202    DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2203      OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2204    if (I != OpcodeTablePtr->end()) {
2205      unsigned MinAlign = I->second.second;
2206      if (Align < MinAlign)
2207        return NULL;
2208      if (isTwoAddrFold)
2209        NewMI = FuseTwoAddrInst(MF, I->second.first, MOs, MI, *this);
2210      else
2211        NewMI = FuseInst(MF, I->second.first, i, MOs, MI, *this);
2212      return NewMI;
2213    }
2214  }
2215
2216  // No fusion
2217  if (PrintFailedFusing)
2218    errs() << "We failed to fuse operand " << i << " in " << *MI;
2219  return NULL;
2220}
2221
2222
2223MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2224                                                  MachineInstr *MI,
2225                                           const SmallVectorImpl<unsigned> &Ops,
2226                                                  int FrameIndex) const {
2227  // Check switch flag
2228  if (NoFusing) return NULL;
2229
2230  const MachineFrameInfo *MFI = MF.getFrameInfo();
2231  unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2232  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2233    unsigned NewOpc = 0;
2234    switch (MI->getOpcode()) {
2235    default: return NULL;
2236    case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
2237    case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2238    case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2239    case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2240    }
2241    // Change to CMPXXri r, 0 first.
2242    MI->setDesc(get(NewOpc));
2243    MI->getOperand(1).ChangeToImmediate(0);
2244  } else if (Ops.size() != 1)
2245    return NULL;
2246
2247  SmallVector<MachineOperand,4> MOs;
2248  MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2249  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Alignment);
2250}
2251
2252MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2253                                                  MachineInstr *MI,
2254                                           const SmallVectorImpl<unsigned> &Ops,
2255                                                  MachineInstr *LoadMI) const {
2256  // Check switch flag
2257  if (NoFusing) return NULL;
2258
2259  // Determine the alignment of the load.
2260  unsigned Alignment = 0;
2261  if (LoadMI->hasOneMemOperand())
2262    Alignment = LoadMI->memoperands_begin()->getAlignment();
2263  else if (LoadMI->getOpcode() == X86::V_SET0 ||
2264           LoadMI->getOpcode() == X86::V_SETALLONES)
2265    Alignment = 16;
2266  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2267    unsigned NewOpc = 0;
2268    switch (MI->getOpcode()) {
2269    default: return NULL;
2270    case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
2271    case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2272    case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2273    case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2274    }
2275    // Change to CMPXXri r, 0 first.
2276    MI->setDesc(get(NewOpc));
2277    MI->getOperand(1).ChangeToImmediate(0);
2278  } else if (Ops.size() != 1)
2279    return NULL;
2280
2281  SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2282  if (LoadMI->getOpcode() == X86::V_SET0 ||
2283      LoadMI->getOpcode() == X86::V_SETALLONES) {
2284    // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2285    // Create a constant-pool entry and operands to load from it.
2286
2287    // x86-32 PIC requires a PIC base register for constant pools.
2288    unsigned PICBase = 0;
2289    if (TM.getRelocationModel() == Reloc::PIC_) {
2290      if (TM.getSubtarget<X86Subtarget>().is64Bit())
2291        PICBase = X86::RIP;
2292      else
2293        // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2294        // This doesn't work for several reasons.
2295        // 1. GlobalBaseReg may have been spilled.
2296        // 2. It may not be live at MI.
2297        return false;
2298    }
2299
2300    // Create a v4i32 constant-pool entry.
2301    MachineConstantPool &MCP = *MF.getConstantPool();
2302    const VectorType *Ty =
2303          VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2304    Constant *C = LoadMI->getOpcode() == X86::V_SET0 ?
2305                    Constant::getNullValue(Ty) :
2306                    Constant::getAllOnesValue(Ty);
2307    unsigned CPI = MCP.getConstantPoolIndex(C, 16);
2308
2309    // Create operands to load from the constant pool entry.
2310    MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2311    MOs.push_back(MachineOperand::CreateImm(1));
2312    MOs.push_back(MachineOperand::CreateReg(0, false));
2313    MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2314    MOs.push_back(MachineOperand::CreateReg(0, false));
2315  } else {
2316    // Folding a normal load. Just copy the load's address operands.
2317    unsigned NumOps = LoadMI->getDesc().getNumOperands();
2318    for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2319      MOs.push_back(LoadMI->getOperand(i));
2320  }
2321  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Alignment);
2322}
2323
2324
2325bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2326                                  const SmallVectorImpl<unsigned> &Ops) const {
2327  // Check switch flag
2328  if (NoFusing) return 0;
2329
2330  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2331    switch (MI->getOpcode()) {
2332    default: return false;
2333    case X86::TEST8rr:
2334    case X86::TEST16rr:
2335    case X86::TEST32rr:
2336    case X86::TEST64rr:
2337      return true;
2338    }
2339  }
2340
2341  if (Ops.size() != 1)
2342    return false;
2343
2344  unsigned OpNum = Ops[0];
2345  unsigned Opc = MI->getOpcode();
2346  unsigned NumOps = MI->getDesc().getNumOperands();
2347  bool isTwoAddr = NumOps > 1 &&
2348    MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2349
2350  // Folding a memory location into the two-address part of a two-address
2351  // instruction is different than folding it other places.  It requires
2352  // replacing the *two* registers with the memory location.
2353  const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2354  if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2355    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2356  } else if (OpNum == 0) { // If operand 0
2357    switch (Opc) {
2358    case X86::MOV8r0:
2359    case X86::MOV16r0:
2360    case X86::MOV32r0:
2361      return true;
2362    default: break;
2363    }
2364    OpcodeTablePtr = &RegOp2MemOpTable0;
2365  } else if (OpNum == 1) {
2366    OpcodeTablePtr = &RegOp2MemOpTable1;
2367  } else if (OpNum == 2) {
2368    OpcodeTablePtr = &RegOp2MemOpTable2;
2369  }
2370
2371  if (OpcodeTablePtr) {
2372    // Find the Opcode to fuse
2373    DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2374      OpcodeTablePtr->find((unsigned*)Opc);
2375    if (I != OpcodeTablePtr->end())
2376      return true;
2377  }
2378  return false;
2379}
2380
2381bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2382                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2383                                SmallVectorImpl<MachineInstr*> &NewMIs) const {
2384  DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2385    MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2386  if (I == MemOp2RegOpTable.end())
2387    return false;
2388  DebugLoc dl = MI->getDebugLoc();
2389  unsigned Opc = I->second.first;
2390  unsigned Index = I->second.second & 0xf;
2391  bool FoldedLoad = I->second.second & (1 << 4);
2392  bool FoldedStore = I->second.second & (1 << 5);
2393  if (UnfoldLoad && !FoldedLoad)
2394    return false;
2395  UnfoldLoad &= FoldedLoad;
2396  if (UnfoldStore && !FoldedStore)
2397    return false;
2398  UnfoldStore &= FoldedStore;
2399
2400  const TargetInstrDesc &TID = get(Opc);
2401  const TargetOperandInfo &TOI = TID.OpInfo[Index];
2402  const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2403  SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2404  SmallVector<MachineOperand,2> BeforeOps;
2405  SmallVector<MachineOperand,2> AfterOps;
2406  SmallVector<MachineOperand,4> ImpOps;
2407  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2408    MachineOperand &Op = MI->getOperand(i);
2409    if (i >= Index && i < Index + X86AddrNumOperands)
2410      AddrOps.push_back(Op);
2411    else if (Op.isReg() && Op.isImplicit())
2412      ImpOps.push_back(Op);
2413    else if (i < Index)
2414      BeforeOps.push_back(Op);
2415    else if (i > Index)
2416      AfterOps.push_back(Op);
2417  }
2418
2419  // Emit the load instruction.
2420  if (UnfoldLoad) {
2421    loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2422    if (UnfoldStore) {
2423      // Address operands cannot be marked isKill.
2424      for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2425        MachineOperand &MO = NewMIs[0]->getOperand(i);
2426        if (MO.isReg())
2427          MO.setIsKill(false);
2428      }
2429    }
2430  }
2431
2432  // Emit the data processing instruction.
2433  MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2434  MachineInstrBuilder MIB(DataMI);
2435
2436  if (FoldedStore)
2437    MIB.addReg(Reg, RegState::Define);
2438  for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2439    MIB.addOperand(BeforeOps[i]);
2440  if (FoldedLoad)
2441    MIB.addReg(Reg);
2442  for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2443    MIB.addOperand(AfterOps[i]);
2444  for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2445    MachineOperand &MO = ImpOps[i];
2446    MIB.addReg(MO.getReg(),
2447               getDefRegState(MO.isDef()) |
2448               RegState::Implicit |
2449               getKillRegState(MO.isKill()) |
2450               getDeadRegState(MO.isDead()) |
2451               getUndefRegState(MO.isUndef()));
2452  }
2453  // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2454  unsigned NewOpc = 0;
2455  switch (DataMI->getOpcode()) {
2456  default: break;
2457  case X86::CMP64ri32:
2458  case X86::CMP32ri:
2459  case X86::CMP16ri:
2460  case X86::CMP8ri: {
2461    MachineOperand &MO0 = DataMI->getOperand(0);
2462    MachineOperand &MO1 = DataMI->getOperand(1);
2463    if (MO1.getImm() == 0) {
2464      switch (DataMI->getOpcode()) {
2465      default: break;
2466      case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2467      case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
2468      case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
2469      case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
2470      }
2471      DataMI->setDesc(get(NewOpc));
2472      MO1.ChangeToRegister(MO0.getReg(), false);
2473    }
2474  }
2475  }
2476  NewMIs.push_back(DataMI);
2477
2478  // Emit the store instruction.
2479  if (UnfoldStore) {
2480    const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2481    storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2482  }
2483
2484  return true;
2485}
2486
2487bool
2488X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2489                                  SmallVectorImpl<SDNode*> &NewNodes) const {
2490  if (!N->isMachineOpcode())
2491    return false;
2492
2493  DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2494    MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2495  if (I == MemOp2RegOpTable.end())
2496    return false;
2497  unsigned Opc = I->second.first;
2498  unsigned Index = I->second.second & 0xf;
2499  bool FoldedLoad = I->second.second & (1 << 4);
2500  bool FoldedStore = I->second.second & (1 << 5);
2501  const TargetInstrDesc &TID = get(Opc);
2502  const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2503  unsigned NumDefs = TID.NumDefs;
2504  std::vector<SDValue> AddrOps;
2505  std::vector<SDValue> BeforeOps;
2506  std::vector<SDValue> AfterOps;
2507  DebugLoc dl = N->getDebugLoc();
2508  unsigned NumOps = N->getNumOperands();
2509  for (unsigned i = 0; i != NumOps-1; ++i) {
2510    SDValue Op = N->getOperand(i);
2511    if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2512      AddrOps.push_back(Op);
2513    else if (i < Index-NumDefs)
2514      BeforeOps.push_back(Op);
2515    else if (i > Index-NumDefs)
2516      AfterOps.push_back(Op);
2517  }
2518  SDValue Chain = N->getOperand(NumOps-1);
2519  AddrOps.push_back(Chain);
2520
2521  // Emit the load instruction.
2522  SDNode *Load = 0;
2523  const MachineFunction &MF = DAG.getMachineFunction();
2524  if (FoldedLoad) {
2525    EVT VT = *RC->vt_begin();
2526    bool isAligned = (RI.getStackAlignment() >= 16) ||
2527      RI.needsStackRealignment(MF);
2528    Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2529                             VT, MVT::Other, &AddrOps[0], AddrOps.size());
2530    NewNodes.push_back(Load);
2531  }
2532
2533  // Emit the data processing instruction.
2534  std::vector<EVT> VTs;
2535  const TargetRegisterClass *DstRC = 0;
2536  if (TID.getNumDefs() > 0) {
2537    DstRC = TID.OpInfo[0].getRegClass(&RI);
2538    VTs.push_back(*DstRC->vt_begin());
2539  }
2540  for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2541    EVT VT = N->getValueType(i);
2542    if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2543      VTs.push_back(VT);
2544  }
2545  if (Load)
2546    BeforeOps.push_back(SDValue(Load, 0));
2547  std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2548  SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0],
2549                                     BeforeOps.size());
2550  NewNodes.push_back(NewNode);
2551
2552  // Emit the store instruction.
2553  if (FoldedStore) {
2554    AddrOps.pop_back();
2555    AddrOps.push_back(SDValue(NewNode, 0));
2556    AddrOps.push_back(Chain);
2557    bool isAligned = (RI.getStackAlignment() >= 16) ||
2558      RI.needsStackRealignment(MF);
2559    SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
2560                                                        isAligned, TM),
2561                                      dl, MVT::Other,
2562                                      &AddrOps[0], AddrOps.size());
2563    NewNodes.push_back(Store);
2564  }
2565
2566  return true;
2567}
2568
2569unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2570                                      bool UnfoldLoad, bool UnfoldStore) const {
2571  DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2572    MemOp2RegOpTable.find((unsigned*)Opc);
2573  if (I == MemOp2RegOpTable.end())
2574    return 0;
2575  bool FoldedLoad = I->second.second & (1 << 4);
2576  bool FoldedStore = I->second.second & (1 << 5);
2577  if (UnfoldLoad && !FoldedLoad)
2578    return 0;
2579  if (UnfoldStore && !FoldedStore)
2580    return 0;
2581  return I->second.first;
2582}
2583
2584bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2585  if (MBB.empty()) return false;
2586
2587  switch (MBB.back().getOpcode()) {
2588  case X86::TCRETURNri:
2589  case X86::TCRETURNdi:
2590  case X86::RET:     // Return.
2591  case X86::RETI:
2592  case X86::TAILJMPd:
2593  case X86::TAILJMPr:
2594  case X86::TAILJMPm:
2595  case X86::JMP:     // Uncond branch.
2596  case X86::JMP32r:  // Indirect branch.
2597  case X86::JMP64r:  // Indirect branch (64-bit).
2598  case X86::JMP32m:  // Indirect branch through mem.
2599  case X86::JMP64m:  // Indirect branch through mem (64-bit).
2600    return true;
2601  default: return false;
2602  }
2603}
2604
2605bool X86InstrInfo::
2606ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2607  assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2608  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2609  if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2610    return true;
2611  Cond[0].setImm(GetOppositeBranchCondition(CC));
2612  return false;
2613}
2614
2615bool X86InstrInfo::
2616isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2617  // FIXME: Return false for x87 stack register classes for now. We can't
2618  // allow any loads of these registers before FpGet_ST0_80.
2619  return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2620           RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2621}
2622
2623unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2624  switch (Desc->TSFlags & X86II::ImmMask) {
2625  case X86II::Imm8:   return 1;
2626  case X86II::Imm16:  return 2;
2627  case X86II::Imm32:  return 4;
2628  case X86II::Imm64:  return 8;
2629  default: llvm_unreachable("Immediate size not set!");
2630    return 0;
2631  }
2632}
2633
2634/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2635/// e.g. r8, xmm8, etc.
2636bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2637  if (!MO.isReg()) return false;
2638  switch (MO.getReg()) {
2639  default: break;
2640  case X86::R8:    case X86::R9:    case X86::R10:   case X86::R11:
2641  case X86::R12:   case X86::R13:   case X86::R14:   case X86::R15:
2642  case X86::R8D:   case X86::R9D:   case X86::R10D:  case X86::R11D:
2643  case X86::R12D:  case X86::R13D:  case X86::R14D:  case X86::R15D:
2644  case X86::R8W:   case X86::R9W:   case X86::R10W:  case X86::R11W:
2645  case X86::R12W:  case X86::R13W:  case X86::R14W:  case X86::R15W:
2646  case X86::R8B:   case X86::R9B:   case X86::R10B:  case X86::R11B:
2647  case X86::R12B:  case X86::R13B:  case X86::R14B:  case X86::R15B:
2648  case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
2649  case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2650    return true;
2651  }
2652  return false;
2653}
2654
2655
2656/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2657/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2658/// size, and 3) use of X86-64 extended registers.
2659unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2660  unsigned REX = 0;
2661  const TargetInstrDesc &Desc = MI.getDesc();
2662
2663  // Pseudo instructions do not need REX prefix byte.
2664  if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2665    return 0;
2666  if (Desc.TSFlags & X86II::REX_W)
2667    REX |= 1 << 3;
2668
2669  unsigned NumOps = Desc.getNumOperands();
2670  if (NumOps) {
2671    bool isTwoAddr = NumOps > 1 &&
2672      Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2673
2674    // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2675    unsigned i = isTwoAddr ? 1 : 0;
2676    for (unsigned e = NumOps; i != e; ++i) {
2677      const MachineOperand& MO = MI.getOperand(i);
2678      if (MO.isReg()) {
2679        unsigned Reg = MO.getReg();
2680        if (isX86_64NonExtLowByteReg(Reg))
2681          REX |= 0x40;
2682      }
2683    }
2684
2685    switch (Desc.TSFlags & X86II::FormMask) {
2686    case X86II::MRMInitReg:
2687      if (isX86_64ExtendedReg(MI.getOperand(0)))
2688        REX |= (1 << 0) | (1 << 2);
2689      break;
2690    case X86II::MRMSrcReg: {
2691      if (isX86_64ExtendedReg(MI.getOperand(0)))
2692        REX |= 1 << 2;
2693      i = isTwoAddr ? 2 : 1;
2694      for (unsigned e = NumOps; i != e; ++i) {
2695        const MachineOperand& MO = MI.getOperand(i);
2696        if (isX86_64ExtendedReg(MO))
2697          REX |= 1 << 0;
2698      }
2699      break;
2700    }
2701    case X86II::MRMSrcMem: {
2702      if (isX86_64ExtendedReg(MI.getOperand(0)))
2703        REX |= 1 << 2;
2704      unsigned Bit = 0;
2705      i = isTwoAddr ? 2 : 1;
2706      for (; i != NumOps; ++i) {
2707        const MachineOperand& MO = MI.getOperand(i);
2708        if (MO.isReg()) {
2709          if (isX86_64ExtendedReg(MO))
2710            REX |= 1 << Bit;
2711          Bit++;
2712        }
2713      }
2714      break;
2715    }
2716    case X86II::MRM0m: case X86II::MRM1m:
2717    case X86II::MRM2m: case X86II::MRM3m:
2718    case X86II::MRM4m: case X86II::MRM5m:
2719    case X86II::MRM6m: case X86II::MRM7m:
2720    case X86II::MRMDestMem: {
2721      unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2722      i = isTwoAddr ? 1 : 0;
2723      if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2724        REX |= 1 << 2;
2725      unsigned Bit = 0;
2726      for (; i != e; ++i) {
2727        const MachineOperand& MO = MI.getOperand(i);
2728        if (MO.isReg()) {
2729          if (isX86_64ExtendedReg(MO))
2730            REX |= 1 << Bit;
2731          Bit++;
2732        }
2733      }
2734      break;
2735    }
2736    default: {
2737      if (isX86_64ExtendedReg(MI.getOperand(0)))
2738        REX |= 1 << 0;
2739      i = isTwoAddr ? 2 : 1;
2740      for (unsigned e = NumOps; i != e; ++i) {
2741        const MachineOperand& MO = MI.getOperand(i);
2742        if (isX86_64ExtendedReg(MO))
2743          REX |= 1 << 2;
2744      }
2745      break;
2746    }
2747    }
2748  }
2749  return REX;
2750}
2751
2752/// sizePCRelativeBlockAddress - This method returns the size of a PC
2753/// relative block address instruction
2754///
2755static unsigned sizePCRelativeBlockAddress() {
2756  return 4;
2757}
2758
2759/// sizeGlobalAddress - Give the size of the emission of this global address
2760///
2761static unsigned sizeGlobalAddress(bool dword) {
2762  return dword ? 8 : 4;
2763}
2764
2765/// sizeConstPoolAddress - Give the size of the emission of this constant
2766/// pool address
2767///
2768static unsigned sizeConstPoolAddress(bool dword) {
2769  return dword ? 8 : 4;
2770}
2771
2772/// sizeExternalSymbolAddress - Give the size of the emission of this external
2773/// symbol
2774///
2775static unsigned sizeExternalSymbolAddress(bool dword) {
2776  return dword ? 8 : 4;
2777}
2778
2779/// sizeJumpTableAddress - Give the size of the emission of this jump
2780/// table address
2781///
2782static unsigned sizeJumpTableAddress(bool dword) {
2783  return dword ? 8 : 4;
2784}
2785
2786static unsigned sizeConstant(unsigned Size) {
2787  return Size;
2788}
2789
2790static unsigned sizeRegModRMByte(){
2791  return 1;
2792}
2793
2794static unsigned sizeSIBByte(){
2795  return 1;
2796}
2797
2798static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2799  unsigned FinalSize = 0;
2800  // If this is a simple integer displacement that doesn't require a relocation.
2801  if (!RelocOp) {
2802    FinalSize += sizeConstant(4);
2803    return FinalSize;
2804  }
2805
2806  // Otherwise, this is something that requires a relocation.
2807  if (RelocOp->isGlobal()) {
2808    FinalSize += sizeGlobalAddress(false);
2809  } else if (RelocOp->isCPI()) {
2810    FinalSize += sizeConstPoolAddress(false);
2811  } else if (RelocOp->isJTI()) {
2812    FinalSize += sizeJumpTableAddress(false);
2813  } else {
2814    llvm_unreachable("Unknown value to relocate!");
2815  }
2816  return FinalSize;
2817}
2818
2819static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2820                                    bool IsPIC, bool Is64BitMode) {
2821  const MachineOperand &Op3 = MI.getOperand(Op+3);
2822  int DispVal = 0;
2823  const MachineOperand *DispForReloc = 0;
2824  unsigned FinalSize = 0;
2825
2826  // Figure out what sort of displacement we have to handle here.
2827  if (Op3.isGlobal()) {
2828    DispForReloc = &Op3;
2829  } else if (Op3.isCPI()) {
2830    if (Is64BitMode || IsPIC) {
2831      DispForReloc = &Op3;
2832    } else {
2833      DispVal = 1;
2834    }
2835  } else if (Op3.isJTI()) {
2836    if (Is64BitMode || IsPIC) {
2837      DispForReloc = &Op3;
2838    } else {
2839      DispVal = 1;
2840    }
2841  } else {
2842    DispVal = 1;
2843  }
2844
2845  const MachineOperand &Base     = MI.getOperand(Op);
2846  const MachineOperand &IndexReg = MI.getOperand(Op+2);
2847
2848  unsigned BaseReg = Base.getReg();
2849
2850  // Is a SIB byte needed?
2851  if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
2852      IndexReg.getReg() == 0 &&
2853      (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2854    if (BaseReg == 0) {  // Just a displacement?
2855      // Emit special case [disp32] encoding
2856      ++FinalSize;
2857      FinalSize += getDisplacementFieldSize(DispForReloc);
2858    } else {
2859      unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2860      if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2861        // Emit simple indirect register encoding... [EAX] f.e.
2862        ++FinalSize;
2863      // Be pessimistic and assume it's a disp32, not a disp8
2864      } else {
2865        // Emit the most general non-SIB encoding: [REG+disp32]
2866        ++FinalSize;
2867        FinalSize += getDisplacementFieldSize(DispForReloc);
2868      }
2869    }
2870
2871  } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
2872    assert(IndexReg.getReg() != X86::ESP &&
2873           IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2874
2875    bool ForceDisp32 = false;
2876    if (BaseReg == 0 || DispForReloc) {
2877      // Emit the normal disp32 encoding.
2878      ++FinalSize;
2879      ForceDisp32 = true;
2880    } else {
2881      ++FinalSize;
2882    }
2883
2884    FinalSize += sizeSIBByte();
2885
2886    // Do we need to output a displacement?
2887    if (DispVal != 0 || ForceDisp32) {
2888      FinalSize += getDisplacementFieldSize(DispForReloc);
2889    }
2890  }
2891  return FinalSize;
2892}
2893
2894
2895static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2896                                    const TargetInstrDesc *Desc,
2897                                    bool IsPIC, bool Is64BitMode) {
2898
2899  unsigned Opcode = Desc->Opcode;
2900  unsigned FinalSize = 0;
2901
2902  // Emit the lock opcode prefix as needed.
2903  if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2904
2905  // Emit segment override opcode prefix as needed.
2906  switch (Desc->TSFlags & X86II::SegOvrMask) {
2907  case X86II::FS:
2908  case X86II::GS:
2909   ++FinalSize;
2910   break;
2911  default: llvm_unreachable("Invalid segment!");
2912  case 0: break;  // No segment override!
2913  }
2914
2915  // Emit the repeat opcode prefix as needed.
2916  if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2917
2918  // Emit the operand size opcode prefix as needed.
2919  if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2920
2921  // Emit the address size opcode prefix as needed.
2922  if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2923
2924  bool Need0FPrefix = false;
2925  switch (Desc->TSFlags & X86II::Op0Mask) {
2926  case X86II::TB:  // Two-byte opcode prefix
2927  case X86II::T8:  // 0F 38
2928  case X86II::TA:  // 0F 3A
2929    Need0FPrefix = true;
2930    break;
2931  case X86II::TF: // F2 0F 38
2932    ++FinalSize;
2933    Need0FPrefix = true;
2934    break;
2935  case X86II::REP: break; // already handled.
2936  case X86II::XS:   // F3 0F
2937    ++FinalSize;
2938    Need0FPrefix = true;
2939    break;
2940  case X86II::XD:   // F2 0F
2941    ++FinalSize;
2942    Need0FPrefix = true;
2943    break;
2944  case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2945  case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2946    ++FinalSize;
2947    break; // Two-byte opcode prefix
2948  default: llvm_unreachable("Invalid prefix!");
2949  case 0: break;  // No prefix!
2950  }
2951
2952  if (Is64BitMode) {
2953    // REX prefix
2954    unsigned REX = X86InstrInfo::determineREX(MI);
2955    if (REX)
2956      ++FinalSize;
2957  }
2958
2959  // 0x0F escape code must be emitted just before the opcode.
2960  if (Need0FPrefix)
2961    ++FinalSize;
2962
2963  switch (Desc->TSFlags & X86II::Op0Mask) {
2964  case X86II::T8:  // 0F 38
2965    ++FinalSize;
2966    break;
2967  case X86II::TA:  // 0F 3A
2968    ++FinalSize;
2969    break;
2970  case X86II::TF: // F2 0F 38
2971    ++FinalSize;
2972    break;
2973  }
2974
2975  // If this is a two-address instruction, skip one of the register operands.
2976  unsigned NumOps = Desc->getNumOperands();
2977  unsigned CurOp = 0;
2978  if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
2979    CurOp++;
2980  else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
2981    // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
2982    --NumOps;
2983
2984  switch (Desc->TSFlags & X86II::FormMask) {
2985  default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
2986  case X86II::Pseudo:
2987    // Remember the current PC offset, this is the PIC relocation
2988    // base address.
2989    switch (Opcode) {
2990    default:
2991      break;
2992    case TargetInstrInfo::INLINEASM: {
2993      const MachineFunction *MF = MI.getParent()->getParent();
2994      const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
2995      FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
2996                                          *MF->getTarget().getMCAsmInfo());
2997      break;
2998    }
2999    case TargetInstrInfo::DBG_LABEL:
3000    case TargetInstrInfo::EH_LABEL:
3001      break;
3002    case TargetInstrInfo::IMPLICIT_DEF:
3003    case X86::DWARF_LOC:
3004    case X86::FP_REG_KILL:
3005      break;
3006    case X86::MOVPC32r: {
3007      // This emits the "call" portion of this pseudo instruction.
3008      ++FinalSize;
3009      FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3010      break;
3011    }
3012    }
3013    CurOp = NumOps;
3014    break;
3015  case X86II::RawFrm:
3016    ++FinalSize;
3017
3018    if (CurOp != NumOps) {
3019      const MachineOperand &MO = MI.getOperand(CurOp++);
3020      if (MO.isMBB()) {
3021        FinalSize += sizePCRelativeBlockAddress();
3022      } else if (MO.isGlobal()) {
3023        FinalSize += sizeGlobalAddress(false);
3024      } else if (MO.isSymbol()) {
3025        FinalSize += sizeExternalSymbolAddress(false);
3026      } else if (MO.isImm()) {
3027        FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3028      } else {
3029        llvm_unreachable("Unknown RawFrm operand!");
3030      }
3031    }
3032    break;
3033
3034  case X86II::AddRegFrm:
3035    ++FinalSize;
3036    ++CurOp;
3037
3038    if (CurOp != NumOps) {
3039      const MachineOperand &MO1 = MI.getOperand(CurOp++);
3040      unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3041      if (MO1.isImm())
3042        FinalSize += sizeConstant(Size);
3043      else {
3044        bool dword = false;
3045        if (Opcode == X86::MOV64ri)
3046          dword = true;
3047        if (MO1.isGlobal()) {
3048          FinalSize += sizeGlobalAddress(dword);
3049        } else if (MO1.isSymbol())
3050          FinalSize += sizeExternalSymbolAddress(dword);
3051        else if (MO1.isCPI())
3052          FinalSize += sizeConstPoolAddress(dword);
3053        else if (MO1.isJTI())
3054          FinalSize += sizeJumpTableAddress(dword);
3055      }
3056    }
3057    break;
3058
3059  case X86II::MRMDestReg: {
3060    ++FinalSize;
3061    FinalSize += sizeRegModRMByte();
3062    CurOp += 2;
3063    if (CurOp != NumOps) {
3064      ++CurOp;
3065      FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3066    }
3067    break;
3068  }
3069  case X86II::MRMDestMem: {
3070    ++FinalSize;
3071    FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3072    CurOp +=  X86AddrNumOperands + 1;
3073    if (CurOp != NumOps) {
3074      ++CurOp;
3075      FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3076    }
3077    break;
3078  }
3079
3080  case X86II::MRMSrcReg:
3081    ++FinalSize;
3082    FinalSize += sizeRegModRMByte();
3083    CurOp += 2;
3084    if (CurOp != NumOps) {
3085      ++CurOp;
3086      FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3087    }
3088    break;
3089
3090  case X86II::MRMSrcMem: {
3091    int AddrOperands;
3092    if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3093        Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3094      AddrOperands = X86AddrNumOperands - 1; // No segment register
3095    else
3096      AddrOperands = X86AddrNumOperands;
3097
3098    ++FinalSize;
3099    FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3100    CurOp += AddrOperands + 1;
3101    if (CurOp != NumOps) {
3102      ++CurOp;
3103      FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3104    }
3105    break;
3106  }
3107
3108  case X86II::MRM0r: case X86II::MRM1r:
3109  case X86II::MRM2r: case X86II::MRM3r:
3110  case X86II::MRM4r: case X86II::MRM5r:
3111  case X86II::MRM6r: case X86II::MRM7r:
3112    ++FinalSize;
3113    if (Desc->getOpcode() == X86::LFENCE ||
3114        Desc->getOpcode() == X86::MFENCE) {
3115      // Special handling of lfence and mfence;
3116      FinalSize += sizeRegModRMByte();
3117    } else if (Desc->getOpcode() == X86::MONITOR ||
3118               Desc->getOpcode() == X86::MWAIT) {
3119      // Special handling of monitor and mwait.
3120      FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3121    } else {
3122      ++CurOp;
3123      FinalSize += sizeRegModRMByte();
3124    }
3125
3126    if (CurOp != NumOps) {
3127      const MachineOperand &MO1 = MI.getOperand(CurOp++);
3128      unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3129      if (MO1.isImm())
3130        FinalSize += sizeConstant(Size);
3131      else {
3132        bool dword = false;
3133        if (Opcode == X86::MOV64ri32)
3134          dword = true;
3135        if (MO1.isGlobal()) {
3136          FinalSize += sizeGlobalAddress(dword);
3137        } else if (MO1.isSymbol())
3138          FinalSize += sizeExternalSymbolAddress(dword);
3139        else if (MO1.isCPI())
3140          FinalSize += sizeConstPoolAddress(dword);
3141        else if (MO1.isJTI())
3142          FinalSize += sizeJumpTableAddress(dword);
3143      }
3144    }
3145    break;
3146
3147  case X86II::MRM0m: case X86II::MRM1m:
3148  case X86II::MRM2m: case X86II::MRM3m:
3149  case X86II::MRM4m: case X86II::MRM5m:
3150  case X86II::MRM6m: case X86II::MRM7m: {
3151
3152    ++FinalSize;
3153    FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3154    CurOp += X86AddrNumOperands;
3155
3156    if (CurOp != NumOps) {
3157      const MachineOperand &MO = MI.getOperand(CurOp++);
3158      unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3159      if (MO.isImm())
3160        FinalSize += sizeConstant(Size);
3161      else {
3162        bool dword = false;
3163        if (Opcode == X86::MOV64mi32)
3164          dword = true;
3165        if (MO.isGlobal()) {
3166          FinalSize += sizeGlobalAddress(dword);
3167        } else if (MO.isSymbol())
3168          FinalSize += sizeExternalSymbolAddress(dword);
3169        else if (MO.isCPI())
3170          FinalSize += sizeConstPoolAddress(dword);
3171        else if (MO.isJTI())
3172          FinalSize += sizeJumpTableAddress(dword);
3173      }
3174    }
3175    break;
3176  }
3177
3178  case X86II::MRMInitReg:
3179    ++FinalSize;
3180    // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3181    FinalSize += sizeRegModRMByte();
3182    ++CurOp;
3183    break;
3184  }
3185
3186  if (!Desc->isVariadic() && CurOp != NumOps) {
3187    std::string msg;
3188    raw_string_ostream Msg(msg);
3189    Msg << "Cannot determine size: " << MI;
3190    llvm_report_error(Msg.str());
3191  }
3192
3193
3194  return FinalSize;
3195}
3196
3197
3198unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3199  const TargetInstrDesc &Desc = MI->getDesc();
3200  bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3201  bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3202  unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3203  if (Desc.getOpcode() == X86::MOVPC32r)
3204    Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3205  return Size;
3206}
3207
3208/// getGlobalBaseReg - Return a virtual register initialized with the
3209/// the global base register value. Output instructions required to
3210/// initialize the register in the function entry block, if necessary.
3211///
3212unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3213  assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3214         "X86-64 PIC uses RIP relative addressing");
3215
3216  X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3217  unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3218  if (GlobalBaseReg != 0)
3219    return GlobalBaseReg;
3220
3221  // Insert the set of GlobalBaseReg into the first MBB of the function
3222  MachineBasicBlock &FirstMBB = MF->front();
3223  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3224  DebugLoc DL = DebugLoc::getUnknownLoc();
3225  if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3226  MachineRegisterInfo &RegInfo = MF->getRegInfo();
3227  unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3228
3229  const TargetInstrInfo *TII = TM.getInstrInfo();
3230  // Operand of MovePCtoStack is completely ignored by asm printer. It's
3231  // only used in JIT code emission as displacement to pc.
3232  BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3233
3234  // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3235  // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3236  if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3237    GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3238    // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3239    BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3240      .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3241                                    X86II::MO_GOT_ABSOLUTE_ADDRESS);
3242  } else {
3243    GlobalBaseReg = PC;
3244  }
3245
3246  X86FI->setGlobalBaseReg(GlobalBaseReg);
3247  return GlobalBaseReg;
3248}
3249