X86InstrInfo.cpp revision c8ea673bc0e19f36738bec998fe27fad01bf9749
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86Subtarget.h" 20#include "X86TargetMachine.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/ADT/STLExtras.h" 24#include "llvm/CodeGen/MachineConstantPool.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/LiveVariables.h" 29#include "llvm/CodeGen/PseudoSourceValue.h" 30#include "llvm/MC/MCInst.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetOptions.h" 36#include "llvm/MC/MCAsmInfo.h" 37 38#include <limits> 39 40using namespace llvm; 41 42static cl::opt<bool> 43NoFusing("disable-spill-fusing", 44 cl::desc("Disable fusing of spill code into instructions")); 45static cl::opt<bool> 46PrintFailedFusing("print-failed-fuse-candidates", 47 cl::desc("Print instructions that the allocator wants to" 48 " fuse, but the X86 backend currently can't"), 49 cl::Hidden); 50static cl::opt<bool> 51ReMatPICStubLoad("remat-pic-stub-load", 52 cl::desc("Re-materialize load from stub in PIC mode"), 53 cl::init(false), cl::Hidden); 54 55X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 56 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), 57 TM(tm), RI(tm, *this) { 58 SmallVector<unsigned,16> AmbEntries; 59 static const unsigned OpTbl2Addr[][2] = { 60 { X86::ADC32ri, X86::ADC32mi }, 61 { X86::ADC32ri8, X86::ADC32mi8 }, 62 { X86::ADC32rr, X86::ADC32mr }, 63 { X86::ADC64ri32, X86::ADC64mi32 }, 64 { X86::ADC64ri8, X86::ADC64mi8 }, 65 { X86::ADC64rr, X86::ADC64mr }, 66 { X86::ADD16ri, X86::ADD16mi }, 67 { X86::ADD16ri8, X86::ADD16mi8 }, 68 { X86::ADD16rr, X86::ADD16mr }, 69 { X86::ADD32ri, X86::ADD32mi }, 70 { X86::ADD32ri8, X86::ADD32mi8 }, 71 { X86::ADD32rr, X86::ADD32mr }, 72 { X86::ADD64ri32, X86::ADD64mi32 }, 73 { X86::ADD64ri8, X86::ADD64mi8 }, 74 { X86::ADD64rr, X86::ADD64mr }, 75 { X86::ADD8ri, X86::ADD8mi }, 76 { X86::ADD8rr, X86::ADD8mr }, 77 { X86::AND16ri, X86::AND16mi }, 78 { X86::AND16ri8, X86::AND16mi8 }, 79 { X86::AND16rr, X86::AND16mr }, 80 { X86::AND32ri, X86::AND32mi }, 81 { X86::AND32ri8, X86::AND32mi8 }, 82 { X86::AND32rr, X86::AND32mr }, 83 { X86::AND64ri32, X86::AND64mi32 }, 84 { X86::AND64ri8, X86::AND64mi8 }, 85 { X86::AND64rr, X86::AND64mr }, 86 { X86::AND8ri, X86::AND8mi }, 87 { X86::AND8rr, X86::AND8mr }, 88 { X86::DEC16r, X86::DEC16m }, 89 { X86::DEC32r, X86::DEC32m }, 90 { X86::DEC64_16r, X86::DEC64_16m }, 91 { X86::DEC64_32r, X86::DEC64_32m }, 92 { X86::DEC64r, X86::DEC64m }, 93 { X86::DEC8r, X86::DEC8m }, 94 { X86::INC16r, X86::INC16m }, 95 { X86::INC32r, X86::INC32m }, 96 { X86::INC64_16r, X86::INC64_16m }, 97 { X86::INC64_32r, X86::INC64_32m }, 98 { X86::INC64r, X86::INC64m }, 99 { X86::INC8r, X86::INC8m }, 100 { X86::NEG16r, X86::NEG16m }, 101 { X86::NEG32r, X86::NEG32m }, 102 { X86::NEG64r, X86::NEG64m }, 103 { X86::NEG8r, X86::NEG8m }, 104 { X86::NOT16r, X86::NOT16m }, 105 { X86::NOT32r, X86::NOT32m }, 106 { X86::NOT64r, X86::NOT64m }, 107 { X86::NOT8r, X86::NOT8m }, 108 { X86::OR16ri, X86::OR16mi }, 109 { X86::OR16ri8, X86::OR16mi8 }, 110 { X86::OR16rr, X86::OR16mr }, 111 { X86::OR32ri, X86::OR32mi }, 112 { X86::OR32ri8, X86::OR32mi8 }, 113 { X86::OR32rr, X86::OR32mr }, 114 { X86::OR64ri32, X86::OR64mi32 }, 115 { X86::OR64ri8, X86::OR64mi8 }, 116 { X86::OR64rr, X86::OR64mr }, 117 { X86::OR8ri, X86::OR8mi }, 118 { X86::OR8rr, X86::OR8mr }, 119 { X86::ROL16r1, X86::ROL16m1 }, 120 { X86::ROL16rCL, X86::ROL16mCL }, 121 { X86::ROL16ri, X86::ROL16mi }, 122 { X86::ROL32r1, X86::ROL32m1 }, 123 { X86::ROL32rCL, X86::ROL32mCL }, 124 { X86::ROL32ri, X86::ROL32mi }, 125 { X86::ROL64r1, X86::ROL64m1 }, 126 { X86::ROL64rCL, X86::ROL64mCL }, 127 { X86::ROL64ri, X86::ROL64mi }, 128 { X86::ROL8r1, X86::ROL8m1 }, 129 { X86::ROL8rCL, X86::ROL8mCL }, 130 { X86::ROL8ri, X86::ROL8mi }, 131 { X86::ROR16r1, X86::ROR16m1 }, 132 { X86::ROR16rCL, X86::ROR16mCL }, 133 { X86::ROR16ri, X86::ROR16mi }, 134 { X86::ROR32r1, X86::ROR32m1 }, 135 { X86::ROR32rCL, X86::ROR32mCL }, 136 { X86::ROR32ri, X86::ROR32mi }, 137 { X86::ROR64r1, X86::ROR64m1 }, 138 { X86::ROR64rCL, X86::ROR64mCL }, 139 { X86::ROR64ri, X86::ROR64mi }, 140 { X86::ROR8r1, X86::ROR8m1 }, 141 { X86::ROR8rCL, X86::ROR8mCL }, 142 { X86::ROR8ri, X86::ROR8mi }, 143 { X86::SAR16r1, X86::SAR16m1 }, 144 { X86::SAR16rCL, X86::SAR16mCL }, 145 { X86::SAR16ri, X86::SAR16mi }, 146 { X86::SAR32r1, X86::SAR32m1 }, 147 { X86::SAR32rCL, X86::SAR32mCL }, 148 { X86::SAR32ri, X86::SAR32mi }, 149 { X86::SAR64r1, X86::SAR64m1 }, 150 { X86::SAR64rCL, X86::SAR64mCL }, 151 { X86::SAR64ri, X86::SAR64mi }, 152 { X86::SAR8r1, X86::SAR8m1 }, 153 { X86::SAR8rCL, X86::SAR8mCL }, 154 { X86::SAR8ri, X86::SAR8mi }, 155 { X86::SBB32ri, X86::SBB32mi }, 156 { X86::SBB32ri8, X86::SBB32mi8 }, 157 { X86::SBB32rr, X86::SBB32mr }, 158 { X86::SBB64ri32, X86::SBB64mi32 }, 159 { X86::SBB64ri8, X86::SBB64mi8 }, 160 { X86::SBB64rr, X86::SBB64mr }, 161 { X86::SHL16rCL, X86::SHL16mCL }, 162 { X86::SHL16ri, X86::SHL16mi }, 163 { X86::SHL32rCL, X86::SHL32mCL }, 164 { X86::SHL32ri, X86::SHL32mi }, 165 { X86::SHL64rCL, X86::SHL64mCL }, 166 { X86::SHL64ri, X86::SHL64mi }, 167 { X86::SHL8rCL, X86::SHL8mCL }, 168 { X86::SHL8ri, X86::SHL8mi }, 169 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 170 { X86::SHLD16rri8, X86::SHLD16mri8 }, 171 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 172 { X86::SHLD32rri8, X86::SHLD32mri8 }, 173 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 174 { X86::SHLD64rri8, X86::SHLD64mri8 }, 175 { X86::SHR16r1, X86::SHR16m1 }, 176 { X86::SHR16rCL, X86::SHR16mCL }, 177 { X86::SHR16ri, X86::SHR16mi }, 178 { X86::SHR32r1, X86::SHR32m1 }, 179 { X86::SHR32rCL, X86::SHR32mCL }, 180 { X86::SHR32ri, X86::SHR32mi }, 181 { X86::SHR64r1, X86::SHR64m1 }, 182 { X86::SHR64rCL, X86::SHR64mCL }, 183 { X86::SHR64ri, X86::SHR64mi }, 184 { X86::SHR8r1, X86::SHR8m1 }, 185 { X86::SHR8rCL, X86::SHR8mCL }, 186 { X86::SHR8ri, X86::SHR8mi }, 187 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 188 { X86::SHRD16rri8, X86::SHRD16mri8 }, 189 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 190 { X86::SHRD32rri8, X86::SHRD32mri8 }, 191 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 192 { X86::SHRD64rri8, X86::SHRD64mri8 }, 193 { X86::SUB16ri, X86::SUB16mi }, 194 { X86::SUB16ri8, X86::SUB16mi8 }, 195 { X86::SUB16rr, X86::SUB16mr }, 196 { X86::SUB32ri, X86::SUB32mi }, 197 { X86::SUB32ri8, X86::SUB32mi8 }, 198 { X86::SUB32rr, X86::SUB32mr }, 199 { X86::SUB64ri32, X86::SUB64mi32 }, 200 { X86::SUB64ri8, X86::SUB64mi8 }, 201 { X86::SUB64rr, X86::SUB64mr }, 202 { X86::SUB8ri, X86::SUB8mi }, 203 { X86::SUB8rr, X86::SUB8mr }, 204 { X86::XOR16ri, X86::XOR16mi }, 205 { X86::XOR16ri8, X86::XOR16mi8 }, 206 { X86::XOR16rr, X86::XOR16mr }, 207 { X86::XOR32ri, X86::XOR32mi }, 208 { X86::XOR32ri8, X86::XOR32mi8 }, 209 { X86::XOR32rr, X86::XOR32mr }, 210 { X86::XOR64ri32, X86::XOR64mi32 }, 211 { X86::XOR64ri8, X86::XOR64mi8 }, 212 { X86::XOR64rr, X86::XOR64mr }, 213 { X86::XOR8ri, X86::XOR8mi }, 214 { X86::XOR8rr, X86::XOR8mr } 215 }; 216 217 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 218 unsigned RegOp = OpTbl2Addr[i][0]; 219 unsigned MemOp = OpTbl2Addr[i][1]; 220 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, 221 std::make_pair(MemOp,0))).second) 222 assert(false && "Duplicated entries?"); 223 // Index 0, folded load and store, no alignment requirement. 224 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); 225 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 226 std::make_pair(RegOp, 227 AuxInfo))).second) 228 AmbEntries.push_back(MemOp); 229 } 230 231 // If the third value is 1, then it's folding either a load or a store. 232 static const unsigned OpTbl0[][4] = { 233 { X86::BT16ri8, X86::BT16mi8, 1, 0 }, 234 { X86::BT32ri8, X86::BT32mi8, 1, 0 }, 235 { X86::BT64ri8, X86::BT64mi8, 1, 0 }, 236 { X86::CALL32r, X86::CALL32m, 1, 0 }, 237 { X86::CALL64r, X86::CALL64m, 1, 0 }, 238 { X86::CMP16ri, X86::CMP16mi, 1, 0 }, 239 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 }, 240 { X86::CMP16rr, X86::CMP16mr, 1, 0 }, 241 { X86::CMP32ri, X86::CMP32mi, 1, 0 }, 242 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 }, 243 { X86::CMP32rr, X86::CMP32mr, 1, 0 }, 244 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 }, 245 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 }, 246 { X86::CMP64rr, X86::CMP64mr, 1, 0 }, 247 { X86::CMP8ri, X86::CMP8mi, 1, 0 }, 248 { X86::CMP8rr, X86::CMP8mr, 1, 0 }, 249 { X86::DIV16r, X86::DIV16m, 1, 0 }, 250 { X86::DIV32r, X86::DIV32m, 1, 0 }, 251 { X86::DIV64r, X86::DIV64m, 1, 0 }, 252 { X86::DIV8r, X86::DIV8m, 1, 0 }, 253 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 }, 254 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 }, 255 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 }, 256 { X86::IDIV16r, X86::IDIV16m, 1, 0 }, 257 { X86::IDIV32r, X86::IDIV32m, 1, 0 }, 258 { X86::IDIV64r, X86::IDIV64m, 1, 0 }, 259 { X86::IDIV8r, X86::IDIV8m, 1, 0 }, 260 { X86::IMUL16r, X86::IMUL16m, 1, 0 }, 261 { X86::IMUL32r, X86::IMUL32m, 1, 0 }, 262 { X86::IMUL64r, X86::IMUL64m, 1, 0 }, 263 { X86::IMUL8r, X86::IMUL8m, 1, 0 }, 264 { X86::JMP32r, X86::JMP32m, 1, 0 }, 265 { X86::JMP64r, X86::JMP64m, 1, 0 }, 266 { X86::MOV16ri, X86::MOV16mi, 0, 0 }, 267 { X86::MOV16rr, X86::MOV16mr, 0, 0 }, 268 { X86::MOV32ri, X86::MOV32mi, 0, 0 }, 269 { X86::MOV32rr, X86::MOV32mr, 0, 0 }, 270 { X86::MOV32rr_TC, X86::MOV32mr_TC, 0, 0 }, 271 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 }, 272 { X86::MOV64rr, X86::MOV64mr, 0, 0 }, 273 { X86::MOV8ri, X86::MOV8mi, 0, 0 }, 274 { X86::MOV8rr, X86::MOV8mr, 0, 0 }, 275 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 }, 276 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 }, 277 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 }, 278 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 }, 279 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 }, 280 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 }, 281 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 }, 282 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 }, 283 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 }, 284 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 }, 285 { X86::MUL16r, X86::MUL16m, 1, 0 }, 286 { X86::MUL32r, X86::MUL32m, 1, 0 }, 287 { X86::MUL64r, X86::MUL64m, 1, 0 }, 288 { X86::MUL8r, X86::MUL8m, 1, 0 }, 289 { X86::SETAEr, X86::SETAEm, 0, 0 }, 290 { X86::SETAr, X86::SETAm, 0, 0 }, 291 { X86::SETBEr, X86::SETBEm, 0, 0 }, 292 { X86::SETBr, X86::SETBm, 0, 0 }, 293 { X86::SETEr, X86::SETEm, 0, 0 }, 294 { X86::SETGEr, X86::SETGEm, 0, 0 }, 295 { X86::SETGr, X86::SETGm, 0, 0 }, 296 { X86::SETLEr, X86::SETLEm, 0, 0 }, 297 { X86::SETLr, X86::SETLm, 0, 0 }, 298 { X86::SETNEr, X86::SETNEm, 0, 0 }, 299 { X86::SETNOr, X86::SETNOm, 0, 0 }, 300 { X86::SETNPr, X86::SETNPm, 0, 0 }, 301 { X86::SETNSr, X86::SETNSm, 0, 0 }, 302 { X86::SETOr, X86::SETOm, 0, 0 }, 303 { X86::SETPr, X86::SETPm, 0, 0 }, 304 { X86::SETSr, X86::SETSm, 0, 0 }, 305 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 }, 306 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 }, 307 { X86::TEST16ri, X86::TEST16mi, 1, 0 }, 308 { X86::TEST32ri, X86::TEST32mi, 1, 0 }, 309 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 }, 310 { X86::TEST8ri, X86::TEST8mi, 1, 0 } 311 }; 312 313 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 314 unsigned RegOp = OpTbl0[i][0]; 315 unsigned MemOp = OpTbl0[i][1]; 316 unsigned Align = OpTbl0[i][3]; 317 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, 318 std::make_pair(MemOp,Align))).second) 319 assert(false && "Duplicated entries?"); 320 unsigned FoldedLoad = OpTbl0[i][2]; 321 // Index 0, folded load or store. 322 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); 323 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 324 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 325 std::make_pair(RegOp, AuxInfo))).second) 326 AmbEntries.push_back(MemOp); 327 } 328 329 static const unsigned OpTbl1[][3] = { 330 { X86::CMP16rr, X86::CMP16rm, 0 }, 331 { X86::CMP32rr, X86::CMP32rm, 0 }, 332 { X86::CMP64rr, X86::CMP64rm, 0 }, 333 { X86::CMP8rr, X86::CMP8rm, 0 }, 334 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 335 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 336 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 337 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 338 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 339 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 340 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 341 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 342 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 343 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 344 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 }, 345 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 }, 346 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 347 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 348 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 349 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 350 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 351 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 352 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 353 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 354 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 355 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 356 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 }, 357 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 }, 358 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 }, 359 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 }, 360 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 }, 361 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 }, 362 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 }, 363 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 }, 364 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 365 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 366 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 367 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 368 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 369 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 370 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 }, 371 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 }, 372 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 }, 373 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 }, 374 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 375 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 376 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 377 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 378 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 379 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 380 { X86::MOV16rr, X86::MOV16rm, 0 }, 381 { X86::MOV32rr, X86::MOV32rm, 0 }, 382 { X86::MOV32rr_TC, X86::MOV32rm_TC, 0 }, 383 { X86::MOV64rr, X86::MOV64rm, 0 }, 384 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 385 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 386 { X86::MOV8rr, X86::MOV8rm, 0 }, 387 { X86::MOVAPDrr, X86::MOVAPDrm, 16 }, 388 { X86::MOVAPSrr, X86::MOVAPSrm, 16 }, 389 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 390 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 391 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 392 { X86::MOVDQArr, X86::MOVDQArm, 16 }, 393 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 }, 394 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 }, 395 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 396 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 397 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 398 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 399 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 400 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 401 { X86::MOVUPDrr, X86::MOVUPDrm, 16 }, 402 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 403 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 404 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 405 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 }, 406 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 407 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 408 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 409 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 410 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 411 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 412 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 413 { X86::PSHUFDri, X86::PSHUFDmi, 16 }, 414 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 }, 415 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 }, 416 { X86::RCPPSr, X86::RCPPSm, 16 }, 417 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 }, 418 { X86::RSQRTPSr, X86::RSQRTPSm, 16 }, 419 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 }, 420 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 421 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 422 { X86::SQRTPDr, X86::SQRTPDm, 16 }, 423 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 }, 424 { X86::SQRTPSr, X86::SQRTPSm, 16 }, 425 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 }, 426 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 427 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 428 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 429 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 430 { X86::TEST16rr, X86::TEST16rm, 0 }, 431 { X86::TEST32rr, X86::TEST32rm, 0 }, 432 { X86::TEST64rr, X86::TEST64rm, 0 }, 433 { X86::TEST8rr, X86::TEST8rm, 0 }, 434 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 435 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 436 { X86::UCOMISSrr, X86::UCOMISSrm, 0 } 437 }; 438 439 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 440 unsigned RegOp = OpTbl1[i][0]; 441 unsigned MemOp = OpTbl1[i][1]; 442 unsigned Align = OpTbl1[i][2]; 443 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, 444 std::make_pair(MemOp,Align))).second) 445 assert(false && "Duplicated entries?"); 446 // Index 1, folded load 447 unsigned AuxInfo = 1 | (1 << 4); 448 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 449 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 450 std::make_pair(RegOp, AuxInfo))).second) 451 AmbEntries.push_back(MemOp); 452 } 453 454 static const unsigned OpTbl2[][3] = { 455 { X86::ADC32rr, X86::ADC32rm, 0 }, 456 { X86::ADC64rr, X86::ADC64rm, 0 }, 457 { X86::ADD16rr, X86::ADD16rm, 0 }, 458 { X86::ADD32rr, X86::ADD32rm, 0 }, 459 { X86::ADD64rr, X86::ADD64rm, 0 }, 460 { X86::ADD8rr, X86::ADD8rm, 0 }, 461 { X86::ADDPDrr, X86::ADDPDrm, 16 }, 462 { X86::ADDPSrr, X86::ADDPSrm, 16 }, 463 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 464 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 465 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 }, 466 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 }, 467 { X86::AND16rr, X86::AND16rm, 0 }, 468 { X86::AND32rr, X86::AND32rm, 0 }, 469 { X86::AND64rr, X86::AND64rm, 0 }, 470 { X86::AND8rr, X86::AND8rm, 0 }, 471 { X86::ANDNPDrr, X86::ANDNPDrm, 16 }, 472 { X86::ANDNPSrr, X86::ANDNPSrm, 16 }, 473 { X86::ANDPDrr, X86::ANDPDrm, 16 }, 474 { X86::ANDPSrr, X86::ANDPSrm, 16 }, 475 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 476 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 477 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 478 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 479 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 480 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 481 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 482 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 483 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 484 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 485 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 486 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 487 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 488 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 489 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 490 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 491 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 492 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 493 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 494 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 495 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 496 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 497 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 498 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 499 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 500 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 501 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 502 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 503 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 504 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 505 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 506 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 507 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 508 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 509 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 510 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 511 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 512 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 513 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 514 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 515 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 516 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 517 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 518 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 519 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 520 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 521 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 522 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 523 { X86::CMPPDrri, X86::CMPPDrmi, 16 }, 524 { X86::CMPPSrri, X86::CMPPSrmi, 16 }, 525 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 526 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 527 { X86::DIVPDrr, X86::DIVPDrm, 16 }, 528 { X86::DIVPSrr, X86::DIVPSrm, 16 }, 529 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 530 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 531 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 }, 532 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 }, 533 { X86::FsANDPDrr, X86::FsANDPDrm, 16 }, 534 { X86::FsANDPSrr, X86::FsANDPSrm, 16 }, 535 { X86::FsORPDrr, X86::FsORPDrm, 16 }, 536 { X86::FsORPSrr, X86::FsORPSrm, 16 }, 537 { X86::FsXORPDrr, X86::FsXORPDrm, 16 }, 538 { X86::FsXORPSrr, X86::FsXORPSrm, 16 }, 539 { X86::HADDPDrr, X86::HADDPDrm, 16 }, 540 { X86::HADDPSrr, X86::HADDPSrm, 16 }, 541 { X86::HSUBPDrr, X86::HSUBPDrm, 16 }, 542 { X86::HSUBPSrr, X86::HSUBPSrm, 16 }, 543 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 544 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 545 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 546 { X86::MAXPDrr, X86::MAXPDrm, 16 }, 547 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 }, 548 { X86::MAXPSrr, X86::MAXPSrm, 16 }, 549 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 }, 550 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 551 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 552 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 553 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 554 { X86::MINPDrr, X86::MINPDrm, 16 }, 555 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 }, 556 { X86::MINPSrr, X86::MINPSrm, 16 }, 557 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 }, 558 { X86::MINSDrr, X86::MINSDrm, 0 }, 559 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 560 { X86::MINSSrr, X86::MINSSrm, 0 }, 561 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 562 { X86::MULPDrr, X86::MULPDrm, 16 }, 563 { X86::MULPSrr, X86::MULPSrm, 16 }, 564 { X86::MULSDrr, X86::MULSDrm, 0 }, 565 { X86::MULSSrr, X86::MULSSrm, 0 }, 566 { X86::OR16rr, X86::OR16rm, 0 }, 567 { X86::OR32rr, X86::OR32rm, 0 }, 568 { X86::OR64rr, X86::OR64rm, 0 }, 569 { X86::OR8rr, X86::OR8rm, 0 }, 570 { X86::ORPDrr, X86::ORPDrm, 16 }, 571 { X86::ORPSrr, X86::ORPSrm, 16 }, 572 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 }, 573 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 }, 574 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 }, 575 { X86::PADDBrr, X86::PADDBrm, 16 }, 576 { X86::PADDDrr, X86::PADDDrm, 16 }, 577 { X86::PADDQrr, X86::PADDQrm, 16 }, 578 { X86::PADDSBrr, X86::PADDSBrm, 16 }, 579 { X86::PADDSWrr, X86::PADDSWrm, 16 }, 580 { X86::PADDWrr, X86::PADDWrm, 16 }, 581 { X86::PANDNrr, X86::PANDNrm, 16 }, 582 { X86::PANDrr, X86::PANDrm, 16 }, 583 { X86::PAVGBrr, X86::PAVGBrm, 16 }, 584 { X86::PAVGWrr, X86::PAVGWrm, 16 }, 585 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 }, 586 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 }, 587 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 }, 588 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 }, 589 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 }, 590 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 }, 591 { X86::PINSRWrri, X86::PINSRWrmi, 16 }, 592 { X86::PMADDWDrr, X86::PMADDWDrm, 16 }, 593 { X86::PMAXSWrr, X86::PMAXSWrm, 16 }, 594 { X86::PMAXUBrr, X86::PMAXUBrm, 16 }, 595 { X86::PMINSWrr, X86::PMINSWrm, 16 }, 596 { X86::PMINUBrr, X86::PMINUBrm, 16 }, 597 { X86::PMULDQrr, X86::PMULDQrm, 16 }, 598 { X86::PMULHUWrr, X86::PMULHUWrm, 16 }, 599 { X86::PMULHWrr, X86::PMULHWrm, 16 }, 600 { X86::PMULLDrr, X86::PMULLDrm, 16 }, 601 { X86::PMULLWrr, X86::PMULLWrm, 16 }, 602 { X86::PMULUDQrr, X86::PMULUDQrm, 16 }, 603 { X86::PORrr, X86::PORrm, 16 }, 604 { X86::PSADBWrr, X86::PSADBWrm, 16 }, 605 { X86::PSLLDrr, X86::PSLLDrm, 16 }, 606 { X86::PSLLQrr, X86::PSLLQrm, 16 }, 607 { X86::PSLLWrr, X86::PSLLWrm, 16 }, 608 { X86::PSRADrr, X86::PSRADrm, 16 }, 609 { X86::PSRAWrr, X86::PSRAWrm, 16 }, 610 { X86::PSRLDrr, X86::PSRLDrm, 16 }, 611 { X86::PSRLQrr, X86::PSRLQrm, 16 }, 612 { X86::PSRLWrr, X86::PSRLWrm, 16 }, 613 { X86::PSUBBrr, X86::PSUBBrm, 16 }, 614 { X86::PSUBDrr, X86::PSUBDrm, 16 }, 615 { X86::PSUBSBrr, X86::PSUBSBrm, 16 }, 616 { X86::PSUBSWrr, X86::PSUBSWrm, 16 }, 617 { X86::PSUBWrr, X86::PSUBWrm, 16 }, 618 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 }, 619 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 }, 620 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 }, 621 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 }, 622 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 }, 623 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 }, 624 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 }, 625 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 }, 626 { X86::PXORrr, X86::PXORrm, 16 }, 627 { X86::SBB32rr, X86::SBB32rm, 0 }, 628 { X86::SBB64rr, X86::SBB64rm, 0 }, 629 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 }, 630 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 }, 631 { X86::SUB16rr, X86::SUB16rm, 0 }, 632 { X86::SUB32rr, X86::SUB32rm, 0 }, 633 { X86::SUB64rr, X86::SUB64rm, 0 }, 634 { X86::SUB8rr, X86::SUB8rm, 0 }, 635 { X86::SUBPDrr, X86::SUBPDrm, 16 }, 636 { X86::SUBPSrr, X86::SUBPSrm, 16 }, 637 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 638 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 639 // FIXME: TEST*rr -> swapped operand of TEST*mr. 640 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 }, 641 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 }, 642 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 }, 643 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 }, 644 { X86::XOR16rr, X86::XOR16rm, 0 }, 645 { X86::XOR32rr, X86::XOR32rm, 0 }, 646 { X86::XOR64rr, X86::XOR64rm, 0 }, 647 { X86::XOR8rr, X86::XOR8rm, 0 }, 648 { X86::XORPDrr, X86::XORPDrm, 16 }, 649 { X86::XORPSrr, X86::XORPSrm, 16 } 650 }; 651 652 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 653 unsigned RegOp = OpTbl2[i][0]; 654 unsigned MemOp = OpTbl2[i][1]; 655 unsigned Align = OpTbl2[i][2]; 656 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, 657 std::make_pair(MemOp,Align))).second) 658 assert(false && "Duplicated entries?"); 659 // Index 2, folded load 660 unsigned AuxInfo = 2 | (1 << 4); 661 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 662 std::make_pair(RegOp, AuxInfo))).second) 663 AmbEntries.push_back(MemOp); 664 } 665 666 // Remove ambiguous entries. 667 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); 668} 669 670bool 671X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 672 unsigned &SrcReg, unsigned &DstReg, 673 unsigned &SubIdx) const { 674 switch (MI.getOpcode()) { 675 default: break; 676 case X86::MOVSX16rr8: 677 case X86::MOVZX16rr8: 678 case X86::MOVSX32rr8: 679 case X86::MOVZX32rr8: 680 case X86::MOVSX64rr8: 681 case X86::MOVZX64rr8: 682 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 683 // It's not always legal to reference the low 8-bit of the larger 684 // register in 32-bit mode. 685 return false; 686 case X86::MOVSX32rr16: 687 case X86::MOVZX32rr16: 688 case X86::MOVSX64rr16: 689 case X86::MOVZX64rr16: 690 case X86::MOVSX64rr32: 691 case X86::MOVZX64rr32: { 692 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 693 // Be conservative. 694 return false; 695 SrcReg = MI.getOperand(1).getReg(); 696 DstReg = MI.getOperand(0).getReg(); 697 switch (MI.getOpcode()) { 698 default: 699 llvm_unreachable(0); 700 break; 701 case X86::MOVSX16rr8: 702 case X86::MOVZX16rr8: 703 case X86::MOVSX32rr8: 704 case X86::MOVZX32rr8: 705 case X86::MOVSX64rr8: 706 case X86::MOVZX64rr8: 707 SubIdx = X86::sub_8bit; 708 break; 709 case X86::MOVSX32rr16: 710 case X86::MOVZX32rr16: 711 case X86::MOVSX64rr16: 712 case X86::MOVZX64rr16: 713 SubIdx = X86::sub_16bit; 714 break; 715 case X86::MOVSX64rr32: 716 case X86::MOVZX64rr32: 717 SubIdx = X86::sub_32bit; 718 break; 719 } 720 return true; 721 } 722 } 723 return false; 724} 725 726/// isFrameOperand - Return true and the FrameIndex if the specified 727/// operand and follow operands form a reference to the stack frame. 728bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 729 int &FrameIndex) const { 730 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 731 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 732 MI->getOperand(Op+1).getImm() == 1 && 733 MI->getOperand(Op+2).getReg() == 0 && 734 MI->getOperand(Op+3).getImm() == 0) { 735 FrameIndex = MI->getOperand(Op).getIndex(); 736 return true; 737 } 738 return false; 739} 740 741static bool isFrameLoadOpcode(int Opcode) { 742 switch (Opcode) { 743 default: break; 744 case X86::MOV8rm: 745 case X86::MOV16rm: 746 case X86::MOV32rm: 747 case X86::MOV32rm_TC: 748 case X86::MOV64rm: 749 case X86::MOV64rm_TC: 750 case X86::LD_Fp64m: 751 case X86::MOVSSrm: 752 case X86::MOVSDrm: 753 case X86::MOVAPSrm: 754 case X86::MOVAPDrm: 755 case X86::MOVDQArm: 756 case X86::MMX_MOVD64rm: 757 case X86::MMX_MOVQ64rm: 758 return true; 759 break; 760 } 761 return false; 762} 763 764static bool isFrameStoreOpcode(int Opcode) { 765 switch (Opcode) { 766 default: break; 767 case X86::MOV8mr: 768 case X86::MOV16mr: 769 case X86::MOV32mr: 770 case X86::MOV32mr_TC: 771 case X86::MOV64mr: 772 case X86::MOV64mr_TC: 773 case X86::ST_FpP64m: 774 case X86::MOVSSmr: 775 case X86::MOVSDmr: 776 case X86::MOVAPSmr: 777 case X86::MOVAPDmr: 778 case X86::MOVDQAmr: 779 case X86::MMX_MOVD64mr: 780 case X86::MMX_MOVQ64mr: 781 case X86::MMX_MOVNTQmr: 782 return true; 783 } 784 return false; 785} 786 787unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 788 int &FrameIndex) const { 789 if (isFrameLoadOpcode(MI->getOpcode())) 790 if (isFrameOperand(MI, 1, FrameIndex)) 791 return MI->getOperand(0).getReg(); 792 return 0; 793} 794 795unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 796 int &FrameIndex) const { 797 if (isFrameLoadOpcode(MI->getOpcode())) { 798 unsigned Reg; 799 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 800 return Reg; 801 // Check for post-frame index elimination operations 802 const MachineMemOperand *Dummy; 803 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 804 } 805 return 0; 806} 807 808bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 809 const MachineMemOperand *&MMO, 810 int &FrameIndex) const { 811 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 812 oe = MI->memoperands_end(); 813 o != oe; 814 ++o) { 815 if ((*o)->isLoad() && (*o)->getValue()) 816 if (const FixedStackPseudoSourceValue *Value = 817 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 818 FrameIndex = Value->getFrameIndex(); 819 MMO = *o; 820 return true; 821 } 822 } 823 return false; 824} 825 826unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 827 int &FrameIndex) const { 828 if (isFrameStoreOpcode(MI->getOpcode())) 829 if (isFrameOperand(MI, 0, FrameIndex)) 830 return MI->getOperand(X86::AddrNumOperands).getReg(); 831 return 0; 832} 833 834unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 835 int &FrameIndex) const { 836 if (isFrameStoreOpcode(MI->getOpcode())) { 837 unsigned Reg; 838 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 839 return Reg; 840 // Check for post-frame index elimination operations 841 const MachineMemOperand *Dummy; 842 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 843 } 844 return 0; 845} 846 847bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI, 848 const MachineMemOperand *&MMO, 849 int &FrameIndex) const { 850 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 851 oe = MI->memoperands_end(); 852 o != oe; 853 ++o) { 854 if ((*o)->isStore() && (*o)->getValue()) 855 if (const FixedStackPseudoSourceValue *Value = 856 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 857 FrameIndex = Value->getFrameIndex(); 858 MMO = *o; 859 return true; 860 } 861 } 862 return false; 863} 864 865/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 866/// X86::MOVPC32r. 867static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 868 bool isPICBase = false; 869 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 870 E = MRI.def_end(); I != E; ++I) { 871 MachineInstr *DefMI = I.getOperand().getParent(); 872 if (DefMI->getOpcode() != X86::MOVPC32r) 873 return false; 874 assert(!isPICBase && "More than one PIC base?"); 875 isPICBase = true; 876 } 877 return isPICBase; 878} 879 880bool 881X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 882 AliasAnalysis *AA) const { 883 switch (MI->getOpcode()) { 884 default: break; 885 case X86::MOV8rm: 886 case X86::MOV16rm: 887 case X86::MOV32rm: 888 case X86::MOV64rm: 889 case X86::LD_Fp64m: 890 case X86::MOVSSrm: 891 case X86::MOVSDrm: 892 case X86::MOVAPSrm: 893 case X86::MOVUPSrm: 894 case X86::MOVUPSrm_Int: 895 case X86::MOVAPDrm: 896 case X86::MOVDQArm: 897 case X86::MMX_MOVD64rm: 898 case X86::MMX_MOVQ64rm: 899 case X86::FsMOVAPSrm: 900 case X86::FsMOVAPDrm: { 901 // Loads from constant pools are trivially rematerializable. 902 if (MI->getOperand(1).isReg() && 903 MI->getOperand(2).isImm() && 904 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 905 MI->isInvariantLoad(AA)) { 906 unsigned BaseReg = MI->getOperand(1).getReg(); 907 if (BaseReg == 0 || BaseReg == X86::RIP) 908 return true; 909 // Allow re-materialization of PIC load. 910 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 911 return false; 912 const MachineFunction &MF = *MI->getParent()->getParent(); 913 const MachineRegisterInfo &MRI = MF.getRegInfo(); 914 bool isPICBase = false; 915 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 916 E = MRI.def_end(); I != E; ++I) { 917 MachineInstr *DefMI = I.getOperand().getParent(); 918 if (DefMI->getOpcode() != X86::MOVPC32r) 919 return false; 920 assert(!isPICBase && "More than one PIC base?"); 921 isPICBase = true; 922 } 923 return isPICBase; 924 } 925 return false; 926 } 927 928 case X86::LEA32r: 929 case X86::LEA64r: { 930 if (MI->getOperand(2).isImm() && 931 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 932 !MI->getOperand(4).isReg()) { 933 // lea fi#, lea GV, etc. are all rematerializable. 934 if (!MI->getOperand(1).isReg()) 935 return true; 936 unsigned BaseReg = MI->getOperand(1).getReg(); 937 if (BaseReg == 0) 938 return true; 939 // Allow re-materialization of lea PICBase + x. 940 const MachineFunction &MF = *MI->getParent()->getParent(); 941 const MachineRegisterInfo &MRI = MF.getRegInfo(); 942 return regIsPICBase(BaseReg, MRI); 943 } 944 return false; 945 } 946 } 947 948 // All other instructions marked M_REMATERIALIZABLE are always trivially 949 // rematerializable. 950 return true; 951} 952 953/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 954/// would clobber the EFLAGS condition register. Note the result may be 955/// conservative. If it cannot definitely determine the safety after visiting 956/// a few instructions in each direction it assumes it's not safe. 957static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 958 MachineBasicBlock::iterator I) { 959 MachineBasicBlock::iterator E = MBB.end(); 960 961 // It's always safe to clobber EFLAGS at the end of a block. 962 if (I == E) 963 return true; 964 965 // For compile time consideration, if we are not able to determine the 966 // safety after visiting 4 instructions in each direction, we will assume 967 // it's not safe. 968 MachineBasicBlock::iterator Iter = I; 969 for (unsigned i = 0; i < 4; ++i) { 970 bool SeenDef = false; 971 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 972 MachineOperand &MO = Iter->getOperand(j); 973 if (!MO.isReg()) 974 continue; 975 if (MO.getReg() == X86::EFLAGS) { 976 if (MO.isUse()) 977 return false; 978 SeenDef = true; 979 } 980 } 981 982 if (SeenDef) 983 // This instruction defines EFLAGS, no need to look any further. 984 return true; 985 ++Iter; 986 // Skip over DBG_VALUE. 987 while (Iter != E && Iter->isDebugValue()) 988 ++Iter; 989 990 // If we make it to the end of the block, it's safe to clobber EFLAGS. 991 if (Iter == E) 992 return true; 993 } 994 995 MachineBasicBlock::iterator B = MBB.begin(); 996 Iter = I; 997 for (unsigned i = 0; i < 4; ++i) { 998 // If we make it to the beginning of the block, it's safe to clobber 999 // EFLAGS iff EFLAGS is not live-in. 1000 if (Iter == B) 1001 return !MBB.isLiveIn(X86::EFLAGS); 1002 1003 --Iter; 1004 // Skip over DBG_VALUE. 1005 while (Iter != B && Iter->isDebugValue()) 1006 --Iter; 1007 1008 bool SawKill = false; 1009 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1010 MachineOperand &MO = Iter->getOperand(j); 1011 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1012 if (MO.isDef()) return MO.isDead(); 1013 if (MO.isKill()) SawKill = true; 1014 } 1015 } 1016 1017 if (SawKill) 1018 // This instruction kills EFLAGS and doesn't redefine it, so 1019 // there's no need to look further. 1020 return true; 1021 } 1022 1023 // Conservative answer. 1024 return false; 1025} 1026 1027void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1028 MachineBasicBlock::iterator I, 1029 unsigned DestReg, unsigned SubIdx, 1030 const MachineInstr *Orig, 1031 const TargetRegisterInfo &TRI) const { 1032 DebugLoc DL = Orig->getDebugLoc(); 1033 1034 // MOV32r0 etc. are implemented with xor which clobbers condition code. 1035 // Re-materialize them as movri instructions to avoid side effects. 1036 bool Clone = true; 1037 unsigned Opc = Orig->getOpcode(); 1038 switch (Opc) { 1039 default: break; 1040 case X86::MOV8r0: 1041 case X86::MOV16r0: 1042 case X86::MOV32r0: 1043 case X86::MOV64r0: { 1044 if (!isSafeToClobberEFLAGS(MBB, I)) { 1045 switch (Opc) { 1046 default: break; 1047 case X86::MOV8r0: Opc = X86::MOV8ri; break; 1048 case X86::MOV16r0: Opc = X86::MOV16ri; break; 1049 case X86::MOV32r0: Opc = X86::MOV32ri; break; 1050 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; 1051 } 1052 Clone = false; 1053 } 1054 break; 1055 } 1056 } 1057 1058 if (Clone) { 1059 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1060 MBB.insert(I, MI); 1061 } else { 1062 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0); 1063 } 1064 1065 MachineInstr *NewMI = prior(I); 1066 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1067} 1068 1069/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1070/// is not marked dead. 1071static bool hasLiveCondCodeDef(MachineInstr *MI) { 1072 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1073 MachineOperand &MO = MI->getOperand(i); 1074 if (MO.isReg() && MO.isDef() && 1075 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1076 return true; 1077 } 1078 } 1079 return false; 1080} 1081 1082/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1083/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1084/// to a 32-bit superregister and then truncating back down to a 16-bit 1085/// subregister. 1086MachineInstr * 1087X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1088 MachineFunction::iterator &MFI, 1089 MachineBasicBlock::iterator &MBBI, 1090 LiveVariables *LV) const { 1091 MachineInstr *MI = MBBI; 1092 unsigned Dest = MI->getOperand(0).getReg(); 1093 unsigned Src = MI->getOperand(1).getReg(); 1094 bool isDead = MI->getOperand(0).isDead(); 1095 bool isKill = MI->getOperand(1).isKill(); 1096 1097 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1098 ? X86::LEA64_32r : X86::LEA32r; 1099 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1100 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1101 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1102 1103 // Build and insert into an implicit UNDEF value. This is OK because 1104 // well be shifting and then extracting the lower 16-bits. 1105 // This has the potential to cause partial register stall. e.g. 1106 // movw (%rbp,%rcx,2), %dx 1107 // leal -65(%rdx), %esi 1108 // But testing has shown this *does* help performance in 64-bit mode (at 1109 // least on modern x86 machines). 1110 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1111 MachineInstr *InsMI = 1112 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1113 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1114 .addReg(Src, getKillRegState(isKill)); 1115 1116 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1117 get(Opc), leaOutReg); 1118 switch (MIOpc) { 1119 default: 1120 llvm_unreachable(0); 1121 break; 1122 case X86::SHL16ri: { 1123 unsigned ShAmt = MI->getOperand(2).getImm(); 1124 MIB.addReg(0).addImm(1 << ShAmt) 1125 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1126 break; 1127 } 1128 case X86::INC16r: 1129 case X86::INC64_16r: 1130 addRegOffset(MIB, leaInReg, true, 1); 1131 break; 1132 case X86::DEC16r: 1133 case X86::DEC64_16r: 1134 addRegOffset(MIB, leaInReg, true, -1); 1135 break; 1136 case X86::ADD16ri: 1137 case X86::ADD16ri8: 1138 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1139 break; 1140 case X86::ADD16rr: { 1141 unsigned Src2 = MI->getOperand(2).getReg(); 1142 bool isKill2 = MI->getOperand(2).isKill(); 1143 unsigned leaInReg2 = 0; 1144 MachineInstr *InsMI2 = 0; 1145 if (Src == Src2) { 1146 // ADD16rr %reg1028<kill>, %reg1028 1147 // just a single insert_subreg. 1148 addRegReg(MIB, leaInReg, true, leaInReg, false); 1149 } else { 1150 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1151 // Build and insert into an implicit UNDEF value. This is OK because 1152 // well be shifting and then extracting the lower 16-bits. 1153 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2); 1154 InsMI2 = 1155 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1156 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1157 .addReg(Src2, getKillRegState(isKill2)); 1158 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1159 } 1160 if (LV && isKill2 && InsMI2) 1161 LV->replaceKillInstruction(Src2, MI, InsMI2); 1162 break; 1163 } 1164 } 1165 1166 MachineInstr *NewMI = MIB; 1167 MachineInstr *ExtMI = 1168 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1169 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1170 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 1171 1172 if (LV) { 1173 // Update live variables 1174 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1175 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1176 if (isKill) 1177 LV->replaceKillInstruction(Src, MI, InsMI); 1178 if (isDead) 1179 LV->replaceKillInstruction(Dest, MI, ExtMI); 1180 } 1181 1182 return ExtMI; 1183} 1184 1185/// convertToThreeAddress - This method must be implemented by targets that 1186/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1187/// may be able to convert a two-address instruction into a true 1188/// three-address instruction on demand. This allows the X86 target (for 1189/// example) to convert ADD and SHL instructions into LEA instructions if they 1190/// would require register copies due to two-addressness. 1191/// 1192/// This method returns a null pointer if the transformation cannot be 1193/// performed, otherwise it returns the new instruction. 1194/// 1195MachineInstr * 1196X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1197 MachineBasicBlock::iterator &MBBI, 1198 LiveVariables *LV) const { 1199 MachineInstr *MI = MBBI; 1200 MachineFunction &MF = *MI->getParent()->getParent(); 1201 // All instructions input are two-addr instructions. Get the known operands. 1202 unsigned Dest = MI->getOperand(0).getReg(); 1203 unsigned Src = MI->getOperand(1).getReg(); 1204 bool isDead = MI->getOperand(0).isDead(); 1205 bool isKill = MI->getOperand(1).isKill(); 1206 1207 MachineInstr *NewMI = NULL; 1208 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1209 // we have better subtarget support, enable the 16-bit LEA generation here. 1210 // 16-bit LEA is also slow on Core2. 1211 bool DisableLEA16 = true; 1212 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1213 1214 unsigned MIOpc = MI->getOpcode(); 1215 switch (MIOpc) { 1216 case X86::SHUFPSrri: { 1217 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1218 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1219 1220 unsigned B = MI->getOperand(1).getReg(); 1221 unsigned C = MI->getOperand(2).getReg(); 1222 if (B != C) return 0; 1223 unsigned A = MI->getOperand(0).getReg(); 1224 unsigned M = MI->getOperand(3).getImm(); 1225 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1226 .addReg(A, RegState::Define | getDeadRegState(isDead)) 1227 .addReg(B, getKillRegState(isKill)).addImm(M); 1228 break; 1229 } 1230 case X86::SHL64ri: { 1231 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1232 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1233 // the flags produced by a shift yet, so this is safe. 1234 unsigned ShAmt = MI->getOperand(2).getImm(); 1235 if (ShAmt == 0 || ShAmt >= 4) return 0; 1236 1237 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1238 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1239 .addReg(0).addImm(1 << ShAmt) 1240 .addReg(Src, getKillRegState(isKill)) 1241 .addImm(0).addReg(0); 1242 break; 1243 } 1244 case X86::SHL32ri: { 1245 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1246 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1247 // the flags produced by a shift yet, so this is safe. 1248 unsigned ShAmt = MI->getOperand(2).getImm(); 1249 if (ShAmt == 0 || ShAmt >= 4) return 0; 1250 1251 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1252 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1253 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1254 .addReg(0).addImm(1 << ShAmt) 1255 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0); 1256 break; 1257 } 1258 case X86::SHL16ri: { 1259 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1260 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1261 // the flags produced by a shift yet, so this is safe. 1262 unsigned ShAmt = MI->getOperand(2).getImm(); 1263 if (ShAmt == 0 || ShAmt >= 4) return 0; 1264 1265 if (DisableLEA16) 1266 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1267 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1268 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1269 .addReg(0).addImm(1 << ShAmt) 1270 .addReg(Src, getKillRegState(isKill)) 1271 .addImm(0).addReg(0); 1272 break; 1273 } 1274 default: { 1275 // The following opcodes also sets the condition code register(s). Only 1276 // convert them to equivalent lea if the condition code register def's 1277 // are dead! 1278 if (hasLiveCondCodeDef(MI)) 1279 return 0; 1280 1281 switch (MIOpc) { 1282 default: return 0; 1283 case X86::INC64r: 1284 case X86::INC32r: 1285 case X86::INC64_32r: { 1286 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1287 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1288 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1289 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1290 .addReg(Dest, RegState::Define | 1291 getDeadRegState(isDead)), 1292 Src, isKill, 1); 1293 break; 1294 } 1295 case X86::INC16r: 1296 case X86::INC64_16r: 1297 if (DisableLEA16) 1298 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1299 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1300 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1301 .addReg(Dest, RegState::Define | 1302 getDeadRegState(isDead)), 1303 Src, isKill, 1); 1304 break; 1305 case X86::DEC64r: 1306 case X86::DEC32r: 1307 case X86::DEC64_32r: { 1308 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1309 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1310 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1311 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1312 .addReg(Dest, RegState::Define | 1313 getDeadRegState(isDead)), 1314 Src, isKill, -1); 1315 break; 1316 } 1317 case X86::DEC16r: 1318 case X86::DEC64_16r: 1319 if (DisableLEA16) 1320 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1321 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1322 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1323 .addReg(Dest, RegState::Define | 1324 getDeadRegState(isDead)), 1325 Src, isKill, -1); 1326 break; 1327 case X86::ADD64rr: 1328 case X86::ADD32rr: { 1329 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1330 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r 1331 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1332 unsigned Src2 = MI->getOperand(2).getReg(); 1333 bool isKill2 = MI->getOperand(2).isKill(); 1334 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1335 .addReg(Dest, RegState::Define | 1336 getDeadRegState(isDead)), 1337 Src, isKill, Src2, isKill2); 1338 if (LV && isKill2) 1339 LV->replaceKillInstruction(Src2, MI, NewMI); 1340 break; 1341 } 1342 case X86::ADD16rr: { 1343 if (DisableLEA16) 1344 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1345 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1346 unsigned Src2 = MI->getOperand(2).getReg(); 1347 bool isKill2 = MI->getOperand(2).isKill(); 1348 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1349 .addReg(Dest, RegState::Define | 1350 getDeadRegState(isDead)), 1351 Src, isKill, Src2, isKill2); 1352 if (LV && isKill2) 1353 LV->replaceKillInstruction(Src2, MI, NewMI); 1354 break; 1355 } 1356 case X86::ADD64ri32: 1357 case X86::ADD64ri8: 1358 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1359 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1360 .addReg(Dest, RegState::Define | 1361 getDeadRegState(isDead)), 1362 Src, isKill, MI->getOperand(2).getImm()); 1363 break; 1364 case X86::ADD32ri: 1365 case X86::ADD32ri8: { 1366 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1367 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1368 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1369 .addReg(Dest, RegState::Define | 1370 getDeadRegState(isDead)), 1371 Src, isKill, MI->getOperand(2).getImm()); 1372 break; 1373 } 1374 case X86::ADD16ri: 1375 case X86::ADD16ri8: 1376 if (DisableLEA16) 1377 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1378 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1379 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1380 .addReg(Dest, RegState::Define | 1381 getDeadRegState(isDead)), 1382 Src, isKill, MI->getOperand(2).getImm()); 1383 break; 1384 } 1385 } 1386 } 1387 1388 if (!NewMI) return 0; 1389 1390 if (LV) { // Update live variables 1391 if (isKill) 1392 LV->replaceKillInstruction(Src, MI, NewMI); 1393 if (isDead) 1394 LV->replaceKillInstruction(Dest, MI, NewMI); 1395 } 1396 1397 MFI->insert(MBBI, NewMI); // Insert the new inst 1398 return NewMI; 1399} 1400 1401/// commuteInstruction - We have a few instructions that must be hacked on to 1402/// commute them. 1403/// 1404MachineInstr * 1405X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1406 switch (MI->getOpcode()) { 1407 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 1408 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 1409 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 1410 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 1411 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 1412 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 1413 unsigned Opc; 1414 unsigned Size; 1415 switch (MI->getOpcode()) { 1416 default: llvm_unreachable("Unreachable!"); 1417 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 1418 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 1419 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 1420 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 1421 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 1422 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 1423 } 1424 unsigned Amt = MI->getOperand(3).getImm(); 1425 if (NewMI) { 1426 MachineFunction &MF = *MI->getParent()->getParent(); 1427 MI = MF.CloneMachineInstr(MI); 1428 NewMI = false; 1429 } 1430 MI->setDesc(get(Opc)); 1431 MI->getOperand(3).setImm(Size-Amt); 1432 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1433 } 1434 case X86::CMOVB16rr: 1435 case X86::CMOVB32rr: 1436 case X86::CMOVB64rr: 1437 case X86::CMOVAE16rr: 1438 case X86::CMOVAE32rr: 1439 case X86::CMOVAE64rr: 1440 case X86::CMOVE16rr: 1441 case X86::CMOVE32rr: 1442 case X86::CMOVE64rr: 1443 case X86::CMOVNE16rr: 1444 case X86::CMOVNE32rr: 1445 case X86::CMOVNE64rr: 1446 case X86::CMOVBE16rr: 1447 case X86::CMOVBE32rr: 1448 case X86::CMOVBE64rr: 1449 case X86::CMOVA16rr: 1450 case X86::CMOVA32rr: 1451 case X86::CMOVA64rr: 1452 case X86::CMOVL16rr: 1453 case X86::CMOVL32rr: 1454 case X86::CMOVL64rr: 1455 case X86::CMOVGE16rr: 1456 case X86::CMOVGE32rr: 1457 case X86::CMOVGE64rr: 1458 case X86::CMOVLE16rr: 1459 case X86::CMOVLE32rr: 1460 case X86::CMOVLE64rr: 1461 case X86::CMOVG16rr: 1462 case X86::CMOVG32rr: 1463 case X86::CMOVG64rr: 1464 case X86::CMOVS16rr: 1465 case X86::CMOVS32rr: 1466 case X86::CMOVS64rr: 1467 case X86::CMOVNS16rr: 1468 case X86::CMOVNS32rr: 1469 case X86::CMOVNS64rr: 1470 case X86::CMOVP16rr: 1471 case X86::CMOVP32rr: 1472 case X86::CMOVP64rr: 1473 case X86::CMOVNP16rr: 1474 case X86::CMOVNP32rr: 1475 case X86::CMOVNP64rr: 1476 case X86::CMOVO16rr: 1477 case X86::CMOVO32rr: 1478 case X86::CMOVO64rr: 1479 case X86::CMOVNO16rr: 1480 case X86::CMOVNO32rr: 1481 case X86::CMOVNO64rr: { 1482 unsigned Opc = 0; 1483 switch (MI->getOpcode()) { 1484 default: break; 1485 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 1486 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 1487 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 1488 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 1489 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 1490 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 1491 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 1492 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 1493 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 1494 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 1495 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 1496 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 1497 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 1498 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 1499 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 1500 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 1501 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 1502 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 1503 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 1504 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 1505 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 1506 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 1507 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 1508 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 1509 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 1510 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 1511 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 1512 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 1513 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 1514 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 1515 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 1516 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 1517 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 1518 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 1519 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 1520 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 1521 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 1522 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 1523 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 1524 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 1525 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 1526 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 1527 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 1528 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 1529 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 1530 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 1531 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 1532 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 1533 } 1534 if (NewMI) { 1535 MachineFunction &MF = *MI->getParent()->getParent(); 1536 MI = MF.CloneMachineInstr(MI); 1537 NewMI = false; 1538 } 1539 MI->setDesc(get(Opc)); 1540 // Fallthrough intended. 1541 } 1542 default: 1543 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1544 } 1545} 1546 1547static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 1548 switch (BrOpc) { 1549 default: return X86::COND_INVALID; 1550 case X86::JE_4: return X86::COND_E; 1551 case X86::JNE_4: return X86::COND_NE; 1552 case X86::JL_4: return X86::COND_L; 1553 case X86::JLE_4: return X86::COND_LE; 1554 case X86::JG_4: return X86::COND_G; 1555 case X86::JGE_4: return X86::COND_GE; 1556 case X86::JB_4: return X86::COND_B; 1557 case X86::JBE_4: return X86::COND_BE; 1558 case X86::JA_4: return X86::COND_A; 1559 case X86::JAE_4: return X86::COND_AE; 1560 case X86::JS_4: return X86::COND_S; 1561 case X86::JNS_4: return X86::COND_NS; 1562 case X86::JP_4: return X86::COND_P; 1563 case X86::JNP_4: return X86::COND_NP; 1564 case X86::JO_4: return X86::COND_O; 1565 case X86::JNO_4: return X86::COND_NO; 1566 } 1567} 1568 1569unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 1570 switch (CC) { 1571 default: llvm_unreachable("Illegal condition code!"); 1572 case X86::COND_E: return X86::JE_4; 1573 case X86::COND_NE: return X86::JNE_4; 1574 case X86::COND_L: return X86::JL_4; 1575 case X86::COND_LE: return X86::JLE_4; 1576 case X86::COND_G: return X86::JG_4; 1577 case X86::COND_GE: return X86::JGE_4; 1578 case X86::COND_B: return X86::JB_4; 1579 case X86::COND_BE: return X86::JBE_4; 1580 case X86::COND_A: return X86::JA_4; 1581 case X86::COND_AE: return X86::JAE_4; 1582 case X86::COND_S: return X86::JS_4; 1583 case X86::COND_NS: return X86::JNS_4; 1584 case X86::COND_P: return X86::JP_4; 1585 case X86::COND_NP: return X86::JNP_4; 1586 case X86::COND_O: return X86::JO_4; 1587 case X86::COND_NO: return X86::JNO_4; 1588 } 1589} 1590 1591/// GetOppositeBranchCondition - Return the inverse of the specified condition, 1592/// e.g. turning COND_E to COND_NE. 1593X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 1594 switch (CC) { 1595 default: llvm_unreachable("Illegal condition code!"); 1596 case X86::COND_E: return X86::COND_NE; 1597 case X86::COND_NE: return X86::COND_E; 1598 case X86::COND_L: return X86::COND_GE; 1599 case X86::COND_LE: return X86::COND_G; 1600 case X86::COND_G: return X86::COND_LE; 1601 case X86::COND_GE: return X86::COND_L; 1602 case X86::COND_B: return X86::COND_AE; 1603 case X86::COND_BE: return X86::COND_A; 1604 case X86::COND_A: return X86::COND_BE; 1605 case X86::COND_AE: return X86::COND_B; 1606 case X86::COND_S: return X86::COND_NS; 1607 case X86::COND_NS: return X86::COND_S; 1608 case X86::COND_P: return X86::COND_NP; 1609 case X86::COND_NP: return X86::COND_P; 1610 case X86::COND_O: return X86::COND_NO; 1611 case X86::COND_NO: return X86::COND_O; 1612 } 1613} 1614 1615bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 1616 const TargetInstrDesc &TID = MI->getDesc(); 1617 if (!TID.isTerminator()) return false; 1618 1619 // Conditional branch is a special case. 1620 if (TID.isBranch() && !TID.isBarrier()) 1621 return true; 1622 if (!TID.isPredicable()) 1623 return true; 1624 return !isPredicated(MI); 1625} 1626 1627bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 1628 MachineBasicBlock *&TBB, 1629 MachineBasicBlock *&FBB, 1630 SmallVectorImpl<MachineOperand> &Cond, 1631 bool AllowModify) const { 1632 // Start from the bottom of the block and work up, examining the 1633 // terminator instructions. 1634 MachineBasicBlock::iterator I = MBB.end(); 1635 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 1636 while (I != MBB.begin()) { 1637 --I; 1638 if (I->isDebugValue()) 1639 continue; 1640 1641 // Working from the bottom, when we see a non-terminator instruction, we're 1642 // done. 1643 if (!isUnpredicatedTerminator(I)) 1644 break; 1645 1646 // A terminator that isn't a branch can't easily be handled by this 1647 // analysis. 1648 if (!I->getDesc().isBranch()) 1649 return true; 1650 1651 // Handle unconditional branches. 1652 if (I->getOpcode() == X86::JMP_4) { 1653 UnCondBrIter = I; 1654 1655 if (!AllowModify) { 1656 TBB = I->getOperand(0).getMBB(); 1657 continue; 1658 } 1659 1660 // If the block has any instructions after a JMP, delete them. 1661 while (llvm::next(I) != MBB.end()) 1662 llvm::next(I)->eraseFromParent(); 1663 1664 Cond.clear(); 1665 FBB = 0; 1666 1667 // Delete the JMP if it's equivalent to a fall-through. 1668 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 1669 TBB = 0; 1670 I->eraseFromParent(); 1671 I = MBB.end(); 1672 UnCondBrIter = MBB.end(); 1673 continue; 1674 } 1675 1676 // TBB is used to indicate the unconditional destination. 1677 TBB = I->getOperand(0).getMBB(); 1678 continue; 1679 } 1680 1681 // Handle conditional branches. 1682 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode()); 1683 if (BranchCode == X86::COND_INVALID) 1684 return true; // Can't handle indirect branch. 1685 1686 // Working from the bottom, handle the first conditional branch. 1687 if (Cond.empty()) { 1688 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 1689 if (AllowModify && UnCondBrIter != MBB.end() && 1690 MBB.isLayoutSuccessor(TargetBB)) { 1691 // If we can modify the code and it ends in something like: 1692 // 1693 // jCC L1 1694 // jmp L2 1695 // L1: 1696 // ... 1697 // L2: 1698 // 1699 // Then we can change this to: 1700 // 1701 // jnCC L2 1702 // L1: 1703 // ... 1704 // L2: 1705 // 1706 // Which is a bit more efficient. 1707 // We conditionally jump to the fall-through block. 1708 BranchCode = GetOppositeBranchCondition(BranchCode); 1709 unsigned JNCC = GetCondBranchFromCond(BranchCode); 1710 MachineBasicBlock::iterator OldInst = I; 1711 1712 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 1713 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 1714 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 1715 .addMBB(TargetBB); 1716 MBB.addSuccessor(TargetBB); 1717 1718 OldInst->eraseFromParent(); 1719 UnCondBrIter->eraseFromParent(); 1720 1721 // Restart the analysis. 1722 UnCondBrIter = MBB.end(); 1723 I = MBB.end(); 1724 continue; 1725 } 1726 1727 FBB = TBB; 1728 TBB = I->getOperand(0).getMBB(); 1729 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 1730 continue; 1731 } 1732 1733 // Handle subsequent conditional branches. Only handle the case where all 1734 // conditional branches branch to the same destination and their condition 1735 // opcodes fit one of the special multi-branch idioms. 1736 assert(Cond.size() == 1); 1737 assert(TBB); 1738 1739 // Only handle the case where all conditional branches branch to the same 1740 // destination. 1741 if (TBB != I->getOperand(0).getMBB()) 1742 return true; 1743 1744 // If the conditions are the same, we can leave them alone. 1745 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 1746 if (OldBranchCode == BranchCode) 1747 continue; 1748 1749 // If they differ, see if they fit one of the known patterns. Theoretically, 1750 // we could handle more patterns here, but we shouldn't expect to see them 1751 // if instruction selection has done a reasonable job. 1752 if ((OldBranchCode == X86::COND_NP && 1753 BranchCode == X86::COND_E) || 1754 (OldBranchCode == X86::COND_E && 1755 BranchCode == X86::COND_NP)) 1756 BranchCode = X86::COND_NP_OR_E; 1757 else if ((OldBranchCode == X86::COND_P && 1758 BranchCode == X86::COND_NE) || 1759 (OldBranchCode == X86::COND_NE && 1760 BranchCode == X86::COND_P)) 1761 BranchCode = X86::COND_NE_OR_P; 1762 else 1763 return true; 1764 1765 // Update the MachineOperand. 1766 Cond[0].setImm(BranchCode); 1767 } 1768 1769 return false; 1770} 1771 1772unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 1773 MachineBasicBlock::iterator I = MBB.end(); 1774 unsigned Count = 0; 1775 1776 while (I != MBB.begin()) { 1777 --I; 1778 if (I->isDebugValue()) 1779 continue; 1780 if (I->getOpcode() != X86::JMP_4 && 1781 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 1782 break; 1783 // Remove the branch. 1784 I->eraseFromParent(); 1785 I = MBB.end(); 1786 ++Count; 1787 } 1788 1789 return Count; 1790} 1791 1792unsigned 1793X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 1794 MachineBasicBlock *FBB, 1795 const SmallVectorImpl<MachineOperand> &Cond, 1796 DebugLoc DL) const { 1797 // Shouldn't be a fall through. 1798 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 1799 assert((Cond.size() == 1 || Cond.size() == 0) && 1800 "X86 branch conditions have one component!"); 1801 1802 if (Cond.empty()) { 1803 // Unconditional branch? 1804 assert(!FBB && "Unconditional branch with multiple successors!"); 1805 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 1806 return 1; 1807 } 1808 1809 // Conditional branch. 1810 unsigned Count = 0; 1811 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 1812 switch (CC) { 1813 case X86::COND_NP_OR_E: 1814 // Synthesize NP_OR_E with two branches. 1815 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 1816 ++Count; 1817 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 1818 ++Count; 1819 break; 1820 case X86::COND_NE_OR_P: 1821 // Synthesize NE_OR_P with two branches. 1822 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 1823 ++Count; 1824 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 1825 ++Count; 1826 break; 1827 default: { 1828 unsigned Opc = GetCondBranchFromCond(CC); 1829 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 1830 ++Count; 1831 } 1832 } 1833 if (FBB) { 1834 // Two-way Conditional branch. Insert the second branch. 1835 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 1836 ++Count; 1837 } 1838 return Count; 1839} 1840 1841/// isHReg - Test if the given register is a physical h register. 1842static bool isHReg(unsigned Reg) { 1843 return X86::GR8_ABCD_HRegClass.contains(Reg); 1844} 1845 1846void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 1847 MachineBasicBlock::iterator MI, DebugLoc DL, 1848 unsigned DestReg, unsigned SrcReg, 1849 bool KillSrc) const { 1850 // First deal with the normal symmetric copies. 1851 unsigned Opc = 0; 1852 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 1853 Opc = X86::MOV64rr; 1854 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 1855 Opc = X86::MOV32rr; 1856 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 1857 Opc = X86::MOV16rr; 1858 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 1859 // Copying to or from a physical H register on x86-64 requires a NOREX 1860 // move. Otherwise use a normal move. 1861 if ((isHReg(DestReg) || isHReg(SrcReg)) && 1862 TM.getSubtarget<X86Subtarget>().is64Bit()) 1863 Opc = X86::MOV8rr_NOREX; 1864 else 1865 Opc = X86::MOV8rr; 1866 } else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 1867 Opc = X86::MOVAPSrr; 1868 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 1869 Opc = X86::MMX_MOVQ64rr; 1870 1871 if (Opc) { 1872 BuildMI(MBB, MI, DL, get(Opc), DestReg) 1873 .addReg(SrcReg, getKillRegState(KillSrc)); 1874 return; 1875 } 1876 1877 // Moving EFLAGS to / from another register requires a push and a pop. 1878 if (SrcReg == X86::EFLAGS) { 1879 if (X86::GR64RegClass.contains(DestReg)) { 1880 BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 1881 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 1882 return; 1883 } else if (X86::GR32RegClass.contains(DestReg)) { 1884 BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 1885 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 1886 return; 1887 } 1888 } 1889 if (DestReg == X86::EFLAGS) { 1890 if (X86::GR64RegClass.contains(SrcReg)) { 1891 BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 1892 .addReg(SrcReg, getKillRegState(KillSrc)); 1893 BuildMI(MBB, MI, DL, get(X86::POPF64)); 1894 return; 1895 } else if (X86::GR32RegClass.contains(SrcReg)) { 1896 BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 1897 .addReg(SrcReg, getKillRegState(KillSrc)); 1898 BuildMI(MBB, MI, DL, get(X86::POPF32)); 1899 return; 1900 } 1901 } 1902 1903 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 1904 << " to " << RI.getName(DestReg) << '\n'); 1905 llvm_unreachable("Cannot emit physreg copy instruction"); 1906} 1907 1908static unsigned getLoadStoreRegOpcode(unsigned Reg, 1909 const TargetRegisterClass *RC, 1910 bool isStackAligned, 1911 const TargetMachine &TM, 1912 bool load) { 1913 switch (RC->getID()) { 1914 default: 1915 llvm_unreachable("Unknown regclass"); 1916 case X86::GR64RegClassID: 1917 case X86::GR64_NOSPRegClassID: 1918 return load ? X86::MOV64rm : X86::MOV64mr; 1919 case X86::GR32RegClassID: 1920 case X86::GR32_NOSPRegClassID: 1921 case X86::GR32_ADRegClassID: 1922 return load ? X86::MOV32rm : X86::MOV32mr; 1923 case X86::GR16RegClassID: 1924 return load ? X86::MOV16rm : X86::MOV16mr; 1925 case X86::GR8RegClassID: 1926 // Copying to or from a physical H register on x86-64 requires a NOREX 1927 // move. Otherwise use a normal move. 1928 if (isHReg(Reg) && 1929 TM.getSubtarget<X86Subtarget>().is64Bit()) 1930 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 1931 else 1932 return load ? X86::MOV8rm : X86::MOV8mr; 1933 case X86::GR64_ABCDRegClassID: 1934 return load ? X86::MOV64rm : X86::MOV64mr; 1935 case X86::GR32_ABCDRegClassID: 1936 return load ? X86::MOV32rm : X86::MOV32mr; 1937 case X86::GR16_ABCDRegClassID: 1938 return load ? X86::MOV16rm : X86::MOV16mr; 1939 case X86::GR8_ABCD_LRegClassID: 1940 return load ? X86::MOV8rm :X86::MOV8mr; 1941 case X86::GR8_ABCD_HRegClassID: 1942 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 1943 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 1944 else 1945 return load ? X86::MOV8rm : X86::MOV8mr; 1946 case X86::GR64_NOREXRegClassID: 1947 case X86::GR64_NOREX_NOSPRegClassID: 1948 return load ? X86::MOV64rm : X86::MOV64mr; 1949 case X86::GR32_NOREXRegClassID: 1950 return load ? X86::MOV32rm : X86::MOV32mr; 1951 case X86::GR16_NOREXRegClassID: 1952 return load ? X86::MOV16rm : X86::MOV16mr; 1953 case X86::GR8_NOREXRegClassID: 1954 return load ? X86::MOV8rm : X86::MOV8mr; 1955 case X86::GR64_TCRegClassID: 1956 return load ? X86::MOV64rm_TC : X86::MOV64mr_TC; 1957 case X86::GR32_TCRegClassID: 1958 return load ? X86::MOV32rm_TC : X86::MOV32mr_TC; 1959 case X86::RFP80RegClassID: 1960 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 1961 case X86::RFP64RegClassID: 1962 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 1963 case X86::RFP32RegClassID: 1964 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 1965 case X86::FR32RegClassID: 1966 return load ? X86::MOVSSrm : X86::MOVSSmr; 1967 case X86::FR64RegClassID: 1968 return load ? X86::MOVSDrm : X86::MOVSDmr; 1969 case X86::VR128RegClassID: 1970 // If stack is realigned we can use aligned stores. 1971 if (isStackAligned) 1972 return load ? X86::MOVAPSrm : X86::MOVAPSmr; 1973 else 1974 return load ? X86::MOVUPSrm : X86::MOVUPSmr; 1975 case X86::VR64RegClassID: 1976 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 1977 } 1978} 1979 1980static unsigned getStoreRegOpcode(unsigned SrcReg, 1981 const TargetRegisterClass *RC, 1982 bool isStackAligned, 1983 TargetMachine &TM) { 1984 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false); 1985} 1986 1987 1988static unsigned getLoadRegOpcode(unsigned DestReg, 1989 const TargetRegisterClass *RC, 1990 bool isStackAligned, 1991 const TargetMachine &TM) { 1992 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true); 1993} 1994 1995void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 1996 MachineBasicBlock::iterator MI, 1997 unsigned SrcReg, bool isKill, int FrameIdx, 1998 const TargetRegisterClass *RC, 1999 const TargetRegisterInfo *TRI) const { 2000 const MachineFunction &MF = *MBB.getParent(); 2001 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2002 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2003 DebugLoc DL = MBB.findDebugLoc(MI); 2004 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2005 .addReg(SrcReg, getKillRegState(isKill)); 2006} 2007 2008void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 2009 bool isKill, 2010 SmallVectorImpl<MachineOperand> &Addr, 2011 const TargetRegisterClass *RC, 2012 MachineInstr::mmo_iterator MMOBegin, 2013 MachineInstr::mmo_iterator MMOEnd, 2014 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2015 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16; 2016 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2017 DebugLoc DL; 2018 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 2019 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2020 MIB.addOperand(Addr[i]); 2021 MIB.addReg(SrcReg, getKillRegState(isKill)); 2022 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2023 NewMIs.push_back(MIB); 2024} 2025 2026 2027void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 2028 MachineBasicBlock::iterator MI, 2029 unsigned DestReg, int FrameIdx, 2030 const TargetRegisterClass *RC, 2031 const TargetRegisterInfo *TRI) const { 2032 const MachineFunction &MF = *MBB.getParent(); 2033 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2034 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2035 DebugLoc DL = MBB.findDebugLoc(MI); 2036 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 2037} 2038 2039void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 2040 SmallVectorImpl<MachineOperand> &Addr, 2041 const TargetRegisterClass *RC, 2042 MachineInstr::mmo_iterator MMOBegin, 2043 MachineInstr::mmo_iterator MMOEnd, 2044 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2045 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16; 2046 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2047 DebugLoc DL; 2048 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 2049 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2050 MIB.addOperand(Addr[i]); 2051 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2052 NewMIs.push_back(MIB); 2053} 2054 2055bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 2056 MachineBasicBlock::iterator MI, 2057 const std::vector<CalleeSavedInfo> &CSI, 2058 const TargetRegisterInfo *TRI) const { 2059 if (CSI.empty()) 2060 return false; 2061 2062 DebugLoc DL = MBB.findDebugLoc(MI); 2063 2064 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 2065 unsigned SlotSize = is64Bit ? 8 : 4; 2066 2067 MachineFunction &MF = *MBB.getParent(); 2068 unsigned FPReg = RI.getFrameRegister(MF); 2069 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 2070 unsigned CalleeFrameSize = 0; 2071 2072 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r; 2073 for (unsigned i = CSI.size(); i != 0; --i) { 2074 unsigned Reg = CSI[i-1].getReg(); 2075 // Add the callee-saved register as live-in. It's killed at the spill. 2076 MBB.addLiveIn(Reg); 2077 if (Reg == FPReg) 2078 // X86RegisterInfo::emitPrologue will handle spilling of frame register. 2079 continue; 2080 if (!X86::VR128RegClass.contains(Reg)) { 2081 CalleeFrameSize += SlotSize; 2082 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill); 2083 } else { 2084 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), 2085 &X86::VR128RegClass, &RI); 2086 } 2087 } 2088 2089 X86FI->setCalleeSavedFrameSize(CalleeFrameSize); 2090 return true; 2091} 2092 2093bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 2094 MachineBasicBlock::iterator MI, 2095 const std::vector<CalleeSavedInfo> &CSI, 2096 const TargetRegisterInfo *TRI) const { 2097 if (CSI.empty()) 2098 return false; 2099 2100 DebugLoc DL = MBB.findDebugLoc(MI); 2101 2102 MachineFunction &MF = *MBB.getParent(); 2103 unsigned FPReg = RI.getFrameRegister(MF); 2104 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 2105 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; 2106 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 2107 unsigned Reg = CSI[i].getReg(); 2108 if (Reg == FPReg) 2109 // X86RegisterInfo::emitEpilogue will handle restoring of frame register. 2110 continue; 2111 if (!X86::VR128RegClass.contains(Reg)) { 2112 BuildMI(MBB, MI, DL, get(Opc), Reg); 2113 } else { 2114 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), 2115 &X86::VR128RegClass, &RI); 2116 } 2117 } 2118 return true; 2119} 2120 2121MachineInstr* 2122X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 2123 int FrameIx, uint64_t Offset, 2124 const MDNode *MDPtr, 2125 DebugLoc DL) const { 2126 X86AddressMode AM; 2127 AM.BaseType = X86AddressMode::FrameIndexBase; 2128 AM.Base.FrameIndex = FrameIx; 2129 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); 2130 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr); 2131 return &*MIB; 2132} 2133 2134static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 2135 const SmallVectorImpl<MachineOperand> &MOs, 2136 MachineInstr *MI, 2137 const TargetInstrInfo &TII) { 2138 // Create the base instruction with the memory operand as the first part. 2139 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2140 MI->getDebugLoc(), true); 2141 MachineInstrBuilder MIB(NewMI); 2142 unsigned NumAddrOps = MOs.size(); 2143 for (unsigned i = 0; i != NumAddrOps; ++i) 2144 MIB.addOperand(MOs[i]); 2145 if (NumAddrOps < 4) // FrameIndex only 2146 addOffset(MIB, 0); 2147 2148 // Loop over the rest of the ri operands, converting them over. 2149 unsigned NumOps = MI->getDesc().getNumOperands()-2; 2150 for (unsigned i = 0; i != NumOps; ++i) { 2151 MachineOperand &MO = MI->getOperand(i+2); 2152 MIB.addOperand(MO); 2153 } 2154 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 2155 MachineOperand &MO = MI->getOperand(i); 2156 MIB.addOperand(MO); 2157 } 2158 return MIB; 2159} 2160 2161static MachineInstr *FuseInst(MachineFunction &MF, 2162 unsigned Opcode, unsigned OpNo, 2163 const SmallVectorImpl<MachineOperand> &MOs, 2164 MachineInstr *MI, const TargetInstrInfo &TII) { 2165 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2166 MI->getDebugLoc(), true); 2167 MachineInstrBuilder MIB(NewMI); 2168 2169 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2170 MachineOperand &MO = MI->getOperand(i); 2171 if (i == OpNo) { 2172 assert(MO.isReg() && "Expected to fold into reg operand!"); 2173 unsigned NumAddrOps = MOs.size(); 2174 for (unsigned i = 0; i != NumAddrOps; ++i) 2175 MIB.addOperand(MOs[i]); 2176 if (NumAddrOps < 4) // FrameIndex only 2177 addOffset(MIB, 0); 2178 } else { 2179 MIB.addOperand(MO); 2180 } 2181 } 2182 return MIB; 2183} 2184 2185static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 2186 const SmallVectorImpl<MachineOperand> &MOs, 2187 MachineInstr *MI) { 2188 MachineFunction &MF = *MI->getParent()->getParent(); 2189 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 2190 2191 unsigned NumAddrOps = MOs.size(); 2192 for (unsigned i = 0; i != NumAddrOps; ++i) 2193 MIB.addOperand(MOs[i]); 2194 if (NumAddrOps < 4) // FrameIndex only 2195 addOffset(MIB, 0); 2196 return MIB.addImm(0); 2197} 2198 2199MachineInstr* 2200X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2201 MachineInstr *MI, unsigned i, 2202 const SmallVectorImpl<MachineOperand> &MOs, 2203 unsigned Size, unsigned Align) const { 2204 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL; 2205 bool isTwoAddrFold = false; 2206 unsigned NumOps = MI->getDesc().getNumOperands(); 2207 bool isTwoAddr = NumOps > 1 && 2208 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2209 2210 MachineInstr *NewMI = NULL; 2211 // Folding a memory location into the two-address part of a two-address 2212 // instruction is different than folding it other places. It requires 2213 // replacing the *two* registers with the memory location. 2214 if (isTwoAddr && NumOps >= 2 && i < 2 && 2215 MI->getOperand(0).isReg() && 2216 MI->getOperand(1).isReg() && 2217 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 2218 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2219 isTwoAddrFold = true; 2220 } else if (i == 0) { // If operand 0 2221 if (MI->getOpcode() == X86::MOV64r0) 2222 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); 2223 else if (MI->getOpcode() == X86::MOV32r0) 2224 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 2225 else if (MI->getOpcode() == X86::MOV16r0) 2226 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); 2227 else if (MI->getOpcode() == X86::MOV8r0) 2228 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); 2229 if (NewMI) 2230 return NewMI; 2231 2232 OpcodeTablePtr = &RegOp2MemOpTable0; 2233 } else if (i == 1) { 2234 OpcodeTablePtr = &RegOp2MemOpTable1; 2235 } else if (i == 2) { 2236 OpcodeTablePtr = &RegOp2MemOpTable2; 2237 } 2238 2239 // If table selected... 2240 if (OpcodeTablePtr) { 2241 // Find the Opcode to fuse 2242 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2243 OpcodeTablePtr->find((unsigned*)MI->getOpcode()); 2244 if (I != OpcodeTablePtr->end()) { 2245 unsigned Opcode = I->second.first; 2246 unsigned MinAlign = I->second.second; 2247 if (Align < MinAlign) 2248 return NULL; 2249 bool NarrowToMOV32rm = false; 2250 if (Size) { 2251 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize(); 2252 if (Size < RCSize) { 2253 // Check if it's safe to fold the load. If the size of the object is 2254 // narrower than the load width, then it's not. 2255 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 2256 return NULL; 2257 // If this is a 64-bit load, but the spill slot is 32, then we can do 2258 // a 32-bit load which is implicitly zero-extended. This likely is due 2259 // to liveintervalanalysis remat'ing a load from stack slot. 2260 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 2261 return NULL; 2262 Opcode = X86::MOV32rm; 2263 NarrowToMOV32rm = true; 2264 } 2265 } 2266 2267 if (isTwoAddrFold) 2268 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 2269 else 2270 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 2271 2272 if (NarrowToMOV32rm) { 2273 // If this is the special case where we use a MOV32rm to load a 32-bit 2274 // value and zero-extend the top bits. Change the destination register 2275 // to a 32-bit one. 2276 unsigned DstReg = NewMI->getOperand(0).getReg(); 2277 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 2278 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 2279 X86::sub_32bit)); 2280 else 2281 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 2282 } 2283 return NewMI; 2284 } 2285 } 2286 2287 // No fusion 2288 if (PrintFailedFusing && !MI->isCopy()) 2289 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 2290 return NULL; 2291} 2292 2293 2294MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2295 MachineInstr *MI, 2296 const SmallVectorImpl<unsigned> &Ops, 2297 int FrameIndex) const { 2298 // Check switch flag 2299 if (NoFusing) return NULL; 2300 2301 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2302 switch (MI->getOpcode()) { 2303 case X86::CVTSD2SSrr: 2304 case X86::Int_CVTSD2SSrr: 2305 case X86::CVTSS2SDrr: 2306 case X86::Int_CVTSS2SDrr: 2307 case X86::RCPSSr: 2308 case X86::RCPSSr_Int: 2309 case X86::ROUNDSDr_Int: 2310 case X86::ROUNDSSr_Int: 2311 case X86::RSQRTSSr: 2312 case X86::RSQRTSSr_Int: 2313 case X86::SQRTSSr: 2314 case X86::SQRTSSr_Int: 2315 return 0; 2316 } 2317 2318 const MachineFrameInfo *MFI = MF.getFrameInfo(); 2319 unsigned Size = MFI->getObjectSize(FrameIndex); 2320 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 2321 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2322 unsigned NewOpc = 0; 2323 unsigned RCSize = 0; 2324 switch (MI->getOpcode()) { 2325 default: return NULL; 2326 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 2327 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 2328 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 2329 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 2330 } 2331 // Check if it's safe to fold the load. If the size of the object is 2332 // narrower than the load width, then it's not. 2333 if (Size < RCSize) 2334 return NULL; 2335 // Change to CMPXXri r, 0 first. 2336 MI->setDesc(get(NewOpc)); 2337 MI->getOperand(1).ChangeToImmediate(0); 2338 } else if (Ops.size() != 1) 2339 return NULL; 2340 2341 SmallVector<MachineOperand,4> MOs; 2342 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 2343 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 2344} 2345 2346MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2347 MachineInstr *MI, 2348 const SmallVectorImpl<unsigned> &Ops, 2349 MachineInstr *LoadMI) const { 2350 // Check switch flag 2351 if (NoFusing) return NULL; 2352 2353 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2354 switch (MI->getOpcode()) { 2355 case X86::CVTSD2SSrr: 2356 case X86::Int_CVTSD2SSrr: 2357 case X86::CVTSS2SDrr: 2358 case X86::Int_CVTSS2SDrr: 2359 case X86::RCPSSr: 2360 case X86::RCPSSr_Int: 2361 case X86::ROUNDSDr_Int: 2362 case X86::ROUNDSSr_Int: 2363 case X86::RSQRTSSr: 2364 case X86::RSQRTSSr_Int: 2365 case X86::SQRTSSr: 2366 case X86::SQRTSSr_Int: 2367 return 0; 2368 } 2369 2370 // Determine the alignment of the load. 2371 unsigned Alignment = 0; 2372 if (LoadMI->hasOneMemOperand()) 2373 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 2374 else 2375 switch (LoadMI->getOpcode()) { 2376 case X86::V_SET0PS: 2377 case X86::V_SET0PD: 2378 case X86::V_SET0PI: 2379 case X86::V_SETALLONES: 2380 Alignment = 16; 2381 break; 2382 case X86::FsFLD0SD: 2383 Alignment = 8; 2384 break; 2385 case X86::FsFLD0SS: 2386 Alignment = 4; 2387 break; 2388 default: 2389 llvm_unreachable("Don't know how to fold this instruction!"); 2390 } 2391 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2392 unsigned NewOpc = 0; 2393 switch (MI->getOpcode()) { 2394 default: return NULL; 2395 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2396 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 2397 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 2398 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 2399 } 2400 // Change to CMPXXri r, 0 first. 2401 MI->setDesc(get(NewOpc)); 2402 MI->getOperand(1).ChangeToImmediate(0); 2403 } else if (Ops.size() != 1) 2404 return NULL; 2405 2406 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 2407 switch (LoadMI->getOpcode()) { 2408 case X86::V_SET0PS: 2409 case X86::V_SET0PD: 2410 case X86::V_SET0PI: 2411 case X86::V_SETALLONES: 2412 case X86::FsFLD0SD: 2413 case X86::FsFLD0SS: { 2414 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure. 2415 // Create a constant-pool entry and operands to load from it. 2416 2417 // Medium and large mode can't fold loads this way. 2418 if (TM.getCodeModel() != CodeModel::Small && 2419 TM.getCodeModel() != CodeModel::Kernel) 2420 return NULL; 2421 2422 // x86-32 PIC requires a PIC base register for constant pools. 2423 unsigned PICBase = 0; 2424 if (TM.getRelocationModel() == Reloc::PIC_) { 2425 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2426 PICBase = X86::RIP; 2427 else 2428 // FIXME: PICBase = getGlobalBaseReg(&MF); 2429 // This doesn't work for several reasons. 2430 // 1. GlobalBaseReg may have been spilled. 2431 // 2. It may not be live at MI. 2432 return NULL; 2433 } 2434 2435 // Create a constant-pool entry. 2436 MachineConstantPool &MCP = *MF.getConstantPool(); 2437 const Type *Ty; 2438 if (LoadMI->getOpcode() == X86::FsFLD0SS) 2439 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 2440 else if (LoadMI->getOpcode() == X86::FsFLD0SD) 2441 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 2442 else 2443 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 2444 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ? 2445 Constant::getAllOnesValue(Ty) : 2446 Constant::getNullValue(Ty); 2447 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 2448 2449 // Create operands to load from the constant pool entry. 2450 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 2451 MOs.push_back(MachineOperand::CreateImm(1)); 2452 MOs.push_back(MachineOperand::CreateReg(0, false)); 2453 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 2454 MOs.push_back(MachineOperand::CreateReg(0, false)); 2455 break; 2456 } 2457 default: { 2458 // Folding a normal load. Just copy the load's address operands. 2459 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 2460 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 2461 MOs.push_back(LoadMI->getOperand(i)); 2462 break; 2463 } 2464 } 2465 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 2466} 2467 2468 2469bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 2470 const SmallVectorImpl<unsigned> &Ops) const { 2471 // Check switch flag 2472 if (NoFusing) return 0; 2473 2474 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2475 switch (MI->getOpcode()) { 2476 default: return false; 2477 case X86::TEST8rr: 2478 case X86::TEST16rr: 2479 case X86::TEST32rr: 2480 case X86::TEST64rr: 2481 return true; 2482 } 2483 } 2484 2485 if (Ops.size() != 1) 2486 return false; 2487 2488 unsigned OpNum = Ops[0]; 2489 unsigned Opc = MI->getOpcode(); 2490 unsigned NumOps = MI->getDesc().getNumOperands(); 2491 bool isTwoAddr = NumOps > 1 && 2492 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2493 2494 // Folding a memory location into the two-address part of a two-address 2495 // instruction is different than folding it other places. It requires 2496 // replacing the *two* registers with the memory location. 2497 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL; 2498 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 2499 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2500 } else if (OpNum == 0) { // If operand 0 2501 switch (Opc) { 2502 case X86::MOV8r0: 2503 case X86::MOV16r0: 2504 case X86::MOV32r0: 2505 case X86::MOV64r0: 2506 return true; 2507 default: break; 2508 } 2509 OpcodeTablePtr = &RegOp2MemOpTable0; 2510 } else if (OpNum == 1) { 2511 OpcodeTablePtr = &RegOp2MemOpTable1; 2512 } else if (OpNum == 2) { 2513 OpcodeTablePtr = &RegOp2MemOpTable2; 2514 } 2515 2516 if (OpcodeTablePtr) { 2517 // Find the Opcode to fuse 2518 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2519 OpcodeTablePtr->find((unsigned*)Opc); 2520 if (I != OpcodeTablePtr->end()) 2521 return true; 2522 } 2523 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops); 2524} 2525 2526bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2527 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2528 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2529 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2530 MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); 2531 if (I == MemOp2RegOpTable.end()) 2532 return false; 2533 unsigned Opc = I->second.first; 2534 unsigned Index = I->second.second & 0xf; 2535 bool FoldedLoad = I->second.second & (1 << 4); 2536 bool FoldedStore = I->second.second & (1 << 5); 2537 if (UnfoldLoad && !FoldedLoad) 2538 return false; 2539 UnfoldLoad &= FoldedLoad; 2540 if (UnfoldStore && !FoldedStore) 2541 return false; 2542 UnfoldStore &= FoldedStore; 2543 2544 const TargetInstrDesc &TID = get(Opc); 2545 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2546 const TargetRegisterClass *RC = TOI.getRegClass(&RI); 2547 if (!MI->hasOneMemOperand() && 2548 RC == &X86::VR128RegClass && 2549 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2550 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 2551 // conservatively assume the address is unaligned. That's bad for 2552 // performance. 2553 return false; 2554 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 2555 SmallVector<MachineOperand,2> BeforeOps; 2556 SmallVector<MachineOperand,2> AfterOps; 2557 SmallVector<MachineOperand,4> ImpOps; 2558 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2559 MachineOperand &Op = MI->getOperand(i); 2560 if (i >= Index && i < Index + X86::AddrNumOperands) 2561 AddrOps.push_back(Op); 2562 else if (Op.isReg() && Op.isImplicit()) 2563 ImpOps.push_back(Op); 2564 else if (i < Index) 2565 BeforeOps.push_back(Op); 2566 else if (i > Index) 2567 AfterOps.push_back(Op); 2568 } 2569 2570 // Emit the load instruction. 2571 if (UnfoldLoad) { 2572 std::pair<MachineInstr::mmo_iterator, 2573 MachineInstr::mmo_iterator> MMOs = 2574 MF.extractLoadMemRefs(MI->memoperands_begin(), 2575 MI->memoperands_end()); 2576 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 2577 if (UnfoldStore) { 2578 // Address operands cannot be marked isKill. 2579 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 2580 MachineOperand &MO = NewMIs[0]->getOperand(i); 2581 if (MO.isReg()) 2582 MO.setIsKill(false); 2583 } 2584 } 2585 } 2586 2587 // Emit the data processing instruction. 2588 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); 2589 MachineInstrBuilder MIB(DataMI); 2590 2591 if (FoldedStore) 2592 MIB.addReg(Reg, RegState::Define); 2593 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 2594 MIB.addOperand(BeforeOps[i]); 2595 if (FoldedLoad) 2596 MIB.addReg(Reg); 2597 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 2598 MIB.addOperand(AfterOps[i]); 2599 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 2600 MachineOperand &MO = ImpOps[i]; 2601 MIB.addReg(MO.getReg(), 2602 getDefRegState(MO.isDef()) | 2603 RegState::Implicit | 2604 getKillRegState(MO.isKill()) | 2605 getDeadRegState(MO.isDead()) | 2606 getUndefRegState(MO.isUndef())); 2607 } 2608 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 2609 unsigned NewOpc = 0; 2610 switch (DataMI->getOpcode()) { 2611 default: break; 2612 case X86::CMP64ri32: 2613 case X86::CMP64ri8: 2614 case X86::CMP32ri: 2615 case X86::CMP32ri8: 2616 case X86::CMP16ri: 2617 case X86::CMP16ri8: 2618 case X86::CMP8ri: { 2619 MachineOperand &MO0 = DataMI->getOperand(0); 2620 MachineOperand &MO1 = DataMI->getOperand(1); 2621 if (MO1.getImm() == 0) { 2622 switch (DataMI->getOpcode()) { 2623 default: break; 2624 case X86::CMP64ri8: 2625 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 2626 case X86::CMP32ri8: 2627 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 2628 case X86::CMP16ri8: 2629 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 2630 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 2631 } 2632 DataMI->setDesc(get(NewOpc)); 2633 MO1.ChangeToRegister(MO0.getReg(), false); 2634 } 2635 } 2636 } 2637 NewMIs.push_back(DataMI); 2638 2639 // Emit the store instruction. 2640 if (UnfoldStore) { 2641 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI); 2642 std::pair<MachineInstr::mmo_iterator, 2643 MachineInstr::mmo_iterator> MMOs = 2644 MF.extractStoreMemRefs(MI->memoperands_begin(), 2645 MI->memoperands_end()); 2646 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 2647 } 2648 2649 return true; 2650} 2651 2652bool 2653X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 2654 SmallVectorImpl<SDNode*> &NewNodes) const { 2655 if (!N->isMachineOpcode()) 2656 return false; 2657 2658 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2659 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode()); 2660 if (I == MemOp2RegOpTable.end()) 2661 return false; 2662 unsigned Opc = I->second.first; 2663 unsigned Index = I->second.second & 0xf; 2664 bool FoldedLoad = I->second.second & (1 << 4); 2665 bool FoldedStore = I->second.second & (1 << 5); 2666 const TargetInstrDesc &TID = get(Opc); 2667 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI); 2668 unsigned NumDefs = TID.NumDefs; 2669 std::vector<SDValue> AddrOps; 2670 std::vector<SDValue> BeforeOps; 2671 std::vector<SDValue> AfterOps; 2672 DebugLoc dl = N->getDebugLoc(); 2673 unsigned NumOps = N->getNumOperands(); 2674 for (unsigned i = 0; i != NumOps-1; ++i) { 2675 SDValue Op = N->getOperand(i); 2676 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 2677 AddrOps.push_back(Op); 2678 else if (i < Index-NumDefs) 2679 BeforeOps.push_back(Op); 2680 else if (i > Index-NumDefs) 2681 AfterOps.push_back(Op); 2682 } 2683 SDValue Chain = N->getOperand(NumOps-1); 2684 AddrOps.push_back(Chain); 2685 2686 // Emit the load instruction. 2687 SDNode *Load = 0; 2688 MachineFunction &MF = DAG.getMachineFunction(); 2689 if (FoldedLoad) { 2690 EVT VT = *RC->vt_begin(); 2691 std::pair<MachineInstr::mmo_iterator, 2692 MachineInstr::mmo_iterator> MMOs = 2693 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2694 cast<MachineSDNode>(N)->memoperands_end()); 2695 if (!(*MMOs.first) && 2696 RC == &X86::VR128RegClass && 2697 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2698 // Do not introduce a slow unaligned load. 2699 return false; 2700 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16; 2701 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 2702 VT, MVT::Other, &AddrOps[0], AddrOps.size()); 2703 NewNodes.push_back(Load); 2704 2705 // Preserve memory reference information. 2706 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2707 } 2708 2709 // Emit the data processing instruction. 2710 std::vector<EVT> VTs; 2711 const TargetRegisterClass *DstRC = 0; 2712 if (TID.getNumDefs() > 0) { 2713 DstRC = TID.OpInfo[0].getRegClass(&RI); 2714 VTs.push_back(*DstRC->vt_begin()); 2715 } 2716 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 2717 EVT VT = N->getValueType(i); 2718 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) 2719 VTs.push_back(VT); 2720 } 2721 if (Load) 2722 BeforeOps.push_back(SDValue(Load, 0)); 2723 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 2724 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], 2725 BeforeOps.size()); 2726 NewNodes.push_back(NewNode); 2727 2728 // Emit the store instruction. 2729 if (FoldedStore) { 2730 AddrOps.pop_back(); 2731 AddrOps.push_back(SDValue(NewNode, 0)); 2732 AddrOps.push_back(Chain); 2733 std::pair<MachineInstr::mmo_iterator, 2734 MachineInstr::mmo_iterator> MMOs = 2735 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2736 cast<MachineSDNode>(N)->memoperands_end()); 2737 if (!(*MMOs.first) && 2738 RC == &X86::VR128RegClass && 2739 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2740 // Do not introduce a slow unaligned store. 2741 return false; 2742 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16; 2743 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 2744 isAligned, TM), 2745 dl, MVT::Other, 2746 &AddrOps[0], AddrOps.size()); 2747 NewNodes.push_back(Store); 2748 2749 // Preserve memory reference information. 2750 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2751 } 2752 2753 return true; 2754} 2755 2756unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 2757 bool UnfoldLoad, bool UnfoldStore, 2758 unsigned *LoadRegIndex) const { 2759 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2760 MemOp2RegOpTable.find((unsigned*)Opc); 2761 if (I == MemOp2RegOpTable.end()) 2762 return 0; 2763 bool FoldedLoad = I->second.second & (1 << 4); 2764 bool FoldedStore = I->second.second & (1 << 5); 2765 if (UnfoldLoad && !FoldedLoad) 2766 return 0; 2767 if (UnfoldStore && !FoldedStore) 2768 return 0; 2769 if (LoadRegIndex) 2770 *LoadRegIndex = I->second.second & 0xf; 2771 return I->second.first; 2772} 2773 2774bool 2775X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 2776 int64_t &Offset1, int64_t &Offset2) const { 2777 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 2778 return false; 2779 unsigned Opc1 = Load1->getMachineOpcode(); 2780 unsigned Opc2 = Load2->getMachineOpcode(); 2781 switch (Opc1) { 2782 default: return false; 2783 case X86::MOV8rm: 2784 case X86::MOV16rm: 2785 case X86::MOV32rm: 2786 case X86::MOV64rm: 2787 case X86::LD_Fp32m: 2788 case X86::LD_Fp64m: 2789 case X86::LD_Fp80m: 2790 case X86::MOVSSrm: 2791 case X86::MOVSDrm: 2792 case X86::MMX_MOVD64rm: 2793 case X86::MMX_MOVQ64rm: 2794 case X86::FsMOVAPSrm: 2795 case X86::FsMOVAPDrm: 2796 case X86::MOVAPSrm: 2797 case X86::MOVUPSrm: 2798 case X86::MOVUPSrm_Int: 2799 case X86::MOVAPDrm: 2800 case X86::MOVDQArm: 2801 case X86::MOVDQUrm: 2802 case X86::MOVDQUrm_Int: 2803 break; 2804 } 2805 switch (Opc2) { 2806 default: return false; 2807 case X86::MOV8rm: 2808 case X86::MOV16rm: 2809 case X86::MOV32rm: 2810 case X86::MOV64rm: 2811 case X86::LD_Fp32m: 2812 case X86::LD_Fp64m: 2813 case X86::LD_Fp80m: 2814 case X86::MOVSSrm: 2815 case X86::MOVSDrm: 2816 case X86::MMX_MOVD64rm: 2817 case X86::MMX_MOVQ64rm: 2818 case X86::FsMOVAPSrm: 2819 case X86::FsMOVAPDrm: 2820 case X86::MOVAPSrm: 2821 case X86::MOVUPSrm: 2822 case X86::MOVUPSrm_Int: 2823 case X86::MOVAPDrm: 2824 case X86::MOVDQArm: 2825 case X86::MOVDQUrm: 2826 case X86::MOVDQUrm_Int: 2827 break; 2828 } 2829 2830 // Check if chain operands and base addresses match. 2831 if (Load1->getOperand(0) != Load2->getOperand(0) || 2832 Load1->getOperand(5) != Load2->getOperand(5)) 2833 return false; 2834 // Segment operands should match as well. 2835 if (Load1->getOperand(4) != Load2->getOperand(4)) 2836 return false; 2837 // Scale should be 1, Index should be Reg0. 2838 if (Load1->getOperand(1) == Load2->getOperand(1) && 2839 Load1->getOperand(2) == Load2->getOperand(2)) { 2840 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 2841 return false; 2842 2843 // Now let's examine the displacements. 2844 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 2845 isa<ConstantSDNode>(Load2->getOperand(3))) { 2846 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 2847 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 2848 return true; 2849 } 2850 } 2851 return false; 2852} 2853 2854bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 2855 int64_t Offset1, int64_t Offset2, 2856 unsigned NumLoads) const { 2857 assert(Offset2 > Offset1); 2858 if ((Offset2 - Offset1) / 8 > 64) 2859 return false; 2860 2861 unsigned Opc1 = Load1->getMachineOpcode(); 2862 unsigned Opc2 = Load2->getMachineOpcode(); 2863 if (Opc1 != Opc2) 2864 return false; // FIXME: overly conservative? 2865 2866 switch (Opc1) { 2867 default: break; 2868 case X86::LD_Fp32m: 2869 case X86::LD_Fp64m: 2870 case X86::LD_Fp80m: 2871 case X86::MMX_MOVD64rm: 2872 case X86::MMX_MOVQ64rm: 2873 return false; 2874 } 2875 2876 EVT VT = Load1->getValueType(0); 2877 switch (VT.getSimpleVT().SimpleTy) { 2878 default: 2879 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 2880 // have 16 of them to play with. 2881 if (TM.getSubtargetImpl()->is64Bit()) { 2882 if (NumLoads >= 3) 2883 return false; 2884 } else if (NumLoads) { 2885 return false; 2886 } 2887 break; 2888 case MVT::i8: 2889 case MVT::i16: 2890 case MVT::i32: 2891 case MVT::i64: 2892 case MVT::f32: 2893 case MVT::f64: 2894 if (NumLoads) 2895 return false; 2896 break; 2897 } 2898 2899 return true; 2900} 2901 2902 2903bool X86InstrInfo:: 2904ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 2905 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 2906 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 2907 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 2908 return true; 2909 Cond[0].setImm(GetOppositeBranchCondition(CC)); 2910 return false; 2911} 2912 2913bool X86InstrInfo:: 2914isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 2915 // FIXME: Return false for x87 stack register classes for now. We can't 2916 // allow any loads of these registers before FpGet_ST0_80. 2917 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 2918 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 2919} 2920 2921 2922/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) 2923/// register? e.g. r8, xmm8, xmm13, etc. 2924bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) { 2925 switch (RegNo) { 2926 default: break; 2927 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 2928 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 2929 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 2930 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 2931 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 2932 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 2933 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 2934 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 2935 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 2936 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 2937 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: 2938 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: 2939 return true; 2940 } 2941 return false; 2942} 2943 2944 2945/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 2946/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 2947/// size, and 3) use of X86-64 extended registers. 2948unsigned X86InstrInfo::determineREX(const MachineInstr &MI) { 2949 unsigned REX = 0; 2950 const TargetInstrDesc &Desc = MI.getDesc(); 2951 2952 // Pseudo instructions do not need REX prefix byte. 2953 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 2954 return 0; 2955 if (Desc.TSFlags & X86II::REX_W) 2956 REX |= 1 << 3; 2957 2958 unsigned NumOps = Desc.getNumOperands(); 2959 if (NumOps) { 2960 bool isTwoAddr = NumOps > 1 && 2961 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; 2962 2963 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 2964 unsigned i = isTwoAddr ? 1 : 0; 2965 for (unsigned e = NumOps; i != e; ++i) { 2966 const MachineOperand& MO = MI.getOperand(i); 2967 if (MO.isReg()) { 2968 unsigned Reg = MO.getReg(); 2969 if (isX86_64NonExtLowByteReg(Reg)) 2970 REX |= 0x40; 2971 } 2972 } 2973 2974 switch (Desc.TSFlags & X86II::FormMask) { 2975 case X86II::MRMInitReg: 2976 if (isX86_64ExtendedReg(MI.getOperand(0))) 2977 REX |= (1 << 0) | (1 << 2); 2978 break; 2979 case X86II::MRMSrcReg: { 2980 if (isX86_64ExtendedReg(MI.getOperand(0))) 2981 REX |= 1 << 2; 2982 i = isTwoAddr ? 2 : 1; 2983 for (unsigned e = NumOps; i != e; ++i) { 2984 const MachineOperand& MO = MI.getOperand(i); 2985 if (isX86_64ExtendedReg(MO)) 2986 REX |= 1 << 0; 2987 } 2988 break; 2989 } 2990 case X86II::MRMSrcMem: { 2991 if (isX86_64ExtendedReg(MI.getOperand(0))) 2992 REX |= 1 << 2; 2993 unsigned Bit = 0; 2994 i = isTwoAddr ? 2 : 1; 2995 for (; i != NumOps; ++i) { 2996 const MachineOperand& MO = MI.getOperand(i); 2997 if (MO.isReg()) { 2998 if (isX86_64ExtendedReg(MO)) 2999 REX |= 1 << Bit; 3000 Bit++; 3001 } 3002 } 3003 break; 3004 } 3005 case X86II::MRM0m: case X86II::MRM1m: 3006 case X86II::MRM2m: case X86II::MRM3m: 3007 case X86II::MRM4m: case X86II::MRM5m: 3008 case X86II::MRM6m: case X86II::MRM7m: 3009 case X86II::MRMDestMem: { 3010 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 3011 i = isTwoAddr ? 1 : 0; 3012 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) 3013 REX |= 1 << 2; 3014 unsigned Bit = 0; 3015 for (; i != e; ++i) { 3016 const MachineOperand& MO = MI.getOperand(i); 3017 if (MO.isReg()) { 3018 if (isX86_64ExtendedReg(MO)) 3019 REX |= 1 << Bit; 3020 Bit++; 3021 } 3022 } 3023 break; 3024 } 3025 default: { 3026 if (isX86_64ExtendedReg(MI.getOperand(0))) 3027 REX |= 1 << 0; 3028 i = isTwoAddr ? 2 : 1; 3029 for (unsigned e = NumOps; i != e; ++i) { 3030 const MachineOperand& MO = MI.getOperand(i); 3031 if (isX86_64ExtendedReg(MO)) 3032 REX |= 1 << 2; 3033 } 3034 break; 3035 } 3036 } 3037 } 3038 return REX; 3039} 3040 3041/// sizePCRelativeBlockAddress - This method returns the size of a PC 3042/// relative block address instruction 3043/// 3044static unsigned sizePCRelativeBlockAddress() { 3045 return 4; 3046} 3047 3048/// sizeGlobalAddress - Give the size of the emission of this global address 3049/// 3050static unsigned sizeGlobalAddress(bool dword) { 3051 return dword ? 8 : 4; 3052} 3053 3054/// sizeConstPoolAddress - Give the size of the emission of this constant 3055/// pool address 3056/// 3057static unsigned sizeConstPoolAddress(bool dword) { 3058 return dword ? 8 : 4; 3059} 3060 3061/// sizeExternalSymbolAddress - Give the size of the emission of this external 3062/// symbol 3063/// 3064static unsigned sizeExternalSymbolAddress(bool dword) { 3065 return dword ? 8 : 4; 3066} 3067 3068/// sizeJumpTableAddress - Give the size of the emission of this jump 3069/// table address 3070/// 3071static unsigned sizeJumpTableAddress(bool dword) { 3072 return dword ? 8 : 4; 3073} 3074 3075static unsigned sizeConstant(unsigned Size) { 3076 return Size; 3077} 3078 3079static unsigned sizeRegModRMByte(){ 3080 return 1; 3081} 3082 3083static unsigned sizeSIBByte(){ 3084 return 1; 3085} 3086 3087static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) { 3088 unsigned FinalSize = 0; 3089 // If this is a simple integer displacement that doesn't require a relocation. 3090 if (!RelocOp) { 3091 FinalSize += sizeConstant(4); 3092 return FinalSize; 3093 } 3094 3095 // Otherwise, this is something that requires a relocation. 3096 if (RelocOp->isGlobal()) { 3097 FinalSize += sizeGlobalAddress(false); 3098 } else if (RelocOp->isCPI()) { 3099 FinalSize += sizeConstPoolAddress(false); 3100 } else if (RelocOp->isJTI()) { 3101 FinalSize += sizeJumpTableAddress(false); 3102 } else { 3103 llvm_unreachable("Unknown value to relocate!"); 3104 } 3105 return FinalSize; 3106} 3107 3108static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op, 3109 bool IsPIC, bool Is64BitMode) { 3110 const MachineOperand &Op3 = MI.getOperand(Op+3); 3111 int DispVal = 0; 3112 const MachineOperand *DispForReloc = 0; 3113 unsigned FinalSize = 0; 3114 3115 // Figure out what sort of displacement we have to handle here. 3116 if (Op3.isGlobal()) { 3117 DispForReloc = &Op3; 3118 } else if (Op3.isCPI()) { 3119 if (Is64BitMode || IsPIC) { 3120 DispForReloc = &Op3; 3121 } else { 3122 DispVal = 1; 3123 } 3124 } else if (Op3.isJTI()) { 3125 if (Is64BitMode || IsPIC) { 3126 DispForReloc = &Op3; 3127 } else { 3128 DispVal = 1; 3129 } 3130 } else { 3131 DispVal = 1; 3132 } 3133 3134 const MachineOperand &Base = MI.getOperand(Op); 3135 const MachineOperand &IndexReg = MI.getOperand(Op+2); 3136 3137 unsigned BaseReg = Base.getReg(); 3138 3139 // Is a SIB byte needed? 3140 if ((!Is64BitMode || DispForReloc || BaseReg != 0) && 3141 IndexReg.getReg() == 0 && 3142 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) { 3143 if (BaseReg == 0) { // Just a displacement? 3144 // Emit special case [disp32] encoding 3145 ++FinalSize; 3146 FinalSize += getDisplacementFieldSize(DispForReloc); 3147 } else { 3148 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg); 3149 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 3150 // Emit simple indirect register encoding... [EAX] f.e. 3151 ++FinalSize; 3152 // Be pessimistic and assume it's a disp32, not a disp8 3153 } else { 3154 // Emit the most general non-SIB encoding: [REG+disp32] 3155 ++FinalSize; 3156 FinalSize += getDisplacementFieldSize(DispForReloc); 3157 } 3158 } 3159 3160 } else { // We need a SIB byte, so start by outputting the ModR/M byte first 3161 assert(IndexReg.getReg() != X86::ESP && 3162 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 3163 3164 bool ForceDisp32 = false; 3165 if (BaseReg == 0 || DispForReloc) { 3166 // Emit the normal disp32 encoding. 3167 ++FinalSize; 3168 ForceDisp32 = true; 3169 } else { 3170 ++FinalSize; 3171 } 3172 3173 FinalSize += sizeSIBByte(); 3174 3175 // Do we need to output a displacement? 3176 if (DispVal != 0 || ForceDisp32) { 3177 FinalSize += getDisplacementFieldSize(DispForReloc); 3178 } 3179 } 3180 return FinalSize; 3181} 3182 3183 3184static unsigned GetInstSizeWithDesc(const MachineInstr &MI, 3185 const TargetInstrDesc *Desc, 3186 bool IsPIC, bool Is64BitMode) { 3187 3188 unsigned Opcode = Desc->Opcode; 3189 unsigned FinalSize = 0; 3190 3191 // Emit the lock opcode prefix as needed. 3192 if (Desc->TSFlags & X86II::LOCK) ++FinalSize; 3193 3194 // Emit segment override opcode prefix as needed. 3195 switch (Desc->TSFlags & X86II::SegOvrMask) { 3196 case X86II::FS: 3197 case X86II::GS: 3198 ++FinalSize; 3199 break; 3200 default: llvm_unreachable("Invalid segment!"); 3201 case 0: break; // No segment override! 3202 } 3203 3204 // Emit the repeat opcode prefix as needed. 3205 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize; 3206 3207 // Emit the operand size opcode prefix as needed. 3208 if (Desc->TSFlags & X86II::OpSize) ++FinalSize; 3209 3210 // Emit the address size opcode prefix as needed. 3211 if (Desc->TSFlags & X86II::AdSize) ++FinalSize; 3212 3213 bool Need0FPrefix = false; 3214 switch (Desc->TSFlags & X86II::Op0Mask) { 3215 case X86II::TB: // Two-byte opcode prefix 3216 case X86II::T8: // 0F 38 3217 case X86II::TA: // 0F 3A 3218 Need0FPrefix = true; 3219 break; 3220 case X86II::TF: // F2 0F 38 3221 ++FinalSize; 3222 Need0FPrefix = true; 3223 break; 3224 case X86II::REP: break; // already handled. 3225 case X86II::XS: // F3 0F 3226 ++FinalSize; 3227 Need0FPrefix = true; 3228 break; 3229 case X86II::XD: // F2 0F 3230 ++FinalSize; 3231 Need0FPrefix = true; 3232 break; 3233 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 3234 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 3235 ++FinalSize; 3236 break; // Two-byte opcode prefix 3237 default: llvm_unreachable("Invalid prefix!"); 3238 case 0: break; // No prefix! 3239 } 3240 3241 if (Is64BitMode) { 3242 // REX prefix 3243 unsigned REX = X86InstrInfo::determineREX(MI); 3244 if (REX) 3245 ++FinalSize; 3246 } 3247 3248 // 0x0F escape code must be emitted just before the opcode. 3249 if (Need0FPrefix) 3250 ++FinalSize; 3251 3252 switch (Desc->TSFlags & X86II::Op0Mask) { 3253 case X86II::T8: // 0F 38 3254 ++FinalSize; 3255 break; 3256 case X86II::TA: // 0F 3A 3257 ++FinalSize; 3258 break; 3259 case X86II::TF: // F2 0F 38 3260 ++FinalSize; 3261 break; 3262 } 3263 3264 // If this is a two-address instruction, skip one of the register operands. 3265 unsigned NumOps = Desc->getNumOperands(); 3266 unsigned CurOp = 0; 3267 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) 3268 CurOp++; 3269 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0) 3270 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 3271 --NumOps; 3272 3273 switch (Desc->TSFlags & X86II::FormMask) { 3274 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); 3275 case X86II::Pseudo: 3276 // Remember the current PC offset, this is the PIC relocation 3277 // base address. 3278 switch (Opcode) { 3279 default: 3280 break; 3281 case TargetOpcode::INLINEASM: { 3282 const MachineFunction *MF = MI.getParent()->getParent(); 3283 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 3284 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(), 3285 *MF->getTarget().getMCAsmInfo()); 3286 break; 3287 } 3288 case TargetOpcode::PROLOG_LABEL: 3289 case TargetOpcode::EH_LABEL: 3290 case TargetOpcode::DBG_VALUE: 3291 break; 3292 case TargetOpcode::IMPLICIT_DEF: 3293 case TargetOpcode::KILL: 3294 break; 3295 case X86::MOVPC32r: { 3296 // This emits the "call" portion of this pseudo instruction. 3297 ++FinalSize; 3298 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3299 break; 3300 } 3301 } 3302 CurOp = NumOps; 3303 break; 3304 case X86II::RawFrm: 3305 ++FinalSize; 3306 3307 if (CurOp != NumOps) { 3308 const MachineOperand &MO = MI.getOperand(CurOp++); 3309 if (MO.isMBB()) { 3310 FinalSize += sizePCRelativeBlockAddress(); 3311 } else if (MO.isGlobal()) { 3312 FinalSize += sizeGlobalAddress(false); 3313 } else if (MO.isSymbol()) { 3314 FinalSize += sizeExternalSymbolAddress(false); 3315 } else if (MO.isImm()) { 3316 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3317 } else { 3318 llvm_unreachable("Unknown RawFrm operand!"); 3319 } 3320 } 3321 break; 3322 3323 case X86II::AddRegFrm: 3324 ++FinalSize; 3325 ++CurOp; 3326 3327 if (CurOp != NumOps) { 3328 const MachineOperand &MO1 = MI.getOperand(CurOp++); 3329 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 3330 if (MO1.isImm()) 3331 FinalSize += sizeConstant(Size); 3332 else { 3333 bool dword = false; 3334 if (Opcode == X86::MOV64ri) 3335 dword = true; 3336 if (MO1.isGlobal()) { 3337 FinalSize += sizeGlobalAddress(dword); 3338 } else if (MO1.isSymbol()) 3339 FinalSize += sizeExternalSymbolAddress(dword); 3340 else if (MO1.isCPI()) 3341 FinalSize += sizeConstPoolAddress(dword); 3342 else if (MO1.isJTI()) 3343 FinalSize += sizeJumpTableAddress(dword); 3344 } 3345 } 3346 break; 3347 3348 case X86II::MRMDestReg: { 3349 ++FinalSize; 3350 FinalSize += sizeRegModRMByte(); 3351 CurOp += 2; 3352 if (CurOp != NumOps) { 3353 ++CurOp; 3354 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3355 } 3356 break; 3357 } 3358 case X86II::MRMDestMem: { 3359 ++FinalSize; 3360 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 3361 CurOp += X86::AddrNumOperands + 1; 3362 if (CurOp != NumOps) { 3363 ++CurOp; 3364 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3365 } 3366 break; 3367 } 3368 3369 case X86II::MRMSrcReg: 3370 ++FinalSize; 3371 FinalSize += sizeRegModRMByte(); 3372 CurOp += 2; 3373 if (CurOp != NumOps) { 3374 ++CurOp; 3375 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3376 } 3377 break; 3378 3379 case X86II::MRMSrcMem: { 3380 ++FinalSize; 3381 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode); 3382 CurOp += X86::AddrNumOperands + 1; 3383 if (CurOp != NumOps) { 3384 ++CurOp; 3385 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3386 } 3387 break; 3388 } 3389 3390 case X86II::MRM0r: case X86II::MRM1r: 3391 case X86II::MRM2r: case X86II::MRM3r: 3392 case X86II::MRM4r: case X86II::MRM5r: 3393 case X86II::MRM6r: case X86II::MRM7r: 3394 ++FinalSize; 3395 if (Desc->getOpcode() == X86::LFENCE || 3396 Desc->getOpcode() == X86::MFENCE) { 3397 // Special handling of lfence and mfence; 3398 FinalSize += sizeRegModRMByte(); 3399 } else if (Desc->getOpcode() == X86::MONITOR || 3400 Desc->getOpcode() == X86::MWAIT) { 3401 // Special handling of monitor and mwait. 3402 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode. 3403 } else { 3404 ++CurOp; 3405 FinalSize += sizeRegModRMByte(); 3406 } 3407 3408 if (CurOp != NumOps) { 3409 const MachineOperand &MO1 = MI.getOperand(CurOp++); 3410 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 3411 if (MO1.isImm()) 3412 FinalSize += sizeConstant(Size); 3413 else { 3414 bool dword = false; 3415 if (Opcode == X86::MOV64ri32) 3416 dword = true; 3417 if (MO1.isGlobal()) { 3418 FinalSize += sizeGlobalAddress(dword); 3419 } else if (MO1.isSymbol()) 3420 FinalSize += sizeExternalSymbolAddress(dword); 3421 else if (MO1.isCPI()) 3422 FinalSize += sizeConstPoolAddress(dword); 3423 else if (MO1.isJTI()) 3424 FinalSize += sizeJumpTableAddress(dword); 3425 } 3426 } 3427 break; 3428 3429 case X86II::MRM0m: case X86II::MRM1m: 3430 case X86II::MRM2m: case X86II::MRM3m: 3431 case X86II::MRM4m: case X86II::MRM5m: 3432 case X86II::MRM6m: case X86II::MRM7m: { 3433 3434 ++FinalSize; 3435 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 3436 CurOp += X86::AddrNumOperands; 3437 3438 if (CurOp != NumOps) { 3439 const MachineOperand &MO = MI.getOperand(CurOp++); 3440 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 3441 if (MO.isImm()) 3442 FinalSize += sizeConstant(Size); 3443 else { 3444 bool dword = false; 3445 if (Opcode == X86::MOV64mi32) 3446 dword = true; 3447 if (MO.isGlobal()) { 3448 FinalSize += sizeGlobalAddress(dword); 3449 } else if (MO.isSymbol()) 3450 FinalSize += sizeExternalSymbolAddress(dword); 3451 else if (MO.isCPI()) 3452 FinalSize += sizeConstPoolAddress(dword); 3453 else if (MO.isJTI()) 3454 FinalSize += sizeJumpTableAddress(dword); 3455 } 3456 } 3457 break; 3458 3459 case X86II::MRM_C1: 3460 case X86II::MRM_C8: 3461 case X86II::MRM_C9: 3462 case X86II::MRM_E8: 3463 case X86II::MRM_F0: 3464 FinalSize += 2; 3465 break; 3466 } 3467 3468 case X86II::MRMInitReg: 3469 ++FinalSize; 3470 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 3471 FinalSize += sizeRegModRMByte(); 3472 ++CurOp; 3473 break; 3474 } 3475 3476 if (!Desc->isVariadic() && CurOp != NumOps) { 3477 std::string msg; 3478 raw_string_ostream Msg(msg); 3479 Msg << "Cannot determine size: " << MI; 3480 report_fatal_error(Msg.str()); 3481 } 3482 3483 3484 return FinalSize; 3485} 3486 3487 3488unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 3489 const TargetInstrDesc &Desc = MI->getDesc(); 3490 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_; 3491 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit(); 3492 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode); 3493 if (Desc.getOpcode() == X86::MOVPC32r) 3494 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode); 3495 return Size; 3496} 3497 3498/// getGlobalBaseReg - Return a virtual register initialized with the 3499/// the global base register value. Output instructions required to 3500/// initialize the register in the function entry block, if necessary. 3501/// 3502/// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 3503/// 3504unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 3505 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 3506 "X86-64 PIC uses RIP relative addressing"); 3507 3508 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 3509 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 3510 if (GlobalBaseReg != 0) 3511 return GlobalBaseReg; 3512 3513 // Create the register. The code to initialize it is inserted 3514 // later, by the CGBR pass (below). 3515 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3516 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3517 X86FI->setGlobalBaseReg(GlobalBaseReg); 3518 return GlobalBaseReg; 3519} 3520 3521// These are the replaceable SSE instructions. Some of these have Int variants 3522// that we don't include here. We don't want to replace instructions selected 3523// by intrinsics. 3524static const unsigned ReplaceableInstrs[][3] = { 3525 //PackedInt PackedSingle PackedDouble 3526 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 3527 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 3528 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 3529 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 3530 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 3531 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 3532 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 3533 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 3534 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 3535 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 3536 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 3537 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 3538 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI }, 3539 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 3540 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 3541}; 3542 3543// FIXME: Some shuffle and unpack instructions have equivalents in different 3544// domains, but they require a bit more work than just switching opcodes. 3545 3546static const unsigned *lookup(unsigned opcode, unsigned domain) { 3547 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 3548 if (ReplaceableInstrs[i][domain-1] == opcode) 3549 return ReplaceableInstrs[i]; 3550 return 0; 3551} 3552 3553std::pair<uint16_t, uint16_t> 3554X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const { 3555 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 3556 return std::make_pair(domain, 3557 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0); 3558} 3559 3560void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const { 3561 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 3562 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 3563 assert(dom && "Not an SSE instruction"); 3564 const unsigned *table = lookup(MI->getOpcode(), dom); 3565 assert(table && "Cannot change domain"); 3566 MI->setDesc(get(table[Domain-1])); 3567} 3568 3569/// getNoopForMachoTarget - Return the noop instruction to use for a noop. 3570void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 3571 NopInst.setOpcode(X86::NOOP); 3572} 3573 3574namespace { 3575 /// CGBR - Create Global Base Reg pass. This initializes the PIC 3576 /// global base register for x86-32. 3577 struct CGBR : public MachineFunctionPass { 3578 static char ID; 3579 CGBR() : MachineFunctionPass(&ID) {} 3580 3581 virtual bool runOnMachineFunction(MachineFunction &MF) { 3582 const X86TargetMachine *TM = 3583 static_cast<const X86TargetMachine *>(&MF.getTarget()); 3584 3585 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() && 3586 "X86-64 PIC uses RIP relative addressing"); 3587 3588 // Only emit a global base reg in PIC mode. 3589 if (TM->getRelocationModel() != Reloc::PIC_) 3590 return false; 3591 3592 // Insert the set of GlobalBaseReg into the first MBB of the function 3593 MachineBasicBlock &FirstMBB = MF.front(); 3594 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 3595 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 3596 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3597 const X86InstrInfo *TII = TM->getInstrInfo(); 3598 3599 unsigned PC; 3600 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 3601 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3602 else 3603 PC = TII->getGlobalBaseReg(&MF); 3604 3605 // Operand of MovePCtoStack is completely ignored by asm printer. It's 3606 // only used in JIT code emission as displacement to pc. 3607 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 3608 3609 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 3610 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 3611 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 3612 unsigned GlobalBaseReg = TII->getGlobalBaseReg(&MF); 3613 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 3614 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 3615 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 3616 X86II::MO_GOT_ABSOLUTE_ADDRESS); 3617 } 3618 3619 return true; 3620 } 3621 3622 virtual const char *getPassName() const { 3623 return "X86 PIC Global Base Reg Initialization"; 3624 } 3625 3626 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 3627 AU.setPreservesCFG(); 3628 MachineFunctionPass::getAnalysisUsage(AU); 3629 } 3630 }; 3631} 3632 3633char CGBR::ID = 0; 3634FunctionPass* 3635llvm::createGlobalBaseRegPass() { return new CGBR(); } 3636