X86InstrInfo.cpp revision e7f702fc2d496aff1e5c1153519931e203b1ca76 
1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/LLVMContext.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/CodeGen/MachineConstantPool.h"
24#include "llvm/CodeGen/MachineDominators.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineRegisterInfo.h"
28#include "llvm/CodeGen/LiveVariables.h"
29#include "llvm/MC/MCAsmInfo.h"
30#include "llvm/MC/MCInst.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetOptions.h"
36#include <limits>
37
38#define GET_INSTRINFO_CTOR
39#include "X86GenInstrInfo.inc"
40
41using namespace llvm;
42
43static cl::opt<bool>
44NoFusing("disable-spill-fusing",
45         cl::desc("Disable fusing of spill code into instructions"));
46static cl::opt<bool>
47PrintFailedFusing("print-failed-fuse-candidates",
48                  cl::desc("Print instructions that the allocator wants to"
49                           " fuse, but the X86 backend currently can't"),
50                  cl::Hidden);
51static cl::opt<bool>
52ReMatPICStubLoad("remat-pic-stub-load",
53                 cl::desc("Re-materialize load from stub in PIC mode"),
54                 cl::init(false), cl::Hidden);
55
56enum {
57  // Select which memory operand is being unfolded.
58  // (stored in bits 0 - 3)
59  TB_INDEX_0    = 0,
60  TB_INDEX_1    = 1,
61  TB_INDEX_2    = 2,
62  TB_INDEX_3    = 3,
63  TB_INDEX_MASK = 0xf,
64
65  // Do not insert the reverse map (MemOp -> RegOp) into the table.
66  // This may be needed because there is a many -> one mapping.
67  TB_NO_REVERSE   = 1 << 4,
68
69  // Do not insert the forward map (RegOp -> MemOp) into the table.
70  // This is needed for Native Client, which prohibits branch
71  // instructions from using a memory operand.
72  TB_NO_FORWARD   = 1 << 5,
73
74  TB_FOLDED_LOAD  = 1 << 6,
75  TB_FOLDED_STORE = 1 << 7,
76
77  // Minimum alignment required for load/store.
78  // Used for RegOp->MemOp conversion.
79  // (stored in bits 8 - 15)
80  TB_ALIGN_SHIFT = 8,
81  TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
82  TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
83  TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
84  TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
85};
86
87struct X86OpTblEntry {
88  uint16_t RegOp;
89  uint16_t MemOp;
90  uint16_t Flags;
91};
92
93X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
94  : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
95                     ? X86::ADJCALLSTACKDOWN64
96                     : X86::ADJCALLSTACKDOWN32),
97                    (tm.getSubtarget<X86Subtarget>().is64Bit()
98                     ? X86::ADJCALLSTACKUP64
99                     : X86::ADJCALLSTACKUP32)),
100    TM(tm), RI(tm, *this) {
101
102  static const X86OpTblEntry OpTbl2Addr[] = {
103    { X86::ADC32ri,     X86::ADC32mi,    0 },
104    { X86::ADC32ri8,    X86::ADC32mi8,   0 },
105    { X86::ADC32rr,     X86::ADC32mr,    0 },
106    { X86::ADC64ri32,   X86::ADC64mi32,  0 },
107    { X86::ADC64ri8,    X86::ADC64mi8,   0 },
108    { X86::ADC64rr,     X86::ADC64mr,    0 },
109    { X86::ADD16ri,     X86::ADD16mi,    0 },
110    { X86::ADD16ri8,    X86::ADD16mi8,   0 },
111    { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
112    { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
113    { X86::ADD16rr,     X86::ADD16mr,    0 },
114    { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
115    { X86::ADD32ri,     X86::ADD32mi,    0 },
116    { X86::ADD32ri8,    X86::ADD32mi8,   0 },
117    { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
118    { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
119    { X86::ADD32rr,     X86::ADD32mr,    0 },
120    { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
121    { X86::ADD64ri32,   X86::ADD64mi32,  0 },
122    { X86::ADD64ri8,    X86::ADD64mi8,   0 },
123    { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
124    { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
125    { X86::ADD64rr,     X86::ADD64mr,    0 },
126    { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
127    { X86::ADD8ri,      X86::ADD8mi,     0 },
128    { X86::ADD8rr,      X86::ADD8mr,     0 },
129    { X86::AND16ri,     X86::AND16mi,    0 },
130    { X86::AND16ri8,    X86::AND16mi8,   0 },
131    { X86::AND16rr,     X86::AND16mr,    0 },
132    { X86::AND32ri,     X86::AND32mi,    0 },
133    { X86::AND32ri8,    X86::AND32mi8,   0 },
134    { X86::AND32rr,     X86::AND32mr,    0 },
135    { X86::AND64ri32,   X86::AND64mi32,  0 },
136    { X86::AND64ri8,    X86::AND64mi8,   0 },
137    { X86::AND64rr,     X86::AND64mr,    0 },
138    { X86::AND8ri,      X86::AND8mi,     0 },
139    { X86::AND8rr,      X86::AND8mr,     0 },
140    { X86::DEC16r,      X86::DEC16m,     0 },
141    { X86::DEC32r,      X86::DEC32m,     0 },
142    { X86::DEC64_16r,   X86::DEC64_16m,  0 },
143    { X86::DEC64_32r,   X86::DEC64_32m,  0 },
144    { X86::DEC64r,      X86::DEC64m,     0 },
145    { X86::DEC8r,       X86::DEC8m,      0 },
146    { X86::INC16r,      X86::INC16m,     0 },
147    { X86::INC32r,      X86::INC32m,     0 },
148    { X86::INC64_16r,   X86::INC64_16m,  0 },
149    { X86::INC64_32r,   X86::INC64_32m,  0 },
150    { X86::INC64r,      X86::INC64m,     0 },
151    { X86::INC8r,       X86::INC8m,      0 },
152    { X86::NEG16r,      X86::NEG16m,     0 },
153    { X86::NEG32r,      X86::NEG32m,     0 },
154    { X86::NEG64r,      X86::NEG64m,     0 },
155    { X86::NEG8r,       X86::NEG8m,      0 },
156    { X86::NOT16r,      X86::NOT16m,     0 },
157    { X86::NOT32r,      X86::NOT32m,     0 },
158    { X86::NOT64r,      X86::NOT64m,     0 },
159    { X86::NOT8r,       X86::NOT8m,      0 },
160    { X86::OR16ri,      X86::OR16mi,     0 },
161    { X86::OR16ri8,     X86::OR16mi8,    0 },
162    { X86::OR16rr,      X86::OR16mr,     0 },
163    { X86::OR32ri,      X86::OR32mi,     0 },
164    { X86::OR32ri8,     X86::OR32mi8,    0 },
165    { X86::OR32rr,      X86::OR32mr,     0 },
166    { X86::OR64ri32,    X86::OR64mi32,   0 },
167    { X86::OR64ri8,     X86::OR64mi8,    0 },
168    { X86::OR64rr,      X86::OR64mr,     0 },
169    { X86::OR8ri,       X86::OR8mi,      0 },
170    { X86::OR8rr,       X86::OR8mr,      0 },
171    { X86::ROL16r1,     X86::ROL16m1,    0 },
172    { X86::ROL16rCL,    X86::ROL16mCL,   0 },
173    { X86::ROL16ri,     X86::ROL16mi,    0 },
174    { X86::ROL32r1,     X86::ROL32m1,    0 },
175    { X86::ROL32rCL,    X86::ROL32mCL,   0 },
176    { X86::ROL32ri,     X86::ROL32mi,    0 },
177    { X86::ROL64r1,     X86::ROL64m1,    0 },
178    { X86::ROL64rCL,    X86::ROL64mCL,   0 },
179    { X86::ROL64ri,     X86::ROL64mi,    0 },
180    { X86::ROL8r1,      X86::ROL8m1,     0 },
181    { X86::ROL8rCL,     X86::ROL8mCL,    0 },
182    { X86::ROL8ri,      X86::ROL8mi,     0 },
183    { X86::ROR16r1,     X86::ROR16m1,    0 },
184    { X86::ROR16rCL,    X86::ROR16mCL,   0 },
185    { X86::ROR16ri,     X86::ROR16mi,    0 },
186    { X86::ROR32r1,     X86::ROR32m1,    0 },
187    { X86::ROR32rCL,    X86::ROR32mCL,   0 },
188    { X86::ROR32ri,     X86::ROR32mi,    0 },
189    { X86::ROR64r1,     X86::ROR64m1,    0 },
190    { X86::ROR64rCL,    X86::ROR64mCL,   0 },
191    { X86::ROR64ri,     X86::ROR64mi,    0 },
192    { X86::ROR8r1,      X86::ROR8m1,     0 },
193    { X86::ROR8rCL,     X86::ROR8mCL,    0 },
194    { X86::ROR8ri,      X86::ROR8mi,     0 },
195    { X86::SAR16r1,     X86::SAR16m1,    0 },
196    { X86::SAR16rCL,    X86::SAR16mCL,   0 },
197    { X86::SAR16ri,     X86::SAR16mi,    0 },
198    { X86::SAR32r1,     X86::SAR32m1,    0 },
199    { X86::SAR32rCL,    X86::SAR32mCL,   0 },
200    { X86::SAR32ri,     X86::SAR32mi,    0 },
201    { X86::SAR64r1,     X86::SAR64m1,    0 },
202    { X86::SAR64rCL,    X86::SAR64mCL,   0 },
203    { X86::SAR64ri,     X86::SAR64mi,    0 },
204    { X86::SAR8r1,      X86::SAR8m1,     0 },
205    { X86::SAR8rCL,     X86::SAR8mCL,    0 },
206    { X86::SAR8ri,      X86::SAR8mi,     0 },
207    { X86::SBB32ri,     X86::SBB32mi,    0 },
208    { X86::SBB32ri8,    X86::SBB32mi8,   0 },
209    { X86::SBB32rr,     X86::SBB32mr,    0 },
210    { X86::SBB64ri32,   X86::SBB64mi32,  0 },
211    { X86::SBB64ri8,    X86::SBB64mi8,   0 },
212    { X86::SBB64rr,     X86::SBB64mr,    0 },
213    { X86::SHL16rCL,    X86::SHL16mCL,   0 },
214    { X86::SHL16ri,     X86::SHL16mi,    0 },
215    { X86::SHL32rCL,    X86::SHL32mCL,   0 },
216    { X86::SHL32ri,     X86::SHL32mi,    0 },
217    { X86::SHL64rCL,    X86::SHL64mCL,   0 },
218    { X86::SHL64ri,     X86::SHL64mi,    0 },
219    { X86::SHL8rCL,     X86::SHL8mCL,    0 },
220    { X86::SHL8ri,      X86::SHL8mi,     0 },
221    { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
222    { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
223    { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
224    { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
225    { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
226    { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
227    { X86::SHR16r1,     X86::SHR16m1,    0 },
228    { X86::SHR16rCL,    X86::SHR16mCL,   0 },
229    { X86::SHR16ri,     X86::SHR16mi,    0 },
230    { X86::SHR32r1,     X86::SHR32m1,    0 },
231    { X86::SHR32rCL,    X86::SHR32mCL,   0 },
232    { X86::SHR32ri,     X86::SHR32mi,    0 },
233    { X86::SHR64r1,     X86::SHR64m1,    0 },
234    { X86::SHR64rCL,    X86::SHR64mCL,   0 },
235    { X86::SHR64ri,     X86::SHR64mi,    0 },
236    { X86::SHR8r1,      X86::SHR8m1,     0 },
237    { X86::SHR8rCL,     X86::SHR8mCL,    0 },
238    { X86::SHR8ri,      X86::SHR8mi,     0 },
239    { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
240    { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
241    { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
242    { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
243    { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
244    { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
245    { X86::SUB16ri,     X86::SUB16mi,    0 },
246    { X86::SUB16ri8,    X86::SUB16mi8,   0 },
247    { X86::SUB16rr,     X86::SUB16mr,    0 },
248    { X86::SUB32ri,     X86::SUB32mi,    0 },
249    { X86::SUB32ri8,    X86::SUB32mi8,   0 },
250    { X86::SUB32rr,     X86::SUB32mr,    0 },
251    { X86::SUB64ri32,   X86::SUB64mi32,  0 },
252    { X86::SUB64ri8,    X86::SUB64mi8,   0 },
253    { X86::SUB64rr,     X86::SUB64mr,    0 },
254    { X86::SUB8ri,      X86::SUB8mi,     0 },
255    { X86::SUB8rr,      X86::SUB8mr,     0 },
256    { X86::XOR16ri,     X86::XOR16mi,    0 },
257    { X86::XOR16ri8,    X86::XOR16mi8,   0 },
258    { X86::XOR16rr,     X86::XOR16mr,    0 },
259    { X86::XOR32ri,     X86::XOR32mi,    0 },
260    { X86::XOR32ri8,    X86::XOR32mi8,   0 },
261    { X86::XOR32rr,     X86::XOR32mr,    0 },
262    { X86::XOR64ri32,   X86::XOR64mi32,  0 },
263    { X86::XOR64ri8,    X86::XOR64mi8,   0 },
264    { X86::XOR64rr,     X86::XOR64mr,    0 },
265    { X86::XOR8ri,      X86::XOR8mi,     0 },
266    { X86::XOR8rr,      X86::XOR8mr,     0 }
267  };
268
269  for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
270    unsigned RegOp = OpTbl2Addr[i].RegOp;
271    unsigned MemOp = OpTbl2Addr[i].MemOp;
272    unsigned Flags = OpTbl2Addr[i].Flags;
273    AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
274                  RegOp, MemOp,
275                  // Index 0, folded load and store, no alignment requirement.
276                  Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
277  }
278
279  static const X86OpTblEntry OpTbl0[] = {
280    { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
281    { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
282    { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
283    { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
284    { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
285    { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
286    { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
287    { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
288    { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
289    { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
290    { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
291    { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
292    { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
293    { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
294    { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
295    { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
296    { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
297    { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
298    { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
299    { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
300    { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE | TB_ALIGN_16 },
301    { X86::FsMOVAPDrr,  X86::MOVSDmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
302    { X86::FsMOVAPSrr,  X86::MOVSSmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
303    { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
304    { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
305    { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
306    { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
307    { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
308    { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
309    { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
310    { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
311    { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
312    { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
313    { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
314    { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
315    { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
316    { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
317    { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
318    { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
319    { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
320    { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
321    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
322    { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
323    { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324    { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
326    { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
327    { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
328    { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
329    { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
330    { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
331    { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
332    { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
333    { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
334    { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
335    { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
336    { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
337    { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
338    { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
339    { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
340    { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
341    { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
342    { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
343    { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
344    { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
345    { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
346    { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
347    { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
348    { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
349    { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
350    { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
351    { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
352    { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
353    { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
354    { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
355    { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
356    { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
357    // AVX 128-bit versions of foldable instructions
358    { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE | TB_ALIGN_16 },
359    { X86::FsVMOVAPDrr, X86::VMOVSDmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
360    { X86::FsVMOVAPSrr, X86::VMOVSSmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
361    { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
362    { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
363    { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
364    { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
365    { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
366    { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
367    { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
368    { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
369    { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
370    { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
371    // AVX 256-bit foldable instructions
372    { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
373    { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
374    { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
375    { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
376    { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
377    { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE }
378  };
379
380  for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
381    unsigned RegOp      = OpTbl0[i].RegOp;
382    unsigned MemOp      = OpTbl0[i].MemOp;
383    unsigned Flags      = OpTbl0[i].Flags;
384    AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
385                  RegOp, MemOp, TB_INDEX_0 | Flags);
386  }
387
388  static const X86OpTblEntry OpTbl1[] = {
389    { X86::CMP16rr,         X86::CMP16rm,             0 },
390    { X86::CMP32rr,         X86::CMP32rm,             0 },
391    { X86::CMP64rr,         X86::CMP64rm,             0 },
392    { X86::CMP8rr,          X86::CMP8rm,              0 },
393    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
394    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
395    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
396    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
397    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
398    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
399    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
400    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
401    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
402    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
403    { X86::FsMOVAPDrr,      X86::MOVSDrm,             TB_NO_REVERSE },
404    { X86::FsMOVAPSrr,      X86::MOVSSrm,             TB_NO_REVERSE },
405    { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
406    { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
407    { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
408    { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
409    { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
410    { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
411    { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
412    { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
413    { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
414    { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
415    { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
416    { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
417    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
418    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
419    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
420    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
421    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
422    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
423    { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
424    { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
425    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
426    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
427    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
428    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
429    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
430    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
431    { X86::MOV16rr,         X86::MOV16rm,             0 },
432    { X86::MOV32rr,         X86::MOV32rm,             0 },
433    { X86::MOV64rr,         X86::MOV64rm,             0 },
434    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
435    { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
436    { X86::MOV8rr,          X86::MOV8rm,              0 },
437    { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
438    { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
439    { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
440    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
441    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
442    { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
443    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
444    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
445    { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
446    { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
447    { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
448    { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
449    { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
450    { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
451    { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
452    { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
453    { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm,        0 },
454    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
455    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
456    { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
457    { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
458    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
459    { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
460    { X86::MOVZX64rr16,     X86::MOVZX64rm16,         0 },
461    { X86::MOVZX64rr32,     X86::MOVZX64rm32,         0 },
462    { X86::MOVZX64rr8,      X86::MOVZX64rm8,          0 },
463    { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
464    { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
465    { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
466    { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
467    { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
468    { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
469    { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
470    { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
471    { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
472    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
473    { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
474    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
475    { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
476    { X86::SQRTPDr_Int,     X86::SQRTPDm_Int,         TB_ALIGN_16 },
477    { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
478    { X86::SQRTPSr_Int,     X86::SQRTPSm_Int,         TB_ALIGN_16 },
479    { X86::SQRTSDr,         X86::SQRTSDm,             0 },
480    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
481    { X86::SQRTSSr,         X86::SQRTSSm,             0 },
482    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
483    { X86::TEST16rr,        X86::TEST16rm,            0 },
484    { X86::TEST32rr,        X86::TEST32rm,            0 },
485    { X86::TEST64rr,        X86::TEST64rm,            0 },
486    { X86::TEST8rr,         X86::TEST8rm,             0 },
487    // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
488    { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
489    { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
490    // AVX 128-bit versions of foldable instructions
491    { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
492    { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
493    { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
494    { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
495    { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
496    { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
497    { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
498    { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
499    { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
500    { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
501    { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
502    { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
503    { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
504    { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
505    { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
506    { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
507    { X86::FsVMOVAPDrr,     X86::VMOVSDrm,            TB_NO_REVERSE },
508    { X86::FsVMOVAPSrr,     X86::VMOVSSrm,            TB_NO_REVERSE },
509    { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
510    { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
511    { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
512    { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
513    { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
514    { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
515    { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
516    { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
517    { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
518    { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
519    { X86::VMOVUPDrr,       X86::VMOVUPDrm,           TB_ALIGN_16 },
520    { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
521    { X86::VMOVZDI2PDIrr,   X86::VMOVZDI2PDIrm,       0 },
522    { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
523    { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
524    { X86::VPABSBrr128,     X86::VPABSBrm128,         TB_ALIGN_16 },
525    { X86::VPABSDrr128,     X86::VPABSDrm128,         TB_ALIGN_16 },
526    { X86::VPABSWrr128,     X86::VPABSWrm128,         TB_ALIGN_16 },
527    { X86::VPERMILPDri,     X86::VPERMILPDmi,         TB_ALIGN_16 },
528    { X86::VPERMILPSri,     X86::VPERMILPSmi,         TB_ALIGN_16 },
529    { X86::VPSHUFDri,       X86::VPSHUFDmi,           TB_ALIGN_16 },
530    { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          TB_ALIGN_16 },
531    { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          TB_ALIGN_16 },
532    { X86::VRCPPSr,         X86::VRCPPSm,             TB_ALIGN_16 },
533    { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         TB_ALIGN_16 },
534    { X86::VRSQRTPSr,       X86::VRSQRTPSm,           TB_ALIGN_16 },
535    { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       TB_ALIGN_16 },
536    { X86::VSQRTPDr,        X86::VSQRTPDm,            TB_ALIGN_16 },
537    { X86::VSQRTPDr_Int,    X86::VSQRTPDm_Int,        TB_ALIGN_16 },
538    { X86::VSQRTPSr,        X86::VSQRTPSm,            TB_ALIGN_16 },
539    { X86::VSQRTPSr_Int,    X86::VSQRTPSm_Int,        TB_ALIGN_16 },
540    { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
541    { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
542    // AVX 256-bit foldable instructions
543    { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
544    { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
545    { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
546    { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
547    { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
548    { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        TB_ALIGN_32 },
549    { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        TB_ALIGN_32 },
550    // AVX2 foldable instructions
551    { X86::VPABSBrr256,     X86::VPABSBrm256,         TB_ALIGN_32 },
552    { X86::VPABSDrr256,     X86::VPABSDrm256,         TB_ALIGN_32 },
553    { X86::VPABSWrr256,     X86::VPABSWrm256,         TB_ALIGN_32 },
554    { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          TB_ALIGN_32 },
555    { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         TB_ALIGN_32 },
556    { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         TB_ALIGN_32 },
557    { X86::VRCPPSYr,        X86::VRCPPSYm,            TB_ALIGN_32 },
558    { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        TB_ALIGN_32 },
559    { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          TB_ALIGN_32 },
560    { X86::VRSQRTPSYr_Int,  X86::VRSQRTPSYm_Int,      TB_ALIGN_32 },
561    { X86::VSQRTPDYr,       X86::VSQRTPDYm,           TB_ALIGN_32 },
562    { X86::VSQRTPDYr_Int,   X86::VSQRTPDYm_Int,       TB_ALIGN_32 },
563    { X86::VSQRTPSYr,       X86::VSQRTPSYm,           TB_ALIGN_32 },
564    { X86::VSQRTPSYr_Int,   X86::VSQRTPSYm_Int,       TB_ALIGN_32 },
565  };
566
567  for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
568    unsigned RegOp = OpTbl1[i].RegOp;
569    unsigned MemOp = OpTbl1[i].MemOp;
570    unsigned Flags = OpTbl1[i].Flags;
571    AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
572                  RegOp, MemOp,
573                  // Index 1, folded load
574                  Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
575  }
576
577  static const X86OpTblEntry OpTbl2[] = {
578    { X86::ADC32rr,         X86::ADC32rm,       0 },
579    { X86::ADC64rr,         X86::ADC64rm,       0 },
580    { X86::ADD16rr,         X86::ADD16rm,       0 },
581    { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
582    { X86::ADD32rr,         X86::ADD32rm,       0 },
583    { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
584    { X86::ADD64rr,         X86::ADD64rm,       0 },
585    { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
586    { X86::ADD8rr,          X86::ADD8rm,        0 },
587    { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
588    { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
589    { X86::ADDSDrr,         X86::ADDSDrm,       0 },
590    { X86::ADDSSrr,         X86::ADDSSrm,       0 },
591    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
592    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
593    { X86::AND16rr,         X86::AND16rm,       0 },
594    { X86::AND32rr,         X86::AND32rm,       0 },
595    { X86::AND64rr,         X86::AND64rm,       0 },
596    { X86::AND8rr,          X86::AND8rm,        0 },
597    { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
598    { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
599    { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
600    { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
601    { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
602    { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
603    { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
604    { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
605    { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
606    { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
607    { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
608    { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
609    { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
610    { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
611    { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
612    { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
613    { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
614    { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
615    { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
616    { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
617    { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
618    { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
619    { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
620    { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
621    { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
622    { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
623    { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
624    { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
625    { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
626    { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
627    { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
628    { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
629    { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
630    { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
631    { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
632    { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
633    { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
634    { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
635    { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
636    { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
637    { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
638    { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
639    { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
640    { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
641    { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
642    { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
643    { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
644    { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
645    { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
646    { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
647    { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
648    { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
649    { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
650    { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
651    { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
652    { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
653    { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
654    { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
655    { X86::CMPSDrr,         X86::CMPSDrm,       0 },
656    { X86::CMPSSrr,         X86::CMPSSrm,       0 },
657    { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
658    { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
659    { X86::DIVSDrr,         X86::DIVSDrm,       0 },
660    { X86::DIVSSrr,         X86::DIVSSrm,       0 },
661    { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
662    { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
663    { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
664    { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
665    { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
666    { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
667    { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
668    { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
669    { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
670    { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
671    { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
672    { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
673    { X86::IMUL16rr,        X86::IMUL16rm,      0 },
674    { X86::IMUL32rr,        X86::IMUL32rm,      0 },
675    { X86::IMUL64rr,        X86::IMUL64rm,      0 },
676    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
677    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
678    { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
679    { X86::MAXPDrr_Int,     X86::MAXPDrm_Int,   TB_ALIGN_16 },
680    { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
681    { X86::MAXPSrr_Int,     X86::MAXPSrm_Int,   TB_ALIGN_16 },
682    { X86::MAXSDrr,         X86::MAXSDrm,       0 },
683    { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
684    { X86::MAXSSrr,         X86::MAXSSrm,       0 },
685    { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
686    { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
687    { X86::MINPDrr_Int,     X86::MINPDrm_Int,   TB_ALIGN_16 },
688    { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
689    { X86::MINPSrr_Int,     X86::MINPSrm_Int,   TB_ALIGN_16 },
690    { X86::MINSDrr,         X86::MINSDrm,       0 },
691    { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
692    { X86::MINSSrr,         X86::MINSSrm,       0 },
693    { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
694    { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
695    { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
696    { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
697    { X86::MULSDrr,         X86::MULSDrm,       0 },
698    { X86::MULSSrr,         X86::MULSSrm,       0 },
699    { X86::OR16rr,          X86::OR16rm,        0 },
700    { X86::OR32rr,          X86::OR32rm,        0 },
701    { X86::OR64rr,          X86::OR64rm,        0 },
702    { X86::OR8rr,           X86::OR8rm,         0 },
703    { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
704    { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
705    { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
706    { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
707    { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
708    { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
709    { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
710    { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
711    { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
712    { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
713    { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
714    { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
715    { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
716    { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
717    { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
718    { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
719    { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
720    { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
721    { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
722    { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
723    { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
724    { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
725    { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
726    { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
727    { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
728    { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
729    { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
730    { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
731    { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
732    { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
733    { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
734    { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
735    { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
736    { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
737    { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
738    { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
739    { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
740    { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
741    { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
742    { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
743    { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
744    { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
745    { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
746    { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
747    { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
748    { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
749    { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
750    { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
751    { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
752    { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
753    { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
754    { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
755    { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
756    { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
757    { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
758    { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
759    { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
760    { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
761    { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
762    { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
763    { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
764    { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
765    { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
766    { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
767    { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
768    { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
769    { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
770    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
771    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
772    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
773    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
774    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
775    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
776    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
777    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
778    { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
779    { X86::SBB32rr,         X86::SBB32rm,       0 },
780    { X86::SBB64rr,         X86::SBB64rm,       0 },
781    { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
782    { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
783    { X86::SUB16rr,         X86::SUB16rm,       0 },
784    { X86::SUB32rr,         X86::SUB32rm,       0 },
785    { X86::SUB64rr,         X86::SUB64rm,       0 },
786    { X86::SUB8rr,          X86::SUB8rm,        0 },
787    { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
788    { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
789    { X86::SUBSDrr,         X86::SUBSDrm,       0 },
790    { X86::SUBSSrr,         X86::SUBSSrm,       0 },
791    // FIXME: TEST*rr -> swapped operand of TEST*mr.
792    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
793    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
794    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
795    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
796    { X86::XOR16rr,         X86::XOR16rm,       0 },
797    { X86::XOR32rr,         X86::XOR32rm,       0 },
798    { X86::XOR64rr,         X86::XOR64rm,       0 },
799    { X86::XOR8rr,          X86::XOR8rm,        0 },
800    { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
801    { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
802    // AVX 128-bit versions of foldable instructions
803    { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
804    { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
805    { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
806    { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
807    { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
808    { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
809    { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
810    { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
811    { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
812    { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
813    { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
814    { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
815    { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQrm,       TB_ALIGN_16 },
816    { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       TB_ALIGN_16 },
817    { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
818    { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
819    { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
820    { X86::VADDPDrr,          X86::VADDPDrm,           TB_ALIGN_16 },
821    { X86::VADDPSrr,          X86::VADDPSrm,           TB_ALIGN_16 },
822    { X86::VADDSDrr,          X86::VADDSDrm,           0 },
823    { X86::VADDSSrr,          X86::VADDSSrm,           0 },
824    { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        TB_ALIGN_16 },
825    { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        TB_ALIGN_16 },
826    { X86::VANDNPDrr,         X86::VANDNPDrm,          TB_ALIGN_16 },
827    { X86::VANDNPSrr,         X86::VANDNPSrm,          TB_ALIGN_16 },
828    { X86::VANDPDrr,          X86::VANDPDrm,           TB_ALIGN_16 },
829    { X86::VANDPSrr,          X86::VANDPSrm,           TB_ALIGN_16 },
830    { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        TB_ALIGN_16 },
831    { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        TB_ALIGN_16 },
832    { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        TB_ALIGN_16 },
833    { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        TB_ALIGN_16 },
834    { X86::VCMPPDrri,         X86::VCMPPDrmi,          TB_ALIGN_16 },
835    { X86::VCMPPSrri,         X86::VCMPPSrmi,          TB_ALIGN_16 },
836    { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
837    { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
838    { X86::VDIVPDrr,          X86::VDIVPDrm,           TB_ALIGN_16 },
839    { X86::VDIVPSrr,          X86::VDIVPSrm,           TB_ALIGN_16 },
840    { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
841    { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
842    { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
843    { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
844    { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
845    { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
846    { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
847    { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
848    { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
849    { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
850    { X86::VHADDPDrr,         X86::VHADDPDrm,          TB_ALIGN_16 },
851    { X86::VHADDPSrr,         X86::VHADDPSrm,          TB_ALIGN_16 },
852    { X86::VHSUBPDrr,         X86::VHSUBPDrm,          TB_ALIGN_16 },
853    { X86::VHSUBPSrr,         X86::VHSUBPSrm,          TB_ALIGN_16 },
854    { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
855    { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
856    { X86::VMAXPDrr,          X86::VMAXPDrm,           TB_ALIGN_16 },
857    { X86::VMAXPDrr_Int,      X86::VMAXPDrm_Int,       TB_ALIGN_16 },
858    { X86::VMAXPSrr,          X86::VMAXPSrm,           TB_ALIGN_16 },
859    { X86::VMAXPSrr_Int,      X86::VMAXPSrm_Int,       TB_ALIGN_16 },
860    { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
861    { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
862    { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
863    { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
864    { X86::VMINPDrr,          X86::VMINPDrm,           TB_ALIGN_16 },
865    { X86::VMINPDrr_Int,      X86::VMINPDrm_Int,       TB_ALIGN_16 },
866    { X86::VMINPSrr,          X86::VMINPSrm,           TB_ALIGN_16 },
867    { X86::VMINPSrr_Int,      X86::VMINPSrm_Int,       TB_ALIGN_16 },
868    { X86::VMINSDrr,          X86::VMINSDrm,           0 },
869    { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
870    { X86::VMINSSrr,          X86::VMINSSrm,           0 },
871    { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
872    { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        TB_ALIGN_16 },
873    { X86::VMULPDrr,          X86::VMULPDrm,           TB_ALIGN_16 },
874    { X86::VMULPSrr,          X86::VMULPSrm,           TB_ALIGN_16 },
875    { X86::VMULSDrr,          X86::VMULSDrm,           0 },
876    { X86::VMULSSrr,          X86::VMULSSrm,           0 },
877    { X86::VORPDrr,           X86::VORPDrm,            TB_ALIGN_16 },
878    { X86::VORPSrr,           X86::VORPSrm,            TB_ALIGN_16 },
879    { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        TB_ALIGN_16 },
880    { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        TB_ALIGN_16 },
881    { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        TB_ALIGN_16 },
882    { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        TB_ALIGN_16 },
883    { X86::VPADDBrr,          X86::VPADDBrm,           TB_ALIGN_16 },
884    { X86::VPADDDrr,          X86::VPADDDrm,           TB_ALIGN_16 },
885    { X86::VPADDQrr,          X86::VPADDQrm,           TB_ALIGN_16 },
886    { X86::VPADDSBrr,         X86::VPADDSBrm,          TB_ALIGN_16 },
887    { X86::VPADDSWrr,         X86::VPADDSWrm,          TB_ALIGN_16 },
888    { X86::VPADDUSBrr,        X86::VPADDUSBrm,         TB_ALIGN_16 },
889    { X86::VPADDUSWrr,        X86::VPADDUSWrm,         TB_ALIGN_16 },
890    { X86::VPADDWrr,          X86::VPADDWrm,           TB_ALIGN_16 },
891    { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      TB_ALIGN_16 },
892    { X86::VPANDNrr,          X86::VPANDNrm,           TB_ALIGN_16 },
893    { X86::VPANDrr,           X86::VPANDrm,            TB_ALIGN_16 },
894    { X86::VPAVGBrr,          X86::VPAVGBrm,           TB_ALIGN_16 },
895    { X86::VPAVGWrr,          X86::VPAVGWrm,           TB_ALIGN_16 },
896    { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        TB_ALIGN_16 },
897    { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         TB_ALIGN_16 },
898    { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         TB_ALIGN_16 },
899    { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         TB_ALIGN_16 },
900    { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         TB_ALIGN_16 },
901    { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         TB_ALIGN_16 },
902    { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         TB_ALIGN_16 },
903    { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         TB_ALIGN_16 },
904    { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         TB_ALIGN_16 },
905    { X86::VPHADDDrr,         X86::VPHADDDrm,          TB_ALIGN_16 },
906    { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      TB_ALIGN_16 },
907    { X86::VPHADDWrr,         X86::VPHADDWrm,          TB_ALIGN_16 },
908    { X86::VPHSUBDrr,         X86::VPHSUBDrm,          TB_ALIGN_16 },
909    { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      TB_ALIGN_16 },
910    { X86::VPHSUBWrr,         X86::VPHSUBWrm,          TB_ALIGN_16 },
911    { X86::VPERMILPDrr,       X86::VPERMILPDrm,        TB_ALIGN_16 },
912    { X86::VPERMILPSrr,       X86::VPERMILPSrm,        TB_ALIGN_16 },
913    { X86::VPINSRWrri,        X86::VPINSRWrmi,         TB_ALIGN_16 },
914    { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    TB_ALIGN_16 },
915    { X86::VPMADDWDrr,        X86::VPMADDWDrm,         TB_ALIGN_16 },
916    { X86::VPMAXSWrr,         X86::VPMAXSWrm,          TB_ALIGN_16 },
917    { X86::VPMAXUBrr,         X86::VPMAXUBrm,          TB_ALIGN_16 },
918    { X86::VPMINSWrr,         X86::VPMINSWrm,          TB_ALIGN_16 },
919    { X86::VPMINUBrr,         X86::VPMINUBrm,          TB_ALIGN_16 },
920    { X86::VPMULDQrr,         X86::VPMULDQrm,          TB_ALIGN_16 },
921    { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     TB_ALIGN_16 },
922    { X86::VPMULHUWrr,        X86::VPMULHUWrm,         TB_ALIGN_16 },
923    { X86::VPMULHWrr,         X86::VPMULHWrm,          TB_ALIGN_16 },
924    { X86::VPMULLDrr,         X86::VPMULLDrm,          TB_ALIGN_16 },
925    { X86::VPMULLWrr,         X86::VPMULLWrm,          TB_ALIGN_16 },
926    { X86::VPMULUDQrr,        X86::VPMULUDQrm,         TB_ALIGN_16 },
927    { X86::VPORrr,            X86::VPORrm,             TB_ALIGN_16 },
928    { X86::VPSADBWrr,         X86::VPSADBWrm,          TB_ALIGN_16 },
929    { X86::VPSHUFBrr,         X86::VPSHUFBrm,          TB_ALIGN_16 },
930    { X86::VPSIGNBrr,         X86::VPSIGNBrm,          TB_ALIGN_16 },
931    { X86::VPSIGNWrr,         X86::VPSIGNWrm,          TB_ALIGN_16 },
932    { X86::VPSIGNDrr,         X86::VPSIGNDrm,          TB_ALIGN_16 },
933    { X86::VPSLLDrr,          X86::VPSLLDrm,           TB_ALIGN_16 },
934    { X86::VPSLLQrr,          X86::VPSLLQrm,           TB_ALIGN_16 },
935    { X86::VPSLLWrr,          X86::VPSLLWrm,           TB_ALIGN_16 },
936    { X86::VPSRADrr,          X86::VPSRADrm,           TB_ALIGN_16 },
937    { X86::VPSRAWrr,          X86::VPSRAWrm,           TB_ALIGN_16 },
938    { X86::VPSRLDrr,          X86::VPSRLDrm,           TB_ALIGN_16 },
939    { X86::VPSRLQrr,          X86::VPSRLQrm,           TB_ALIGN_16 },
940    { X86::VPSRLWrr,          X86::VPSRLWrm,           TB_ALIGN_16 },
941    { X86::VPSUBBrr,          X86::VPSUBBrm,           TB_ALIGN_16 },
942    { X86::VPSUBDrr,          X86::VPSUBDrm,           TB_ALIGN_16 },
943    { X86::VPSUBSBrr,         X86::VPSUBSBrm,          TB_ALIGN_16 },
944    { X86::VPSUBSWrr,         X86::VPSUBSWrm,          TB_ALIGN_16 },
945    { X86::VPSUBWrr,          X86::VPSUBWrm,           TB_ALIGN_16 },
946    { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       TB_ALIGN_16 },
947    { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       TB_ALIGN_16 },
948    { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      TB_ALIGN_16 },
949    { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       TB_ALIGN_16 },
950    { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       TB_ALIGN_16 },
951    { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       TB_ALIGN_16 },
952    { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      TB_ALIGN_16 },
953    { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       TB_ALIGN_16 },
954    { X86::VPXORrr,           X86::VPXORrm,            TB_ALIGN_16 },
955    { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         TB_ALIGN_16 },
956    { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         TB_ALIGN_16 },
957    { X86::VSUBPDrr,          X86::VSUBPDrm,           TB_ALIGN_16 },
958    { X86::VSUBPSrr,          X86::VSUBPSrm,           TB_ALIGN_16 },
959    { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
960    { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
961    { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        TB_ALIGN_16 },
962    { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        TB_ALIGN_16 },
963    { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        TB_ALIGN_16 },
964    { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        TB_ALIGN_16 },
965    { X86::VXORPDrr,          X86::VXORPDrm,           TB_ALIGN_16 },
966    { X86::VXORPSrr,          X86::VXORPSrm,           TB_ALIGN_16 },
967    // AVX 256-bit foldable instructions
968    { X86::VADDPDYrr,         X86::VADDPDYrm,          TB_ALIGN_32 },
969    { X86::VADDPSYrr,         X86::VADDPSYrm,          TB_ALIGN_32 },
970    { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       TB_ALIGN_32 },
971    { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       TB_ALIGN_32 },
972    { X86::VANDNPDYrr,        X86::VANDNPDYrm,         TB_ALIGN_32 },
973    { X86::VANDNPSYrr,        X86::VANDNPSYrm,         TB_ALIGN_32 },
974    { X86::VANDPDYrr,         X86::VANDPDYrm,          TB_ALIGN_32 },
975    { X86::VANDPSYrr,         X86::VANDPSYrm,          TB_ALIGN_32 },
976    { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       TB_ALIGN_32 },
977    { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       TB_ALIGN_32 },
978    { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       TB_ALIGN_32 },
979    { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       TB_ALIGN_32 },
980    { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         TB_ALIGN_32 },
981    { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         TB_ALIGN_32 },
982    { X86::VDIVPDYrr,         X86::VDIVPDYrm,          TB_ALIGN_32 },
983    { X86::VDIVPSYrr,         X86::VDIVPSYrm,          TB_ALIGN_32 },
984    { X86::VHADDPDYrr,        X86::VHADDPDYrm,         TB_ALIGN_32 },
985    { X86::VHADDPSYrr,        X86::VHADDPSYrm,         TB_ALIGN_32 },
986    { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         TB_ALIGN_32 },
987    { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         TB_ALIGN_32 },
988    { X86::VINSERTF128rr,     X86::VINSERTF128rm,      TB_ALIGN_32 },
989    { X86::VMAXPDYrr,         X86::VMAXPDYrm,          TB_ALIGN_32 },
990    { X86::VMAXPDYrr_Int,     X86::VMAXPDYrm_Int,      TB_ALIGN_32 },
991    { X86::VMAXPSYrr,         X86::VMAXPSYrm,          TB_ALIGN_32 },
992    { X86::VMAXPSYrr_Int,     X86::VMAXPSYrm_Int,      TB_ALIGN_32 },
993    { X86::VMINPDYrr,         X86::VMINPDYrm,          TB_ALIGN_32 },
994    { X86::VMINPDYrr_Int,     X86::VMINPDYrm_Int,      TB_ALIGN_32 },
995    { X86::VMINPSYrr,         X86::VMINPSYrm,          TB_ALIGN_32 },
996    { X86::VMINPSYrr_Int,     X86::VMINPSYrm_Int,      TB_ALIGN_32 },
997    { X86::VMULPDYrr,         X86::VMULPDYrm,          TB_ALIGN_32 },
998    { X86::VMULPSYrr,         X86::VMULPSYrm,          TB_ALIGN_32 },
999    { X86::VORPDYrr,          X86::VORPDYrm,           TB_ALIGN_32 },
1000    { X86::VORPSYrr,          X86::VORPSYrm,           TB_ALIGN_32 },
1001    { X86::VPERM2F128rr,      X86::VPERM2F128rm,       TB_ALIGN_32 },
1002    { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       TB_ALIGN_32 },
1003    { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       TB_ALIGN_32 },
1004    { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        TB_ALIGN_32 },
1005    { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        TB_ALIGN_32 },
1006    { X86::VSUBPDYrr,         X86::VSUBPDYrm,          TB_ALIGN_32 },
1007    { X86::VSUBPSYrr,         X86::VSUBPSYrm,          TB_ALIGN_32 },
1008    { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       TB_ALIGN_32 },
1009    { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       TB_ALIGN_32 },
1010    { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       TB_ALIGN_32 },
1011    { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       TB_ALIGN_32 },
1012    { X86::VXORPDYrr,         X86::VXORPDYrm,          TB_ALIGN_32 },
1013    { X86::VXORPSYrr,         X86::VXORPSYrm,          TB_ALIGN_32 },
1014    // AVX2 foldable instructions
1015    { X86::VINSERTI128rr,     X86::VINSERTI128rm,      TB_ALIGN_16 },
1016    { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       TB_ALIGN_32 },
1017    { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       TB_ALIGN_32 },
1018    { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       TB_ALIGN_32 },
1019    { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       TB_ALIGN_32 },
1020    { X86::VPADDBYrr,         X86::VPADDBYrm,          TB_ALIGN_32 },
1021    { X86::VPADDDYrr,         X86::VPADDDYrm,          TB_ALIGN_32 },
1022    { X86::VPADDQYrr,         X86::VPADDQYrm,          TB_ALIGN_32 },
1023    { X86::VPADDSBYrr,        X86::VPADDSBYrm,         TB_ALIGN_32 },
1024    { X86::VPADDSWYrr,        X86::VPADDSWYrm,         TB_ALIGN_32 },
1025    { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        TB_ALIGN_32 },
1026    { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        TB_ALIGN_32 },
1027    { X86::VPADDWYrr,         X86::VPADDWYrm,          TB_ALIGN_32 },
1028    { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      TB_ALIGN_32 },
1029    { X86::VPANDNYrr,         X86::VPANDNYrm,          TB_ALIGN_32 },
1030    { X86::VPANDYrr,          X86::VPANDYrm,           TB_ALIGN_32 },
1031    { X86::VPAVGBYrr,         X86::VPAVGBYrm,          TB_ALIGN_32 },
1032    { X86::VPAVGWYrr,         X86::VPAVGWYrm,          TB_ALIGN_32 },
1033    { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        TB_ALIGN_32 },
1034    { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       TB_ALIGN_32 },
1035    { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       TB_ALIGN_32 },
1036    { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        TB_ALIGN_32 },
1037    { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        TB_ALIGN_32 },
1038    { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        TB_ALIGN_32 },
1039    { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        TB_ALIGN_32 },
1040    { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        TB_ALIGN_32 },
1041    { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        TB_ALIGN_32 },
1042    { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        TB_ALIGN_32 },
1043    { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        TB_ALIGN_32 },
1044    { X86::VPERM2I128rr,      X86::VPERM2I128rm,       TB_ALIGN_32 },
1045    { X86::VPERMDYrr,         X86::VPERMDYrm,          TB_ALIGN_32 },
1046    { X86::VPERMPDYri,        X86::VPERMPDYmi,         TB_ALIGN_32 },
1047    { X86::VPERMPSYrr,        X86::VPERMPSYrm,         TB_ALIGN_32 },
1048    { X86::VPERMQYri,         X86::VPERMQYmi,          TB_ALIGN_32 },
1049    { X86::VPHADDDYrr,        X86::VPHADDDYrm,         TB_ALIGN_32 },
1050    { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      TB_ALIGN_32 },
1051    { X86::VPHADDWYrr,        X86::VPHADDWYrm,         TB_ALIGN_32 },
1052    { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         TB_ALIGN_32 },
1053    { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      TB_ALIGN_32 },
1054    { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         TB_ALIGN_32 },
1055    { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    TB_ALIGN_32 },
1056    { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        TB_ALIGN_32 },
1057    { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         TB_ALIGN_32 },
1058    { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         TB_ALIGN_32 },
1059    { X86::VPMINSWYrr,        X86::VPMINSWYrm,         TB_ALIGN_32 },
1060    { X86::VPMINUBYrr,        X86::VPMINUBYrm,         TB_ALIGN_32 },
1061    { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       TB_ALIGN_32 },
1062    { X86::VPMULDQYrr,        X86::VPMULDQYrm,         TB_ALIGN_32 },
1063    { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     TB_ALIGN_32 },
1064    { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        TB_ALIGN_32 },
1065    { X86::VPMULHWYrr,        X86::VPMULHWYrm,         TB_ALIGN_32 },
1066    { X86::VPMULLDYrr,        X86::VPMULLDYrm,         TB_ALIGN_32 },
1067    { X86::VPMULLWYrr,        X86::VPMULLWYrm,         TB_ALIGN_32 },
1068    { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        TB_ALIGN_32 },
1069    { X86::VPORYrr,           X86::VPORYrm,            TB_ALIGN_32 },
1070    { X86::VPSADBWYrr,        X86::VPSADBWYrm,         TB_ALIGN_32 },
1071    { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         TB_ALIGN_32 },
1072    { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         TB_ALIGN_32 },
1073    { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         TB_ALIGN_32 },
1074    { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         TB_ALIGN_32 },
1075    { X86::VPSLLDYrr,         X86::VPSLLDYrm,          TB_ALIGN_16 },
1076    { X86::VPSLLQYrr,         X86::VPSLLQYrm,          TB_ALIGN_16 },
1077    { X86::VPSLLWYrr,         X86::VPSLLWYrm,          TB_ALIGN_16 },
1078    { X86::VPSLLVDrr,         X86::VPSLLVDrm,          TB_ALIGN_16 },
1079    { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         TB_ALIGN_32 },
1080    { X86::VPSLLVQrr,         X86::VPSLLVQrm,          TB_ALIGN_16 },
1081    { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         TB_ALIGN_32 },
1082    { X86::VPSRADYrr,         X86::VPSRADYrm,          TB_ALIGN_16 },
1083    { X86::VPSRAWYrr,         X86::VPSRAWYrm,          TB_ALIGN_16 },
1084    { X86::VPSRAVDrr,         X86::VPSRAVDrm,          TB_ALIGN_16 },
1085    { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         TB_ALIGN_32 },
1086    { X86::VPSRLDYrr,         X86::VPSRLDYrm,          TB_ALIGN_16 },
1087    { X86::VPSRLQYrr,         X86::VPSRLQYrm,          TB_ALIGN_16 },
1088    { X86::VPSRLWYrr,         X86::VPSRLWYrm,          TB_ALIGN_16 },
1089    { X86::VPSRLVDrr,         X86::VPSRLVDrm,          TB_ALIGN_16 },
1090    { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         TB_ALIGN_32 },
1091    { X86::VPSRLVQrr,         X86::VPSRLVQrm,          TB_ALIGN_16 },
1092    { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         TB_ALIGN_32 },
1093    { X86::VPSUBBYrr,         X86::VPSUBBYrm,          TB_ALIGN_32 },
1094    { X86::VPSUBDYrr,         X86::VPSUBDYrm,          TB_ALIGN_32 },
1095    { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         TB_ALIGN_32 },
1096    { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         TB_ALIGN_32 },
1097    { X86::VPSUBWYrr,         X86::VPSUBWYrm,          TB_ALIGN_32 },
1098    { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      TB_ALIGN_32 },
1099    { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      TB_ALIGN_32 },
1100    { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     TB_ALIGN_16 },
1101    { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      TB_ALIGN_32 },
1102    { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      TB_ALIGN_32 },
1103    { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      TB_ALIGN_32 },
1104    { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     TB_ALIGN_32 },
1105    { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      TB_ALIGN_32 },
1106    { X86::VPXORYrr,          X86::VPXORYrm,           TB_ALIGN_32 },
1107    // FIXME: add AVX 256-bit foldable instructions
1108  };
1109
1110  for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1111    unsigned RegOp = OpTbl2[i].RegOp;
1112    unsigned MemOp = OpTbl2[i].MemOp;
1113    unsigned Flags = OpTbl2[i].Flags;
1114    AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1115                  RegOp, MemOp,
1116                  // Index 2, folded load
1117                  Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1118  }
1119
1120  static const X86OpTblEntry OpTbl3[] = {
1121    // FMA foldable instructions
1122    { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         0 },
1123    { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         0 },
1124    { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         0 },
1125    { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         0 },
1126    { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         0 },
1127    { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         0 },
1128    { X86::VFMADDSSr132r_Int,     X86::VFMADDSSr132m_Int,     0 },
1129    { X86::VFMADDSDr132r_Int,     X86::VFMADDSDr132m_Int,     0 },
1130
1131    { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_16 },
1132    { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_16 },
1133    { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_16 },
1134    { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_16 },
1135    { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_16 },
1136    { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_16 },
1137    { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_32 },
1138    { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_32 },
1139    { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_32 },
1140    { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_32 },
1141    { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_32 },
1142    { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_32 },
1143    { X86::VFMADDPSr132r_Int,     X86::VFMADDPSr132m_Int,     TB_ALIGN_16 },
1144    { X86::VFMADDPDr132r_Int,     X86::VFMADDPDr132m_Int,     TB_ALIGN_16 },
1145    { X86::VFMADDPSr132rY_Int,    X86::VFMADDPSr132mY_Int,    TB_ALIGN_32 },
1146    { X86::VFMADDPDr132rY_Int,    X86::VFMADDPDr132mY_Int,    TB_ALIGN_32 },
1147
1148    { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        0 },
1149    { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        0 },
1150    { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        0 },
1151    { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        0 },
1152    { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        0 },
1153    { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        0 },
1154    { X86::VFNMADDSSr132r_Int,    X86::VFNMADDSSr132m_Int,    0 },
1155    { X86::VFNMADDSDr132r_Int,    X86::VFNMADDSDr132m_Int,    0 },
1156
1157    { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_16 },
1158    { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_16 },
1159    { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_16 },
1160    { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_16 },
1161    { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_16 },
1162    { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_16 },
1163    { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_32 },
1164    { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_32 },
1165    { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_32 },
1166    { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_32 },
1167    { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_32 },
1168    { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_32 },
1169    { X86::VFNMADDPSr132r_Int,    X86::VFNMADDPSr132m_Int,    TB_ALIGN_16 },
1170    { X86::VFNMADDPDr132r_Int,    X86::VFNMADDPDr132m_Int,    TB_ALIGN_16 },
1171    { X86::VFNMADDPSr132rY_Int,   X86::VFNMADDPSr132mY_Int,   TB_ALIGN_32 },
1172    { X86::VFNMADDPDr132rY_Int,   X86::VFNMADDPDr132mY_Int,   TB_ALIGN_32 },
1173
1174    { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         0 },
1175    { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         0 },
1176    { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         0 },
1177    { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         0 },
1178    { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         0 },
1179    { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         0 },
1180    { X86::VFMSUBSSr132r_Int,     X86::VFMSUBSSr132m_Int,     0 },
1181    { X86::VFMSUBSDr132r_Int,     X86::VFMSUBSDr132m_Int,     0 },
1182
1183    { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_16 },
1184    { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_16 },
1185    { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_16 },
1186    { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_16 },
1187    { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_16 },
1188    { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_16 },
1189    { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_32 },
1190    { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_32 },
1191    { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_32 },
1192    { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_32 },
1193    { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_32 },
1194    { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_32 },
1195    { X86::VFMSUBPSr132r_Int,     X86::VFMSUBPSr132m_Int,     TB_ALIGN_16 },
1196    { X86::VFMSUBPDr132r_Int,     X86::VFMSUBPDr132m_Int,     TB_ALIGN_16 },
1197    { X86::VFMSUBPSr132rY_Int,    X86::VFMSUBPSr132mY_Int,    TB_ALIGN_32 },
1198    { X86::VFMSUBPDr132rY_Int,    X86::VFMSUBPDr132mY_Int,    TB_ALIGN_32 },
1199
1200    { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        0 },
1201    { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        0 },
1202    { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        0 },
1203    { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        0 },
1204    { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        0 },
1205    { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        0 },
1206    { X86::VFNMSUBSSr132r_Int,    X86::VFNMSUBSSr132m_Int,    0 },
1207    { X86::VFNMSUBSDr132r_Int,    X86::VFNMSUBSDr132m_Int,    0 },
1208
1209    { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_16 },
1210    { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_16 },
1211    { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_16 },
1212    { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_16 },
1213    { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_16 },
1214    { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_16 },
1215    { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_32 },
1216    { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_32 },
1217    { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_32 },
1218    { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_32 },
1219    { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_32 },
1220    { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_32 },
1221    { X86::VFNMSUBPSr132r_Int,    X86::VFNMSUBPSr132m_Int,    TB_ALIGN_16 },
1222    { X86::VFNMSUBPDr132r_Int,    X86::VFNMSUBPDr132m_Int,    TB_ALIGN_16 },
1223    { X86::VFNMSUBPSr132rY_Int,   X86::VFNMSUBPSr132mY_Int,   TB_ALIGN_32 },
1224    { X86::VFNMSUBPDr132rY_Int,   X86::VFNMSUBPDr132mY_Int,   TB_ALIGN_32 },
1225
1226    { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_16 },
1227    { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_16 },
1228    { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_16 },
1229    { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_16 },
1230    { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_16 },
1231    { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_16 },
1232    { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_32 },
1233    { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_32 },
1234    { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_32 },
1235    { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_32 },
1236    { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_32 },
1237    { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_32 },
1238    { X86::VFMADDSUBPSr132r_Int,  X86::VFMADDSUBPSr132m_Int,  TB_ALIGN_16 },
1239    { X86::VFMADDSUBPDr132r_Int,  X86::VFMADDSUBPDr132m_Int,  TB_ALIGN_16 },
1240    { X86::VFMADDSUBPSr132rY_Int, X86::VFMADDSUBPSr132mY_Int, TB_ALIGN_32 },
1241    { X86::VFMADDSUBPDr132rY_Int, X86::VFMADDSUBPDr132mY_Int, TB_ALIGN_32 },
1242
1243    { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_16 },
1244    { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_16 },
1245    { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_16 },
1246    { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_16 },
1247    { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_16 },
1248    { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_16 },
1249    { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_32 },
1250    { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_32 },
1251    { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_32 },
1252    { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_32 },
1253    { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_32 },
1254    { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_32 },
1255    { X86::VFMSUBADDPSr132r_Int,  X86::VFMSUBADDPSr132m_Int,  TB_ALIGN_16 },
1256    { X86::VFMSUBADDPDr132r_Int,  X86::VFMSUBADDPDr132m_Int,  TB_ALIGN_16 },
1257    { X86::VFMSUBADDPSr132rY_Int, X86::VFMSUBADDPSr132mY_Int, TB_ALIGN_32 },
1258    { X86::VFMSUBADDPDr132rY_Int, X86::VFMSUBADDPDr132mY_Int, TB_ALIGN_32 },
1259  };
1260
1261  for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1262    unsigned RegOp = OpTbl3[i].RegOp;
1263    unsigned MemOp = OpTbl3[i].MemOp;
1264    unsigned Flags = OpTbl3[i].Flags;
1265    AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1266                  RegOp, MemOp,
1267                  // Index 3, folded load
1268                  Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1269  }
1270
1271}
1272
1273void
1274X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1275                            MemOp2RegOpTableType &M2RTable,
1276                            unsigned RegOp, unsigned MemOp, unsigned Flags) {
1277    if ((Flags & TB_NO_FORWARD) == 0) {
1278      assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1279      R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1280    }
1281    if ((Flags & TB_NO_REVERSE) == 0) {
1282      assert(!M2RTable.count(MemOp) &&
1283           "Duplicated entries in unfolding maps?");
1284      M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1285    }
1286}
1287
1288bool
1289X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1290                                    unsigned &SrcReg, unsigned &DstReg,
1291                                    unsigned &SubIdx) const {
1292  switch (MI.getOpcode()) {
1293  default: break;
1294  case X86::MOVSX16rr8:
1295  case X86::MOVZX16rr8:
1296  case X86::MOVSX32rr8:
1297  case X86::MOVZX32rr8:
1298  case X86::MOVSX64rr8:
1299  case X86::MOVZX64rr8:
1300    if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1301      // It's not always legal to reference the low 8-bit of the larger
1302      // register in 32-bit mode.
1303      return false;
1304  case X86::MOVSX32rr16:
1305  case X86::MOVZX32rr16:
1306  case X86::MOVSX64rr16:
1307  case X86::MOVZX64rr16:
1308  case X86::MOVSX64rr32:
1309  case X86::MOVZX64rr32: {
1310    if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1311      // Be conservative.
1312      return false;
1313    SrcReg = MI.getOperand(1).getReg();
1314    DstReg = MI.getOperand(0).getReg();
1315    switch (MI.getOpcode()) {
1316    default:
1317      llvm_unreachable(0);
1318    case X86::MOVSX16rr8:
1319    case X86::MOVZX16rr8:
1320    case X86::MOVSX32rr8:
1321    case X86::MOVZX32rr8:
1322    case X86::MOVSX64rr8:
1323    case X86::MOVZX64rr8:
1324      SubIdx = X86::sub_8bit;
1325      break;
1326    case X86::MOVSX32rr16:
1327    case X86::MOVZX32rr16:
1328    case X86::MOVSX64rr16:
1329    case X86::MOVZX64rr16:
1330      SubIdx = X86::sub_16bit;
1331      break;
1332    case X86::MOVSX64rr32:
1333    case X86::MOVZX64rr32:
1334      SubIdx = X86::sub_32bit;
1335      break;
1336    }
1337    return true;
1338  }
1339  }
1340  return false;
1341}
1342
1343/// isFrameOperand - Return true and the FrameIndex if the specified
1344/// operand and follow operands form a reference to the stack frame.
1345bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1346                                  int &FrameIndex) const {
1347  if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1348      MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1349      MI->getOperand(Op+1).getImm() == 1 &&
1350      MI->getOperand(Op+2).getReg() == 0 &&
1351      MI->getOperand(Op+3).getImm() == 0) {
1352    FrameIndex = MI->getOperand(Op).getIndex();
1353    return true;
1354  }
1355  return false;
1356}
1357
1358static bool isFrameLoadOpcode(int Opcode) {
1359  switch (Opcode) {
1360  default:
1361    return false;
1362  case X86::MOV8rm:
1363  case X86::MOV16rm:
1364  case X86::MOV32rm:
1365  case X86::MOV64rm:
1366  case X86::LD_Fp64m:
1367  case X86::MOVSSrm:
1368  case X86::MOVSDrm:
1369  case X86::MOVAPSrm:
1370  case X86::MOVAPDrm:
1371  case X86::MOVDQArm:
1372  case X86::VMOVSSrm:
1373  case X86::VMOVSDrm:
1374  case X86::VMOVAPSrm:
1375  case X86::VMOVAPDrm:
1376  case X86::VMOVDQArm:
1377  case X86::VMOVAPSYrm:
1378  case X86::VMOVAPDYrm:
1379  case X86::VMOVDQAYrm:
1380  case X86::MMX_MOVD64rm:
1381  case X86::MMX_MOVQ64rm:
1382    return true;
1383  }
1384}
1385
1386static bool isFrameStoreOpcode(int Opcode) {
1387  switch (Opcode) {
1388  default: break;
1389  case X86::MOV8mr:
1390  case X86::MOV16mr:
1391  case X86::MOV32mr:
1392  case X86::MOV64mr:
1393  case X86::ST_FpP64m:
1394  case X86::MOVSSmr:
1395  case X86::MOVSDmr:
1396  case X86::MOVAPSmr:
1397  case X86::MOVAPDmr:
1398  case X86::MOVDQAmr:
1399  case X86::VMOVSSmr:
1400  case X86::VMOVSDmr:
1401  case X86::VMOVAPSmr:
1402  case X86::VMOVAPDmr:
1403  case X86::VMOVDQAmr:
1404  case X86::VMOVAPSYmr:
1405  case X86::VMOVAPDYmr:
1406  case X86::VMOVDQAYmr:
1407  case X86::MMX_MOVD64mr:
1408  case X86::MMX_MOVQ64mr:
1409  case X86::MMX_MOVNTQmr:
1410    return true;
1411  }
1412  return false;
1413}
1414
1415unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1416                                           int &FrameIndex) const {
1417  if (isFrameLoadOpcode(MI->getOpcode()))
1418    if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1419      return MI->getOperand(0).getReg();
1420  return 0;
1421}
1422
1423unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1424                                                 int &FrameIndex) const {
1425  if (isFrameLoadOpcode(MI->getOpcode())) {
1426    unsigned Reg;
1427    if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1428      return Reg;
1429    // Check for post-frame index elimination operations
1430    const MachineMemOperand *Dummy;
1431    return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1432  }
1433  return 0;
1434}
1435
1436unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1437                                          int &FrameIndex) const {
1438  if (isFrameStoreOpcode(MI->getOpcode()))
1439    if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1440        isFrameOperand(MI, 0, FrameIndex))
1441      return MI->getOperand(X86::AddrNumOperands).getReg();
1442  return 0;
1443}
1444
1445unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1446                                                int &FrameIndex) const {
1447  if (isFrameStoreOpcode(MI->getOpcode())) {
1448    unsigned Reg;
1449    if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1450      return Reg;
1451    // Check for post-frame index elimination operations
1452    const MachineMemOperand *Dummy;
1453    return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1454  }
1455  return 0;
1456}
1457
1458/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1459/// X86::MOVPC32r.
1460static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1461  bool isPICBase = false;
1462  for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1463         E = MRI.def_end(); I != E; ++I) {
1464    MachineInstr *DefMI = I.getOperand().getParent();
1465    if (DefMI->getOpcode() != X86::MOVPC32r)
1466      return false;
1467    assert(!isPICBase && "More than one PIC base?");
1468    isPICBase = true;
1469  }
1470  return isPICBase;
1471}
1472
1473bool
1474X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1475                                                AliasAnalysis *AA) const {
1476  switch (MI->getOpcode()) {
1477  default: break;
1478    case X86::MOV8rm:
1479    case X86::MOV16rm:
1480    case X86::MOV32rm:
1481    case X86::MOV64rm:
1482    case X86::LD_Fp64m:
1483    case X86::MOVSSrm:
1484    case X86::MOVSDrm:
1485    case X86::MOVAPSrm:
1486    case X86::MOVUPSrm:
1487    case X86::MOVAPDrm:
1488    case X86::MOVDQArm:
1489    case X86::VMOVSSrm:
1490    case X86::VMOVSDrm:
1491    case X86::VMOVAPSrm:
1492    case X86::VMOVUPSrm:
1493    case X86::VMOVAPDrm:
1494    case X86::VMOVDQArm:
1495    case X86::VMOVAPSYrm:
1496    case X86::VMOVUPSYrm:
1497    case X86::VMOVAPDYrm:
1498    case X86::VMOVDQAYrm:
1499    case X86::MMX_MOVD64rm:
1500    case X86::MMX_MOVQ64rm:
1501    case X86::FsVMOVAPSrm:
1502    case X86::FsVMOVAPDrm:
1503    case X86::FsMOVAPSrm:
1504    case X86::FsMOVAPDrm: {
1505      // Loads from constant pools are trivially rematerializable.
1506      if (MI->getOperand(1).isReg() &&
1507          MI->getOperand(2).isImm() &&
1508          MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1509          MI->isInvariantLoad(AA)) {
1510        unsigned BaseReg = MI->getOperand(1).getReg();
1511        if (BaseReg == 0 || BaseReg == X86::RIP)
1512          return true;
1513        // Allow re-materialization of PIC load.
1514        if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1515          return false;
1516        const MachineFunction &MF = *MI->getParent()->getParent();
1517        const MachineRegisterInfo &MRI = MF.getRegInfo();
1518        bool isPICBase = false;
1519        for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1520               E = MRI.def_end(); I != E; ++I) {
1521          MachineInstr *DefMI = I.getOperand().getParent();
1522          if (DefMI->getOpcode() != X86::MOVPC32r)
1523            return false;
1524          assert(!isPICBase && "More than one PIC base?");
1525          isPICBase = true;
1526        }
1527        return isPICBase;
1528      }
1529      return false;
1530    }
1531
1532     case X86::LEA32r:
1533     case X86::LEA64r: {
1534       if (MI->getOperand(2).isImm() &&
1535           MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1536           !MI->getOperand(4).isReg()) {
1537         // lea fi#, lea GV, etc. are all rematerializable.
1538         if (!MI->getOperand(1).isReg())
1539           return true;
1540         unsigned BaseReg = MI->getOperand(1).getReg();
1541         if (BaseReg == 0)
1542           return true;
1543         // Allow re-materialization of lea PICBase + x.
1544         const MachineFunction &MF = *MI->getParent()->getParent();
1545         const MachineRegisterInfo &MRI = MF.getRegInfo();
1546         return regIsPICBase(BaseReg, MRI);
1547       }
1548       return false;
1549     }
1550  }
1551
1552  // All other instructions marked M_REMATERIALIZABLE are always trivially
1553  // rematerializable.
1554  return true;
1555}
1556
1557/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1558/// would clobber the EFLAGS condition register. Note the result may be
1559/// conservative. If it cannot definitely determine the safety after visiting
1560/// a few instructions in each direction it assumes it's not safe.
1561static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1562                                  MachineBasicBlock::iterator I) {
1563  MachineBasicBlock::iterator E = MBB.end();
1564
1565  // For compile time consideration, if we are not able to determine the
1566  // safety after visiting 4 instructions in each direction, we will assume
1567  // it's not safe.
1568  MachineBasicBlock::iterator Iter = I;
1569  for (unsigned i = 0; Iter != E && i < 4; ++i) {
1570    bool SeenDef = false;
1571    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1572      MachineOperand &MO = Iter->getOperand(j);
1573      if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1574        SeenDef = true;
1575      if (!MO.isReg())
1576        continue;
1577      if (MO.getReg() == X86::EFLAGS) {
1578        if (MO.isUse())
1579          return false;
1580        SeenDef = true;
1581      }
1582    }
1583
1584    if (SeenDef)
1585      // This instruction defines EFLAGS, no need to look any further.
1586      return true;
1587    ++Iter;
1588    // Skip over DBG_VALUE.
1589    while (Iter != E && Iter->isDebugValue())
1590      ++Iter;
1591  }
1592
1593  // It is safe to clobber EFLAGS at the end of a block of no successor has it
1594  // live in.
1595  if (Iter == E) {
1596    for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1597           SE = MBB.succ_end(); SI != SE; ++SI)
1598      if ((*SI)->isLiveIn(X86::EFLAGS))
1599        return false;
1600    return true;
1601  }
1602
1603  MachineBasicBlock::iterator B = MBB.begin();
1604  Iter = I;
1605  for (unsigned i = 0; i < 4; ++i) {
1606    // If we make it to the beginning of the block, it's safe to clobber
1607    // EFLAGS iff EFLAGS is not live-in.
1608    if (Iter == B)
1609      return !MBB.isLiveIn(X86::EFLAGS);
1610
1611    --Iter;
1612    // Skip over DBG_VALUE.
1613    while (Iter != B && Iter->isDebugValue())
1614      --Iter;
1615
1616    bool SawKill = false;
1617    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1618      MachineOperand &MO = Iter->getOperand(j);
1619      // A register mask may clobber EFLAGS, but we should still look for a
1620      // live EFLAGS def.
1621      if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1622        SawKill = true;
1623      if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1624        if (MO.isDef()) return MO.isDead();
1625        if (MO.isKill()) SawKill = true;
1626      }
1627    }
1628
1629    if (SawKill)
1630      // This instruction kills EFLAGS and doesn't redefine it, so
1631      // there's no need to look further.
1632      return true;
1633  }
1634
1635  // Conservative answer.
1636  return false;
1637}
1638
1639void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1640                                 MachineBasicBlock::iterator I,
1641                                 unsigned DestReg, unsigned SubIdx,
1642                                 const MachineInstr *Orig,
1643                                 const TargetRegisterInfo &TRI) const {
1644  DebugLoc DL = Orig->getDebugLoc();
1645
1646  // MOV32r0 etc. are implemented with xor which clobbers condition code.
1647  // Re-materialize them as movri instructions to avoid side effects.
1648  bool Clone = true;
1649  unsigned Opc = Orig->getOpcode();
1650  switch (Opc) {
1651  default: break;
1652  case X86::MOV8r0:
1653  case X86::MOV16r0:
1654  case X86::MOV32r0:
1655  case X86::MOV64r0: {
1656    if (!isSafeToClobberEFLAGS(MBB, I)) {
1657      switch (Opc) {
1658      default: break;
1659      case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
1660      case X86::MOV16r0: Opc = X86::MOV16ri; break;
1661      case X86::MOV32r0: Opc = X86::MOV32ri; break;
1662      case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1663      }
1664      Clone = false;
1665    }
1666    break;
1667  }
1668  }
1669
1670  if (Clone) {
1671    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1672    MBB.insert(I, MI);
1673  } else {
1674    BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1675  }
1676
1677  MachineInstr *NewMI = prior(I);
1678  NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1679}
1680
1681/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1682/// is not marked dead.
1683static bool hasLiveCondCodeDef(MachineInstr *MI) {
1684  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1685    MachineOperand &MO = MI->getOperand(i);
1686    if (MO.isReg() && MO.isDef() &&
1687        MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1688      return true;
1689    }
1690  }
1691  return false;
1692}
1693
1694/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1695/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1696/// to a 32-bit superregister and then truncating back down to a 16-bit
1697/// subregister.
1698MachineInstr *
1699X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1700                                           MachineFunction::iterator &MFI,
1701                                           MachineBasicBlock::iterator &MBBI,
1702                                           LiveVariables *LV) const {
1703  MachineInstr *MI = MBBI;
1704  unsigned Dest = MI->getOperand(0).getReg();
1705  unsigned Src = MI->getOperand(1).getReg();
1706  bool isDead = MI->getOperand(0).isDead();
1707  bool isKill = MI->getOperand(1).isKill();
1708
1709  unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1710    ? X86::LEA64_32r : X86::LEA32r;
1711  MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1712  unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1713  unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1714
1715  // Build and insert into an implicit UNDEF value. This is OK because
1716  // well be shifting and then extracting the lower 16-bits.
1717  // This has the potential to cause partial register stall. e.g.
1718  //   movw    (%rbp,%rcx,2), %dx
1719  //   leal    -65(%rdx), %esi
1720  // But testing has shown this *does* help performance in 64-bit mode (at
1721  // least on modern x86 machines).
1722  BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1723  MachineInstr *InsMI =
1724    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1725    .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1726    .addReg(Src, getKillRegState(isKill));
1727
1728  MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1729                                    get(Opc), leaOutReg);
1730  switch (MIOpc) {
1731  default:
1732    llvm_unreachable(0);
1733  case X86::SHL16ri: {
1734    unsigned ShAmt = MI->getOperand(2).getImm();
1735    MIB.addReg(0).addImm(1 << ShAmt)
1736       .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1737    break;
1738  }
1739  case X86::INC16r:
1740  case X86::INC64_16r:
1741    addRegOffset(MIB, leaInReg, true, 1);
1742    break;
1743  case X86::DEC16r:
1744  case X86::DEC64_16r:
1745    addRegOffset(MIB, leaInReg, true, -1);
1746    break;
1747  case X86::ADD16ri:
1748  case X86::ADD16ri8:
1749  case X86::ADD16ri_DB:
1750  case X86::ADD16ri8_DB:
1751    addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1752    break;
1753  case X86::ADD16rr:
1754  case X86::ADD16rr_DB: {
1755    unsigned Src2 = MI->getOperand(2).getReg();
1756    bool isKill2 = MI->getOperand(2).isKill();
1757    unsigned leaInReg2 = 0;
1758    MachineInstr *InsMI2 = 0;
1759    if (Src == Src2) {
1760      // ADD16rr %reg1028<kill>, %reg1028
1761      // just a single insert_subreg.
1762      addRegReg(MIB, leaInReg, true, leaInReg, false);
1763    } else {
1764      leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1765      // Build and insert into an implicit UNDEF value. This is OK because
1766      // well be shifting and then extracting the lower 16-bits.
1767      BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1768      InsMI2 =
1769        BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1770        .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1771        .addReg(Src2, getKillRegState(isKill2));
1772      addRegReg(MIB, leaInReg, true, leaInReg2, true);
1773    }
1774    if (LV && isKill2 && InsMI2)
1775      LV->replaceKillInstruction(Src2, MI, InsMI2);
1776    break;
1777  }
1778  }
1779
1780  MachineInstr *NewMI = MIB;
1781  MachineInstr *ExtMI =
1782    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1783    .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1784    .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1785
1786  if (LV) {
1787    // Update live variables
1788    LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1789    LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1790    if (isKill)
1791      LV->replaceKillInstruction(Src, MI, InsMI);
1792    if (isDead)
1793      LV->replaceKillInstruction(Dest, MI, ExtMI);
1794  }
1795
1796  return ExtMI;
1797}
1798
1799/// convertToThreeAddress - This method must be implemented by targets that
1800/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1801/// may be able to convert a two-address instruction into a true
1802/// three-address instruction on demand.  This allows the X86 target (for
1803/// example) to convert ADD and SHL instructions into LEA instructions if they
1804/// would require register copies due to two-addressness.
1805///
1806/// This method returns a null pointer if the transformation cannot be
1807/// performed, otherwise it returns the new instruction.
1808///
1809MachineInstr *
1810X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1811                                    MachineBasicBlock::iterator &MBBI,
1812                                    LiveVariables *LV) const {
1813  MachineInstr *MI = MBBI;
1814  MachineFunction &MF = *MI->getParent()->getParent();
1815  // All instructions input are two-addr instructions.  Get the known operands.
1816  unsigned Dest = MI->getOperand(0).getReg();
1817  unsigned Src = MI->getOperand(1).getReg();
1818  bool isDead = MI->getOperand(0).isDead();
1819  bool isKill = MI->getOperand(1).isKill();
1820
1821  MachineInstr *NewMI = NULL;
1822  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
1823  // we have better subtarget support, enable the 16-bit LEA generation here.
1824  // 16-bit LEA is also slow on Core2.
1825  bool DisableLEA16 = true;
1826  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1827
1828  unsigned MIOpc = MI->getOpcode();
1829  switch (MIOpc) {
1830  case X86::SHUFPSrri: {
1831    assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1832    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1833
1834    unsigned B = MI->getOperand(1).getReg();
1835    unsigned C = MI->getOperand(2).getReg();
1836    if (B != C) return 0;
1837    unsigned A = MI->getOperand(0).getReg();
1838    unsigned M = MI->getOperand(3).getImm();
1839    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1840      .addReg(A, RegState::Define | getDeadRegState(isDead))
1841      .addReg(B, getKillRegState(isKill)).addImm(M);
1842    break;
1843  }
1844  case X86::SHUFPDrri: {
1845    assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
1846    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1847
1848    unsigned B = MI->getOperand(1).getReg();
1849    unsigned C = MI->getOperand(2).getReg();
1850    if (B != C) return 0;
1851    unsigned A = MI->getOperand(0).getReg();
1852    unsigned M = MI->getOperand(3).getImm();
1853
1854    // Convert to PSHUFD mask.
1855    M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
1856
1857    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1858      .addReg(A, RegState::Define | getDeadRegState(isDead))
1859      .addReg(B, getKillRegState(isKill)).addImm(M);
1860    break;
1861  }
1862  case X86::SHL64ri: {
1863    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1864    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1865    // the flags produced by a shift yet, so this is safe.
1866    unsigned ShAmt = MI->getOperand(2).getImm();
1867    if (ShAmt == 0 || ShAmt >= 4) return 0;
1868
1869    // LEA can't handle RSP.
1870    if (TargetRegisterInfo::isVirtualRegister(Src) &&
1871        !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1872      return 0;
1873
1874    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1875      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1876      .addReg(0).addImm(1 << ShAmt)
1877      .addReg(Src, getKillRegState(isKill))
1878      .addImm(0).addReg(0);
1879    break;
1880  }
1881  case X86::SHL32ri: {
1882    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1883    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1884    // the flags produced by a shift yet, so this is safe.
1885    unsigned ShAmt = MI->getOperand(2).getImm();
1886    if (ShAmt == 0 || ShAmt >= 4) return 0;
1887
1888    // LEA can't handle ESP.
1889    if (TargetRegisterInfo::isVirtualRegister(Src) &&
1890        !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1891      return 0;
1892
1893    unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1894    NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1895      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1896      .addReg(0).addImm(1 << ShAmt)
1897      .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1898    break;
1899  }
1900  case X86::SHL16ri: {
1901    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1902    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1903    // the flags produced by a shift yet, so this is safe.
1904    unsigned ShAmt = MI->getOperand(2).getImm();
1905    if (ShAmt == 0 || ShAmt >= 4) return 0;
1906
1907    if (DisableLEA16)
1908      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1909    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1910      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1911      .addReg(0).addImm(1 << ShAmt)
1912      .addReg(Src, getKillRegState(isKill))
1913      .addImm(0).addReg(0);
1914    break;
1915  }
1916  default: {
1917    // The following opcodes also sets the condition code register(s). Only
1918    // convert them to equivalent lea if the condition code register def's
1919    // are dead!
1920    if (hasLiveCondCodeDef(MI))
1921      return 0;
1922
1923    switch (MIOpc) {
1924    default: return 0;
1925    case X86::INC64r:
1926    case X86::INC32r:
1927    case X86::INC64_32r: {
1928      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1929      unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1930        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1931      const TargetRegisterClass *RC = MIOpc == X86::INC64r ?
1932        (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
1933        (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
1934
1935      // LEA can't handle RSP.
1936      if (TargetRegisterInfo::isVirtualRegister(Src) &&
1937          !MF.getRegInfo().constrainRegClass(Src, RC))
1938        return 0;
1939
1940      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1941                              .addReg(Dest, RegState::Define |
1942                                      getDeadRegState(isDead)),
1943                              Src, isKill, 1);
1944      break;
1945    }
1946    case X86::INC16r:
1947    case X86::INC64_16r:
1948      if (DisableLEA16)
1949        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1950      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1951      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1952                           .addReg(Dest, RegState::Define |
1953                                   getDeadRegState(isDead)),
1954                           Src, isKill, 1);
1955      break;
1956    case X86::DEC64r:
1957    case X86::DEC32r:
1958    case X86::DEC64_32r: {
1959      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1960      unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1961        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1962      const TargetRegisterClass *RC = MIOpc == X86::DEC64r ?
1963        (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
1964        (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
1965      // LEA can't handle RSP.
1966      if (TargetRegisterInfo::isVirtualRegister(Src) &&
1967          !MF.getRegInfo().constrainRegClass(Src, RC))
1968        return 0;
1969
1970      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1971                              .addReg(Dest, RegState::Define |
1972                                      getDeadRegState(isDead)),
1973                              Src, isKill, -1);
1974      break;
1975    }
1976    case X86::DEC16r:
1977    case X86::DEC64_16r:
1978      if (DisableLEA16)
1979        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1980      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1981      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1982                           .addReg(Dest, RegState::Define |
1983                                   getDeadRegState(isDead)),
1984                           Src, isKill, -1);
1985      break;
1986    case X86::ADD64rr:
1987    case X86::ADD64rr_DB:
1988    case X86::ADD32rr:
1989    case X86::ADD32rr_DB: {
1990      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1991      unsigned Opc;
1992      const TargetRegisterClass *RC;
1993      if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1994        Opc = X86::LEA64r;
1995        RC = &X86::GR64_NOSPRegClass;
1996      } else {
1997        Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1998        RC = &X86::GR32_NOSPRegClass;
1999      }
2000
2001
2002      unsigned Src2 = MI->getOperand(2).getReg();
2003      bool isKill2 = MI->getOperand(2).isKill();
2004
2005      // LEA can't handle RSP.
2006      if (TargetRegisterInfo::isVirtualRegister(Src2) &&
2007          !MF.getRegInfo().constrainRegClass(Src2, RC))
2008        return 0;
2009
2010      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
2011                        .addReg(Dest, RegState::Define |
2012                                getDeadRegState(isDead)),
2013                        Src, isKill, Src2, isKill2);
2014      if (LV && isKill2)
2015        LV->replaceKillInstruction(Src2, MI, NewMI);
2016      break;
2017    }
2018    case X86::ADD16rr:
2019    case X86::ADD16rr_DB: {
2020      if (DisableLEA16)
2021        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2022      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2023      unsigned Src2 = MI->getOperand(2).getReg();
2024      bool isKill2 = MI->getOperand(2).isKill();
2025      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2026                        .addReg(Dest, RegState::Define |
2027                                getDeadRegState(isDead)),
2028                        Src, isKill, Src2, isKill2);
2029      if (LV && isKill2)
2030        LV->replaceKillInstruction(Src2, MI, NewMI);
2031      break;
2032    }
2033    case X86::ADD64ri32:
2034    case X86::ADD64ri8:
2035    case X86::ADD64ri32_DB:
2036    case X86::ADD64ri8_DB:
2037      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2038      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2039                              .addReg(Dest, RegState::Define |
2040                                      getDeadRegState(isDead)),
2041                              Src, isKill, MI->getOperand(2).getImm());
2042      break;
2043    case X86::ADD32ri:
2044    case X86::ADD32ri8:
2045    case X86::ADD32ri_DB:
2046    case X86::ADD32ri8_DB: {
2047      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2048      unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2049      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
2050                              .addReg(Dest, RegState::Define |
2051                                      getDeadRegState(isDead)),
2052                                Src, isKill, MI->getOperand(2).getImm());
2053      break;
2054    }
2055    case X86::ADD16ri:
2056    case X86::ADD16ri8:
2057    case X86::ADD16ri_DB:
2058    case X86::ADD16ri8_DB:
2059      if (DisableLEA16)
2060        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2061      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2062      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2063                              .addReg(Dest, RegState::Define |
2064                                      getDeadRegState(isDead)),
2065                              Src, isKill, MI->getOperand(2).getImm());
2066      break;
2067    }
2068  }
2069  }
2070
2071  if (!NewMI) return 0;
2072
2073  if (LV) {  // Update live variables
2074    if (isKill)
2075      LV->replaceKillInstruction(Src, MI, NewMI);
2076    if (isDead)
2077      LV->replaceKillInstruction(Dest, MI, NewMI);
2078  }
2079
2080  MFI->insert(MBBI, NewMI);          // Insert the new inst
2081  return NewMI;
2082}
2083
2084/// commuteInstruction - We have a few instructions that must be hacked on to
2085/// commute them.
2086///
2087MachineInstr *
2088X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2089  switch (MI->getOpcode()) {
2090  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2091  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2092  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2093  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2094  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2095  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2096    unsigned Opc;
2097    unsigned Size;
2098    switch (MI->getOpcode()) {
2099    default: llvm_unreachable("Unreachable!");
2100    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2101    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2102    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2103    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2104    case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2105    case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2106    }
2107    unsigned Amt = MI->getOperand(3).getImm();
2108    if (NewMI) {
2109      MachineFunction &MF = *MI->getParent()->getParent();
2110      MI = MF.CloneMachineInstr(MI);
2111      NewMI = false;
2112    }
2113    MI->setDesc(get(Opc));
2114    MI->getOperand(3).setImm(Size-Amt);
2115    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
2116  }
2117  case X86::CMOVB16rr:
2118  case X86::CMOVB32rr:
2119  case X86::CMOVB64rr:
2120  case X86::CMOVAE16rr:
2121  case X86::CMOVAE32rr:
2122  case X86::CMOVAE64rr:
2123  case X86::CMOVE16rr:
2124  case X86::CMOVE32rr:
2125  case X86::CMOVE64rr:
2126  case X86::CMOVNE16rr:
2127  case X86::CMOVNE32rr:
2128  case X86::CMOVNE64rr:
2129  case X86::CMOVBE16rr:
2130  case X86::CMOVBE32rr:
2131  case X86::CMOVBE64rr:
2132  case X86::CMOVA16rr:
2133  case X86::CMOVA32rr:
2134  case X86::CMOVA64rr:
2135  case X86::CMOVL16rr:
2136  case X86::CMOVL32rr:
2137  case X86::CMOVL64rr:
2138  case X86::CMOVGE16rr:
2139  case X86::CMOVGE32rr:
2140  case X86::CMOVGE64rr:
2141  case X86::CMOVLE16rr:
2142  case X86::CMOVLE32rr:
2143  case X86::CMOVLE64rr:
2144  case X86::CMOVG16rr:
2145  case X86::CMOVG32rr:
2146  case X86::CMOVG64rr:
2147  case X86::CMOVS16rr:
2148  case X86::CMOVS32rr:
2149  case X86::CMOVS64rr:
2150  case X86::CMOVNS16rr:
2151  case X86::CMOVNS32rr:
2152  case X86::CMOVNS64rr:
2153  case X86::CMOVP16rr:
2154  case X86::CMOVP32rr:
2155  case X86::CMOVP64rr:
2156  case X86::CMOVNP16rr:
2157  case X86::CMOVNP32rr:
2158  case X86::CMOVNP64rr:
2159  case X86::CMOVO16rr:
2160  case X86::CMOVO32rr:
2161  case X86::CMOVO64rr:
2162  case X86::CMOVNO16rr:
2163  case X86::CMOVNO32rr:
2164  case X86::CMOVNO64rr: {
2165    unsigned Opc = 0;
2166    switch (MI->getOpcode()) {
2167    default: break;
2168    case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2169    case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2170    case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2171    case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2172    case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2173    case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2174    case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2175    case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2176    case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2177    case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2178    case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2179    case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2180    case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2181    case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2182    case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2183    case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2184    case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2185    case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2186    case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2187    case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2188    case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2189    case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2190    case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2191    case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2192    case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2193    case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2194    case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2195    case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2196    case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2197    case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2198    case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2199    case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2200    case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2201    case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2202    case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2203    case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2204    case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2205    case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2206    case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2207    case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2208    case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2209    case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2210    case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2211    case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2212    case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2213    case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2214    case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2215    case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2216    }
2217    if (NewMI) {
2218      MachineFunction &MF = *MI->getParent()->getParent();
2219      MI = MF.CloneMachineInstr(MI);
2220      NewMI = false;
2221    }
2222    MI->setDesc(get(Opc));
2223    // Fallthrough intended.
2224  }
2225  default:
2226    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
2227  }
2228}
2229
2230static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
2231  switch (BrOpc) {
2232  default: return X86::COND_INVALID;
2233  case X86::JE_4:  return X86::COND_E;
2234  case X86::JNE_4: return X86::COND_NE;
2235  case X86::JL_4:  return X86::COND_L;
2236  case X86::JLE_4: return X86::COND_LE;
2237  case X86::JG_4:  return X86::COND_G;
2238  case X86::JGE_4: return X86::COND_GE;
2239  case X86::JB_4:  return X86::COND_B;
2240  case X86::JBE_4: return X86::COND_BE;
2241  case X86::JA_4:  return X86::COND_A;
2242  case X86::JAE_4: return X86::COND_AE;
2243  case X86::JS_4:  return X86::COND_S;
2244  case X86::JNS_4: return X86::COND_NS;
2245  case X86::JP_4:  return X86::COND_P;
2246  case X86::JNP_4: return X86::COND_NP;
2247  case X86::JO_4:  return X86::COND_O;
2248  case X86::JNO_4: return X86::COND_NO;
2249  }
2250}
2251
2252unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2253  switch (CC) {
2254  default: llvm_unreachable("Illegal condition code!");
2255  case X86::COND_E:  return X86::JE_4;
2256  case X86::COND_NE: return X86::JNE_4;
2257  case X86::COND_L:  return X86::JL_4;
2258  case X86::COND_LE: return X86::JLE_4;
2259  case X86::COND_G:  return X86::JG_4;
2260  case X86::COND_GE: return X86::JGE_4;
2261  case X86::COND_B:  return X86::JB_4;
2262  case X86::COND_BE: return X86::JBE_4;
2263  case X86::COND_A:  return X86::JA_4;
2264  case X86::COND_AE: return X86::JAE_4;
2265  case X86::COND_S:  return X86::JS_4;
2266  case X86::COND_NS: return X86::JNS_4;
2267  case X86::COND_P:  return X86::JP_4;
2268  case X86::COND_NP: return X86::JNP_4;
2269  case X86::COND_O:  return X86::JO_4;
2270  case X86::COND_NO: return X86::JNO_4;
2271  }
2272}
2273
2274/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2275/// e.g. turning COND_E to COND_NE.
2276X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2277  switch (CC) {
2278  default: llvm_unreachable("Illegal condition code!");
2279  case X86::COND_E:  return X86::COND_NE;
2280  case X86::COND_NE: return X86::COND_E;
2281  case X86::COND_L:  return X86::COND_GE;
2282  case X86::COND_LE: return X86::COND_G;
2283  case X86::COND_G:  return X86::COND_LE;
2284  case X86::COND_GE: return X86::COND_L;
2285  case X86::COND_B:  return X86::COND_AE;
2286  case X86::COND_BE: return X86::COND_A;
2287  case X86::COND_A:  return X86::COND_BE;
2288  case X86::COND_AE: return X86::COND_B;
2289  case X86::COND_S:  return X86::COND_NS;
2290  case X86::COND_NS: return X86::COND_S;
2291  case X86::COND_P:  return X86::COND_NP;
2292  case X86::COND_NP: return X86::COND_P;
2293  case X86::COND_O:  return X86::COND_NO;
2294  case X86::COND_NO: return X86::COND_O;
2295  }
2296}
2297
2298bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2299  if (!MI->isTerminator()) return false;
2300
2301  // Conditional branch is a special case.
2302  if (MI->isBranch() && !MI->isBarrier())
2303    return true;
2304  if (!MI->isPredicable())
2305    return true;
2306  return !isPredicated(MI);
2307}
2308
2309bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2310                                 MachineBasicBlock *&TBB,
2311                                 MachineBasicBlock *&FBB,
2312                                 SmallVectorImpl<MachineOperand> &Cond,
2313                                 bool AllowModify) const {
2314  // Start from the bottom of the block and work up, examining the
2315  // terminator instructions.
2316  MachineBasicBlock::iterator I = MBB.end();
2317  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2318  while (I != MBB.begin()) {
2319    --I;
2320    if (I->isDebugValue())
2321      continue;
2322
2323    // Working from the bottom, when we see a non-terminator instruction, we're
2324    // done.
2325    if (!isUnpredicatedTerminator(I))
2326      break;
2327
2328    // A terminator that isn't a branch can't easily be handled by this
2329    // analysis.
2330    if (!I->isBranch())
2331      return true;
2332
2333    // Handle unconditional branches.
2334    if (I->getOpcode() == X86::JMP_4) {
2335      UnCondBrIter = I;
2336
2337      if (!AllowModify) {
2338        TBB = I->getOperand(0).getMBB();
2339        continue;
2340      }
2341
2342      // If the block has any instructions after a JMP, delete them.
2343      while (llvm::next(I) != MBB.end())
2344        llvm::next(I)->eraseFromParent();
2345
2346      Cond.clear();
2347      FBB = 0;
2348
2349      // Delete the JMP if it's equivalent to a fall-through.
2350      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2351        TBB = 0;
2352        I->eraseFromParent();
2353        I = MBB.end();
2354        UnCondBrIter = MBB.end();
2355        continue;
2356      }
2357
2358      // TBB is used to indicate the unconditional destination.
2359      TBB = I->getOperand(0).getMBB();
2360      continue;
2361    }
2362
2363    // Handle conditional branches.
2364    X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
2365    if (BranchCode == X86::COND_INVALID)
2366      return true;  // Can't handle indirect branch.
2367
2368    // Working from the bottom, handle the first conditional branch.
2369    if (Cond.empty()) {
2370      MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2371      if (AllowModify && UnCondBrIter != MBB.end() &&
2372          MBB.isLayoutSuccessor(TargetBB)) {
2373        // If we can modify the code and it ends in something like:
2374        //
2375        //     jCC L1
2376        //     jmp L2
2377        //   L1:
2378        //     ...
2379        //   L2:
2380        //
2381        // Then we can change this to:
2382        //
2383        //     jnCC L2
2384        //   L1:
2385        //     ...
2386        //   L2:
2387        //
2388        // Which is a bit more efficient.
2389        // We conditionally jump to the fall-through block.
2390        BranchCode = GetOppositeBranchCondition(BranchCode);
2391        unsigned JNCC = GetCondBranchFromCond(BranchCode);
2392        MachineBasicBlock::iterator OldInst = I;
2393
2394        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2395          .addMBB(UnCondBrIter->getOperand(0).getMBB());
2396        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2397          .addMBB(TargetBB);
2398
2399        OldInst->eraseFromParent();
2400        UnCondBrIter->eraseFromParent();
2401
2402        // Restart the analysis.
2403        UnCondBrIter = MBB.end();
2404        I = MBB.end();
2405        continue;
2406      }
2407
2408      FBB = TBB;
2409      TBB = I->getOperand(0).getMBB();
2410      Cond.push_back(MachineOperand::CreateImm(BranchCode));
2411      continue;
2412    }
2413
2414    // Handle subsequent conditional branches. Only handle the case where all
2415    // conditional branches branch to the same destination and their condition
2416    // opcodes fit one of the special multi-branch idioms.
2417    assert(Cond.size() == 1);
2418    assert(TBB);
2419
2420    // Only handle the case where all conditional branches branch to the same
2421    // destination.
2422    if (TBB != I->getOperand(0).getMBB())
2423      return true;
2424
2425    // If the conditions are the same, we can leave them alone.
2426    X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2427    if (OldBranchCode == BranchCode)
2428      continue;
2429
2430    // If they differ, see if they fit one of the known patterns. Theoretically,
2431    // we could handle more patterns here, but we shouldn't expect to see them
2432    // if instruction selection has done a reasonable job.
2433    if ((OldBranchCode == X86::COND_NP &&
2434         BranchCode == X86::COND_E) ||
2435        (OldBranchCode == X86::COND_E &&
2436         BranchCode == X86::COND_NP))
2437      BranchCode = X86::COND_NP_OR_E;
2438    else if ((OldBranchCode == X86::COND_P &&
2439              BranchCode == X86::COND_NE) ||
2440             (OldBranchCode == X86::COND_NE &&
2441              BranchCode == X86::COND_P))
2442      BranchCode = X86::COND_NE_OR_P;
2443    else
2444      return true;
2445
2446    // Update the MachineOperand.
2447    Cond[0].setImm(BranchCode);
2448  }
2449
2450  return false;
2451}
2452
2453unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2454  MachineBasicBlock::iterator I = MBB.end();
2455  unsigned Count = 0;
2456
2457  while (I != MBB.begin()) {
2458    --I;
2459    if (I->isDebugValue())
2460      continue;
2461    if (I->getOpcode() != X86::JMP_4 &&
2462        GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2463      break;
2464    // Remove the branch.
2465    I->eraseFromParent();
2466    I = MBB.end();
2467    ++Count;
2468  }
2469
2470  return Count;
2471}
2472
2473unsigned
2474X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2475                           MachineBasicBlock *FBB,
2476                           const SmallVectorImpl<MachineOperand> &Cond,
2477                           DebugLoc DL) const {
2478  // Shouldn't be a fall through.
2479  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2480  assert((Cond.size() == 1 || Cond.size() == 0) &&
2481         "X86 branch conditions have one component!");
2482
2483  if (Cond.empty()) {
2484    // Unconditional branch?
2485    assert(!FBB && "Unconditional branch with multiple successors!");
2486    BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2487    return 1;
2488  }
2489
2490  // Conditional branch.
2491  unsigned Count = 0;
2492  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2493  switch (CC) {
2494  case X86::COND_NP_OR_E:
2495    // Synthesize NP_OR_E with two branches.
2496    BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2497    ++Count;
2498    BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2499    ++Count;
2500    break;
2501  case X86::COND_NE_OR_P:
2502    // Synthesize NE_OR_P with two branches.
2503    BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2504    ++Count;
2505    BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2506    ++Count;
2507    break;
2508  default: {
2509    unsigned Opc = GetCondBranchFromCond(CC);
2510    BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2511    ++Count;
2512  }
2513  }
2514  if (FBB) {
2515    // Two-way Conditional branch. Insert the second branch.
2516    BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2517    ++Count;
2518  }
2519  return Count;
2520}
2521
2522/// isHReg - Test if the given register is a physical h register.
2523static bool isHReg(unsigned Reg) {
2524  return X86::GR8_ABCD_HRegClass.contains(Reg);
2525}
2526
2527// Try and copy between VR128/VR64 and GR64 registers.
2528static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2529                                        bool HasAVX) {
2530  // SrcReg(VR128) -> DestReg(GR64)
2531  // SrcReg(VR64)  -> DestReg(GR64)
2532  // SrcReg(GR64)  -> DestReg(VR128)
2533  // SrcReg(GR64)  -> DestReg(VR64)
2534
2535  if (X86::GR64RegClass.contains(DestReg)) {
2536    if (X86::VR128RegClass.contains(SrcReg)) {
2537      // Copy from a VR128 register to a GR64 register.
2538      return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2539    } else if (X86::VR64RegClass.contains(SrcReg)) {
2540      // Copy from a VR64 register to a GR64 register.
2541      return X86::MOVSDto64rr;
2542    }
2543  } else if (X86::GR64RegClass.contains(SrcReg)) {
2544    // Copy from a GR64 register to a VR128 register.
2545    if (X86::VR128RegClass.contains(DestReg))
2546      return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2547    // Copy from a GR64 register to a VR64 register.
2548    else if (X86::VR64RegClass.contains(DestReg))
2549      return X86::MOV64toSDrr;
2550  }
2551
2552  // SrcReg(FR32) -> DestReg(GR32)
2553  // SrcReg(GR32) -> DestReg(FR32)
2554
2555  if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2556      // Copy from a FR32 register to a GR32 register.
2557      return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2558
2559  if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2560      // Copy from a GR32 register to a FR32 register.
2561      return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2562
2563  return 0;
2564}
2565
2566void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2567                               MachineBasicBlock::iterator MI, DebugLoc DL,
2568                               unsigned DestReg, unsigned SrcReg,
2569                               bool KillSrc) const {
2570  // First deal with the normal symmetric copies.
2571  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2572  unsigned Opc = 0;
2573  if (X86::GR64RegClass.contains(DestReg, SrcReg))
2574    Opc = X86::MOV64rr;
2575  else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2576    Opc = X86::MOV32rr;
2577  else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2578    Opc = X86::MOV16rr;
2579  else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2580    // Copying to or from a physical H register on x86-64 requires a NOREX
2581    // move.  Otherwise use a normal move.
2582    if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2583        TM.getSubtarget<X86Subtarget>().is64Bit()) {
2584      Opc = X86::MOV8rr_NOREX;
2585      // Both operands must be encodable without an REX prefix.
2586      assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2587             "8-bit H register can not be copied outside GR8_NOREX");
2588    } else
2589      Opc = X86::MOV8rr;
2590  } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2591    Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2592  else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2593    Opc = X86::VMOVAPSYrr;
2594  else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2595    Opc = X86::MMX_MOVQ64rr;
2596  else
2597    Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2598
2599  if (Opc) {
2600    BuildMI(MBB, MI, DL, get(Opc), DestReg)
2601      .addReg(SrcReg, getKillRegState(KillSrc));
2602    return;
2603  }
2604
2605  // Moving EFLAGS to / from another register requires a push and a pop.
2606  if (SrcReg == X86::EFLAGS) {
2607    if (X86::GR64RegClass.contains(DestReg)) {
2608      BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2609      BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2610      return;
2611    } else if (X86::GR32RegClass.contains(DestReg)) {
2612      BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2613      BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2614      return;
2615    }
2616  }
2617  if (DestReg == X86::EFLAGS) {
2618    if (X86::GR64RegClass.contains(SrcReg)) {
2619      BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2620        .addReg(SrcReg, getKillRegState(KillSrc));
2621      BuildMI(MBB, MI, DL, get(X86::POPF64));
2622      return;
2623    } else if (X86::GR32RegClass.contains(SrcReg)) {
2624      BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2625        .addReg(SrcReg, getKillRegState(KillSrc));
2626      BuildMI(MBB, MI, DL, get(X86::POPF32));
2627      return;
2628    }
2629  }
2630
2631  DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2632               << " to " << RI.getName(DestReg) << '\n');
2633  llvm_unreachable("Cannot emit physreg copy instruction");
2634}
2635
2636static unsigned getLoadStoreRegOpcode(unsigned Reg,
2637                                      const TargetRegisterClass *RC,
2638                                      bool isStackAligned,
2639                                      const TargetMachine &TM,
2640                                      bool load) {
2641  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2642  switch (RC->getSize()) {
2643  default:
2644    llvm_unreachable("Unknown spill size");
2645  case 1:
2646    assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2647    if (TM.getSubtarget<X86Subtarget>().is64Bit())
2648      // Copying to or from a physical H register on x86-64 requires a NOREX
2649      // move.  Otherwise use a normal move.
2650      if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2651        return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2652    return load ? X86::MOV8rm : X86::MOV8mr;
2653  case 2:
2654    assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2655    return load ? X86::MOV16rm : X86::MOV16mr;
2656  case 4:
2657    if (X86::GR32RegClass.hasSubClassEq(RC))
2658      return load ? X86::MOV32rm : X86::MOV32mr;
2659    if (X86::FR32RegClass.hasSubClassEq(RC))
2660      return load ?
2661        (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2662        (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2663    if (X86::RFP32RegClass.hasSubClassEq(RC))
2664      return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2665    llvm_unreachable("Unknown 4-byte regclass");
2666  case 8:
2667    if (X86::GR64RegClass.hasSubClassEq(RC))
2668      return load ? X86::MOV64rm : X86::MOV64mr;
2669    if (X86::FR64RegClass.hasSubClassEq(RC))
2670      return load ?
2671        (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2672        (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2673    if (X86::VR64RegClass.hasSubClassEq(RC))
2674      return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2675    if (X86::RFP64RegClass.hasSubClassEq(RC))
2676      return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2677    llvm_unreachable("Unknown 8-byte regclass");
2678  case 10:
2679    assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2680    return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2681  case 16: {
2682    assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2683    // If stack is realigned we can use aligned stores.
2684    if (isStackAligned)
2685      return load ?
2686        (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2687        (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2688    else
2689      return load ?
2690        (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2691        (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2692  }
2693  case 32:
2694    assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2695    // If stack is realigned we can use aligned stores.
2696    if (isStackAligned)
2697      return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2698    else
2699      return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2700  }
2701}
2702
2703static unsigned getStoreRegOpcode(unsigned SrcReg,
2704                                  const TargetRegisterClass *RC,
2705                                  bool isStackAligned,
2706                                  TargetMachine &TM) {
2707  return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2708}
2709
2710
2711static unsigned getLoadRegOpcode(unsigned DestReg,
2712                                 const TargetRegisterClass *RC,
2713                                 bool isStackAligned,
2714                                 const TargetMachine &TM) {
2715  return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2716}
2717
2718void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2719                                       MachineBasicBlock::iterator MI,
2720                                       unsigned SrcReg, bool isKill, int FrameIdx,
2721                                       const TargetRegisterClass *RC,
2722                                       const TargetRegisterInfo *TRI) const {
2723  const MachineFunction &MF = *MBB.getParent();
2724  assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2725         "Stack slot too small for store");
2726  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2727  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2728    RI.canRealignStack(MF);
2729  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2730  DebugLoc DL = MBB.findDebugLoc(MI);
2731  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2732    .addReg(SrcReg, getKillRegState(isKill));
2733}
2734
2735void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2736                                  bool isKill,
2737                                  SmallVectorImpl<MachineOperand> &Addr,
2738                                  const TargetRegisterClass *RC,
2739                                  MachineInstr::mmo_iterator MMOBegin,
2740                                  MachineInstr::mmo_iterator MMOEnd,
2741                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
2742  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2743  bool isAligned = MMOBegin != MMOEnd &&
2744                   (*MMOBegin)->getAlignment() >= Alignment;
2745  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2746  DebugLoc DL;
2747  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2748  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2749    MIB.addOperand(Addr[i]);
2750  MIB.addReg(SrcReg, getKillRegState(isKill));
2751  (*MIB).setMemRefs(MMOBegin, MMOEnd);
2752  NewMIs.push_back(MIB);
2753}
2754
2755
2756void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2757                                        MachineBasicBlock::iterator MI,
2758                                        unsigned DestReg, int FrameIdx,
2759                                        const TargetRegisterClass *RC,
2760                                        const TargetRegisterInfo *TRI) const {
2761  const MachineFunction &MF = *MBB.getParent();
2762  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2763  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2764    RI.canRealignStack(MF);
2765  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2766  DebugLoc DL = MBB.findDebugLoc(MI);
2767  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2768}
2769
2770void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2771                                 SmallVectorImpl<MachineOperand> &Addr,
2772                                 const TargetRegisterClass *RC,
2773                                 MachineInstr::mmo_iterator MMOBegin,
2774                                 MachineInstr::mmo_iterator MMOEnd,
2775                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2776  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2777  bool isAligned = MMOBegin != MMOEnd &&
2778                   (*MMOBegin)->getAlignment() >= Alignment;
2779  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2780  DebugLoc DL;
2781  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2782  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2783    MIB.addOperand(Addr[i]);
2784  (*MIB).setMemRefs(MMOBegin, MMOEnd);
2785  NewMIs.push_back(MIB);
2786}
2787
2788/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
2789/// instruction with two undef reads of the register being defined.  This is
2790/// used for mapping:
2791///   %xmm4 = V_SET0
2792/// to:
2793///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
2794///
2795static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
2796  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
2797  unsigned Reg = MI->getOperand(0).getReg();
2798  MI->setDesc(Desc);
2799
2800  // MachineInstr::addOperand() will insert explicit operands before any
2801  // implicit operands.
2802  MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
2803                         .addReg(Reg, RegState::Undef);
2804  // But we don't trust that.
2805  assert(MI->getOperand(1).getReg() == Reg &&
2806         MI->getOperand(2).getReg() == Reg && "Misplaced operand");
2807  return true;
2808}
2809
2810bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
2811  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2812  switch (MI->getOpcode()) {
2813  case X86::V_SET0:
2814  case X86::FsFLD0SS:
2815  case X86::FsFLD0SD:
2816    return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
2817  case X86::TEST8ri_NOREX:
2818    MI->setDesc(get(X86::TEST8ri));
2819    return true;
2820  }
2821  return false;
2822}
2823
2824MachineInstr*
2825X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2826                                       int FrameIx, uint64_t Offset,
2827                                       const MDNode *MDPtr,
2828                                       DebugLoc DL) const {
2829  X86AddressMode AM;
2830  AM.BaseType = X86AddressMode::FrameIndexBase;
2831  AM.Base.FrameIndex = FrameIx;
2832  MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2833  addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2834  return &*MIB;
2835}
2836
2837static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2838                                     const SmallVectorImpl<MachineOperand> &MOs,
2839                                     MachineInstr *MI,
2840                                     const TargetInstrInfo &TII) {
2841  // Create the base instruction with the memory operand as the first part.
2842  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2843                                              MI->getDebugLoc(), true);
2844  MachineInstrBuilder MIB(NewMI);
2845  unsigned NumAddrOps = MOs.size();
2846  for (unsigned i = 0; i != NumAddrOps; ++i)
2847    MIB.addOperand(MOs[i]);
2848  if (NumAddrOps < 4)  // FrameIndex only
2849    addOffset(MIB, 0);
2850
2851  // Loop over the rest of the ri operands, converting them over.
2852  unsigned NumOps = MI->getDesc().getNumOperands()-2;
2853  for (unsigned i = 0; i != NumOps; ++i) {
2854    MachineOperand &MO = MI->getOperand(i+2);
2855    MIB.addOperand(MO);
2856  }
2857  for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2858    MachineOperand &MO = MI->getOperand(i);
2859    MIB.addOperand(MO);
2860  }
2861  return MIB;
2862}
2863
2864static MachineInstr *FuseInst(MachineFunction &MF,
2865                              unsigned Opcode, unsigned OpNo,
2866                              const SmallVectorImpl<MachineOperand> &MOs,
2867                              MachineInstr *MI, const TargetInstrInfo &TII) {
2868  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2869                                              MI->getDebugLoc(), true);
2870  MachineInstrBuilder MIB(NewMI);
2871
2872  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2873    MachineOperand &MO = MI->getOperand(i);
2874    if (i == OpNo) {
2875      assert(MO.isReg() && "Expected to fold into reg operand!");
2876      unsigned NumAddrOps = MOs.size();
2877      for (unsigned i = 0; i != NumAddrOps; ++i)
2878        MIB.addOperand(MOs[i]);
2879      if (NumAddrOps < 4)  // FrameIndex only
2880        addOffset(MIB, 0);
2881    } else {
2882      MIB.addOperand(MO);
2883    }
2884  }
2885  return MIB;
2886}
2887
2888static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2889                                const SmallVectorImpl<MachineOperand> &MOs,
2890                                MachineInstr *MI) {
2891  MachineFunction &MF = *MI->getParent()->getParent();
2892  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2893
2894  unsigned NumAddrOps = MOs.size();
2895  for (unsigned i = 0; i != NumAddrOps; ++i)
2896    MIB.addOperand(MOs[i]);
2897  if (NumAddrOps < 4)  // FrameIndex only
2898    addOffset(MIB, 0);
2899  return MIB.addImm(0);
2900}
2901
2902MachineInstr*
2903X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2904                                    MachineInstr *MI, unsigned i,
2905                                    const SmallVectorImpl<MachineOperand> &MOs,
2906                                    unsigned Size, unsigned Align) const {
2907  const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2908  bool isTwoAddrFold = false;
2909  unsigned NumOps = MI->getDesc().getNumOperands();
2910  bool isTwoAddr = NumOps > 1 &&
2911    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2912
2913  // FIXME: AsmPrinter doesn't know how to handle
2914  // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2915  if (MI->getOpcode() == X86::ADD32ri &&
2916      MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2917    return NULL;
2918
2919  MachineInstr *NewMI = NULL;
2920  // Folding a memory location into the two-address part of a two-address
2921  // instruction is different than folding it other places.  It requires
2922  // replacing the *two* registers with the memory location.
2923  if (isTwoAddr && NumOps >= 2 && i < 2 &&
2924      MI->getOperand(0).isReg() &&
2925      MI->getOperand(1).isReg() &&
2926      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2927    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2928    isTwoAddrFold = true;
2929  } else if (i == 0) { // If operand 0
2930    if (MI->getOpcode() == X86::MOV64r0)
2931      NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2932    else if (MI->getOpcode() == X86::MOV32r0)
2933      NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2934    else if (MI->getOpcode() == X86::MOV16r0)
2935      NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2936    else if (MI->getOpcode() == X86::MOV8r0)
2937      NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2938    if (NewMI)
2939      return NewMI;
2940
2941    OpcodeTablePtr = &RegOp2MemOpTable0;
2942  } else if (i == 1) {
2943    OpcodeTablePtr = &RegOp2MemOpTable1;
2944  } else if (i == 2) {
2945    OpcodeTablePtr = &RegOp2MemOpTable2;
2946  }
2947
2948  // If table selected...
2949  if (OpcodeTablePtr) {
2950    // Find the Opcode to fuse
2951    DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2952      OpcodeTablePtr->find(MI->getOpcode());
2953    if (I != OpcodeTablePtr->end()) {
2954      unsigned Opcode = I->second.first;
2955      unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
2956      if (Align < MinAlign)
2957        return NULL;
2958      bool NarrowToMOV32rm = false;
2959      if (Size) {
2960        unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
2961        if (Size < RCSize) {
2962          // Check if it's safe to fold the load. If the size of the object is
2963          // narrower than the load width, then it's not.
2964          if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2965            return NULL;
2966          // If this is a 64-bit load, but the spill slot is 32, then we can do
2967          // a 32-bit load which is implicitly zero-extended. This likely is due
2968          // to liveintervalanalysis remat'ing a load from stack slot.
2969          if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2970            return NULL;
2971          Opcode = X86::MOV32rm;
2972          NarrowToMOV32rm = true;
2973        }
2974      }
2975
2976      if (isTwoAddrFold)
2977        NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2978      else
2979        NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2980
2981      if (NarrowToMOV32rm) {
2982        // If this is the special case where we use a MOV32rm to load a 32-bit
2983        // value and zero-extend the top bits. Change the destination register
2984        // to a 32-bit one.
2985        unsigned DstReg = NewMI->getOperand(0).getReg();
2986        if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2987          NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2988                                                   X86::sub_32bit));
2989        else
2990          NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2991      }
2992      return NewMI;
2993    }
2994  }
2995
2996  // No fusion
2997  if (PrintFailedFusing && !MI->isCopy())
2998    dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2999  return NULL;
3000}
3001
3002/// hasPartialRegUpdate - Return true for all instructions that only update
3003/// the first 32 or 64-bits of the destination register and leave the rest
3004/// unmodified. This can be used to avoid folding loads if the instructions
3005/// only update part of the destination register, and the non-updated part is
3006/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
3007/// instructions breaks the partial register dependency and it can improve
3008/// performance. e.g.:
3009///
3010///   movss (%rdi), %xmm0
3011///   cvtss2sd %xmm0, %xmm0
3012///
3013/// Instead of
3014///   cvtss2sd (%rdi), %xmm0
3015///
3016/// FIXME: This should be turned into a TSFlags.
3017///
3018static bool hasPartialRegUpdate(unsigned Opcode) {
3019  switch (Opcode) {
3020  case X86::CVTSI2SSrr:
3021  case X86::CVTSI2SS64rr:
3022  case X86::CVTSI2SDrr:
3023  case X86::CVTSI2SD64rr:
3024  case X86::CVTSD2SSrr:
3025  case X86::Int_CVTSD2SSrr:
3026  case X86::CVTSS2SDrr:
3027  case X86::Int_CVTSS2SDrr:
3028  case X86::RCPSSr:
3029  case X86::RCPSSr_Int:
3030  case X86::ROUNDSDr:
3031  case X86::ROUNDSDr_Int:
3032  case X86::ROUNDSSr:
3033  case X86::ROUNDSSr_Int:
3034  case X86::RSQRTSSr:
3035  case X86::RSQRTSSr_Int:
3036  case X86::SQRTSSr:
3037  case X86::SQRTSSr_Int:
3038  // AVX encoded versions
3039  case X86::VCVTSD2SSrr:
3040  case X86::Int_VCVTSD2SSrr:
3041  case X86::VCVTSS2SDrr:
3042  case X86::Int_VCVTSS2SDrr:
3043  case X86::VRCPSSr:
3044  case X86::VROUNDSDr:
3045  case X86::VROUNDSDr_Int:
3046  case X86::VROUNDSSr:
3047  case X86::VROUNDSSr_Int:
3048  case X86::VRSQRTSSr:
3049  case X86::VSQRTSSr:
3050    return true;
3051  }
3052
3053  return false;
3054}
3055
3056/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
3057/// instructions we would like before a partial register update.
3058unsigned X86InstrInfo::
3059getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
3060                             const TargetRegisterInfo *TRI) const {
3061  if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
3062    return 0;
3063
3064  // If MI is marked as reading Reg, the partial register update is wanted.
3065  const MachineOperand &MO = MI->getOperand(0);
3066  unsigned Reg = MO.getReg();
3067  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
3068    if (MO.readsReg() || MI->readsVirtualRegister(Reg))
3069      return 0;
3070  } else {
3071    if (MI->readsRegister(Reg, TRI))
3072      return 0;
3073  }
3074
3075  // If any of the preceding 16 instructions are reading Reg, insert a
3076  // dependency breaking instruction.  The magic number is based on a few
3077  // Nehalem experiments.
3078  return 16;
3079}
3080
3081void X86InstrInfo::
3082breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
3083                          const TargetRegisterInfo *TRI) const {
3084  unsigned Reg = MI->getOperand(OpNum).getReg();
3085  if (X86::VR128RegClass.contains(Reg)) {
3086    // These instructions are all floating point domain, so xorps is the best
3087    // choice.
3088    bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3089    unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
3090    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
3091      .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3092  } else if (X86::VR256RegClass.contains(Reg)) {
3093    // Use vxorps to clear the full ymm register.
3094    // It wants to read and write the xmm sub-register.
3095    unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
3096    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
3097      .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
3098      .addReg(Reg, RegState::ImplicitDefine);
3099  } else
3100    return;
3101  MI->addRegisterKilled(Reg, TRI, true);
3102}
3103
3104MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3105                                                  MachineInstr *MI,
3106                                           const SmallVectorImpl<unsigned> &Ops,
3107                                                  int FrameIndex) const {
3108  // Check switch flag
3109  if (NoFusing) return NULL;
3110
3111  // Unless optimizing for size, don't fold to avoid partial
3112  // register update stalls
3113  if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
3114      hasPartialRegUpdate(MI->getOpcode()))
3115    return 0;
3116
3117  const MachineFrameInfo *MFI = MF.getFrameInfo();
3118  unsigned Size = MFI->getObjectSize(FrameIndex);
3119  unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
3120  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3121    unsigned NewOpc = 0;
3122    unsigned RCSize = 0;
3123    switch (MI->getOpcode()) {
3124    default: return NULL;
3125    case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
3126    case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
3127    case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
3128    case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
3129    }
3130    // Check if it's safe to fold the load. If the size of the object is
3131    // narrower than the load width, then it's not.
3132    if (Size < RCSize)
3133      return NULL;
3134    // Change to CMPXXri r, 0 first.
3135    MI->setDesc(get(NewOpc));
3136    MI->getOperand(1).ChangeToImmediate(0);
3137  } else if (Ops.size() != 1)
3138    return NULL;
3139
3140  SmallVector<MachineOperand,4> MOs;
3141  MOs.push_back(MachineOperand::CreateFI(FrameIndex));
3142  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
3143}
3144
3145MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3146                                                  MachineInstr *MI,
3147                                           const SmallVectorImpl<unsigned> &Ops,
3148                                                  MachineInstr *LoadMI) const {
3149  // Check switch flag
3150  if (NoFusing) return NULL;
3151
3152  // Unless optimizing for size, don't fold to avoid partial
3153  // register update stalls
3154  if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
3155      hasPartialRegUpdate(MI->getOpcode()))
3156    return 0;
3157
3158  // Determine the alignment of the load.
3159  unsigned Alignment = 0;
3160  if (LoadMI->hasOneMemOperand())
3161    Alignment = (*LoadMI->memoperands_begin())->getAlignment();
3162  else
3163    switch (LoadMI->getOpcode()) {
3164    case X86::AVX_SET0PSY:
3165    case X86::AVX_SET0PDY:
3166    case X86::AVX2_SETALLONES:
3167    case X86::AVX2_SET0:
3168      Alignment = 32;
3169      break;
3170    case X86::V_SET0:
3171    case X86::V_SETALLONES:
3172    case X86::AVX_SETALLONES:
3173      Alignment = 16;
3174      break;
3175    case X86::FsFLD0SD:
3176      Alignment = 8;
3177      break;
3178    case X86::FsFLD0SS:
3179      Alignment = 4;
3180      break;
3181    default:
3182      return 0;
3183    }
3184  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3185    unsigned NewOpc = 0;
3186    switch (MI->getOpcode()) {
3187    default: return NULL;
3188    case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
3189    case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
3190    case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
3191    case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
3192    }
3193    // Change to CMPXXri r, 0 first.
3194    MI->setDesc(get(NewOpc));
3195    MI->getOperand(1).ChangeToImmediate(0);
3196  } else if (Ops.size() != 1)
3197    return NULL;
3198
3199  // Make sure the subregisters match.
3200  // Otherwise we risk changing the size of the load.
3201  if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
3202    return NULL;
3203
3204  SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
3205  switch (LoadMI->getOpcode()) {
3206  case X86::V_SET0:
3207  case X86::V_SETALLONES:
3208  case X86::AVX_SET0PSY:
3209  case X86::AVX_SET0PDY:
3210  case X86::AVX_SETALLONES:
3211  case X86::AVX2_SETALLONES:
3212  case X86::AVX2_SET0:
3213  case X86::FsFLD0SD:
3214  case X86::FsFLD0SS: {
3215    // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
3216    // Create a constant-pool entry and operands to load from it.
3217
3218    // Medium and large mode can't fold loads this way.
3219    if (TM.getCodeModel() != CodeModel::Small &&
3220        TM.getCodeModel() != CodeModel::Kernel)
3221      return NULL;
3222
3223    // x86-32 PIC requires a PIC base register for constant pools.
3224    unsigned PICBase = 0;
3225    if (TM.getRelocationModel() == Reloc::PIC_) {
3226      if (TM.getSubtarget<X86Subtarget>().is64Bit())
3227        PICBase = X86::RIP;
3228      else
3229        // FIXME: PICBase = getGlobalBaseReg(&MF);
3230        // This doesn't work for several reasons.
3231        // 1. GlobalBaseReg may have been spilled.
3232        // 2. It may not be live at MI.
3233        return NULL;
3234    }
3235
3236    // Create a constant-pool entry.
3237    MachineConstantPool &MCP = *MF.getConstantPool();
3238    Type *Ty;
3239    unsigned Opc = LoadMI->getOpcode();
3240    if (Opc == X86::FsFLD0SS)
3241      Ty = Type::getFloatTy(MF.getFunction()->getContext());
3242    else if (Opc == X86::FsFLD0SD)
3243      Ty = Type::getDoubleTy(MF.getFunction()->getContext());
3244    else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
3245      Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
3246    else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX2_SET0)
3247      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
3248    else
3249      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
3250
3251    bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES ||
3252                      Opc == X86::AVX2_SETALLONES);
3253    const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
3254                                    Constant::getNullValue(Ty);
3255    unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
3256
3257    // Create operands to load from the constant pool entry.
3258    MOs.push_back(MachineOperand::CreateReg(PICBase, false));
3259    MOs.push_back(MachineOperand::CreateImm(1));
3260    MOs.push_back(MachineOperand::CreateReg(0, false));
3261    MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
3262    MOs.push_back(MachineOperand::CreateReg(0, false));
3263    break;
3264  }
3265  default: {
3266    // Folding a normal load. Just copy the load's address operands.
3267    unsigned NumOps = LoadMI->getDesc().getNumOperands();
3268    for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
3269      MOs.push_back(LoadMI->getOperand(i));
3270    break;
3271  }
3272  }
3273  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
3274}
3275
3276
3277bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
3278                                  const SmallVectorImpl<unsigned> &Ops) const {
3279  // Check switch flag
3280  if (NoFusing) return 0;
3281
3282  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3283    switch (MI->getOpcode()) {
3284    default: return false;
3285    case X86::TEST8rr:
3286    case X86::TEST16rr:
3287    case X86::TEST32rr:
3288    case X86::TEST64rr:
3289      return true;
3290    case X86::ADD32ri:
3291      // FIXME: AsmPrinter doesn't know how to handle
3292      // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3293      if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3294        return false;
3295      break;
3296    }
3297  }
3298
3299  if (Ops.size() != 1)
3300    return false;
3301
3302  unsigned OpNum = Ops[0];
3303  unsigned Opc = MI->getOpcode();
3304  unsigned NumOps = MI->getDesc().getNumOperands();
3305  bool isTwoAddr = NumOps > 1 &&
3306    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3307
3308  // Folding a memory location into the two-address part of a two-address
3309  // instruction is different than folding it other places.  It requires
3310  // replacing the *two* registers with the memory location.
3311  const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3312  if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
3313    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3314  } else if (OpNum == 0) { // If operand 0
3315    switch (Opc) {
3316    case X86::MOV8r0:
3317    case X86::MOV16r0:
3318    case X86::MOV32r0:
3319    case X86::MOV64r0: return true;
3320    default: break;
3321    }
3322    OpcodeTablePtr = &RegOp2MemOpTable0;
3323  } else if (OpNum == 1) {
3324    OpcodeTablePtr = &RegOp2MemOpTable1;
3325  } else if (OpNum == 2) {
3326    OpcodeTablePtr = &RegOp2MemOpTable2;
3327  }
3328
3329  if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
3330    return true;
3331  return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
3332}
3333
3334bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
3335                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
3336                                SmallVectorImpl<MachineInstr*> &NewMIs) const {
3337  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3338    MemOp2RegOpTable.find(MI->getOpcode());
3339  if (I == MemOp2RegOpTable.end())
3340    return false;
3341  unsigned Opc = I->second.first;
3342  unsigned Index = I->second.second & TB_INDEX_MASK;
3343  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3344  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3345  if (UnfoldLoad && !FoldedLoad)
3346    return false;
3347  UnfoldLoad &= FoldedLoad;
3348  if (UnfoldStore && !FoldedStore)
3349    return false;
3350  UnfoldStore &= FoldedStore;
3351
3352  const MCInstrDesc &MCID = get(Opc);
3353  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
3354  if (!MI->hasOneMemOperand() &&
3355      RC == &X86::VR128RegClass &&
3356      !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3357    // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
3358    // conservatively assume the address is unaligned. That's bad for
3359    // performance.
3360    return false;
3361  SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
3362  SmallVector<MachineOperand,2> BeforeOps;
3363  SmallVector<MachineOperand,2> AfterOps;
3364  SmallVector<MachineOperand,4> ImpOps;
3365  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3366    MachineOperand &Op = MI->getOperand(i);
3367    if (i >= Index && i < Index + X86::AddrNumOperands)
3368      AddrOps.push_back(Op);
3369    else if (Op.isReg() && Op.isImplicit())
3370      ImpOps.push_back(Op);
3371    else if (i < Index)
3372      BeforeOps.push_back(Op);
3373    else if (i > Index)
3374      AfterOps.push_back(Op);
3375  }
3376
3377  // Emit the load instruction.
3378  if (UnfoldLoad) {
3379    std::pair<MachineInstr::mmo_iterator,
3380              MachineInstr::mmo_iterator> MMOs =
3381      MF.extractLoadMemRefs(MI->memoperands_begin(),
3382                            MI->memoperands_end());
3383    loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
3384    if (UnfoldStore) {
3385      // Address operands cannot be marked isKill.
3386      for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
3387        MachineOperand &MO = NewMIs[0]->getOperand(i);
3388        if (MO.isReg())
3389          MO.setIsKill(false);
3390      }
3391    }
3392  }
3393
3394  // Emit the data processing instruction.
3395  MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
3396  MachineInstrBuilder MIB(DataMI);
3397
3398  if (FoldedStore)
3399    MIB.addReg(Reg, RegState::Define);
3400  for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
3401    MIB.addOperand(BeforeOps[i]);
3402  if (FoldedLoad)
3403    MIB.addReg(Reg);
3404  for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
3405    MIB.addOperand(AfterOps[i]);
3406  for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
3407    MachineOperand &MO = ImpOps[i];
3408    MIB.addReg(MO.getReg(),
3409               getDefRegState(MO.isDef()) |
3410               RegState::Implicit |
3411               getKillRegState(MO.isKill()) |
3412               getDeadRegState(MO.isDead()) |
3413               getUndefRegState(MO.isUndef()));
3414  }
3415  // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
3416  unsigned NewOpc = 0;
3417  switch (DataMI->getOpcode()) {
3418  default: break;
3419  case X86::CMP64ri32:
3420  case X86::CMP64ri8:
3421  case X86::CMP32ri:
3422  case X86::CMP32ri8:
3423  case X86::CMP16ri:
3424  case X86::CMP16ri8:
3425  case X86::CMP8ri: {
3426    MachineOperand &MO0 = DataMI->getOperand(0);
3427    MachineOperand &MO1 = DataMI->getOperand(1);
3428    if (MO1.getImm() == 0) {
3429      switch (DataMI->getOpcode()) {
3430      default: break;
3431      case X86::CMP64ri8:
3432      case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
3433      case X86::CMP32ri8:
3434      case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
3435      case X86::CMP16ri8:
3436      case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
3437      case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
3438      }
3439      DataMI->setDesc(get(NewOpc));
3440      MO1.ChangeToRegister(MO0.getReg(), false);
3441    }
3442  }
3443  }
3444  NewMIs.push_back(DataMI);
3445
3446  // Emit the store instruction.
3447  if (UnfoldStore) {
3448    const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
3449    std::pair<MachineInstr::mmo_iterator,
3450              MachineInstr::mmo_iterator> MMOs =
3451      MF.extractStoreMemRefs(MI->memoperands_begin(),
3452                             MI->memoperands_end());
3453    storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
3454  }
3455
3456  return true;
3457}
3458
3459bool
3460X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
3461                                  SmallVectorImpl<SDNode*> &NewNodes) const {
3462  if (!N->isMachineOpcode())
3463    return false;
3464
3465  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3466    MemOp2RegOpTable.find(N->getMachineOpcode());
3467  if (I == MemOp2RegOpTable.end())
3468    return false;
3469  unsigned Opc = I->second.first;
3470  unsigned Index = I->second.second & TB_INDEX_MASK;
3471  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3472  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3473  const MCInstrDesc &MCID = get(Opc);
3474  MachineFunction &MF = DAG.getMachineFunction();
3475  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
3476  unsigned NumDefs = MCID.NumDefs;
3477  std::vector<SDValue> AddrOps;
3478  std::vector<SDValue> BeforeOps;
3479  std::vector<SDValue> AfterOps;
3480  DebugLoc dl = N->getDebugLoc();
3481  unsigned NumOps = N->getNumOperands();
3482  for (unsigned i = 0; i != NumOps-1; ++i) {
3483    SDValue Op = N->getOperand(i);
3484    if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
3485      AddrOps.push_back(Op);
3486    else if (i < Index-NumDefs)
3487      BeforeOps.push_back(Op);
3488    else if (i > Index-NumDefs)
3489      AfterOps.push_back(Op);
3490  }
3491  SDValue Chain = N->getOperand(NumOps-1);
3492  AddrOps.push_back(Chain);
3493
3494  // Emit the load instruction.
3495  SDNode *Load = 0;
3496  if (FoldedLoad) {
3497    EVT VT = *RC->vt_begin();
3498    std::pair<MachineInstr::mmo_iterator,
3499              MachineInstr::mmo_iterator> MMOs =
3500      MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3501                            cast<MachineSDNode>(N)->memoperands_end());
3502    if (!(*MMOs.first) &&
3503        RC == &X86::VR128RegClass &&
3504        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3505      // Do not introduce a slow unaligned load.
3506      return false;
3507    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3508    bool isAligned = (*MMOs.first) &&
3509                     (*MMOs.first)->getAlignment() >= Alignment;
3510    Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3511                              VT, MVT::Other, &AddrOps[0], AddrOps.size());
3512    NewNodes.push_back(Load);
3513
3514    // Preserve memory reference information.
3515    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3516  }
3517
3518  // Emit the data processing instruction.
3519  std::vector<EVT> VTs;
3520  const TargetRegisterClass *DstRC = 0;
3521  if (MCID.getNumDefs() > 0) {
3522    DstRC = getRegClass(MCID, 0, &RI, MF);
3523    VTs.push_back(*DstRC->vt_begin());
3524  }
3525  for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
3526    EVT VT = N->getValueType(i);
3527    if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
3528      VTs.push_back(VT);
3529  }
3530  if (Load)
3531    BeforeOps.push_back(SDValue(Load, 0));
3532  std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
3533  SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
3534                                      BeforeOps.size());
3535  NewNodes.push_back(NewNode);
3536
3537  // Emit the store instruction.
3538  if (FoldedStore) {
3539    AddrOps.pop_back();
3540    AddrOps.push_back(SDValue(NewNode, 0));
3541    AddrOps.push_back(Chain);
3542    std::pair<MachineInstr::mmo_iterator,
3543              MachineInstr::mmo_iterator> MMOs =
3544      MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3545                             cast<MachineSDNode>(N)->memoperands_end());
3546    if (!(*MMOs.first) &&
3547        RC == &X86::VR128RegClass &&
3548        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3549      // Do not introduce a slow unaligned store.
3550      return false;
3551    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3552    bool isAligned = (*MMOs.first) &&
3553                     (*MMOs.first)->getAlignment() >= Alignment;
3554    SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
3555                                                         isAligned, TM),
3556                                       dl, MVT::Other,
3557                                       &AddrOps[0], AddrOps.size());
3558    NewNodes.push_back(Store);
3559
3560    // Preserve memory reference information.
3561    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3562  }
3563
3564  return true;
3565}
3566
3567unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
3568                                      bool UnfoldLoad, bool UnfoldStore,
3569                                      unsigned *LoadRegIndex) const {
3570  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3571    MemOp2RegOpTable.find(Opc);
3572  if (I == MemOp2RegOpTable.end())
3573    return 0;
3574  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3575  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3576  if (UnfoldLoad && !FoldedLoad)
3577    return 0;
3578  if (UnfoldStore && !FoldedStore)
3579    return 0;
3580  if (LoadRegIndex)
3581    *LoadRegIndex = I->second.second & TB_INDEX_MASK;
3582  return I->second.first;
3583}
3584
3585bool
3586X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
3587                                     int64_t &Offset1, int64_t &Offset2) const {
3588  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
3589    return false;
3590  unsigned Opc1 = Load1->getMachineOpcode();
3591  unsigned Opc2 = Load2->getMachineOpcode();
3592  switch (Opc1) {
3593  default: return false;
3594  case X86::MOV8rm:
3595  case X86::MOV16rm:
3596  case X86::MOV32rm:
3597  case X86::MOV64rm:
3598  case X86::LD_Fp32m:
3599  case X86::LD_Fp64m:
3600  case X86::LD_Fp80m:
3601  case X86::MOVSSrm:
3602  case X86::MOVSDrm:
3603  case X86::MMX_MOVD64rm:
3604  case X86::MMX_MOVQ64rm:
3605  case X86::FsMOVAPSrm:
3606  case X86::FsMOVAPDrm:
3607  case X86::MOVAPSrm:
3608  case X86::MOVUPSrm:
3609  case X86::MOVAPDrm:
3610  case X86::MOVDQArm:
3611  case X86::MOVDQUrm:
3612  // AVX load instructions
3613  case X86::VMOVSSrm:
3614  case X86::VMOVSDrm:
3615  case X86::FsVMOVAPSrm:
3616  case X86::FsVMOVAPDrm:
3617  case X86::VMOVAPSrm:
3618  case X86::VMOVUPSrm:
3619  case X86::VMOVAPDrm:
3620  case X86::VMOVDQArm:
3621  case X86::VMOVDQUrm:
3622  case X86::VMOVAPSYrm:
3623  case X86::VMOVUPSYrm:
3624  case X86::VMOVAPDYrm:
3625  case X86::VMOVDQAYrm:
3626  case X86::VMOVDQUYrm:
3627    break;
3628  }
3629  switch (Opc2) {
3630  default: return false;
3631  case X86::MOV8rm:
3632  case X86::MOV16rm:
3633  case X86::MOV32rm:
3634  case X86::MOV64rm:
3635  case X86::LD_Fp32m:
3636  case X86::LD_Fp64m:
3637  case X86::LD_Fp80m:
3638  case X86::MOVSSrm:
3639  case X86::MOVSDrm:
3640  case X86::MMX_MOVD64rm:
3641  case X86::MMX_MOVQ64rm:
3642  case X86::FsMOVAPSrm:
3643  case X86::FsMOVAPDrm:
3644  case X86::MOVAPSrm:
3645  case X86::MOVUPSrm:
3646  case X86::MOVAPDrm:
3647  case X86::MOVDQArm:
3648  case X86::MOVDQUrm:
3649  // AVX load instructions
3650  case X86::VMOVSSrm:
3651  case X86::VMOVSDrm:
3652  case X86::FsVMOVAPSrm:
3653  case X86::FsVMOVAPDrm:
3654  case X86::VMOVAPSrm:
3655  case X86::VMOVUPSrm:
3656  case X86::VMOVAPDrm:
3657  case X86::VMOVDQArm:
3658  case X86::VMOVDQUrm:
3659  case X86::VMOVAPSYrm:
3660  case X86::VMOVUPSYrm:
3661  case X86::VMOVAPDYrm:
3662  case X86::VMOVDQAYrm:
3663  case X86::VMOVDQUYrm:
3664    break;
3665  }
3666
3667  // Check if chain operands and base addresses match.
3668  if (Load1->getOperand(0) != Load2->getOperand(0) ||
3669      Load1->getOperand(5) != Load2->getOperand(5))
3670    return false;
3671  // Segment operands should match as well.
3672  if (Load1->getOperand(4) != Load2->getOperand(4))
3673    return false;
3674  // Scale should be 1, Index should be Reg0.
3675  if (Load1->getOperand(1) == Load2->getOperand(1) &&
3676      Load1->getOperand(2) == Load2->getOperand(2)) {
3677    if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3678      return false;
3679
3680    // Now let's examine the displacements.
3681    if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3682        isa<ConstantSDNode>(Load2->getOperand(3))) {
3683      Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3684      Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3685      return true;
3686    }
3687  }
3688  return false;
3689}
3690
3691bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3692                                           int64_t Offset1, int64_t Offset2,
3693                                           unsigned NumLoads) const {
3694  assert(Offset2 > Offset1);
3695  if ((Offset2 - Offset1) / 8 > 64)
3696    return false;
3697
3698  unsigned Opc1 = Load1->getMachineOpcode();
3699  unsigned Opc2 = Load2->getMachineOpcode();
3700  if (Opc1 != Opc2)
3701    return false;  // FIXME: overly conservative?
3702
3703  switch (Opc1) {
3704  default: break;
3705  case X86::LD_Fp32m:
3706  case X86::LD_Fp64m:
3707  case X86::LD_Fp80m:
3708  case X86::MMX_MOVD64rm:
3709  case X86::MMX_MOVQ64rm:
3710    return false;
3711  }
3712
3713  EVT VT = Load1->getValueType(0);
3714  switch (VT.getSimpleVT().SimpleTy) {
3715  default:
3716    // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3717    // have 16 of them to play with.
3718    if (TM.getSubtargetImpl()->is64Bit()) {
3719      if (NumLoads >= 3)
3720        return false;
3721    } else if (NumLoads) {
3722      return false;
3723    }
3724    break;
3725  case MVT::i8:
3726  case MVT::i16:
3727  case MVT::i32:
3728  case MVT::i64:
3729  case MVT::f32:
3730  case MVT::f64:
3731    if (NumLoads)
3732      return false;
3733    break;
3734  }
3735
3736  return true;
3737}
3738
3739
3740bool X86InstrInfo::
3741ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3742  assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3743  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3744  if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3745    return true;
3746  Cond[0].setImm(GetOppositeBranchCondition(CC));
3747  return false;
3748}
3749
3750bool X86InstrInfo::
3751isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3752  // FIXME: Return false for x87 stack register classes for now. We can't
3753  // allow any loads of these registers before FpGet_ST0_80.
3754  return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3755           RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3756}
3757
3758/// getGlobalBaseReg - Return a virtual register initialized with the
3759/// the global base register value. Output instructions required to
3760/// initialize the register in the function entry block, if necessary.
3761///
3762/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3763///
3764unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3765  assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3766         "X86-64 PIC uses RIP relative addressing");
3767
3768  X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3769  unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3770  if (GlobalBaseReg != 0)
3771    return GlobalBaseReg;
3772
3773  // Create the register. The code to initialize it is inserted
3774  // later, by the CGBR pass (below).
3775  MachineRegisterInfo &RegInfo = MF->getRegInfo();
3776  GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
3777  X86FI->setGlobalBaseReg(GlobalBaseReg);
3778  return GlobalBaseReg;
3779}
3780
3781// These are the replaceable SSE instructions. Some of these have Int variants
3782// that we don't include here. We don't want to replace instructions selected
3783// by intrinsics.
3784static const uint16_t ReplaceableInstrs[][3] = {
3785  //PackedSingle     PackedDouble    PackedInt
3786  { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
3787  { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
3788  { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
3789  { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
3790  { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
3791  { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
3792  { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
3793  { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
3794  { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
3795  { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
3796  { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
3797  { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
3798  { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
3799  { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
3800  // AVX 128-bit support
3801  { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
3802  { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
3803  { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
3804  { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
3805  { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
3806  { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3807  { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
3808  { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
3809  { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
3810  { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
3811  { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
3812  { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
3813  { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
3814  { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
3815  // AVX 256-bit support
3816  { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
3817  { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
3818  { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
3819  { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
3820  { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
3821  { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
3822};
3823
3824static const uint16_t ReplaceableInstrsAVX2[][3] = {
3825  //PackedSingle       PackedDouble       PackedInt
3826  { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
3827  { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
3828  { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
3829  { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
3830  { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
3831  { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
3832  { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
3833  { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
3834  { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
3835  { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
3836  { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
3837  { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
3838  { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
3839  { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr }
3840};
3841
3842// FIXME: Some shuffle and unpack instructions have equivalents in different
3843// domains, but they require a bit more work than just switching opcodes.
3844
3845static const uint16_t *lookup(unsigned opcode, unsigned domain) {
3846  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3847    if (ReplaceableInstrs[i][domain-1] == opcode)
3848      return ReplaceableInstrs[i];
3849  return 0;
3850}
3851
3852static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
3853  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
3854    if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
3855      return ReplaceableInstrsAVX2[i];
3856  return 0;
3857}
3858
3859std::pair<uint16_t, uint16_t>
3860X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3861  uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3862  bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
3863  uint16_t validDomains = 0;
3864  if (domain && lookup(MI->getOpcode(), domain))
3865    validDomains = 0xe;
3866  else if (domain && lookupAVX2(MI->getOpcode(), domain))
3867    validDomains = hasAVX2 ? 0xe : 0x6;
3868  return std::make_pair(domain, validDomains);
3869}
3870
3871void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3872  assert(Domain>0 && Domain<4 && "Invalid execution domain");
3873  uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3874  assert(dom && "Not an SSE instruction");
3875  const uint16_t *table = lookup(MI->getOpcode(), dom);
3876  if (!table) { // try the other table
3877    assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
3878           "256-bit vector operations only available in AVX2");
3879    table = lookupAVX2(MI->getOpcode(), dom);
3880  }
3881  assert(table && "Cannot change domain");
3882  MI->setDesc(get(table[Domain-1]));
3883}
3884
3885/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3886void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3887  NopInst.setOpcode(X86::NOOP);
3888}
3889
3890bool X86InstrInfo::isHighLatencyDef(int opc) const {
3891  switch (opc) {
3892  default: return false;
3893  case X86::DIVSDrm:
3894  case X86::DIVSDrm_Int:
3895  case X86::DIVSDrr:
3896  case X86::DIVSDrr_Int:
3897  case X86::DIVSSrm:
3898  case X86::DIVSSrm_Int:
3899  case X86::DIVSSrr:
3900  case X86::DIVSSrr_Int:
3901  case X86::SQRTPDm:
3902  case X86::SQRTPDm_Int:
3903  case X86::SQRTPDr:
3904  case X86::SQRTPDr_Int:
3905  case X86::SQRTPSm:
3906  case X86::SQRTPSm_Int:
3907  case X86::SQRTPSr:
3908  case X86::SQRTPSr_Int:
3909  case X86::SQRTSDm:
3910  case X86::SQRTSDm_Int:
3911  case X86::SQRTSDr:
3912  case X86::SQRTSDr_Int:
3913  case X86::SQRTSSm:
3914  case X86::SQRTSSm_Int:
3915  case X86::SQRTSSr:
3916  case X86::SQRTSSr_Int:
3917  // AVX instructions with high latency
3918  case X86::VDIVSDrm:
3919  case X86::VDIVSDrm_Int:
3920  case X86::VDIVSDrr:
3921  case X86::VDIVSDrr_Int:
3922  case X86::VDIVSSrm:
3923  case X86::VDIVSSrm_Int:
3924  case X86::VDIVSSrr:
3925  case X86::VDIVSSrr_Int:
3926  case X86::VSQRTPDm:
3927  case X86::VSQRTPDm_Int:
3928  case X86::VSQRTPDr:
3929  case X86::VSQRTPDr_Int:
3930  case X86::VSQRTPSm:
3931  case X86::VSQRTPSm_Int:
3932  case X86::VSQRTPSr:
3933  case X86::VSQRTPSr_Int:
3934  case X86::VSQRTSDm:
3935  case X86::VSQRTSDm_Int:
3936  case X86::VSQRTSDr:
3937  case X86::VSQRTSSm:
3938  case X86::VSQRTSSm_Int:
3939  case X86::VSQRTSSr:
3940    return true;
3941  }
3942}
3943
3944bool X86InstrInfo::
3945hasHighOperandLatency(const InstrItineraryData *ItinData,
3946                      const MachineRegisterInfo *MRI,
3947                      const MachineInstr *DefMI, unsigned DefIdx,
3948                      const MachineInstr *UseMI, unsigned UseIdx) const {
3949  return isHighLatencyDef(DefMI->getOpcode());
3950}
3951
3952namespace {
3953  /// CGBR - Create Global Base Reg pass. This initializes the PIC
3954  /// global base register for x86-32.
3955  struct CGBR : public MachineFunctionPass {
3956    static char ID;
3957    CGBR() : MachineFunctionPass(ID) {}
3958
3959    virtual bool runOnMachineFunction(MachineFunction &MF) {
3960      const X86TargetMachine *TM =
3961        static_cast<const X86TargetMachine *>(&MF.getTarget());
3962
3963      assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3964             "X86-64 PIC uses RIP relative addressing");
3965
3966      // Only emit a global base reg in PIC mode.
3967      if (TM->getRelocationModel() != Reloc::PIC_)
3968        return false;
3969
3970      X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3971      unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3972
3973      // If we didn't need a GlobalBaseReg, don't insert code.
3974      if (GlobalBaseReg == 0)
3975        return false;
3976
3977      // Insert the set of GlobalBaseReg into the first MBB of the function
3978      MachineBasicBlock &FirstMBB = MF.front();
3979      MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3980      DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3981      MachineRegisterInfo &RegInfo = MF.getRegInfo();
3982      const X86InstrInfo *TII = TM->getInstrInfo();
3983
3984      unsigned PC;
3985      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3986        PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
3987      else
3988        PC = GlobalBaseReg;
3989
3990      // Operand of MovePCtoStack is completely ignored by asm printer. It's
3991      // only used in JIT code emission as displacement to pc.
3992      BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3993
3994      // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3995      // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3996      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3997        // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3998        BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3999          .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
4000                                        X86II::MO_GOT_ABSOLUTE_ADDRESS);
4001      }
4002
4003      return true;
4004    }
4005
4006    virtual const char *getPassName() const {
4007      return "X86 PIC Global Base Reg Initialization";
4008    }
4009
4010    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
4011      AU.setPreservesCFG();
4012      MachineFunctionPass::getAnalysisUsage(AU);
4013    }
4014  };
4015}
4016
4017char CGBR::ID = 0;
4018FunctionPass*
4019llvm::createGlobalBaseRegPass() { return new CGBR(); }
4020
4021namespace {
4022  struct LDTLSCleanup : public MachineFunctionPass {
4023    static char ID;
4024    LDTLSCleanup() : MachineFunctionPass(ID) {}
4025
4026    virtual bool runOnMachineFunction(MachineFunction &MF) {
4027      X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
4028      if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
4029        // No point folding accesses if there isn't at least two.
4030        return false;
4031      }
4032
4033      MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
4034      return VisitNode(DT->getRootNode(), 0);
4035    }
4036
4037    // Visit the dominator subtree rooted at Node in pre-order.
4038    // If TLSBaseAddrReg is non-null, then use that to replace any
4039    // TLS_base_addr instructions. Otherwise, create the register
4040    // when the first such instruction is seen, and then use it
4041    // as we encounter more instructions.
4042    bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
4043      MachineBasicBlock *BB = Node->getBlock();
4044      bool Changed = false;
4045
4046      // Traverse the current block.
4047      for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
4048           ++I) {
4049        switch (I->getOpcode()) {
4050          case X86::TLS_base_addr32:
4051          case X86::TLS_base_addr64:
4052            if (TLSBaseAddrReg)
4053              I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
4054            else
4055              I = SetRegister(I, &TLSBaseAddrReg);
4056            Changed = true;
4057            break;
4058          default:
4059            break;
4060        }
4061      }
4062
4063      // Visit the children of this block in the dominator tree.
4064      for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
4065           I != E; ++I) {
4066        Changed |= VisitNode(*I, TLSBaseAddrReg);
4067      }
4068
4069      return Changed;
4070    }
4071
4072    // Replace the TLS_base_addr instruction I with a copy from
4073    // TLSBaseAddrReg, returning the new instruction.
4074    MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
4075                                         unsigned TLSBaseAddrReg) {
4076      MachineFunction *MF = I->getParent()->getParent();
4077      const X86TargetMachine *TM =
4078          static_cast<const X86TargetMachine *>(&MF->getTarget());
4079      const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
4080      const X86InstrInfo *TII = TM->getInstrInfo();
4081
4082      // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
4083      MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
4084                                   TII->get(TargetOpcode::COPY),
4085                                   is64Bit ? X86::RAX : X86::EAX)
4086                                   .addReg(TLSBaseAddrReg);
4087
4088      // Erase the TLS_base_addr instruction.
4089      I->eraseFromParent();
4090
4091      return Copy;
4092    }
4093
4094    // Create a virtal register in *TLSBaseAddrReg, and populate it by
4095    // inserting a copy instruction after I. Returns the new instruction.
4096    MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
4097      MachineFunction *MF = I->getParent()->getParent();
4098      const X86TargetMachine *TM =
4099          static_cast<const X86TargetMachine *>(&MF->getTarget());
4100      const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
4101      const X86InstrInfo *TII = TM->getInstrInfo();
4102
4103      // Create a virtual register for the TLS base address.
4104      MachineRegisterInfo &RegInfo = MF->getRegInfo();
4105      *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
4106                                                      ? &X86::GR64RegClass
4107                                                      : &X86::GR32RegClass);
4108
4109      // Insert a copy from RAX/EAX to TLSBaseAddrReg.
4110      MachineInstr *Next = I->getNextNode();
4111      MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
4112                                   TII->get(TargetOpcode::COPY),
4113                                   *TLSBaseAddrReg)
4114                                   .addReg(is64Bit ? X86::RAX : X86::EAX);
4115
4116      return Copy;
4117    }
4118
4119    virtual const char *getPassName() const {
4120      return "Local Dynamic TLS Access Clean-up";
4121    }
4122
4123    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
4124      AU.setPreservesCFG();
4125      AU.addRequired<MachineDominatorTree>();
4126      MachineFunctionPass::getAnalysisUsage(AU);
4127    }
4128  };
4129}
4130
4131char LDTLSCleanup::ID = 0;
4132FunctionPass*
4133llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
4134