XCoreInstrInfo.cpp revision c7f3ace20c325521c68335a1689645b43b06ddf0
1//===- XCoreInstrInfo.cpp - XCore Instruction Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the XCore implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "XCoreMachineFunctionInfo.h" 15#include "XCoreInstrInfo.h" 16#include "XCore.h" 17#include "llvm/ADT/STLExtras.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineLocation.h" 21#include "llvm/CodeGen/MachineModuleInfo.h" 22#include "XCoreGenInstrInfo.inc" 23#include "llvm/Support/Debug.h" 24#include "llvm/Support/ErrorHandling.h" 25 26namespace llvm { 27namespace XCore { 28 29 // XCore Condition Codes 30 enum CondCode { 31 COND_TRUE, 32 COND_FALSE, 33 COND_INVALID 34 }; 35} 36} 37 38using namespace llvm; 39 40XCoreInstrInfo::XCoreInstrInfo() 41 : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)), 42 RI(*this) { 43} 44 45static bool isZeroImm(const MachineOperand &op) { 46 return op.isImm() && op.getImm() == 0; 47} 48 49/// Return true if the instruction is a register to register move and 50/// leave the source and dest operands in the passed parameters. 51/// 52bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI, 53 unsigned &SrcReg, unsigned &DstReg, 54 unsigned &SrcSR, unsigned &DstSR) const { 55 SrcSR = DstSR = 0; // No sub-registers. 56 57 // We look for 4 kinds of patterns here: 58 // add dst, src, 0 59 // sub dst, src, 0 60 // or dst, src, src 61 // and dst, src, src 62 if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus) 63 && isZeroImm(MI.getOperand(2))) { 64 DstReg = MI.getOperand(0).getReg(); 65 SrcReg = MI.getOperand(1).getReg(); 66 return true; 67 } else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r) 68 && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { 69 DstReg = MI.getOperand(0).getReg(); 70 SrcReg = MI.getOperand(1).getReg(); 71 return true; 72 } 73 return false; 74} 75 76/// isLoadFromStackSlot - If the specified machine instruction is a direct 77/// load from a stack slot, return the virtual or physical register number of 78/// the destination along with the FrameIndex of the loaded stack slot. If 79/// not, return 0. This predicate must return 0 if the instruction has 80/// any side effects other than loading from the stack slot. 81unsigned 82XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{ 83 int Opcode = MI->getOpcode(); 84 if (Opcode == XCore::LDWFI) 85 { 86 if ((MI->getOperand(1).isFI()) && // is a stack slot 87 (MI->getOperand(2).isImm()) && // the imm is zero 88 (isZeroImm(MI->getOperand(2)))) 89 { 90 FrameIndex = MI->getOperand(1).getIndex(); 91 return MI->getOperand(0).getReg(); 92 } 93 } 94 return 0; 95} 96 97 /// isStoreToStackSlot - If the specified machine instruction is a direct 98 /// store to a stack slot, return the virtual or physical register number of 99 /// the source reg along with the FrameIndex of the loaded stack slot. If 100 /// not, return 0. This predicate must return 0 if the instruction has 101 /// any side effects other than storing to the stack slot. 102unsigned 103XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 104 int &FrameIndex) const { 105 int Opcode = MI->getOpcode(); 106 if (Opcode == XCore::STWFI) 107 { 108 if ((MI->getOperand(1).isFI()) && // is a stack slot 109 (MI->getOperand(2).isImm()) && // the imm is zero 110 (isZeroImm(MI->getOperand(2)))) 111 { 112 FrameIndex = MI->getOperand(1).getIndex(); 113 return MI->getOperand(0).getReg(); 114 } 115 } 116 return 0; 117} 118 119//===----------------------------------------------------------------------===// 120// Branch Analysis 121//===----------------------------------------------------------------------===// 122 123static inline bool IsBRU(unsigned BrOpc) { 124 return BrOpc == XCore::BRFU_u6 125 || BrOpc == XCore::BRFU_lu6 126 || BrOpc == XCore::BRBU_u6 127 || BrOpc == XCore::BRBU_lu6; 128} 129 130static inline bool IsBRT(unsigned BrOpc) { 131 return BrOpc == XCore::BRFT_ru6 132 || BrOpc == XCore::BRFT_lru6 133 || BrOpc == XCore::BRBT_ru6 134 || BrOpc == XCore::BRBT_lru6; 135} 136 137static inline bool IsBRF(unsigned BrOpc) { 138 return BrOpc == XCore::BRFF_ru6 139 || BrOpc == XCore::BRFF_lru6 140 || BrOpc == XCore::BRBF_ru6 141 || BrOpc == XCore::BRBF_lru6; 142} 143 144static inline bool IsCondBranch(unsigned BrOpc) { 145 return IsBRF(BrOpc) || IsBRT(BrOpc); 146} 147 148static inline bool IsBR_JT(unsigned BrOpc) { 149 return BrOpc == XCore::BR_JT 150 || BrOpc == XCore::BR_JT32; 151} 152 153/// GetCondFromBranchOpc - Return the XCore CC that matches 154/// the correspondent Branch instruction opcode. 155static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) 156{ 157 if (IsBRT(BrOpc)) { 158 return XCore::COND_TRUE; 159 } else if (IsBRF(BrOpc)) { 160 return XCore::COND_FALSE; 161 } else { 162 return XCore::COND_INVALID; 163 } 164} 165 166/// GetCondBranchFromCond - Return the Branch instruction 167/// opcode that matches the cc. 168static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 169{ 170 switch (CC) { 171 default: llvm_unreachable("Illegal condition code!"); 172 case XCore::COND_TRUE : return XCore::BRFT_lru6; 173 case XCore::COND_FALSE : return XCore::BRFF_lru6; 174 } 175} 176 177/// GetOppositeBranchCondition - Return the inverse of the specified 178/// condition, e.g. turning COND_E to COND_NE. 179static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) 180{ 181 switch (CC) { 182 default: llvm_unreachable("Illegal condition code!"); 183 case XCore::COND_TRUE : return XCore::COND_FALSE; 184 case XCore::COND_FALSE : return XCore::COND_TRUE; 185 } 186} 187 188/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 189/// true if it cannot be understood (e.g. it's a switch dispatch or isn't 190/// implemented for a target). Upon success, this returns false and returns 191/// with the following information in various cases: 192/// 193/// 1. If this block ends with no branches (it just falls through to its succ) 194/// just return false, leaving TBB/FBB null. 195/// 2. If this block ends with only an unconditional branch, it sets TBB to be 196/// the destination block. 197/// 3. If this block ends with an conditional branch and it falls through to 198/// an successor block, it sets TBB to be the branch destination block and a 199/// list of operands that evaluate the condition. These 200/// operands can be passed to other TargetInstrInfo methods to create new 201/// branches. 202/// 4. If this block ends with an conditional branch and an unconditional 203/// block, it returns the 'true' destination in TBB, the 'false' destination 204/// in FBB, and a list of operands that evaluate the condition. These 205/// operands can be passed to other TargetInstrInfo methods to create new 206/// branches. 207/// 208/// Note that RemoveBranch and InsertBranch must be implemented to support 209/// cases where this method returns success. 210/// 211bool 212XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 213 MachineBasicBlock *&FBB, 214 SmallVectorImpl<MachineOperand> &Cond, 215 bool AllowModify) const { 216 // If the block has no terminators, it just falls into the block after it. 217 MachineBasicBlock::iterator I = MBB.end(); 218 if (I == MBB.begin()) 219 return false; 220 --I; 221 while (I->isDebugValue()) { 222 if (I == MBB.begin()) 223 return false; 224 --I; 225 } 226 if (!isUnpredicatedTerminator(I)) 227 return false; 228 229 // Get the last instruction in the block. 230 MachineInstr *LastInst = I; 231 232 // If there is only one terminator instruction, process it. 233 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 234 if (IsBRU(LastInst->getOpcode())) { 235 TBB = LastInst->getOperand(0).getMBB(); 236 return false; 237 } 238 239 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 240 if (BranchCode == XCore::COND_INVALID) 241 return true; // Can't handle indirect branch. 242 243 // Conditional branch 244 // Block ends with fall-through condbranch. 245 246 TBB = LastInst->getOperand(1).getMBB(); 247 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 248 Cond.push_back(LastInst->getOperand(0)); 249 return false; 250 } 251 252 // Get the instruction before it if it's a terminator. 253 MachineInstr *SecondLastInst = I; 254 255 // If there are three terminators, we don't know what sort of block this is. 256 if (SecondLastInst && I != MBB.begin() && 257 isUnpredicatedTerminator(--I)) 258 return true; 259 260 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 261 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 262 263 // If the block ends with conditional branch followed by unconditional, 264 // handle it. 265 if (BranchCode != XCore::COND_INVALID 266 && IsBRU(LastInst->getOpcode())) { 267 268 TBB = SecondLastInst->getOperand(1).getMBB(); 269 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 270 Cond.push_back(SecondLastInst->getOperand(0)); 271 272 FBB = LastInst->getOperand(0).getMBB(); 273 return false; 274 } 275 276 // If the block ends with two unconditional branches, handle it. The second 277 // one is not executed, so remove it. 278 if (IsBRU(SecondLastInst->getOpcode()) && 279 IsBRU(LastInst->getOpcode())) { 280 TBB = SecondLastInst->getOperand(0).getMBB(); 281 I = LastInst; 282 if (AllowModify) 283 I->eraseFromParent(); 284 return false; 285 } 286 287 // Likewise if it ends with a branch table followed by an unconditional branch. 288 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { 289 I = LastInst; 290 if (AllowModify) 291 I->eraseFromParent(); 292 return true; 293 } 294 295 // Otherwise, can't handle this. 296 return true; 297} 298 299unsigned 300XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 301 MachineBasicBlock *FBB, 302 const SmallVectorImpl<MachineOperand> &Cond)const{ 303 // FIXME there should probably be a DebugLoc argument here 304 DebugLoc dl; 305 // Shouldn't be a fall through. 306 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 307 assert((Cond.size() == 2 || Cond.size() == 0) && 308 "Unexpected number of components!"); 309 310 if (FBB == 0) { // One way branch. 311 if (Cond.empty()) { 312 // Unconditional branch 313 BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(TBB); 314 } else { 315 // Conditional branch. 316 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 317 BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) 318 .addMBB(TBB); 319 } 320 return 1; 321 } 322 323 // Two-way Conditional branch. 324 assert(Cond.size() == 2 && "Unexpected number of components!"); 325 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 326 BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) 327 .addMBB(TBB); 328 BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(FBB); 329 return 2; 330} 331 332unsigned 333XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 334 MachineBasicBlock::iterator I = MBB.end(); 335 if (I == MBB.begin()) return 0; 336 --I; 337 while (I->isDebugValue()) { 338 if (I == MBB.begin()) 339 return 0; 340 --I; 341 } 342 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) 343 return 0; 344 345 // Remove the branch. 346 I->eraseFromParent(); 347 348 I = MBB.end(); 349 350 if (I == MBB.begin()) return 1; 351 --I; 352 if (!IsCondBranch(I->getOpcode())) 353 return 1; 354 355 // Remove the branch. 356 I->eraseFromParent(); 357 return 2; 358} 359 360bool XCoreInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 361 MachineBasicBlock::iterator I, 362 unsigned DestReg, unsigned SrcReg, 363 const TargetRegisterClass *DestRC, 364 const TargetRegisterClass *SrcRC) const { 365 DebugLoc DL; 366 if (I != MBB.end()) DL = I->getDebugLoc(); 367 368 if (DestRC == SrcRC) { 369 if (DestRC == XCore::GRRegsRegisterClass) { 370 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) 371 .addReg(SrcReg) 372 .addImm(0); 373 return true; 374 } else { 375 return false; 376 } 377 } 378 379 if (SrcRC == XCore::RRegsRegisterClass && SrcReg == XCore::SP && 380 DestRC == XCore::GRRegsRegisterClass) { 381 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg) 382 .addImm(0); 383 return true; 384 } 385 if (DestRC == XCore::RRegsRegisterClass && DestReg == XCore::SP && 386 SrcRC == XCore::GRRegsRegisterClass) { 387 BuildMI(MBB, I, DL, get(XCore::SETSP_1r)) 388 .addReg(SrcReg); 389 return true; 390 } 391 return false; 392} 393 394void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 395 MachineBasicBlock::iterator I, 396 unsigned SrcReg, bool isKill, 397 int FrameIndex, 398 const TargetRegisterClass *RC) const 399{ 400 DebugLoc DL; 401 if (I != MBB.end()) DL = I->getDebugLoc(); 402 BuildMI(MBB, I, DL, get(XCore::STWFI)) 403 .addReg(SrcReg, getKillRegState(isKill)) 404 .addFrameIndex(FrameIndex) 405 .addImm(0); 406} 407 408void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 409 MachineBasicBlock::iterator I, 410 unsigned DestReg, int FrameIndex, 411 const TargetRegisterClass *RC) const 412{ 413 DebugLoc DL; 414 if (I != MBB.end()) DL = I->getDebugLoc(); 415 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) 416 .addFrameIndex(FrameIndex) 417 .addImm(0); 418} 419 420bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 421 MachineBasicBlock::iterator MI, 422 const std::vector<CalleeSavedInfo> &CSI) const 423{ 424 if (CSI.empty()) { 425 return true; 426 } 427 MachineFunction *MF = MBB.getParent(); 428 const MachineFrameInfo *MFI = MF->getFrameInfo(); 429 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 430 XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>(); 431 432 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); 433 434 DebugLoc DL; 435 if (MI != MBB.end()) DL = MI->getDebugLoc(); 436 437 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin(); 438 it != CSI.end(); ++it) { 439 // Add the callee-saved register as live-in. It's killed at the spill. 440 MBB.addLiveIn(it->getReg()); 441 442 storeRegToStackSlot(MBB, MI, it->getReg(), true, 443 it->getFrameIdx(), it->getRegClass()); 444 if (emitFrameMoves) { 445 MCSymbol *SaveLabel = MMI->getContext().CreateTempSymbol(); 446 BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addSym(SaveLabel); 447 XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it)); 448 } 449 } 450 return true; 451} 452 453bool XCoreInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 454 MachineBasicBlock::iterator MI, 455 const std::vector<CalleeSavedInfo> &CSI) const 456{ 457 bool AtStart = MI == MBB.begin(); 458 MachineBasicBlock::iterator BeforeI = MI; 459 if (!AtStart) 460 --BeforeI; 461 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin(); 462 it != CSI.end(); ++it) { 463 464 loadRegFromStackSlot(MBB, MI, it->getReg(), 465 it->getFrameIdx(), 466 it->getRegClass()); 467 assert(MI != MBB.begin() && 468 "loadRegFromStackSlot didn't insert any code!"); 469 // Insert in reverse order. loadRegFromStackSlot can insert multiple 470 // instructions. 471 if (AtStart) 472 MI = MBB.begin(); 473 else { 474 MI = BeforeI; 475 ++MI; 476 } 477 } 478 return true; 479} 480 481/// ReverseBranchCondition - Return the inverse opcode of the 482/// specified Branch instruction. 483bool XCoreInstrInfo:: 484ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 485{ 486 assert((Cond.size() == 2) && 487 "Invalid XCore branch condition!"); 488 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); 489 return false; 490} 491