InstrInfoEmitter.cpp revision 04677a3b49b2dfb151c4f77345702da489293627 
1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of the target
11// instruction set for the code generator.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrInfoEmitter.h"
16#include "CodeGenTarget.h"
17#include "llvm/Target/TargetInstrInfo.h"
18#include "Record.h"
19#include <algorithm>
20using namespace llvm;
21
22// runEnums - Print out enum values for all of the instructions.
23void InstrInfoEmitter::runEnums(std::ostream &OS) {
24  EmitSourceFileHeader("Target Instruction Enum Values", OS);
25  OS << "namespace llvm {\n\n";
26
27  CodeGenTarget Target;
28
29  // We must emit the PHI opcode first...
30  std::string Namespace;
31  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
32       E = Target.inst_end(); II != E; ++II) {
33    if (II->second.Namespace != "TargetInstrInfo") {
34      Namespace = II->second.Namespace;
35      break;
36    }
37  }
38
39  if (Namespace.empty()) {
40    cerr << "No instructions defined!\n";
41    exit(1);
42  }
43
44  std::vector<const CodeGenInstruction*> NumberedInstructions;
45  Target.getInstructionsByEnumValue(NumberedInstructions);
46
47  OS << "namespace " << Namespace << " {\n";
48  OS << "  enum {\n";
49  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
50    OS << "    " << NumberedInstructions[i]->TheDef->getName()
51       << "\t= " << i << ",\n";
52  }
53  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
54  OS << "  };\n}\n";
55  OS << "} // End llvm namespace \n";
56}
57
58void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
59                                    unsigned Num, std::ostream &OS) const {
60  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
61  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
62    OS << getQualifiedName(Uses[i]) << ", ";
63  OS << "0 };\n";
64}
65
66std::vector<std::string>
67InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
68  std::vector<std::string> Result;
69
70  for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
71    // Handle aggregate operands and normal operands the same way by expanding
72    // either case into a list of operands for this op.
73    std::vector<CodeGenInstruction::OperandInfo> OperandList;
74
75    // This might be a multiple operand thing.  Targets like X86 have
76    // registers in their multi-operand operands.  It may also be an anonymous
77    // operand, which has a single operand, but no declared class for the
78    // operand.
79    DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
80
81    if (!MIOI || MIOI->getNumArgs() == 0) {
82      // Single, anonymous, operand.
83      OperandList.push_back(Inst.OperandList[i]);
84    } else {
85      for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
86        OperandList.push_back(Inst.OperandList[i]);
87
88        Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
89        OperandList.back().Rec = OpR;
90      }
91    }
92
93    for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
94      Record *OpR = OperandList[j].Rec;
95      std::string Res;
96
97      if (OpR->isSubClassOf("RegisterClass"))
98        Res += getQualifiedName(OpR) + "RegClassID, ";
99      else
100        Res += "0, ";
101      // Fill in applicable flags.
102      Res += "0";
103
104      // Ptr value whose register class is resolved via callback.
105      if (OpR->getName() == "ptr_rc")
106        Res += "|M_LOOK_UP_PTR_REG_CLASS";
107
108      // Predicate operands.  Check to see if the original unexpanded operand
109      // was of type PredicateOperand.
110      if (j == 0 && Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
111        Res += "|M_PREDICATE_OPERAND";
112
113      // Fill in constraint info.
114      Res += ", " + Inst.OperandList[i].Constraints[j];
115      Result.push_back(Res);
116    }
117  }
118
119  return Result;
120}
121
122
123// run - Emit the main instruction description records for the target...
124void InstrInfoEmitter::run(std::ostream &OS) {
125  GatherItinClasses();
126
127  EmitSourceFileHeader("Target Instruction Descriptors", OS);
128  OS << "namespace llvm {\n\n";
129
130  CodeGenTarget Target;
131  const std::string &TargetName = Target.getName();
132  Record *InstrInfo = Target.getInstructionSet();
133
134  // Keep track of all of the def lists we have emitted already.
135  std::map<std::vector<Record*>, unsigned> EmittedLists;
136  unsigned ListNumber = 0;
137
138  // Emit all of the instruction's implicit uses and defs.
139  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
140         E = Target.inst_end(); II != E; ++II) {
141    Record *Inst = II->second.TheDef;
142    std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
143    if (!Uses.empty()) {
144      unsigned &IL = EmittedLists[Uses];
145      if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
146    }
147    std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
148    if (!Defs.empty()) {
149      unsigned &IL = EmittedLists[Defs];
150      if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
151    }
152  }
153
154  std::map<std::vector<std::string>, unsigned> OperandInfosEmitted;
155  unsigned OperandListNum = 0;
156  OperandInfosEmitted[std::vector<std::string>()] = ++OperandListNum;
157
158  // Emit all of the operand info records.
159  OS << "\n";
160  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
161       E = Target.inst_end(); II != E; ++II) {
162    std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
163    unsigned &N = OperandInfosEmitted[OperandInfo];
164    if (N == 0) {
165      N = ++OperandListNum;
166      OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
167      for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
168        OS << "{ " << OperandInfo[i] << " }, ";
169      OS << "};\n";
170    }
171  }
172
173  // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
174  //
175  OS << "\nstatic const TargetInstrDescriptor " << TargetName
176     << "Insts[] = {\n";
177  std::vector<const CodeGenInstruction*> NumberedInstructions;
178  Target.getInstructionsByEnumValue(NumberedInstructions);
179
180  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
181    emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
182               OperandInfosEmitted, OS);
183  OS << "};\n";
184  OS << "} // End llvm namespace \n";
185}
186
187void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
188                                  Record *InstrInfo,
189                         std::map<std::vector<Record*>, unsigned> &EmittedLists,
190                           std::map<std::vector<std::string>, unsigned> &OpInfo,
191                                  std::ostream &OS) {
192  int MinOperands;
193  if (!Inst.OperandList.empty())
194    // Each logical operand can be multiple MI operands.
195    MinOperands = Inst.OperandList.back().MIOperandNo +
196                  Inst.OperandList.back().MINumOperands;
197  else
198    MinOperands = 0;
199
200  OS << "  { ";
201  OS << Num << ",\t" << MinOperands << ",\t\"";
202
203  if (Inst.Name.empty())
204    OS << Inst.TheDef->getName();
205  else
206    OS << Inst.Name;
207
208  unsigned ItinClass = !IsItineraries ? 0 :
209            ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
210
211  OS << "\",\t" << ItinClass << ", 0";
212
213  // Try to determine (from the pattern), if the instruction is a store.
214  bool isStore = false;
215  if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
216    ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
217    if (LI && LI->getSize() > 0) {
218      DagInit *Dag = (DagInit *)LI->getElement(0);
219      DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
220      if (OpDef) {
221        Record *Operator = OpDef->getDef();
222        if (Operator->isSubClassOf("SDNode")) {
223          const std::string Opcode = Operator->getValueAsString("Opcode");
224          if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
225            isStore = true;
226        }
227      }
228    }
229  }
230
231  // Emit all of the target indepedent flags...
232  if (Inst.isReturn)     OS << "|M_RET_FLAG";
233  if (Inst.isBranch)     OS << "|M_BRANCH_FLAG";
234  if (Inst.isBarrier)    OS << "|M_BARRIER_FLAG";
235  if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
236  if (Inst.isCall)       OS << "|M_CALL_FLAG";
237  if (Inst.isLoad)       OS << "|M_LOAD_FLAG";
238  if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
239  if (Inst.isPredicated) OS << "|M_PREDICATED";
240  if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
241  if (Inst.isCommutable) OS << "|M_COMMUTABLE";
242  if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
243  if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE";
244  if (Inst.usesCustomDAGSchedInserter)
245    OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
246  if (Inst.hasVariableNumberOfOperands)
247    OS << "|M_VARIABLE_OPS";
248  OS << ", 0";
249
250  // Emit all of the target-specific flags...
251  ListInit *LI    = InstrInfo->getValueAsListInit("TSFlagsFields");
252  ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
253  if (LI->getSize() != Shift->getSize())
254    throw "Lengths of " + InstrInfo->getName() +
255          ":(TargetInfoFields, TargetInfoPositions) must be equal!";
256
257  for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
258    emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
259                     dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
260
261  OS << ", ";
262
263  // Emit the implicit uses and defs lists...
264  std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
265  if (UseList.empty())
266    OS << "NULL, ";
267  else
268    OS << "ImplicitList" << EmittedLists[UseList] << ", ";
269
270  std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
271  if (DefList.empty())
272    OS << "NULL, ";
273  else
274    OS << "ImplicitList" << EmittedLists[DefList] << ", ";
275
276  // Emit the operand info.
277  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
278  if (OperandInfo.empty())
279    OS << "0";
280  else
281    OS << "OperandInfo" << OpInfo[OperandInfo];
282
283  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
284}
285
286struct LessRecord {
287  bool operator()(const Record *Rec1, const Record *Rec2) const {
288    return Rec1->getName() < Rec2->getName();
289  }
290};
291void InstrInfoEmitter::GatherItinClasses() {
292  std::vector<Record*> DefList =
293                          Records.getAllDerivedDefinitions("InstrItinClass");
294  IsItineraries = !DefList.empty();
295
296  if (!IsItineraries) return;
297
298  std::sort(DefList.begin(), DefList.end(), LessRecord());
299
300  for (unsigned i = 0, N = DefList.size(); i < N; i++) {
301    Record *Def = DefList[i];
302    ItinClassMap[Def->getName()] = i;
303  }
304}
305
306unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
307  return ItinClassMap[ItinName];
308}
309
310void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
311                                        IntInit *ShiftInt, std::ostream &OS) {
312  if (Val == 0 || ShiftInt == 0)
313    throw std::string("Illegal value or shift amount in TargetInfo*!");
314  RecordVal *RV = R->getValue(Val->getValue());
315  int Shift = ShiftInt->getValue();
316
317  if (RV == 0 || RV->getValue() == 0) {
318    // This isn't an error if this is a builtin instruction.
319    if (R->getName() != "PHI" &&
320        R->getName() != "INLINEASM" &&
321        R->getName() != "LABEL")
322      throw R->getName() + " doesn't have a field named '" +
323            Val->getValue() + "'!";
324    return;
325  }
326
327  Init *Value = RV->getValue();
328  if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
329    if (BI->getValue()) OS << "|(1<<" << Shift << ")";
330    return;
331  } else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
332    // Convert the Bits to an integer to print...
333    Init *I = BI->convertInitializerTo(new IntRecTy());
334    if (I)
335      if (IntInit *II = dynamic_cast<IntInit*>(I)) {
336        if (II->getValue()) {
337          if (Shift)
338            OS << "|(" << II->getValue() << "<<" << Shift << ")";
339          else
340            OS << "|" << II->getValue();
341        }
342        return;
343      }
344
345  } else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
346    if (II->getValue()) {
347      if (Shift)
348        OS << "|(" << II->getValue() << "<<" << Shift << ")";
349      else
350        OS << II->getValue();
351    }
352    return;
353  }
354
355  cerr << "Unhandled initializer: " << *Val << "\n";
356  throw "In record '" + R->getName() + "' for TSFlag emission.";
357}
358
359