1//===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the main function for LLVM's TableGen. 11// 12//===----------------------------------------------------------------------===// 13 14#include "TableGenBackends.h" // Declares all backends. 15#include "SetTheory.h" 16#include "llvm/Support/CommandLine.h" 17#include "llvm/Support/PrettyStackTrace.h" 18#include "llvm/Support/Signals.h" 19#include "llvm/TableGen/Error.h" 20#include "llvm/TableGen/Main.h" 21#include "llvm/TableGen/Record.h" 22 23using namespace llvm; 24 25enum ActionType { 26 PrintRecords, 27 GenEmitter, 28 GenRegisterInfo, 29 GenInstrInfo, 30 GenAsmWriter, 31 GenAsmMatcher, 32 GenDisassembler, 33 GenPseudoLowering, 34 GenCallingConv, 35 GenDAGISel, 36 GenDFAPacketizer, 37 GenFastISel, 38 GenSubtarget, 39 GenIntrinsic, 40 GenTgtIntrinsic, 41 PrintEnums, 42 PrintSets, 43 GenOptParserDefs 44}; 45 46namespace { 47 cl::opt<ActionType> 48 Action(cl::desc("Action to perform:"), 49 cl::values(clEnumValN(PrintRecords, "print-records", 50 "Print all records to stdout (default)"), 51 clEnumValN(GenEmitter, "gen-emitter", 52 "Generate machine code emitter"), 53 clEnumValN(GenRegisterInfo, "gen-register-info", 54 "Generate registers and register classes info"), 55 clEnumValN(GenInstrInfo, "gen-instr-info", 56 "Generate instruction descriptions"), 57 clEnumValN(GenCallingConv, "gen-callingconv", 58 "Generate calling convention descriptions"), 59 clEnumValN(GenAsmWriter, "gen-asm-writer", 60 "Generate assembly writer"), 61 clEnumValN(GenDisassembler, "gen-disassembler", 62 "Generate disassembler"), 63 clEnumValN(GenPseudoLowering, "gen-pseudo-lowering", 64 "Generate pseudo instruction lowering"), 65 clEnumValN(GenAsmMatcher, "gen-asm-matcher", 66 "Generate assembly instruction matcher"), 67 clEnumValN(GenDAGISel, "gen-dag-isel", 68 "Generate a DAG instruction selector"), 69 clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer", 70 "Generate DFA Packetizer for VLIW targets"), 71 clEnumValN(GenFastISel, "gen-fast-isel", 72 "Generate a \"fast\" instruction selector"), 73 clEnumValN(GenSubtarget, "gen-subtarget", 74 "Generate subtarget enumerations"), 75 clEnumValN(GenIntrinsic, "gen-intrinsic", 76 "Generate intrinsic information"), 77 clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", 78 "Generate target intrinsic information"), 79 clEnumValN(PrintEnums, "print-enums", 80 "Print enum values for a class"), 81 clEnumValN(PrintSets, "print-sets", 82 "Print expanded sets for testing DAG exprs"), 83 clEnumValN(GenOptParserDefs, "gen-opt-parser-defs", 84 "Generate option definitions"), 85 clEnumValEnd)); 86 87 cl::opt<std::string> 88 Class("class", cl::desc("Print Enum list for this class"), 89 cl::value_desc("class name")); 90 91bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { 92 switch (Action) { 93 case PrintRecords: 94 OS << Records; // No argument, dump all contents 95 break; 96 case GenEmitter: 97 EmitCodeEmitter(Records, OS); 98 break; 99 case GenRegisterInfo: 100 EmitRegisterInfo(Records, OS); 101 break; 102 case GenInstrInfo: 103 EmitInstrInfo(Records, OS); 104 break; 105 case GenCallingConv: 106 EmitCallingConv(Records, OS); 107 break; 108 case GenAsmWriter: 109 EmitAsmWriter(Records, OS); 110 break; 111 case GenAsmMatcher: 112 EmitAsmMatcher(Records, OS); 113 break; 114 case GenDisassembler: 115 EmitDisassembler(Records, OS); 116 break; 117 case GenPseudoLowering: 118 EmitPseudoLowering(Records, OS); 119 break; 120 case GenDAGISel: 121 EmitDAGISel(Records, OS); 122 break; 123 case GenDFAPacketizer: 124 EmitDFAPacketizer(Records, OS); 125 break; 126 case GenFastISel: 127 EmitFastISel(Records, OS); 128 break; 129 case GenSubtarget: 130 EmitSubtarget(Records, OS); 131 break; 132 case GenIntrinsic: 133 EmitIntrinsics(Records, OS); 134 break; 135 case GenTgtIntrinsic: 136 EmitIntrinsics(Records, OS, true); 137 break; 138 case GenOptParserDefs: 139 EmitOptParser(Records, OS); 140 break; 141 case PrintEnums: 142 { 143 std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class); 144 for (unsigned i = 0, e = Recs.size(); i != e; ++i) 145 OS << Recs[i]->getName() << ", "; 146 OS << "\n"; 147 break; 148 } 149 case PrintSets: 150 { 151 SetTheory Sets; 152 Sets.addFieldExpander("Set", "Elements"); 153 std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set"); 154 for (unsigned i = 0, e = Recs.size(); i != e; ++i) { 155 OS << Recs[i]->getName() << " = ["; 156 const std::vector<Record*> *Elts = Sets.expand(Recs[i]); 157 assert(Elts && "Couldn't expand Set instance"); 158 for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei) 159 OS << ' ' << (*Elts)[ei]->getName(); 160 OS << " ]\n"; 161 } 162 break; 163 } 164 } 165 166 return false; 167} 168} 169 170int main(int argc, char **argv) { 171 sys::PrintStackTraceOnErrorSignal(); 172 PrettyStackTraceProgram X(argc, argv); 173 cl::ParseCommandLineOptions(argc, argv); 174 175 return TableGenMain(argv[0], &LLVMTableGenMain); 176} 177