18b112d2025046f85ef7f6be087c6129c872ebad2Ben Murdoch// Copyright 2011 the V8 project authors. All rights reserved. 2a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Redistribution and use in source and binary forms, with or without 3a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// modification, are permitted provided that the following conditions are 4a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// met: 5a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// 6a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// * Redistributions of source code must retain the above copyright 7a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// notice, this list of conditions and the following disclaimer. 8a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// * Redistributions in binary form must reproduce the above 9a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// copyright notice, this list of conditions and the following 10a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// disclaimer in the documentation and/or other materials provided 11a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// with the distribution. 12a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// * Neither the name of Google Inc. nor the names of its 13a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// contributors may be used to endorse or promote products derived 14a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// from this software without specific prior written permission. 15a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// 16a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 28a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#ifndef V8_ARM_CONSTANTS_ARM_H_ 29a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#define V8_ARM_CONSTANTS_ARM_H_ 30a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 318b112d2025046f85ef7f6be087c6129c872ebad2Ben Murdoch// ARM EABI is required. 328b112d2025046f85ef7f6be087c6129c872ebad2Ben Murdoch#if defined(__arm__) && !defined(__ARM_EABI__) 338b112d2025046f85ef7f6be087c6129c872ebad2Ben Murdoch#error ARM EABI support is required. 34a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#endif 35a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 36a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// This means that interwork-compatible jump instructions are generated. We 37a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// want to generate them on the simulator too so it makes snapshots that can 38a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// be used on real hardware. 39a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#if defined(__THUMB_INTERWORK__) || !defined(__arm__) 40a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block# define USE_THUMB_INTERWORK 1 41a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#endif 42a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 43d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block#if defined(__ARM_ARCH_7A__) || \ 44d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block defined(__ARM_ARCH_7R__) || \ 45a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block defined(__ARM_ARCH_7__) 46d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block# define CAN_USE_ARMV7_INSTRUCTIONS 1 47a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#endif 48a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 49d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block#if defined(__ARM_ARCH_6__) || \ 50d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block defined(__ARM_ARCH_6J__) || \ 51d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block defined(__ARM_ARCH_6K__) || \ 52d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block defined(__ARM_ARCH_6Z__) || \ 53d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block defined(__ARM_ARCH_6ZK__) || \ 54d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block defined(__ARM_ARCH_6T2__) || \ 55d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block defined(CAN_USE_ARMV7_INSTRUCTIONS) 56a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block# define CAN_USE_ARMV6_INSTRUCTIONS 1 57a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#endif 58a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 59d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block#if defined(__ARM_ARCH_5T__) || \ 60d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block defined(__ARM_ARCH_5TE__) || \ 61d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block defined(CAN_USE_ARMV6_INSTRUCTIONS) 62d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block# define CAN_USE_ARMV5_INSTRUCTIONS 1 63d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block# define CAN_USE_THUMB_INSTRUCTIONS 1 64a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#endif 65a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 667f4d5bd8c03935e2c0cd412e561b8fc5a6a880aeBen Murdoch// Simulator should support ARM5 instructions and unaligned access by default. 67a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#if !defined(__arm__) 68a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block# define CAN_USE_ARMV5_INSTRUCTIONS 1 69a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block# define CAN_USE_THUMB_INSTRUCTIONS 1 707f4d5bd8c03935e2c0cd412e561b8fc5a6a880aeBen Murdoch 717f4d5bd8c03935e2c0cd412e561b8fc5a6a880aeBen Murdoch# ifndef CAN_USE_UNALIGNED_ACCESSES 727f4d5bd8c03935e2c0cd412e561b8fc5a6a880aeBen Murdoch# define CAN_USE_UNALIGNED_ACCESSES 1 737f4d5bd8c03935e2c0cd412e561b8fc5a6a880aeBen Murdoch# endif 747f4d5bd8c03935e2c0cd412e561b8fc5a6a880aeBen Murdoch 75a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#endif 76a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 7725f6136652d8341ed047e7fc1a450af5bd218ea9Kristian Monsen#if CAN_USE_UNALIGNED_ACCESSES 7825f6136652d8341ed047e7fc1a450af5bd218ea9Kristian Monsen#define V8_TARGET_CAN_READ_UNALIGNED 1 7925f6136652d8341ed047e7fc1a450af5bd218ea9Kristian Monsen#endif 8025f6136652d8341ed047e7fc1a450af5bd218ea9Kristian Monsen 816ded16be15dd865a9b21ea304d5273c8be299c87Steve Block// Using blx may yield better code, so use it when required or when available 826ded16be15dd865a9b21ea304d5273c8be299c87Steve Block#if defined(USE_THUMB_INTERWORK) || defined(CAN_USE_ARMV5_INSTRUCTIONS) 836ded16be15dd865a9b21ea304d5273c8be299c87Steve Block#define USE_BLX 1 846ded16be15dd865a9b21ea304d5273c8be299c87Steve Block#endif 856ded16be15dd865a9b21ea304d5273c8be299c87Steve Block 861e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blocknamespace v8 { 871e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blocknamespace internal { 88a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 8944f0eee88ff00398ff7f715fab053374d808c90dSteve Block// Constant pool marker. 903ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst int kConstantPoolMarkerMask = 0xffe00000; 913ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst int kConstantPoolMarker = 0x0c000000; 923ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst int kConstantPoolLengthMask = 0x001ffff; 9344f0eee88ff00398ff7f715fab053374d808c90dSteve Block 94a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Number of registers in normal ARM mode. 953ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst int kNumRegisters = 16; 96a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 97d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block// VFP support. 983ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst int kNumVFPSingleRegisters = 32; 993ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst int kNumVFPDoubleRegisters = 16; 1003ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters; 101d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block 102a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// PC is register 15. 1033ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst int kPCRegister = 15; 1043ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst int kNoRegister = -1; 105a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 1061e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// ----------------------------------------------------------------------------- 1071e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Conditions. 1081e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 109a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Defines constants and accessor classes to assemble, disassemble and 110a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// simulate ARM instructions. 111a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// 112a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Section references in the code refer to the "ARM Architecture Reference 113a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) 114a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// 115a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Constants for specific fields are defined in their respective named enums. 116a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// General constants are in an anonymous enum in class Instr. 117a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 118a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Values for the condition field as defined in section A3.2 119a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Blockenum Condition { 1201e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kNoCondition = -1, 1211e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 1221e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block eq = 0 << 28, // Z set Equal. 1231e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ne = 1 << 28, // Z clear Not equal. 1241e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block cs = 2 << 28, // C set Unsigned higher or same. 1251e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block cc = 3 << 28, // C clear Unsigned lower. 1261e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block mi = 4 << 28, // N set Negative. 1271e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block pl = 5 << 28, // N clear Positive or zero. 1281e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block vs = 6 << 28, // V set Overflow. 1291e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block vc = 7 << 28, // V clear No overflow. 1301e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block hi = 8 << 28, // C set, Z clear Unsigned higher. 1311e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ls = 9 << 28, // C clear or Z set Unsigned lower or same. 1321e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ge = 10 << 28, // N == V Greater or equal. 1331e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block lt = 11 << 28, // N != V Less than. 1341e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block gt = 12 << 28, // Z clear, N == V Greater than. 1351e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block le = 13 << 28, // Z set or N != V Less then or equal 1361e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block al = 14 << 28, // Always. 1371e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 1381e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1). 1391e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kNumberOfConditions = 16, 1401e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 1411e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Aliases. 1421e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block hs = cs, // C set Unsigned higher or same. 1431e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block lo = cc // C clear Unsigned lower. 144a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block}; 145a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 146a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 1471e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockinline Condition NegateCondition(Condition cond) { 1481e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ASSERT(cond != al); 1491e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return static_cast<Condition>(cond ^ ne); 1501e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block} 1511e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 1521e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 1531e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Corresponds to transposing the operands of a comparison. 1541e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockinline Condition ReverseCondition(Condition cond) { 1551e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block switch (cond) { 1561e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block case lo: 1571e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return hi; 1581e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block case hi: 1591e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return lo; 1601e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block case hs: 1611e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return ls; 1621e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block case ls: 1631e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return hs; 1641e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block case lt: 1651e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return gt; 1661e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block case gt: 1671e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return lt; 1681e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block case ge: 1691e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return le; 1701e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block case le: 1711e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return ge; 1721e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block default: 1731e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return cond; 1741e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block }; 1751e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block} 1761e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 1771e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 1781e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// ----------------------------------------------------------------------------- 1791e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Instructions encoding. 1801e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 1811e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Instr is merely used by the Assembler to distinguish 32bit integers 1821e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// representing instructions from usual 32 bit values. 1831e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Instruction objects are pointers to 32bit values, and provide methods to 1841e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// access the various ISA fields. 1851e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blocktypedef int32_t Instr; 1861e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 1871e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 188a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Opcodes for Data-processing instructions (instructions with a type 0 and 1) 189a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// as defined in section A3.4 190a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Blockenum Opcode { 1911e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block AND = 0 << 21, // Logical AND. 1921e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block EOR = 1 << 21, // Logical Exclusive OR. 1931e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block SUB = 2 << 21, // Subtract. 1941e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block RSB = 3 << 21, // Reverse Subtract. 1951e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ADD = 4 << 21, // Add. 1961e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ADC = 5 << 21, // Add with Carry. 1971e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block SBC = 6 << 21, // Subtract with Carry. 1981e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block RSC = 7 << 21, // Reverse Subtract with Carry. 1991e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block TST = 8 << 21, // Test. 2001e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block TEQ = 9 << 21, // Test Equivalence. 2011e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block CMP = 10 << 21, // Compare. 2021e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block CMN = 11 << 21, // Compare Negated. 2031e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ORR = 12 << 21, // Logical (inclusive) OR. 2041e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block MOV = 13 << 21, // Move. 2051e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block BIC = 14 << 21, // Bit Clear. 2061e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block MVN = 15 << 21 // Move Not. 207a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block}; 208a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 209a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 2106ded16be15dd865a9b21ea304d5273c8be299c87Steve Block// The bits for bit 7-4 for some type 0 miscellaneous instructions. 2116ded16be15dd865a9b21ea304d5273c8be299c87Steve Blockenum MiscInstructionsBits74 { 2126ded16be15dd865a9b21ea304d5273c8be299c87Steve Block // With bits 22-21 01. 2131e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block BX = 1 << 4, 2141e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block BXJ = 2 << 4, 2151e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block BLX = 3 << 4, 2161e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block BKPT = 7 << 4, 217a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 2186ded16be15dd865a9b21ea304d5273c8be299c87Steve Block // With bits 22-21 11. 2191e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block CLZ = 1 << 4 2201e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block}; 2211e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 2221e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 2231e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Instruction encoding bits and masks. 2241e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum { 2251e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block H = 1 << 5, // Halfword (or byte). 2261e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block S6 = 1 << 6, // Signed (or unsigned). 2271e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block L = 1 << 20, // Load (or store). 2281e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block S = 1 << 20, // Set condition code (or leave unchanged). 2291e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block W = 1 << 21, // Writeback base register (or leave unchanged). 2301e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block A = 1 << 21, // Accumulate in multiply instruction (or not). 2311e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B = 1 << 22, // Unsigned byte (or word). 2321e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block N = 1 << 22, // Long (or short). 2331e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block U = 1 << 23, // Positive (or negative) offset/index. 2341e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing). 2351e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block I = 1 << 25, // Immediate shifter operand (or not). 2361e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 2371e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B4 = 1 << 4, 2381e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B5 = 1 << 5, 2391e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B6 = 1 << 6, 2401e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B7 = 1 << 7, 2411e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B8 = 1 << 8, 2421e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B9 = 1 << 9, 2431e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B12 = 1 << 12, 2441e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B16 = 1 << 16, 2451e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B18 = 1 << 18, 2461e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B19 = 1 << 19, 2471e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B20 = 1 << 20, 2481e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B21 = 1 << 21, 2491e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B22 = 1 << 22, 2501e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B23 = 1 << 23, 2511e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B24 = 1 << 24, 2521e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B25 = 1 << 25, 2531e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B26 = 1 << 26, 2541e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B27 = 1 << 27, 2551e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block B28 = 1 << 28, 2561e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 2571e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Instruction bit masks. 2581e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kCondMask = 15 << 28, 2591e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kALUMask = 0x6f << 21, 2601e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kRdMask = 15 << 12, // In str instruction. 2611e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kCoprocessorMask = 15 << 8, 2621e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kOpCodeMask = 15 << 21, // In data-processing instructions. 2631e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kImm24Mask = (1 << 24) - 1, 2641e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kOff12Mask = (1 << 12) - 1 2651e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block}; 2661e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 2671e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 2681e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// ----------------------------------------------------------------------------- 2691e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Addressing modes and instruction variants. 2701e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 2711e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Condition code updating mode. 2721e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum SBit { 2731e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block SetCC = 1 << 20, // Set condition code. 2741e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block LeaveCC = 0 << 20 // Leave condition code unchanged. 2751e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block}; 2761e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 2771e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 2781e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Status register selection. 2791e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum SRegister { 2801e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block CPSR = 0 << 22, 2811e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block SPSR = 1 << 22 282a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block}; 283a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 284a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 285a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Shifter types for Data-processing operands as defined in section A5.1.2. 2861e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum ShiftOp { 2871e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block LSL = 0 << 5, // Logical shift left. 2881e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block LSR = 1 << 5, // Logical shift right. 2891e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ASR = 2 << 5, // Arithmetic shift right. 2901e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ROR = 3 << 5, // Rotate right. 2911e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 2921e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // RRX is encoded as ROR with shift_imm == 0. 2931e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Use a special code to make the distinction. The RRX ShiftOp is only used 2941e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // as an argument, and will never actually be encoded. The Assembler will 2951e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // detect it and emit the correct ROR shift operand with shift_imm == 0. 2961e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block RRX = -1, 2971e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kNumberOfShifts = 4 2981e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block}; 2991e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3001e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3011e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Status register fields. 3021e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum SRegisterField { 3031e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block CPSR_c = CPSR | 1 << 16, 3041e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block CPSR_x = CPSR | 1 << 17, 3051e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block CPSR_s = CPSR | 1 << 18, 3061e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block CPSR_f = CPSR | 1 << 19, 3071e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block SPSR_c = SPSR | 1 << 16, 3081e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block SPSR_x = SPSR | 1 << 17, 3091e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block SPSR_s = SPSR | 1 << 18, 3101e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block SPSR_f = SPSR | 1 << 19 3111e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block}; 3121e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3131e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Status register field mask (or'ed SRegisterField enum values). 3141e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blocktypedef uint32_t SRegisterFieldMask; 3151e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3161e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3171e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Memory operand addressing mode. 3181e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum AddrMode { 3191e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Bit encoding P U W. 3201e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block Offset = (8|4|0) << 21, // Offset (without writeback to base). 3211e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback. 3221e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback. 3231e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base). 3241e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback. 3251e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback. 3261e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block}; 3271e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3281e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3291e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Load/store multiple addressing mode. 3301e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum BlockAddrMode { 3311e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Bit encoding P U W . 3321e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block da = (0|0|0) << 21, // Decrement after. 3331e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ia = (0|4|0) << 21, // Increment after. 3341e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block db = (8|0|0) << 21, // Decrement before. 3351e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ib = (8|4|0) << 21, // Increment before. 3361e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block da_w = (0|0|1) << 21, // Decrement after with writeback to base. 3371e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ia_w = (0|4|1) << 21, // Increment after with writeback to base. 3381e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block db_w = (8|0|1) << 21, // Decrement before with writeback to base. 3391e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ib_w = (8|4|1) << 21, // Increment before with writeback to base. 3401e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3411e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Alias modes for comparison when writeback does not matter. 3421e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block da_x = (0|0|0) << 21, // Decrement after. 3431e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block ia_x = (0|4|0) << 21, // Increment after. 3441e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block db_x = (8|0|0) << 21, // Decrement before. 3458b112d2025046f85ef7f6be087c6129c872ebad2Ben Murdoch ib_x = (8|4|0) << 21, // Increment before. 3468b112d2025046f85ef7f6be087c6129c872ebad2Ben Murdoch 3478b112d2025046f85ef7f6be087c6129c872ebad2Ben Murdoch kBlockAddrModeMask = (8|4|1) << 21 348a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block}; 349a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 350a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 3511e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Coprocessor load/store operand size. 3521e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum LFlag { 3531e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block Long = 1 << 22, // Long load/store coprocessor. 3541e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block Short = 0 << 22 // Short load/store coprocessor. 3551e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block}; 3561e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3571e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3581e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// ----------------------------------------------------------------------------- 3591e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Supervisor Call (svc) specific support. 3601e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 361a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Special Software Interrupt codes when used in the presence of the ARM 362a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// simulator. 3633e5fa29ddb82551500b118e9bf37af3966277b70Teng-Hui Zhu// svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for 3643e5fa29ddb82551500b118e9bf37af3966277b70Teng-Hui Zhu// standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. 365a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Blockenum SoftwareInterruptCodes { 366a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // transition to C code 3671e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kCallRtRedirected= 0x10, 368a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // break point 3691e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kBreakpoint= 0x20, 3703e5fa29ddb82551500b118e9bf37af3966277b70Teng-Hui Zhu // stop 3711e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kStopCode = 1 << 23 372a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block}; 3733ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kStopCodeMask = kStopCode - 1; 3743ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kMaxStopCode = kStopCode - 1; 3753ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst int32_t kDefaultStopCode = -1; 376a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 377a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 37880d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen// Type of VFP register. Determines register encoding. 37980d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsenenum VFPRegPrecision { 38080d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen kSinglePrecision = 0, 38180d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen kDoublePrecision = 1 38280d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen}; 38380d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen 3841e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 3851e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// VFP FPSCR constants. 3861e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum VFPConversionMode { 3871e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kFPSCRRounding = 0, 3881e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kDefaultRoundToZero = 1 3891e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block}; 3901e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 391e0cee9b3ed82e2391fd85d118aeaa4ea361c687dBen Murdoch// This mask does not include the "inexact" or "input denormal" cumulative 392e0cee9b3ed82e2391fd85d118aeaa4ea361c687dBen Murdoch// exceptions flags, because we usually don't want to check for it. 3933ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPExceptionMask = 0xf; 3943ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPInvalidOpExceptionBit = 1 << 0; 3953ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPOverflowExceptionBit = 1 << 2; 3963ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPUnderflowExceptionBit = 1 << 3; 3973ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPInexactExceptionBit = 1 << 4; 3983ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPFlushToZeroMask = 1 << 24; 3991e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4003ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPNConditionFlagBit = 1 << 31; 4013ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPZConditionFlagBit = 1 << 30; 4023ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPCConditionFlagBit = 1 << 29; 4033ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPVConditionFlagBit = 1 << 28; 4041e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4051e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 40690bac256d9f48d4ee52d0e08bf0e5cad57b3c51cRussell Brenner// VFP rounding modes. See ARM DDI 0406B Page A2-29. 4071e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum VFPRoundingMode { 4081e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block RN = 0 << 22, // Round to Nearest. 4091e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block RP = 1 << 22, // Round towards Plus Infinity. 4101e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block RM = 2 << 22, // Round towards Minus Infinity. 4111e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block RZ = 3 << 22, // Round towards zero. 4121e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4131e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Aliases. 4141e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kRoundToNearest = RN, 4151e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kRoundToPlusInf = RP, 4161e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kRoundToMinusInf = RM, 4171e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block kRoundToZero = RZ 41890bac256d9f48d4ee52d0e08bf0e5cad57b3c51cRussell Brenner}; 41980d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen 4203ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdochconst uint32_t kVFPRoundingModeMask = 3 << 22; 4211e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 422e0cee9b3ed82e2391fd85d118aeaa4ea361c687dBen Murdochenum CheckForInexactConversion { 423e0cee9b3ed82e2391fd85d118aeaa4ea361c687dBen Murdoch kCheckForInexactConversion, 424e0cee9b3ed82e2391fd85d118aeaa4ea361c687dBen Murdoch kDontCheckForInexactConversion 425e0cee9b3ed82e2391fd85d118aeaa4ea361c687dBen Murdoch}; 426e0cee9b3ed82e2391fd85d118aeaa4ea361c687dBen Murdoch 4271e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// ----------------------------------------------------------------------------- 4281e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Hints. 4291e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4301e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Branch hints are not used on the ARM. They are defined so that they can 4311e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// appear in shared function signatures, but will be ignored in ARM 4321e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// implementations. 4331e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockenum Hint { no_hint }; 4341e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4351e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Hints are not used on the arm. Negating is trivial. 4361e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockinline Hint NegateHint(Hint ignored) { return no_hint; } 4371e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4381e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4391e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// ----------------------------------------------------------------------------- 4401e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Specific instructions, constants, and masks. 4411e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// These constants are declared in assembler-arm.cc, as they use named registers 4421e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// and other constants. 4431e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 444a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 4451e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// add(sp, sp, 4) instruction (aka Pop()) 4461e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kPopInstruction; 447a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 4481e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r)) 4491e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// register r is not encoded. 4501e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kPushRegPattern; 4511e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4521e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) 4531e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// register r is not encoded. 4541e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kPopRegPattern; 4551e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4561e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// mov lr, pc 4571e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kMovLrPc; 4581e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// ldr rd, [pc, #offset] 4591e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kLdrPCMask; 4601e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kLdrPCPattern; 4611e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// blxcc rm 4621e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kBlxRegMask; 4631e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4641e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kBlxRegPattern; 4651e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4661e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kMovMvnMask; 4671e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kMovMvnPattern; 4681e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kMovMvnFlip; 4691e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kMovLeaveCCMask; 4701e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kMovLeaveCCPattern; 4711e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kMovwMask; 4721e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kMovwPattern; 4731e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kMovwLeaveCCFlip; 4741e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kCmpCmnMask; 4751e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kCmpCmnPattern; 4761e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kCmpCmnFlip; 4771e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kAddSubFlip; 4781e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kAndBicFlip; 4791e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4801e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// A mask for the Rd register for push, pop, ldr, str instructions. 4811e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kLdrRegFpOffsetPattern; 4821e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4831e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kStrRegFpOffsetPattern; 4841e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4851e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kLdrRegFpNegOffsetPattern; 4861e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4871e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kStrRegFpNegOffsetPattern; 4881e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4891e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kLdrStrInstrTypeMask; 4901e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kLdrStrInstrArgumentMask; 4911e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockextern const Instr kLdrStrOffsetMask; 4921e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4931e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4941e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// ----------------------------------------------------------------------------- 4951e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Instruction abstraction. 4961e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 4971e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// The class Instruction enables access to individual fields defined in the ARM 498a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// architecture instruction set encoding as described in figure A3-1. 4991e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Note that the Assembler uses typedef int32_t Instr. 500a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// 501a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Example: Test whether the instruction at ptr does set the condition code 502a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// bits. 503a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// 504a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// bool InstructionSetsConditionCodes(byte* ptr) { 5051e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// Instruction* instr = Instruction::At(ptr); 5061e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block// int type = instr->TypeValue(); 507a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// return ((type == 0) || (type == 1)) && instr->HasS(); 508a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// } 509a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// 5101e0659c275bb392c045087af4f6b0d7565cb3d77Steve Blockclass Instruction { 511a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block public: 512a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block enum { 513a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block kInstrSize = 4, 514a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block kInstrSizeLog2 = 2, 515a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block kPCReadOffset = 8 516a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block }; 517a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 5181e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Helper macro to define static accessors. 5191e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // We use the cast to char* trick to bypass the strict anti-aliasing rules. 5201e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ 5211e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block static inline return_type Name(Instr instr) { \ 5221e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block char* temp = reinterpret_cast<char*>(&instr); \ 5231e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return reinterpret_cast<Instruction*>(temp)->Name(); \ 5241e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block } 5251e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 5261e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) 5271e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 528a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Get the raw instruction bits. 5291e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline Instr InstructionBits() const { 5301e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return *reinterpret_cast<const Instr*>(this); 531a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block } 532a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 533a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Set the raw instruction bits to value. 5341e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline void SetInstructionBits(Instr value) { 5351e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block *reinterpret_cast<Instr*>(this) = value; 536a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block } 537a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 538a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Read one particular bit out of the instruction bits. 539a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block inline int Bit(int nr) const { 540a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block return (InstructionBits() >> nr) & 1; 541a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block } 542a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 5431e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Read a bit field's value out of the instruction bits. 544a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block inline int Bits(int hi, int lo) const { 545a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); 546a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block } 547a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 5481e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Read a bit field out of the instruction bits. 5491e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int BitField(int hi, int lo) const { 5501e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); 5511e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block } 5521e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 5531e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Static support. 5541e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 5551e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Read one particular bit out of the instruction bits. 5561e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block static inline int Bit(Instr instr, int nr) { 5571e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return (instr >> nr) & 1; 5581e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block } 5591e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 5601e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Read the value of a bit field out of the instruction bits. 5611e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block static inline int Bits(Instr instr, int hi, int lo) { 5621e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return (instr >> lo) & ((2 << (hi - lo)) - 1); 5631e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block } 5641e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 5651e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 5661e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Read a bit field out of the instruction bits. 5671e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block static inline int BitField(Instr instr, int hi, int lo) { 5681e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return instr & (((2 << (hi - lo)) - 1) << lo); 5691e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block } 5701e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 571a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 572a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Accessors for the different named fields used in the ARM encoding. 573a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // The naming of these accessor corresponds to figure A3-1. 5741e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // 5751e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Two kind of accessors are declared: 5763ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdoch // - <Name>Field() will return the raw field, i.e. the field's bits at their 5771e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // original place in the instruction encoding. 5783ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdoch // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as 5793ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdoch // 0xC0810002 ConditionField(instr) will return 0xC0000000. 5801e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // - <Name>Value() will return the field value, shifted back to bit 0. 5813ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdoch // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as 5823ef787dbeca8a5fb1086949cda830dccee07bfbdBen Murdoch // 0xC0810002 ConditionField(instr) will return 0xC. 5831e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 5841e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 585a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Generally applicable fields 5861e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline Condition ConditionValue() const { 587a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block return static_cast<Condition>(Bits(31, 28)); 588a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block } 5891e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline Condition ConditionField() const { 5901e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return static_cast<Condition>(BitField(31, 28)); 5911e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block } 5921e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue); 5931e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); 5941e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 5951e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int TypeValue() const { return Bits(27, 25); } 596a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 5971e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int RnValue() const { return Bits(19, 16); } 5981e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block DECLARE_STATIC_ACCESSOR(RnValue); 5991e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int RdValue() const { return Bits(15, 12); } 6001e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block DECLARE_STATIC_ACCESSOR(RdValue); 601a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 6021e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int CoprocessorValue() const { return Bits(11, 8); } 603d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block // Support for VFP. 604d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block // Vn(19-16) | Vd(15-12) | Vm(3-0) 6051e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VnValue() const { return Bits(19, 16); } 6061e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VmValue() const { return Bits(3, 0); } 6071e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VdValue() const { return Bits(15, 12); } 6081e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int NValue() const { return Bit(7); } 6091e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int MValue() const { return Bit(5); } 6101e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int DValue() const { return Bit(22); } 6111e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int RtValue() const { return Bits(15, 12); } 6121e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int PValue() const { return Bit(24); } 6131e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int UValue() const { return Bit(23); } 6141e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); } 6151e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int Opc2Value() const { return Bits(19, 16); } 6161e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int Opc3Value() const { return Bits(7, 6); } 6171e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int SzValue() const { return Bit(8); } 6181e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VLValue() const { return Bit(20); } 6191e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VCValue() const { return Bit(8); } 6201e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VAValue() const { return Bits(23, 21); } 6211e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VBValue() const { return Bits(6, 5); } 6221e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VFPNRegValue(VFPRegPrecision pre) { 6231e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return VFPGlueRegValue(pre, 16, 7); 62480d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen } 6251e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VFPMRegValue(VFPRegPrecision pre) { 6261e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return VFPGlueRegValue(pre, 0, 5); 62780d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen } 6281e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VFPDRegValue(VFPRegPrecision pre) { 6291e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return VFPGlueRegValue(pre, 12, 22); 63080d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen } 631d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block 632a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Fields used in Data processing instructions 6331e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int OpcodeValue() const { 634a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block return static_cast<Opcode>(Bits(24, 21)); 635a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block } 6361e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline Opcode OpcodeField() const { 6371e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return static_cast<Opcode>(BitField(24, 21)); 6381e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block } 6391e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int SValue() const { return Bit(20); } 640a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // with register 6411e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int RmValue() const { return Bits(3, 0); } 6421e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block DECLARE_STATIC_ACCESSOR(RmValue); 6431e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } 6441e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline ShiftOp ShiftField() const { 6451e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return static_cast<ShiftOp>(BitField(6, 5)); 6461e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block } 6471e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int RegShiftValue() const { return Bit(4); } 6481e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int RsValue() const { return Bits(11, 8); } 6491e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int ShiftAmountValue() const { return Bits(11, 7); } 650a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // with immediate 6511e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int RotateValue() const { return Bits(11, 8); } 6521e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int Immed8Value() const { return Bits(7, 0); } 6531e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int Immed4Value() const { return Bits(19, 16); } 6541e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int ImmedMovwMovtValue() const { 6551e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return Immed4Value() << 12 | Offset12Value(); } 656a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 657a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Fields used in Load/Store instructions 6581e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int PUValue() const { return Bits(24, 23); } 6591e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int PUField() const { return BitField(24, 23); } 6601e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int BValue() const { return Bit(22); } 6611e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int WValue() const { return Bit(21); } 6621e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int LValue() const { return Bit(20); } 663a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // with register uses same fields as Data processing instructions above 664a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // with immediate 6651e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int Offset12Value() const { return Bits(11, 0); } 666a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // multiple 6671e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int RlistValue() const { return Bits(15, 0); } 668a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // extra loads and stores 6691e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int SignValue() const { return Bit(6); } 6701e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int HValue() const { return Bit(5); } 6711e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int ImmedHValue() const { return Bits(11, 8); } 6721e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int ImmedLValue() const { return Bits(3, 0); } 673a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 674a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Fields used in Branch instructions 6751e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int LinkValue() const { return Bit(24); } 6761e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); } 677a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 678a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Fields used in Software interrupt instructions 6791e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline SoftwareInterruptCodes SvcValue() const { 680a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); 681a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block } 682a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 683a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Test for special encodings of type 0 instructions (extra loads and stores, 684a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // as well as multiplications). 685a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } 686a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 6876ded16be15dd865a9b21ea304d5273c8be299c87Steve Block // Test for miscellaneous instructions encodings of type 0 instructions. 6886ded16be15dd865a9b21ea304d5273c8be299c87Steve Block inline bool IsMiscType0() const { return (Bit(24) == 1) 6896ded16be15dd865a9b21ea304d5273c8be299c87Steve Block && (Bit(23) == 0) 6906ded16be15dd865a9b21ea304d5273c8be299c87Steve Block && (Bit(20) == 0) 6916ded16be15dd865a9b21ea304d5273c8be299c87Steve Block && ((Bit(7) == 0)); } 6926ded16be15dd865a9b21ea304d5273c8be299c87Steve Block 6931e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Test for a stop instruction. 6941e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline bool IsStop() const { 6951e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode); 6961e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block } 6971e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 698a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Special accessors that test for existence of a value. 6991e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline bool HasS() const { return SValue() == 1; } 7001e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline bool HasB() const { return BValue() == 1; } 7011e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline bool HasW() const { return WValue() == 1; } 7021e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline bool HasL() const { return LValue() == 1; } 7031e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline bool HasU() const { return UValue() == 1; } 7041e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline bool HasSign() const { return SignValue() == 1; } 7051e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline bool HasH() const { return HValue() == 1; } 7061e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline bool HasLink() const { return LinkValue() == 1; } 707a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 7083bec4d28b1f388dbc06a9c4276e1a03e86c52b04Ben Murdoch // Decoding the double immediate in the vmov instruction. 7093bec4d28b1f388dbc06a9c4276e1a03e86c52b04Ben Murdoch double DoubleImmedVmov() const; 7103bec4d28b1f388dbc06a9c4276e1a03e86c52b04Ben Murdoch 711a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Instructions are read of out a code stream. The only way to get a 712a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // reference to an instruction is to convert a pointer. There is no way 7131e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // to allocate or create instances of class Instruction. 7141e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // Use the At(pc) function to create references to Instruction. 7151e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block static Instruction* At(byte* pc) { 7161e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block return reinterpret_cast<Instruction*>(pc); 7171e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block } 7181e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block 719a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 720a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block private: 72180d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen // Join split register codes, depending on single or double precision. 72280d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen // four_bit is the position of the least-significant bit of the four 72380d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen // bit specifier. one_bit is the position of the additional single bit 72480d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen // specifier. 7251e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) { 72680d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen if (pre == kSinglePrecision) { 72780d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit); 72880d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen } 72980d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit); 73080d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen } 73180d68eab642096c1a48b6474d6ec33064b0ad1f5Kristian Monsen 7321e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block // We need to prevent the creation of instances of class Instruction. 7331e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 734a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block}; 735a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 736a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 737a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block// Helper functions for converting between register numbers and names. 738a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Blockclass Registers { 739a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block public: 740a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Return the name of the register. 741a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block static const char* Name(int reg); 742a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 743a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block // Lookup the register number for the name provided. 744a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block static int Number(const char* name); 745a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 746a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block struct RegisterAlias { 747a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block int reg; 748d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block const char* name; 749a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block }; 750a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 751a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block private: 752a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block static const char* names_[kNumRegisters]; 753a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block static const RegisterAlias aliases_[]; 754a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block}; 755a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 756d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block// Helper functions for converting between VFP register numbers and names. 757d0582a6c46733687d045e4188a1bcd0123c758a1Steve Blockclass VFPRegisters { 758d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block public: 759d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block // Return the name of the register. 7606ded16be15dd865a9b21ea304d5273c8be299c87Steve Block static const char* Name(int reg, bool is_double); 7616ded16be15dd865a9b21ea304d5273c8be299c87Steve Block 7626ded16be15dd865a9b21ea304d5273c8be299c87Steve Block // Lookup the register number for the name provided. 7636ded16be15dd865a9b21ea304d5273c8be299c87Steve Block // Set flag pointed by is_double to true if register 7646ded16be15dd865a9b21ea304d5273c8be299c87Steve Block // is double-precision. 7656ded16be15dd865a9b21ea304d5273c8be299c87Steve Block static int Number(const char* name, bool* is_double); 766d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block 767d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block private: 768d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block static const char* names_[kNumVFPRegisters]; 769d0582a6c46733687d045e4188a1bcd0123c758a1Steve Block}; 770a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 771a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 7721e0659c275bb392c045087af4f6b0d7565cb3d77Steve Block} } // namespace v8::internal 773a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block 774a7e24c173cf37484693b9abb38e494fa7bd7baebSteve Block#endif // V8_ARM_CONSTANTS_ARM_H_ 775