simulator-arm.cc revision 7f4d5bd8c03935e2c0cd412e561b8fc5a6a880ae
1// Copyright 2010 the V8 project authors. All rights reserved. 2// Redistribution and use in source and binary forms, with or without 3// modification, are permitted provided that the following conditions are 4// met: 5// 6// * Redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer. 8// * Redistributions in binary form must reproduce the above 9// copyright notice, this list of conditions and the following 10// disclaimer in the documentation and/or other materials provided 11// with the distribution. 12// * Neither the name of Google Inc. nor the names of its 13// contributors may be used to endorse or promote products derived 14// from this software without specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 28#include <stdlib.h> 29#include <cstdarg> 30#include "v8.h" 31 32#if defined(V8_TARGET_ARCH_ARM) 33 34#include "disasm.h" 35#include "assembler.h" 36#include "arm/constants-arm.h" 37#include "arm/simulator-arm.h" 38 39#if !defined(__arm__) 40 41// Only build the simulator if not compiling for real ARM hardware. 42namespace assembler { 43namespace arm { 44 45using ::v8::internal::Object; 46using ::v8::internal::PrintF; 47using ::v8::internal::OS; 48using ::v8::internal::ReadLine; 49using ::v8::internal::DeleteArray; 50 51// This macro provides a platform independent use of sscanf. The reason for 52// SScanF not being implemented in a platform independent way through 53// ::v8::internal::OS in the same way as SNPrintF is that the 54// Windows C Run-Time Library does not provide vsscanf. 55#define SScanF sscanf // NOLINT 56 57// The Debugger class is used by the simulator while debugging simulated ARM 58// code. 59class Debugger { 60 public: 61 explicit Debugger(Simulator* sim); 62 ~Debugger(); 63 64 void Stop(Instr* instr); 65 void Debug(); 66 67 private: 68 static const instr_t kBreakpointInstr = 69 ((AL << 28) | (7 << 25) | (1 << 24) | break_point); 70 static const instr_t kNopInstr = 71 ((AL << 28) | (13 << 21)); 72 73 Simulator* sim_; 74 75 int32_t GetRegisterValue(int regnum); 76 bool GetValue(const char* desc, int32_t* value); 77 bool GetVFPSingleValue(const char* desc, float* value); 78 bool GetVFPDoubleValue(const char* desc, double* value); 79 80 // Set or delete a breakpoint. Returns true if successful. 81 bool SetBreakpoint(Instr* breakpc); 82 bool DeleteBreakpoint(Instr* breakpc); 83 84 // Undo and redo all breakpoints. This is needed to bracket disassembly and 85 // execution to skip past breakpoints when run from the debugger. 86 void UndoBreakpoints(); 87 void RedoBreakpoints(); 88}; 89 90 91Debugger::Debugger(Simulator* sim) { 92 sim_ = sim; 93} 94 95 96Debugger::~Debugger() { 97} 98 99 100 101#ifdef GENERATED_CODE_COVERAGE 102static FILE* coverage_log = NULL; 103 104 105static void InitializeCoverage() { 106 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG"); 107 if (file_name != NULL) { 108 coverage_log = fopen(file_name, "aw+"); 109 } 110} 111 112 113void Debugger::Stop(Instr* instr) { 114 char* str = reinterpret_cast<char*>(instr->InstructionBits() & 0x0fffffff); 115 if (strlen(str) > 0) { 116 if (coverage_log != NULL) { 117 fprintf(coverage_log, "%s\n", str); 118 fflush(coverage_log); 119 } 120 instr->SetInstructionBits(0xe1a00000); // Overwrite with nop. 121 } 122 sim_->set_pc(sim_->get_pc() + Instr::kInstrSize); 123} 124 125#else // ndef GENERATED_CODE_COVERAGE 126 127static void InitializeCoverage() { 128} 129 130 131void Debugger::Stop(Instr* instr) { 132 const char* str = (const char*)(instr->InstructionBits() & 0x0fffffff); 133 PrintF("Simulator hit %s\n", str); 134 sim_->set_pc(sim_->get_pc() + Instr::kInstrSize); 135 Debug(); 136} 137#endif 138 139 140int32_t Debugger::GetRegisterValue(int regnum) { 141 if (regnum == kPCRegister) { 142 return sim_->get_pc(); 143 } else { 144 return sim_->get_register(regnum); 145 } 146} 147 148 149bool Debugger::GetValue(const char* desc, int32_t* value) { 150 int regnum = Registers::Number(desc); 151 if (regnum != kNoRegister) { 152 *value = GetRegisterValue(regnum); 153 return true; 154 } else { 155 if (strncmp(desc, "0x", 2) == 0) { 156 return SScanF(desc + 2, "%x", reinterpret_cast<uint32_t*>(value)) == 1; 157 } else { 158 return SScanF(desc, "%u", reinterpret_cast<uint32_t*>(value)) == 1; 159 } 160 } 161 return false; 162} 163 164 165bool Debugger::GetVFPSingleValue(const char* desc, float* value) { 166 bool is_double; 167 int regnum = VFPRegisters::Number(desc, &is_double); 168 if (regnum != kNoRegister && !is_double) { 169 *value = sim_->get_float_from_s_register(regnum); 170 return true; 171 } 172 return false; 173} 174 175 176bool Debugger::GetVFPDoubleValue(const char* desc, double* value) { 177 bool is_double; 178 int regnum = VFPRegisters::Number(desc, &is_double); 179 if (regnum != kNoRegister && is_double) { 180 *value = sim_->get_double_from_d_register(regnum); 181 return true; 182 } 183 return false; 184} 185 186 187bool Debugger::SetBreakpoint(Instr* breakpc) { 188 // Check if a breakpoint can be set. If not return without any side-effects. 189 if (sim_->break_pc_ != NULL) { 190 return false; 191 } 192 193 // Set the breakpoint. 194 sim_->break_pc_ = breakpc; 195 sim_->break_instr_ = breakpc->InstructionBits(); 196 // Not setting the breakpoint instruction in the code itself. It will be set 197 // when the debugger shell continues. 198 return true; 199} 200 201 202bool Debugger::DeleteBreakpoint(Instr* breakpc) { 203 if (sim_->break_pc_ != NULL) { 204 sim_->break_pc_->SetInstructionBits(sim_->break_instr_); 205 } 206 207 sim_->break_pc_ = NULL; 208 sim_->break_instr_ = 0; 209 return true; 210} 211 212 213void Debugger::UndoBreakpoints() { 214 if (sim_->break_pc_ != NULL) { 215 sim_->break_pc_->SetInstructionBits(sim_->break_instr_); 216 } 217} 218 219 220void Debugger::RedoBreakpoints() { 221 if (sim_->break_pc_ != NULL) { 222 sim_->break_pc_->SetInstructionBits(kBreakpointInstr); 223 } 224} 225 226 227void Debugger::Debug() { 228 intptr_t last_pc = -1; 229 bool done = false; 230 231#define COMMAND_SIZE 63 232#define ARG_SIZE 255 233 234#define STR(a) #a 235#define XSTR(a) STR(a) 236 237 char cmd[COMMAND_SIZE + 1]; 238 char arg1[ARG_SIZE + 1]; 239 char arg2[ARG_SIZE + 1]; 240 char* argv[3] = { cmd, arg1, arg2 }; 241 242 // make sure to have a proper terminating character if reaching the limit 243 cmd[COMMAND_SIZE] = 0; 244 arg1[ARG_SIZE] = 0; 245 arg2[ARG_SIZE] = 0; 246 247 // Undo all set breakpoints while running in the debugger shell. This will 248 // make them invisible to all commands. 249 UndoBreakpoints(); 250 251 while (!done) { 252 if (last_pc != sim_->get_pc()) { 253 disasm::NameConverter converter; 254 disasm::Disassembler dasm(converter); 255 // use a reasonably large buffer 256 v8::internal::EmbeddedVector<char, 256> buffer; 257 dasm.InstructionDecode(buffer, 258 reinterpret_cast<byte*>(sim_->get_pc())); 259 PrintF(" 0x%08x %s\n", sim_->get_pc(), buffer.start()); 260 last_pc = sim_->get_pc(); 261 } 262 char* line = ReadLine("sim> "); 263 if (line == NULL) { 264 break; 265 } else { 266 // Use sscanf to parse the individual parts of the command line. At the 267 // moment no command expects more than two parameters. 268 int argc = SScanF(line, 269 "%" XSTR(COMMAND_SIZE) "s " 270 "%" XSTR(ARG_SIZE) "s " 271 "%" XSTR(ARG_SIZE) "s", 272 cmd, arg1, arg2); 273 if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) { 274 sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc())); 275 } else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) { 276 // Execute the one instruction we broke at with breakpoints disabled. 277 sim_->InstructionDecode(reinterpret_cast<Instr*>(sim_->get_pc())); 278 // Leave the debugger shell. 279 done = true; 280 } else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) { 281 if (argc == 2) { 282 int32_t value; 283 float svalue; 284 double dvalue; 285 if (strcmp(arg1, "all") == 0) { 286 for (int i = 0; i < kNumRegisters; i++) { 287 value = GetRegisterValue(i); 288 PrintF("%3s: 0x%08x %10d\n", Registers::Name(i), value, value); 289 } 290 } else { 291 if (GetValue(arg1, &value)) { 292 PrintF("%s: 0x%08x %d \n", arg1, value, value); 293 } else if (GetVFPSingleValue(arg1, &svalue)) { 294 PrintF("%s: %f \n", arg1, svalue); 295 } else if (GetVFPDoubleValue(arg1, &dvalue)) { 296 PrintF("%s: %lf \n", arg1, dvalue); 297 } else { 298 PrintF("%s unrecognized\n", arg1); 299 } 300 } 301 } else { 302 PrintF("print <register>\n"); 303 } 304 } else if ((strcmp(cmd, "po") == 0) 305 || (strcmp(cmd, "printobject") == 0)) { 306 if (argc == 2) { 307 int32_t value; 308 if (GetValue(arg1, &value)) { 309 Object* obj = reinterpret_cast<Object*>(value); 310 PrintF("%s: \n", arg1); 311#ifdef DEBUG 312 obj->PrintLn(); 313#else 314 obj->ShortPrint(); 315 PrintF("\n"); 316#endif 317 } else { 318 PrintF("%s unrecognized\n", arg1); 319 } 320 } else { 321 PrintF("printobject <value>\n"); 322 } 323 } else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) { 324 int32_t* cur = NULL; 325 int32_t* end = NULL; 326 int next_arg = 1; 327 328 if (strcmp(cmd, "stack") == 0) { 329 cur = reinterpret_cast<int32_t*>(sim_->get_register(Simulator::sp)); 330 } else { // "mem" 331 int32_t value; 332 if (!GetValue(arg1, &value)) { 333 PrintF("%s unrecognized\n", arg1); 334 continue; 335 } 336 cur = reinterpret_cast<int32_t*>(value); 337 next_arg++; 338 } 339 340 int32_t words; 341 if (argc == next_arg) { 342 words = 10; 343 } else if (argc == next_arg + 1) { 344 if (!GetValue(argv[next_arg], &words)) { 345 words = 10; 346 } 347 } 348 end = cur + words; 349 350 while (cur < end) { 351 PrintF(" 0x%08x: 0x%08x %10d\n", cur, *cur, *cur); 352 cur++; 353 } 354 } else if (strcmp(cmd, "disasm") == 0) { 355 disasm::NameConverter converter; 356 disasm::Disassembler dasm(converter); 357 // use a reasonably large buffer 358 v8::internal::EmbeddedVector<char, 256> buffer; 359 360 byte* cur = NULL; 361 byte* end = NULL; 362 363 if (argc == 1) { 364 cur = reinterpret_cast<byte*>(sim_->get_pc()); 365 end = cur + (10 * Instr::kInstrSize); 366 } else if (argc == 2) { 367 int32_t value; 368 if (GetValue(arg1, &value)) { 369 cur = reinterpret_cast<byte*>(value); 370 // no length parameter passed, assume 10 instructions 371 end = cur + (10 * Instr::kInstrSize); 372 } 373 } else { 374 int32_t value1; 375 int32_t value2; 376 if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) { 377 cur = reinterpret_cast<byte*>(value1); 378 end = cur + (value2 * Instr::kInstrSize); 379 } 380 } 381 382 while (cur < end) { 383 dasm.InstructionDecode(buffer, cur); 384 PrintF(" 0x%08x %s\n", cur, buffer.start()); 385 cur += Instr::kInstrSize; 386 } 387 } else if (strcmp(cmd, "gdb") == 0) { 388 PrintF("relinquishing control to gdb\n"); 389 v8::internal::OS::DebugBreak(); 390 PrintF("regaining control from gdb\n"); 391 } else if (strcmp(cmd, "break") == 0) { 392 if (argc == 2) { 393 int32_t value; 394 if (GetValue(arg1, &value)) { 395 if (!SetBreakpoint(reinterpret_cast<Instr*>(value))) { 396 PrintF("setting breakpoint failed\n"); 397 } 398 } else { 399 PrintF("%s unrecognized\n", arg1); 400 } 401 } else { 402 PrintF("break <address>\n"); 403 } 404 } else if (strcmp(cmd, "del") == 0) { 405 if (!DeleteBreakpoint(NULL)) { 406 PrintF("deleting breakpoint failed\n"); 407 } 408 } else if (strcmp(cmd, "flags") == 0) { 409 PrintF("N flag: %d; ", sim_->n_flag_); 410 PrintF("Z flag: %d; ", sim_->z_flag_); 411 PrintF("C flag: %d; ", sim_->c_flag_); 412 PrintF("V flag: %d\n", sim_->v_flag_); 413 PrintF("INVALID OP flag: %d; ", sim_->inv_op_vfp_flag_); 414 PrintF("DIV BY ZERO flag: %d; ", sim_->div_zero_vfp_flag_); 415 PrintF("OVERFLOW flag: %d; ", sim_->overflow_vfp_flag_); 416 PrintF("UNDERFLOW flag: %d; ", sim_->underflow_vfp_flag_); 417 PrintF("INEXACT flag: %d; ", sim_->inexact_vfp_flag_); 418 } else if (strcmp(cmd, "unstop") == 0) { 419 intptr_t stop_pc = sim_->get_pc() - Instr::kInstrSize; 420 Instr* stop_instr = reinterpret_cast<Instr*>(stop_pc); 421 if (stop_instr->ConditionField() == special_condition) { 422 stop_instr->SetInstructionBits(kNopInstr); 423 } else { 424 PrintF("Not at debugger stop."); 425 } 426 } else if ((strcmp(cmd, "t") == 0) || strcmp(cmd, "trace") == 0) { 427 ::v8::internal::FLAG_trace_sim = !::v8::internal::FLAG_trace_sim; 428 PrintF("Trace of executed instructions is %s\n", 429 ::v8::internal::FLAG_trace_sim ? "on" : "off"); 430 } else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) { 431 PrintF("cont\n"); 432 PrintF(" continue execution (alias 'c')\n"); 433 PrintF("stepi\n"); 434 PrintF(" step one instruction (alias 'si')\n"); 435 PrintF("print <register>\n"); 436 PrintF(" print register content (alias 'p')\n"); 437 PrintF(" use register name 'all' to print all registers\n"); 438 PrintF("printobject <register>\n"); 439 PrintF(" print an object from a register (alias 'po')\n"); 440 PrintF("flags\n"); 441 PrintF(" print flags\n"); 442 PrintF("stack [<words>]\n"); 443 PrintF(" dump stack content, default dump 10 words)\n"); 444 PrintF("mem <address> [<words>]\n"); 445 PrintF(" dump memory content, default dump 10 words)\n"); 446 PrintF("disasm [<instructions>]\n"); 447 PrintF("disasm [[<address>] <instructions>]\n"); 448 PrintF(" disassemble code, default is 10 instructions from pc\n"); 449 PrintF("gdb\n"); 450 PrintF(" enter gdb\n"); 451 PrintF("break <address>\n"); 452 PrintF(" set a break point on the address\n"); 453 PrintF("del\n"); 454 PrintF(" delete the breakpoint\n"); 455 PrintF("unstop\n"); 456 PrintF(" ignore the stop instruction at the current location"); 457 PrintF(" from now on\n"); 458 PrintF("trace (alias 't')\n"); 459 PrintF(" toogle the tracing of all executed statements\n"); 460 } else { 461 PrintF("Unknown command: %s\n", cmd); 462 } 463 } 464 DeleteArray(line); 465 } 466 467 // Add all the breakpoints back to stop execution and enter the debugger 468 // shell when hit. 469 RedoBreakpoints(); 470 471#undef COMMAND_SIZE 472#undef ARG_SIZE 473 474#undef STR 475#undef XSTR 476} 477 478 479static bool ICacheMatch(void* one, void* two) { 480 ASSERT((reinterpret_cast<intptr_t>(one) & CachePage::kPageMask) == 0); 481 ASSERT((reinterpret_cast<intptr_t>(two) & CachePage::kPageMask) == 0); 482 return one == two; 483} 484 485 486static uint32_t ICacheHash(void* key) { 487 return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2; 488} 489 490 491static bool AllOnOnePage(uintptr_t start, int size) { 492 intptr_t start_page = (start & ~CachePage::kPageMask); 493 intptr_t end_page = ((start + size) & ~CachePage::kPageMask); 494 return start_page == end_page; 495} 496 497 498void Simulator::FlushICache(void* start_addr, size_t size) { 499 intptr_t start = reinterpret_cast<intptr_t>(start_addr); 500 int intra_line = (start & CachePage::kLineMask); 501 start -= intra_line; 502 size += intra_line; 503 size = ((size - 1) | CachePage::kLineMask) + 1; 504 int offset = (start & CachePage::kPageMask); 505 while (!AllOnOnePage(start, size - 1)) { 506 int bytes_to_flush = CachePage::kPageSize - offset; 507 FlushOnePage(start, bytes_to_flush); 508 start += bytes_to_flush; 509 size -= bytes_to_flush; 510 ASSERT_EQ(0, start & CachePage::kPageMask); 511 offset = 0; 512 } 513 if (size != 0) { 514 FlushOnePage(start, size); 515 } 516} 517 518 519CachePage* Simulator::GetCachePage(void* page) { 520 v8::internal::HashMap::Entry* entry = i_cache_->Lookup(page, 521 ICacheHash(page), 522 true); 523 if (entry->value == NULL) { 524 CachePage* new_page = new CachePage(); 525 entry->value = new_page; 526 } 527 return reinterpret_cast<CachePage*>(entry->value); 528} 529 530 531// Flush from start up to and not including start + size. 532void Simulator::FlushOnePage(intptr_t start, int size) { 533 ASSERT(size <= CachePage::kPageSize); 534 ASSERT(AllOnOnePage(start, size - 1)); 535 ASSERT((start & CachePage::kLineMask) == 0); 536 ASSERT((size & CachePage::kLineMask) == 0); 537 void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask)); 538 int offset = (start & CachePage::kPageMask); 539 CachePage* cache_page = GetCachePage(page); 540 char* valid_bytemap = cache_page->ValidityByte(offset); 541 memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift); 542} 543 544 545void Simulator::CheckICache(Instr* instr) { 546 intptr_t address = reinterpret_cast<intptr_t>(instr); 547 void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask)); 548 void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask)); 549 int offset = (address & CachePage::kPageMask); 550 CachePage* cache_page = GetCachePage(page); 551 char* cache_valid_byte = cache_page->ValidityByte(offset); 552 bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID); 553 char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask); 554 if (cache_hit) { 555 // Check that the data in memory matches the contents of the I-cache. 556 CHECK(memcmp(reinterpret_cast<void*>(instr), 557 cache_page->CachedData(offset), 558 Instr::kInstrSize) == 0); 559 } else { 560 // Cache miss. Load memory into the cache. 561 memcpy(cached_line, line, CachePage::kLineLength); 562 *cache_valid_byte = CachePage::LINE_VALID; 563 } 564} 565 566 567// Create one simulator per thread and keep it in thread local storage. 568static v8::internal::Thread::LocalStorageKey simulator_key; 569 570 571bool Simulator::initialized_ = false; 572 573 574void Simulator::Initialize() { 575 if (initialized_) return; 576 simulator_key = v8::internal::Thread::CreateThreadLocalKey(); 577 initialized_ = true; 578 ::v8::internal::ExternalReference::set_redirector(&RedirectExternalReference); 579} 580 581 582v8::internal::HashMap* Simulator::i_cache_ = NULL; 583 584 585Simulator::Simulator() { 586 if (i_cache_ == NULL) { 587 i_cache_ = new v8::internal::HashMap(&ICacheMatch); 588 } 589 Initialize(); 590 // Setup simulator support first. Some of this information is needed to 591 // setup the architecture state. 592 size_t stack_size = 1 * 1024*1024; // allocate 1MB for stack 593 stack_ = reinterpret_cast<char*>(malloc(stack_size)); 594 pc_modified_ = false; 595 icount_ = 0; 596 break_pc_ = NULL; 597 break_instr_ = 0; 598 599 // Setup architecture state. 600 // All registers are initialized to zero to start with. 601 for (int i = 0; i < num_registers; i++) { 602 registers_[i] = 0; 603 } 604 n_flag_ = false; 605 z_flag_ = false; 606 c_flag_ = false; 607 v_flag_ = false; 608 609 // Initializing VFP registers. 610 // All registers are initialized to zero to start with 611 // even though s_registers_ & d_registers_ share the same 612 // physical registers in the target. 613 for (int i = 0; i < num_s_registers; i++) { 614 vfp_register[i] = 0; 615 } 616 n_flag_FPSCR_ = false; 617 z_flag_FPSCR_ = false; 618 c_flag_FPSCR_ = false; 619 v_flag_FPSCR_ = false; 620 621 inv_op_vfp_flag_ = false; 622 div_zero_vfp_flag_ = false; 623 overflow_vfp_flag_ = false; 624 underflow_vfp_flag_ = false; 625 inexact_vfp_flag_ = false; 626 627 // The sp is initialized to point to the bottom (high address) of the 628 // allocated stack area. To be safe in potential stack underflows we leave 629 // some buffer below. 630 registers_[sp] = reinterpret_cast<int32_t>(stack_) + stack_size - 64; 631 // The lr and pc are initialized to a known bad value that will cause an 632 // access violation if the simulator ever tries to execute it. 633 registers_[pc] = bad_lr; 634 registers_[lr] = bad_lr; 635 InitializeCoverage(); 636} 637 638 639// When the generated code calls an external reference we need to catch that in 640// the simulator. The external reference will be a function compiled for the 641// host architecture. We need to call that function instead of trying to 642// execute it with the simulator. We do that by redirecting the external 643// reference to a swi (software-interrupt) instruction that is handled by 644// the simulator. We write the original destination of the jump just at a known 645// offset from the swi instruction so the simulator knows what to call. 646class Redirection { 647 public: 648 Redirection(void* external_function, bool fp_return) 649 : external_function_(external_function), 650 swi_instruction_((AL << 28) | (0xf << 24) | call_rt_redirected), 651 fp_return_(fp_return), 652 next_(list_) { 653 Simulator::current()-> 654 FlushICache(reinterpret_cast<void*>(&swi_instruction_), 655 Instr::kInstrSize); 656 list_ = this; 657 } 658 659 void* address_of_swi_instruction() { 660 return reinterpret_cast<void*>(&swi_instruction_); 661 } 662 663 void* external_function() { return external_function_; } 664 bool fp_return() { return fp_return_; } 665 666 static Redirection* Get(void* external_function, bool fp_return) { 667 Redirection* current; 668 for (current = list_; current != NULL; current = current->next_) { 669 if (current->external_function_ == external_function) return current; 670 } 671 return new Redirection(external_function, fp_return); 672 } 673 674 static Redirection* FromSwiInstruction(Instr* swi_instruction) { 675 char* addr_of_swi = reinterpret_cast<char*>(swi_instruction); 676 char* addr_of_redirection = 677 addr_of_swi - OFFSET_OF(Redirection, swi_instruction_); 678 return reinterpret_cast<Redirection*>(addr_of_redirection); 679 } 680 681 private: 682 void* external_function_; 683 uint32_t swi_instruction_; 684 bool fp_return_; 685 Redirection* next_; 686 static Redirection* list_; 687}; 688 689 690Redirection* Redirection::list_ = NULL; 691 692 693void* Simulator::RedirectExternalReference(void* external_function, 694 bool fp_return) { 695 Redirection* redirection = Redirection::Get(external_function, fp_return); 696 return redirection->address_of_swi_instruction(); 697} 698 699 700// Get the active Simulator for the current thread. 701Simulator* Simulator::current() { 702 Initialize(); 703 Simulator* sim = reinterpret_cast<Simulator*>( 704 v8::internal::Thread::GetThreadLocal(simulator_key)); 705 if (sim == NULL) { 706 // TODO(146): delete the simulator object when a thread goes away. 707 sim = new Simulator(); 708 v8::internal::Thread::SetThreadLocal(simulator_key, sim); 709 } 710 return sim; 711} 712 713 714// Sets the register in the architecture state. It will also deal with updating 715// Simulator internal state for special registers such as PC. 716void Simulator::set_register(int reg, int32_t value) { 717 ASSERT((reg >= 0) && (reg < num_registers)); 718 if (reg == pc) { 719 pc_modified_ = true; 720 } 721 registers_[reg] = value; 722} 723 724 725// Get the register from the architecture state. This function does handle 726// the special case of accessing the PC register. 727int32_t Simulator::get_register(int reg) const { 728 ASSERT((reg >= 0) && (reg < num_registers)); 729 return registers_[reg] + ((reg == pc) ? Instr::kPCReadOffset : 0); 730} 731 732 733void Simulator::set_dw_register(int dreg, const int* dbl) { 734 ASSERT((dreg >= 0) && (dreg < num_d_registers)); 735 registers_[dreg] = dbl[0]; 736 registers_[dreg + 1] = dbl[1]; 737} 738 739 740// Raw access to the PC register. 741void Simulator::set_pc(int32_t value) { 742 pc_modified_ = true; 743 registers_[pc] = value; 744} 745 746 747// Raw access to the PC register without the special adjustment when reading. 748int32_t Simulator::get_pc() const { 749 return registers_[pc]; 750} 751 752 753// Getting from and setting into VFP registers. 754void Simulator::set_s_register(int sreg, unsigned int value) { 755 ASSERT((sreg >= 0) && (sreg < num_s_registers)); 756 vfp_register[sreg] = value; 757} 758 759 760unsigned int Simulator::get_s_register(int sreg) const { 761 ASSERT((sreg >= 0) && (sreg < num_s_registers)); 762 return vfp_register[sreg]; 763} 764 765 766void Simulator::set_s_register_from_float(int sreg, const float flt) { 767 ASSERT((sreg >= 0) && (sreg < num_s_registers)); 768 // Read the bits from the single precision floating point value 769 // into the unsigned integer element of vfp_register[] given by index=sreg. 770 char buffer[sizeof(vfp_register[0])]; 771 memcpy(buffer, &flt, sizeof(vfp_register[0])); 772 memcpy(&vfp_register[sreg], buffer, sizeof(vfp_register[0])); 773} 774 775 776void Simulator::set_s_register_from_sinteger(int sreg, const int sint) { 777 ASSERT((sreg >= 0) && (sreg < num_s_registers)); 778 // Read the bits from the integer value into the unsigned integer element of 779 // vfp_register[] given by index=sreg. 780 char buffer[sizeof(vfp_register[0])]; 781 memcpy(buffer, &sint, sizeof(vfp_register[0])); 782 memcpy(&vfp_register[sreg], buffer, sizeof(vfp_register[0])); 783} 784 785 786void Simulator::set_d_register_from_double(int dreg, const double& dbl) { 787 ASSERT((dreg >= 0) && (dreg < num_d_registers)); 788 // Read the bits from the double precision floating point value into the two 789 // consecutive unsigned integer elements of vfp_register[] given by index 790 // 2*sreg and 2*sreg+1. 791 char buffer[2 * sizeof(vfp_register[0])]; 792 memcpy(buffer, &dbl, 2 * sizeof(vfp_register[0])); 793#ifndef BIG_ENDIAN_FLOATING_POINT 794 memcpy(&vfp_register[dreg * 2], buffer, 2 * sizeof(vfp_register[0])); 795#else 796 memcpy(&vfp_register[dreg * 2], &buffer[4], sizeof(vfp_register[0])); 797 memcpy(&vfp_register[dreg * 2 + 1], &buffer[0], sizeof(vfp_register[0])); 798#endif 799} 800 801 802float Simulator::get_float_from_s_register(int sreg) { 803 ASSERT((sreg >= 0) && (sreg < num_s_registers)); 804 805 float sm_val = 0.0; 806 // Read the bits from the unsigned integer vfp_register[] array 807 // into the single precision floating point value and return it. 808 char buffer[sizeof(vfp_register[0])]; 809 memcpy(buffer, &vfp_register[sreg], sizeof(vfp_register[0])); 810 memcpy(&sm_val, buffer, sizeof(vfp_register[0])); 811 return(sm_val); 812} 813 814 815int Simulator::get_sinteger_from_s_register(int sreg) { 816 ASSERT((sreg >= 0) && (sreg < num_s_registers)); 817 818 int sm_val = 0; 819 // Read the bits from the unsigned integer vfp_register[] array 820 // into the single precision floating point value and return it. 821 char buffer[sizeof(vfp_register[0])]; 822 memcpy(buffer, &vfp_register[sreg], sizeof(vfp_register[0])); 823 memcpy(&sm_val, buffer, sizeof(vfp_register[0])); 824 return(sm_val); 825} 826 827 828double Simulator::get_double_from_d_register(int dreg) { 829 ASSERT((dreg >= 0) && (dreg < num_d_registers)); 830 831 double dm_val = 0.0; 832 // Read the bits from the unsigned integer vfp_register[] array 833 // into the double precision floating point value and return it. 834 char buffer[2 * sizeof(vfp_register[0])]; 835#ifdef BIG_ENDIAN_FLOATING_POINT 836 memcpy(&buffer[0], &vfp_register[2 * dreg + 1], sizeof(vfp_register[0])); 837 memcpy(&buffer[4], &vfp_register[2 * dreg], sizeof(vfp_register[0])); 838#else 839 memcpy(buffer, &vfp_register[2 * dreg], 2 * sizeof(vfp_register[0])); 840#endif 841 memcpy(&dm_val, buffer, 2 * sizeof(vfp_register[0])); 842 return(dm_val); 843} 844 845 846// For use in calls that take two double values, constructed from r0, r1, r2 847// and r3. 848void Simulator::GetFpArgs(double* x, double* y) { 849 // We use a char buffer to get around the strict-aliasing rules which 850 // otherwise allow the compiler to optimize away the copy. 851 char buffer[2 * sizeof(registers_[0])]; 852 // Registers 0 and 1 -> x. 853 memcpy(buffer, registers_, sizeof(buffer)); 854 memcpy(x, buffer, sizeof(buffer)); 855 // Registers 2 and 3 -> y. 856 memcpy(buffer, registers_ + 2, sizeof(buffer)); 857 memcpy(y, buffer, sizeof(buffer)); 858} 859 860 861void Simulator::SetFpResult(const double& result) { 862 char buffer[2 * sizeof(registers_[0])]; 863 memcpy(buffer, &result, sizeof(buffer)); 864 // result -> registers 0 and 1. 865 memcpy(registers_, buffer, sizeof(buffer)); 866} 867 868 869void Simulator::TrashCallerSaveRegisters() { 870 // We don't trash the registers with the return value. 871 registers_[2] = 0x50Bad4U; 872 registers_[3] = 0x50Bad4U; 873 registers_[12] = 0x50Bad4U; 874} 875 876// Some Operating Systems allow unaligned access on ARMv7 targets. We 877// assume that unaligned accesses are not allowed unless the v8 build system 878// defines the CAN_USE_UNALIGNED_ACCESSES macro to be non-zero. 879// The following statements below describes the behavior of the ARM CPUs 880// that don't support unaligned access. 881// Some ARM platforms raise an interrupt on detecting unaligned access. 882// On others it does a funky rotation thing. For now we 883// simply disallow unaligned reads. Note that simulator runs have the runtime 884// system running directly on the host system and only generated code is 885// executed in the simulator. Since the host is typically IA32 we will not 886// get the correct ARM-like behaviour on unaligned accesses for those ARM 887// targets that don't support unaligned loads and stores. 888 889 890int Simulator::ReadW(int32_t addr, Instr* instr) { 891#if V8_TARGET_CAN_READ_UNALIGNED 892 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); 893 return *ptr; 894#else 895 if ((addr & 3) == 0) { 896 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); 897 return *ptr; 898 } 899 PrintF("Unaligned read at 0x%08x, pc=%p\n", addr, instr); 900 UNIMPLEMENTED(); 901 return 0; 902#endif 903} 904 905 906void Simulator::WriteW(int32_t addr, int value, Instr* instr) { 907#if V8_TARGET_CAN_READ_UNALIGNED 908 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); 909 *ptr = value; 910 return; 911#else 912 if ((addr & 3) == 0) { 913 intptr_t* ptr = reinterpret_cast<intptr_t*>(addr); 914 *ptr = value; 915 return; 916 } 917 PrintF("Unaligned write at 0x%08x, pc=%p\n", addr, instr); 918 UNIMPLEMENTED(); 919#endif 920} 921 922 923uint16_t Simulator::ReadHU(int32_t addr, Instr* instr) { 924#if V8_TARGET_CAN_READ_UNALIGNED 925 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); 926 return *ptr; 927#else 928 if ((addr & 1) == 0) { 929 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); 930 return *ptr; 931 } 932 PrintF("Unaligned unsigned halfword read at 0x%08x, pc=%p\n", addr, instr); 933 UNIMPLEMENTED(); 934 return 0; 935#endif 936} 937 938 939int16_t Simulator::ReadH(int32_t addr, Instr* instr) { 940#if V8_TARGET_CAN_READ_UNALIGNED 941 int16_t* ptr = reinterpret_cast<int16_t*>(addr); 942 return *ptr; 943#else 944 if ((addr & 1) == 0) { 945 int16_t* ptr = reinterpret_cast<int16_t*>(addr); 946 return *ptr; 947 } 948 PrintF("Unaligned signed halfword read at 0x%08x\n", addr); 949 UNIMPLEMENTED(); 950 return 0; 951#endif 952} 953 954 955void Simulator::WriteH(int32_t addr, uint16_t value, Instr* instr) { 956#if V8_TARGET_CAN_READ_UNALIGNED 957 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); 958 *ptr = value; 959 return; 960#else 961 if ((addr & 1) == 0) { 962 uint16_t* ptr = reinterpret_cast<uint16_t*>(addr); 963 *ptr = value; 964 return; 965 } 966 PrintF("Unaligned unsigned halfword write at 0x%08x, pc=%p\n", addr, instr); 967 UNIMPLEMENTED(); 968#endif 969} 970 971 972void Simulator::WriteH(int32_t addr, int16_t value, Instr* instr) { 973#if V8_TARGET_CAN_READ_UNALIGNED 974 int16_t* ptr = reinterpret_cast<int16_t*>(addr); 975 *ptr = value; 976 return; 977#else 978 if ((addr & 1) == 0) { 979 int16_t* ptr = reinterpret_cast<int16_t*>(addr); 980 *ptr = value; 981 return; 982 } 983 PrintF("Unaligned halfword write at 0x%08x, pc=%p\n", addr, instr); 984 UNIMPLEMENTED(); 985#endif 986} 987 988 989uint8_t Simulator::ReadBU(int32_t addr) { 990 uint8_t* ptr = reinterpret_cast<uint8_t*>(addr); 991 return *ptr; 992} 993 994 995int8_t Simulator::ReadB(int32_t addr) { 996 int8_t* ptr = reinterpret_cast<int8_t*>(addr); 997 return *ptr; 998} 999 1000 1001void Simulator::WriteB(int32_t addr, uint8_t value) { 1002 uint8_t* ptr = reinterpret_cast<uint8_t*>(addr); 1003 *ptr = value; 1004} 1005 1006 1007void Simulator::WriteB(int32_t addr, int8_t value) { 1008 int8_t* ptr = reinterpret_cast<int8_t*>(addr); 1009 *ptr = value; 1010} 1011 1012 1013int32_t* Simulator::ReadDW(int32_t addr) { 1014#if V8_TARGET_CAN_READ_UNALIGNED 1015 int32_t* ptr = reinterpret_cast<int32_t*>(addr); 1016 return ptr; 1017#else 1018 if ((addr & 3) == 0) { 1019 int32_t* ptr = reinterpret_cast<int32_t*>(addr); 1020 return ptr; 1021 } 1022 PrintF("Unaligned read at 0x%08x\n", addr); 1023 UNIMPLEMENTED(); 1024 return 0; 1025#endif 1026} 1027 1028 1029void Simulator::WriteDW(int32_t addr, int32_t value1, int32_t value2) { 1030#if V8_TARGET_CAN_READ_UNALIGNED 1031 int32_t* ptr = reinterpret_cast<int32_t*>(addr); 1032 *ptr++ = value1; 1033 *ptr = value2; 1034 return; 1035#else 1036 if ((addr & 3) == 0) { 1037 int32_t* ptr = reinterpret_cast<int32_t*>(addr); 1038 *ptr++ = value1; 1039 *ptr = value2; 1040 return; 1041 } 1042 PrintF("Unaligned write at 0x%08x\n", addr); 1043 UNIMPLEMENTED(); 1044#endif 1045} 1046 1047 1048// Returns the limit of the stack area to enable checking for stack overflows. 1049uintptr_t Simulator::StackLimit() const { 1050 // Leave a safety margin of 256 bytes to prevent overrunning the stack when 1051 // pushing values. 1052 return reinterpret_cast<uintptr_t>(stack_) + 256; 1053} 1054 1055 1056// Unsupported instructions use Format to print an error and stop execution. 1057void Simulator::Format(Instr* instr, const char* format) { 1058 PrintF("Simulator found unsupported instruction:\n 0x%08x: %s\n", 1059 instr, format); 1060 UNIMPLEMENTED(); 1061} 1062 1063 1064// Checks if the current instruction should be executed based on its 1065// condition bits. 1066bool Simulator::ConditionallyExecute(Instr* instr) { 1067 switch (instr->ConditionField()) { 1068 case EQ: return z_flag_; 1069 case NE: return !z_flag_; 1070 case CS: return c_flag_; 1071 case CC: return !c_flag_; 1072 case MI: return n_flag_; 1073 case PL: return !n_flag_; 1074 case VS: return v_flag_; 1075 case VC: return !v_flag_; 1076 case HI: return c_flag_ && !z_flag_; 1077 case LS: return !c_flag_ || z_flag_; 1078 case GE: return n_flag_ == v_flag_; 1079 case LT: return n_flag_ != v_flag_; 1080 case GT: return !z_flag_ && (n_flag_ == v_flag_); 1081 case LE: return z_flag_ || (n_flag_ != v_flag_); 1082 case AL: return true; 1083 default: UNREACHABLE(); 1084 } 1085 return false; 1086} 1087 1088 1089// Calculate and set the Negative and Zero flags. 1090void Simulator::SetNZFlags(int32_t val) { 1091 n_flag_ = (val < 0); 1092 z_flag_ = (val == 0); 1093} 1094 1095 1096// Set the Carry flag. 1097void Simulator::SetCFlag(bool val) { 1098 c_flag_ = val; 1099} 1100 1101 1102// Set the oVerflow flag. 1103void Simulator::SetVFlag(bool val) { 1104 v_flag_ = val; 1105} 1106 1107 1108// Calculate C flag value for additions. 1109bool Simulator::CarryFrom(int32_t left, int32_t right) { 1110 uint32_t uleft = static_cast<uint32_t>(left); 1111 uint32_t uright = static_cast<uint32_t>(right); 1112 uint32_t urest = 0xffffffffU - uleft; 1113 1114 return (uright > urest); 1115} 1116 1117 1118// Calculate C flag value for subtractions. 1119bool Simulator::BorrowFrom(int32_t left, int32_t right) { 1120 uint32_t uleft = static_cast<uint32_t>(left); 1121 uint32_t uright = static_cast<uint32_t>(right); 1122 1123 return (uright > uleft); 1124} 1125 1126 1127// Calculate V flag value for additions and subtractions. 1128bool Simulator::OverflowFrom(int32_t alu_out, 1129 int32_t left, int32_t right, bool addition) { 1130 bool overflow; 1131 if (addition) { 1132 // operands have the same sign 1133 overflow = ((left >= 0 && right >= 0) || (left < 0 && right < 0)) 1134 // and operands and result have different sign 1135 && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0)); 1136 } else { 1137 // operands have different signs 1138 overflow = ((left < 0 && right >= 0) || (left >= 0 && right < 0)) 1139 // and first operand and result have different signs 1140 && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0)); 1141 } 1142 return overflow; 1143} 1144 1145 1146// Support for VFP comparisons. 1147void Simulator::Compute_FPSCR_Flags(double val1, double val2) { 1148 if (isnan(val1) || isnan(val2)) { 1149 n_flag_FPSCR_ = false; 1150 z_flag_FPSCR_ = false; 1151 c_flag_FPSCR_ = true; 1152 v_flag_FPSCR_ = true; 1153 // All non-NaN cases. 1154 } else if (val1 == val2) { 1155 n_flag_FPSCR_ = false; 1156 z_flag_FPSCR_ = true; 1157 c_flag_FPSCR_ = true; 1158 v_flag_FPSCR_ = false; 1159 } else if (val1 < val2) { 1160 n_flag_FPSCR_ = true; 1161 z_flag_FPSCR_ = false; 1162 c_flag_FPSCR_ = false; 1163 v_flag_FPSCR_ = false; 1164 } else { 1165 // Case when (val1 > val2). 1166 n_flag_FPSCR_ = false; 1167 z_flag_FPSCR_ = false; 1168 c_flag_FPSCR_ = true; 1169 v_flag_FPSCR_ = false; 1170 } 1171} 1172 1173 1174void Simulator::Copy_FPSCR_to_APSR() { 1175 n_flag_ = n_flag_FPSCR_; 1176 z_flag_ = z_flag_FPSCR_; 1177 c_flag_ = c_flag_FPSCR_; 1178 v_flag_ = v_flag_FPSCR_; 1179} 1180 1181 1182// Addressing Mode 1 - Data-processing operands: 1183// Get the value based on the shifter_operand with register. 1184int32_t Simulator::GetShiftRm(Instr* instr, bool* carry_out) { 1185 Shift shift = instr->ShiftField(); 1186 int shift_amount = instr->ShiftAmountField(); 1187 int32_t result = get_register(instr->RmField()); 1188 if (instr->Bit(4) == 0) { 1189 // by immediate 1190 if ((shift == ROR) && (shift_amount == 0)) { 1191 UNIMPLEMENTED(); 1192 return result; 1193 } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) { 1194 shift_amount = 32; 1195 } 1196 switch (shift) { 1197 case ASR: { 1198 if (shift_amount == 0) { 1199 if (result < 0) { 1200 result = 0xffffffff; 1201 *carry_out = true; 1202 } else { 1203 result = 0; 1204 *carry_out = false; 1205 } 1206 } else { 1207 result >>= (shift_amount - 1); 1208 *carry_out = (result & 1) == 1; 1209 result >>= 1; 1210 } 1211 break; 1212 } 1213 1214 case LSL: { 1215 if (shift_amount == 0) { 1216 *carry_out = c_flag_; 1217 } else { 1218 result <<= (shift_amount - 1); 1219 *carry_out = (result < 0); 1220 result <<= 1; 1221 } 1222 break; 1223 } 1224 1225 case LSR: { 1226 if (shift_amount == 0) { 1227 result = 0; 1228 *carry_out = c_flag_; 1229 } else { 1230 uint32_t uresult = static_cast<uint32_t>(result); 1231 uresult >>= (shift_amount - 1); 1232 *carry_out = (uresult & 1) == 1; 1233 uresult >>= 1; 1234 result = static_cast<int32_t>(uresult); 1235 } 1236 break; 1237 } 1238 1239 case ROR: { 1240 UNIMPLEMENTED(); 1241 break; 1242 } 1243 1244 default: { 1245 UNREACHABLE(); 1246 break; 1247 } 1248 } 1249 } else { 1250 // by register 1251 int rs = instr->RsField(); 1252 shift_amount = get_register(rs) &0xff; 1253 switch (shift) { 1254 case ASR: { 1255 if (shift_amount == 0) { 1256 *carry_out = c_flag_; 1257 } else if (shift_amount < 32) { 1258 result >>= (shift_amount - 1); 1259 *carry_out = (result & 1) == 1; 1260 result >>= 1; 1261 } else { 1262 ASSERT(shift_amount >= 32); 1263 if (result < 0) { 1264 *carry_out = true; 1265 result = 0xffffffff; 1266 } else { 1267 *carry_out = false; 1268 result = 0; 1269 } 1270 } 1271 break; 1272 } 1273 1274 case LSL: { 1275 if (shift_amount == 0) { 1276 *carry_out = c_flag_; 1277 } else if (shift_amount < 32) { 1278 result <<= (shift_amount - 1); 1279 *carry_out = (result < 0); 1280 result <<= 1; 1281 } else if (shift_amount == 32) { 1282 *carry_out = (result & 1) == 1; 1283 result = 0; 1284 } else { 1285 ASSERT(shift_amount > 32); 1286 *carry_out = false; 1287 result = 0; 1288 } 1289 break; 1290 } 1291 1292 case LSR: { 1293 if (shift_amount == 0) { 1294 *carry_out = c_flag_; 1295 } else if (shift_amount < 32) { 1296 uint32_t uresult = static_cast<uint32_t>(result); 1297 uresult >>= (shift_amount - 1); 1298 *carry_out = (uresult & 1) == 1; 1299 uresult >>= 1; 1300 result = static_cast<int32_t>(uresult); 1301 } else if (shift_amount == 32) { 1302 *carry_out = (result < 0); 1303 result = 0; 1304 } else { 1305 *carry_out = false; 1306 result = 0; 1307 } 1308 break; 1309 } 1310 1311 case ROR: { 1312 UNIMPLEMENTED(); 1313 break; 1314 } 1315 1316 default: { 1317 UNREACHABLE(); 1318 break; 1319 } 1320 } 1321 } 1322 return result; 1323} 1324 1325 1326// Addressing Mode 1 - Data-processing operands: 1327// Get the value based on the shifter_operand with immediate. 1328int32_t Simulator::GetImm(Instr* instr, bool* carry_out) { 1329 int rotate = instr->RotateField() * 2; 1330 int immed8 = instr->Immed8Field(); 1331 int imm = (immed8 >> rotate) | (immed8 << (32 - rotate)); 1332 *carry_out = (rotate == 0) ? c_flag_ : (imm < 0); 1333 return imm; 1334} 1335 1336 1337static int count_bits(int bit_vector) { 1338 int count = 0; 1339 while (bit_vector != 0) { 1340 if ((bit_vector & 1) != 0) { 1341 count++; 1342 } 1343 bit_vector >>= 1; 1344 } 1345 return count; 1346} 1347 1348 1349// Addressing Mode 4 - Load and Store Multiple 1350void Simulator::HandleRList(Instr* instr, bool load) { 1351 int rn = instr->RnField(); 1352 int32_t rn_val = get_register(rn); 1353 int rlist = instr->RlistField(); 1354 int num_regs = count_bits(rlist); 1355 1356 intptr_t start_address = 0; 1357 intptr_t end_address = 0; 1358 switch (instr->PUField()) { 1359 case 0: { 1360 // Print("da"); 1361 UNIMPLEMENTED(); 1362 break; 1363 } 1364 case 1: { 1365 // Print("ia"); 1366 start_address = rn_val; 1367 end_address = rn_val + (num_regs * 4) - 4; 1368 rn_val = rn_val + (num_regs * 4); 1369 break; 1370 } 1371 case 2: { 1372 // Print("db"); 1373 start_address = rn_val - (num_regs * 4); 1374 end_address = rn_val - 4; 1375 rn_val = start_address; 1376 break; 1377 } 1378 case 3: { 1379 // Print("ib"); 1380 UNIMPLEMENTED(); 1381 break; 1382 } 1383 default: { 1384 UNREACHABLE(); 1385 break; 1386 } 1387 } 1388 if (instr->HasW()) { 1389 set_register(rn, rn_val); 1390 } 1391 intptr_t* address = reinterpret_cast<intptr_t*>(start_address); 1392 int reg = 0; 1393 while (rlist != 0) { 1394 if ((rlist & 1) != 0) { 1395 if (load) { 1396 set_register(reg, *address); 1397 } else { 1398 *address = get_register(reg); 1399 } 1400 address += 1; 1401 } 1402 reg++; 1403 rlist >>= 1; 1404 } 1405 ASSERT(end_address == ((intptr_t)address) - 4); 1406} 1407 1408 1409// Calls into the V8 runtime are based on this very simple interface. 1410// Note: To be able to return two values from some calls the code in runtime.cc 1411// uses the ObjectPair which is essentially two 32-bit values stuffed into a 1412// 64-bit value. With the code below we assume that all runtime calls return 1413// 64 bits of result. If they don't, the r1 result register contains a bogus 1414// value, which is fine because it is caller-saved. 1415typedef int64_t (*SimulatorRuntimeCall)(int32_t arg0, 1416 int32_t arg1, 1417 int32_t arg2, 1418 int32_t arg3); 1419typedef double (*SimulatorRuntimeFPCall)(int32_t arg0, 1420 int32_t arg1, 1421 int32_t arg2, 1422 int32_t arg3); 1423 1424 1425// Software interrupt instructions are used by the simulator to call into the 1426// C-based V8 runtime. 1427void Simulator::SoftwareInterrupt(Instr* instr) { 1428 int swi = instr->SwiField(); 1429 switch (swi) { 1430 case call_rt_redirected: { 1431 // Check if stack is aligned. Error if not aligned is reported below to 1432 // include information on the function called. 1433 bool stack_aligned = 1434 (get_register(sp) 1435 & (::v8::internal::FLAG_sim_stack_alignment - 1)) == 0; 1436 Redirection* redirection = Redirection::FromSwiInstruction(instr); 1437 int32_t arg0 = get_register(r0); 1438 int32_t arg1 = get_register(r1); 1439 int32_t arg2 = get_register(r2); 1440 int32_t arg3 = get_register(r3); 1441 // This is dodgy but it works because the C entry stubs are never moved. 1442 // See comment in codegen-arm.cc and bug 1242173. 1443 int32_t saved_lr = get_register(lr); 1444 if (redirection->fp_return()) { 1445 intptr_t external = 1446 reinterpret_cast<intptr_t>(redirection->external_function()); 1447 SimulatorRuntimeFPCall target = 1448 reinterpret_cast<SimulatorRuntimeFPCall>(external); 1449 if (::v8::internal::FLAG_trace_sim || !stack_aligned) { 1450 double x, y; 1451 GetFpArgs(&x, &y); 1452 PrintF("Call to host function at %p with args %f, %f", 1453 FUNCTION_ADDR(target), x, y); 1454 if (!stack_aligned) { 1455 PrintF(" with unaligned stack %08x\n", get_register(sp)); 1456 } 1457 PrintF("\n"); 1458 } 1459 CHECK(stack_aligned); 1460 double result = target(arg0, arg1, arg2, arg3); 1461 SetFpResult(result); 1462 } else { 1463 intptr_t external = 1464 reinterpret_cast<int32_t>(redirection->external_function()); 1465 SimulatorRuntimeCall target = 1466 reinterpret_cast<SimulatorRuntimeCall>(external); 1467 if (::v8::internal::FLAG_trace_sim || !stack_aligned) { 1468 PrintF( 1469 "Call to host function at %p with args %08x, %08x, %08x, %08x", 1470 FUNCTION_ADDR(target), 1471 arg0, 1472 arg1, 1473 arg2, 1474 arg3); 1475 if (!stack_aligned) { 1476 PrintF(" with unaligned stack %08x\n", get_register(sp)); 1477 } 1478 PrintF("\n"); 1479 } 1480 CHECK(stack_aligned); 1481 int64_t result = target(arg0, arg1, arg2, arg3); 1482 int32_t lo_res = static_cast<int32_t>(result); 1483 int32_t hi_res = static_cast<int32_t>(result >> 32); 1484 if (::v8::internal::FLAG_trace_sim) { 1485 PrintF("Returned %08x\n", lo_res); 1486 } 1487 set_register(r0, lo_res); 1488 set_register(r1, hi_res); 1489 } 1490 set_register(lr, saved_lr); 1491 set_pc(get_register(lr)); 1492 break; 1493 } 1494 case break_point: { 1495 Debugger dbg(this); 1496 dbg.Debug(); 1497 break; 1498 } 1499 default: { 1500 UNREACHABLE(); 1501 break; 1502 } 1503 } 1504} 1505 1506 1507// Handle execution based on instruction types. 1508 1509// Instruction types 0 and 1 are both rolled into one function because they 1510// only differ in the handling of the shifter_operand. 1511void Simulator::DecodeType01(Instr* instr) { 1512 int type = instr->TypeField(); 1513 if ((type == 0) && instr->IsSpecialType0()) { 1514 // multiply instruction or extra loads and stores 1515 if (instr->Bits(7, 4) == 9) { 1516 if (instr->Bit(24) == 0) { 1517 // Raw field decoding here. Multiply instructions have their Rd in 1518 // funny places. 1519 int rn = instr->RnField(); 1520 int rm = instr->RmField(); 1521 int rs = instr->RsField(); 1522 int32_t rs_val = get_register(rs); 1523 int32_t rm_val = get_register(rm); 1524 if (instr->Bit(23) == 0) { 1525 if (instr->Bit(21) == 0) { 1526 // The MUL instruction description (A 4.1.33) refers to Rd as being 1527 // the destination for the operation, but it confusingly uses the 1528 // Rn field to encode it. 1529 // Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 1530 int rd = rn; // Remap the rn field to the Rd register. 1531 int32_t alu_out = rm_val * rs_val; 1532 set_register(rd, alu_out); 1533 if (instr->HasS()) { 1534 SetNZFlags(alu_out); 1535 } 1536 } else { 1537 // The MLA instruction description (A 4.1.28) refers to the order 1538 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 1539 // Rn field to encode the Rd register and the Rd field to encode 1540 // the Rn register. 1541 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); 1542 } 1543 } else { 1544 // The signed/long multiply instructions use the terms RdHi and RdLo 1545 // when referring to the target registers. They are mapped to the Rn 1546 // and Rd fields as follows: 1547 // RdLo == Rd 1548 // RdHi == Rn (This is confusingly stored in variable rd here 1549 // because the mul instruction from above uses the 1550 // Rn field to encode the Rd register. Good luck figuring 1551 // this out without reading the ARM instruction manual 1552 // at a very detailed level.) 1553 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm"); 1554 int rd_hi = rn; // Remap the rn field to the RdHi register. 1555 int rd_lo = instr->RdField(); 1556 int32_t hi_res = 0; 1557 int32_t lo_res = 0; 1558 if (instr->Bit(22) == 1) { 1559 int64_t left_op = static_cast<int32_t>(rm_val); 1560 int64_t right_op = static_cast<int32_t>(rs_val); 1561 uint64_t result = left_op * right_op; 1562 hi_res = static_cast<int32_t>(result >> 32); 1563 lo_res = static_cast<int32_t>(result & 0xffffffff); 1564 } else { 1565 // unsigned multiply 1566 uint64_t left_op = static_cast<uint32_t>(rm_val); 1567 uint64_t right_op = static_cast<uint32_t>(rs_val); 1568 uint64_t result = left_op * right_op; 1569 hi_res = static_cast<int32_t>(result >> 32); 1570 lo_res = static_cast<int32_t>(result & 0xffffffff); 1571 } 1572 set_register(rd_lo, lo_res); 1573 set_register(rd_hi, hi_res); 1574 if (instr->HasS()) { 1575 UNIMPLEMENTED(); 1576 } 1577 } 1578 } else { 1579 UNIMPLEMENTED(); // Not used by V8. 1580 } 1581 } else { 1582 // extra load/store instructions 1583 int rd = instr->RdField(); 1584 int rn = instr->RnField(); 1585 int32_t rn_val = get_register(rn); 1586 int32_t addr = 0; 1587 if (instr->Bit(22) == 0) { 1588 int rm = instr->RmField(); 1589 int32_t rm_val = get_register(rm); 1590 switch (instr->PUField()) { 1591 case 0: { 1592 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm"); 1593 ASSERT(!instr->HasW()); 1594 addr = rn_val; 1595 rn_val -= rm_val; 1596 set_register(rn, rn_val); 1597 break; 1598 } 1599 case 1: { 1600 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm"); 1601 ASSERT(!instr->HasW()); 1602 addr = rn_val; 1603 rn_val += rm_val; 1604 set_register(rn, rn_val); 1605 break; 1606 } 1607 case 2: { 1608 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w"); 1609 rn_val -= rm_val; 1610 addr = rn_val; 1611 if (instr->HasW()) { 1612 set_register(rn, rn_val); 1613 } 1614 break; 1615 } 1616 case 3: { 1617 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w"); 1618 rn_val += rm_val; 1619 addr = rn_val; 1620 if (instr->HasW()) { 1621 set_register(rn, rn_val); 1622 } 1623 break; 1624 } 1625 default: { 1626 // The PU field is a 2-bit field. 1627 UNREACHABLE(); 1628 break; 1629 } 1630 } 1631 } else { 1632 int32_t imm_val = (instr->ImmedHField() << 4) | instr->ImmedLField(); 1633 switch (instr->PUField()) { 1634 case 0: { 1635 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8"); 1636 ASSERT(!instr->HasW()); 1637 addr = rn_val; 1638 rn_val -= imm_val; 1639 set_register(rn, rn_val); 1640 break; 1641 } 1642 case 1: { 1643 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8"); 1644 ASSERT(!instr->HasW()); 1645 addr = rn_val; 1646 rn_val += imm_val; 1647 set_register(rn, rn_val); 1648 break; 1649 } 1650 case 2: { 1651 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w"); 1652 rn_val -= imm_val; 1653 addr = rn_val; 1654 if (instr->HasW()) { 1655 set_register(rn, rn_val); 1656 } 1657 break; 1658 } 1659 case 3: { 1660 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w"); 1661 rn_val += imm_val; 1662 addr = rn_val; 1663 if (instr->HasW()) { 1664 set_register(rn, rn_val); 1665 } 1666 break; 1667 } 1668 default: { 1669 // The PU field is a 2-bit field. 1670 UNREACHABLE(); 1671 break; 1672 } 1673 } 1674 } 1675 if (((instr->Bits(7, 4) & 0xd) == 0xd) && (instr->Bit(20) == 0)) { 1676 ASSERT((rd % 2) == 0); 1677 if (instr->HasH()) { 1678 // The strd instruction. 1679 int32_t value1 = get_register(rd); 1680 int32_t value2 = get_register(rd+1); 1681 WriteDW(addr, value1, value2); 1682 } else { 1683 // The ldrd instruction. 1684 int* rn_data = ReadDW(addr); 1685 set_dw_register(rd, rn_data); 1686 } 1687 } else if (instr->HasH()) { 1688 if (instr->HasSign()) { 1689 if (instr->HasL()) { 1690 int16_t val = ReadH(addr, instr); 1691 set_register(rd, val); 1692 } else { 1693 int16_t val = get_register(rd); 1694 WriteH(addr, val, instr); 1695 } 1696 } else { 1697 if (instr->HasL()) { 1698 uint16_t val = ReadHU(addr, instr); 1699 set_register(rd, val); 1700 } else { 1701 uint16_t val = get_register(rd); 1702 WriteH(addr, val, instr); 1703 } 1704 } 1705 } else { 1706 // signed byte loads 1707 ASSERT(instr->HasSign()); 1708 ASSERT(instr->HasL()); 1709 int8_t val = ReadB(addr); 1710 set_register(rd, val); 1711 } 1712 return; 1713 } 1714 } else if ((type == 0) && instr->IsMiscType0()) { 1715 if (instr->Bits(22, 21) == 1) { 1716 int rm = instr->RmField(); 1717 switch (instr->Bits(7, 4)) { 1718 case BX: 1719 set_pc(get_register(rm)); 1720 break; 1721 case BLX: { 1722 uint32_t old_pc = get_pc(); 1723 set_pc(get_register(rm)); 1724 set_register(lr, old_pc + Instr::kInstrSize); 1725 break; 1726 } 1727 case BKPT: 1728 v8::internal::OS::DebugBreak(); 1729 break; 1730 default: 1731 UNIMPLEMENTED(); 1732 } 1733 } else if (instr->Bits(22, 21) == 3) { 1734 int rm = instr->RmField(); 1735 int rd = instr->RdField(); 1736 switch (instr->Bits(7, 4)) { 1737 case CLZ: { 1738 uint32_t bits = get_register(rm); 1739 int leading_zeros = 0; 1740 if (bits == 0) { 1741 leading_zeros = 32; 1742 } else { 1743 while ((bits & 0x80000000u) == 0) { 1744 bits <<= 1; 1745 leading_zeros++; 1746 } 1747 } 1748 set_register(rd, leading_zeros); 1749 break; 1750 } 1751 default: 1752 UNIMPLEMENTED(); 1753 } 1754 } else { 1755 PrintF("%08x\n", instr->InstructionBits()); 1756 UNIMPLEMENTED(); 1757 } 1758 } else { 1759 int rd = instr->RdField(); 1760 int rn = instr->RnField(); 1761 int32_t rn_val = get_register(rn); 1762 int32_t shifter_operand = 0; 1763 bool shifter_carry_out = 0; 1764 if (type == 0) { 1765 shifter_operand = GetShiftRm(instr, &shifter_carry_out); 1766 } else { 1767 ASSERT(instr->TypeField() == 1); 1768 shifter_operand = GetImm(instr, &shifter_carry_out); 1769 } 1770 int32_t alu_out; 1771 1772 switch (instr->OpcodeField()) { 1773 case AND: { 1774 // Format(instr, "and'cond's 'rd, 'rn, 'shift_rm"); 1775 // Format(instr, "and'cond's 'rd, 'rn, 'imm"); 1776 alu_out = rn_val & shifter_operand; 1777 set_register(rd, alu_out); 1778 if (instr->HasS()) { 1779 SetNZFlags(alu_out); 1780 SetCFlag(shifter_carry_out); 1781 } 1782 break; 1783 } 1784 1785 case EOR: { 1786 // Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm"); 1787 // Format(instr, "eor'cond's 'rd, 'rn, 'imm"); 1788 alu_out = rn_val ^ shifter_operand; 1789 set_register(rd, alu_out); 1790 if (instr->HasS()) { 1791 SetNZFlags(alu_out); 1792 SetCFlag(shifter_carry_out); 1793 } 1794 break; 1795 } 1796 1797 case SUB: { 1798 // Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm"); 1799 // Format(instr, "sub'cond's 'rd, 'rn, 'imm"); 1800 alu_out = rn_val - shifter_operand; 1801 set_register(rd, alu_out); 1802 if (instr->HasS()) { 1803 SetNZFlags(alu_out); 1804 SetCFlag(!BorrowFrom(rn_val, shifter_operand)); 1805 SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false)); 1806 } 1807 break; 1808 } 1809 1810 case RSB: { 1811 // Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm"); 1812 // Format(instr, "rsb'cond's 'rd, 'rn, 'imm"); 1813 alu_out = shifter_operand - rn_val; 1814 set_register(rd, alu_out); 1815 if (instr->HasS()) { 1816 SetNZFlags(alu_out); 1817 SetCFlag(!BorrowFrom(shifter_operand, rn_val)); 1818 SetVFlag(OverflowFrom(alu_out, shifter_operand, rn_val, false)); 1819 } 1820 break; 1821 } 1822 1823 case ADD: { 1824 // Format(instr, "add'cond's 'rd, 'rn, 'shift_rm"); 1825 // Format(instr, "add'cond's 'rd, 'rn, 'imm"); 1826 alu_out = rn_val + shifter_operand; 1827 set_register(rd, alu_out); 1828 if (instr->HasS()) { 1829 SetNZFlags(alu_out); 1830 SetCFlag(CarryFrom(rn_val, shifter_operand)); 1831 SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true)); 1832 } 1833 break; 1834 } 1835 1836 case ADC: { 1837 Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm"); 1838 Format(instr, "adc'cond's 'rd, 'rn, 'imm"); 1839 break; 1840 } 1841 1842 case SBC: { 1843 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm"); 1844 Format(instr, "sbc'cond's 'rd, 'rn, 'imm"); 1845 break; 1846 } 1847 1848 case RSC: { 1849 Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm"); 1850 Format(instr, "rsc'cond's 'rd, 'rn, 'imm"); 1851 break; 1852 } 1853 1854 case TST: { 1855 if (instr->HasS()) { 1856 // Format(instr, "tst'cond 'rn, 'shift_rm"); 1857 // Format(instr, "tst'cond 'rn, 'imm"); 1858 alu_out = rn_val & shifter_operand; 1859 SetNZFlags(alu_out); 1860 SetCFlag(shifter_carry_out); 1861 } else { 1862 UNIMPLEMENTED(); 1863 } 1864 break; 1865 } 1866 1867 case TEQ: { 1868 if (instr->HasS()) { 1869 // Format(instr, "teq'cond 'rn, 'shift_rm"); 1870 // Format(instr, "teq'cond 'rn, 'imm"); 1871 alu_out = rn_val ^ shifter_operand; 1872 SetNZFlags(alu_out); 1873 SetCFlag(shifter_carry_out); 1874 } else { 1875 // Other instructions matching this pattern are handled in the 1876 // miscellaneous instructions part above. 1877 UNREACHABLE(); 1878 } 1879 break; 1880 } 1881 1882 case CMP: { 1883 if (instr->HasS()) { 1884 // Format(instr, "cmp'cond 'rn, 'shift_rm"); 1885 // Format(instr, "cmp'cond 'rn, 'imm"); 1886 alu_out = rn_val - shifter_operand; 1887 SetNZFlags(alu_out); 1888 SetCFlag(!BorrowFrom(rn_val, shifter_operand)); 1889 SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false)); 1890 } else { 1891 UNIMPLEMENTED(); 1892 } 1893 break; 1894 } 1895 1896 case CMN: { 1897 if (instr->HasS()) { 1898 // Format(instr, "cmn'cond 'rn, 'shift_rm"); 1899 // Format(instr, "cmn'cond 'rn, 'imm"); 1900 alu_out = rn_val + shifter_operand; 1901 SetNZFlags(alu_out); 1902 SetCFlag(!CarryFrom(rn_val, shifter_operand)); 1903 SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true)); 1904 } else { 1905 // Other instructions matching this pattern are handled in the 1906 // miscellaneous instructions part above. 1907 UNREACHABLE(); 1908 } 1909 break; 1910 } 1911 1912 case ORR: { 1913 // Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm"); 1914 // Format(instr, "orr'cond's 'rd, 'rn, 'imm"); 1915 alu_out = rn_val | shifter_operand; 1916 set_register(rd, alu_out); 1917 if (instr->HasS()) { 1918 SetNZFlags(alu_out); 1919 SetCFlag(shifter_carry_out); 1920 } 1921 break; 1922 } 1923 1924 case MOV: { 1925 // Format(instr, "mov'cond's 'rd, 'shift_rm"); 1926 // Format(instr, "mov'cond's 'rd, 'imm"); 1927 alu_out = shifter_operand; 1928 set_register(rd, alu_out); 1929 if (instr->HasS()) { 1930 SetNZFlags(alu_out); 1931 SetCFlag(shifter_carry_out); 1932 } 1933 break; 1934 } 1935 1936 case BIC: { 1937 // Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm"); 1938 // Format(instr, "bic'cond's 'rd, 'rn, 'imm"); 1939 alu_out = rn_val & ~shifter_operand; 1940 set_register(rd, alu_out); 1941 if (instr->HasS()) { 1942 SetNZFlags(alu_out); 1943 SetCFlag(shifter_carry_out); 1944 } 1945 break; 1946 } 1947 1948 case MVN: { 1949 // Format(instr, "mvn'cond's 'rd, 'shift_rm"); 1950 // Format(instr, "mvn'cond's 'rd, 'imm"); 1951 alu_out = ~shifter_operand; 1952 set_register(rd, alu_out); 1953 if (instr->HasS()) { 1954 SetNZFlags(alu_out); 1955 SetCFlag(shifter_carry_out); 1956 } 1957 break; 1958 } 1959 1960 default: { 1961 UNREACHABLE(); 1962 break; 1963 } 1964 } 1965 } 1966} 1967 1968 1969void Simulator::DecodeType2(Instr* instr) { 1970 int rd = instr->RdField(); 1971 int rn = instr->RnField(); 1972 int32_t rn_val = get_register(rn); 1973 int32_t im_val = instr->Offset12Field(); 1974 int32_t addr = 0; 1975 switch (instr->PUField()) { 1976 case 0: { 1977 // Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12"); 1978 ASSERT(!instr->HasW()); 1979 addr = rn_val; 1980 rn_val -= im_val; 1981 set_register(rn, rn_val); 1982 break; 1983 } 1984 case 1: { 1985 // Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12"); 1986 ASSERT(!instr->HasW()); 1987 addr = rn_val; 1988 rn_val += im_val; 1989 set_register(rn, rn_val); 1990 break; 1991 } 1992 case 2: { 1993 // Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w"); 1994 rn_val -= im_val; 1995 addr = rn_val; 1996 if (instr->HasW()) { 1997 set_register(rn, rn_val); 1998 } 1999 break; 2000 } 2001 case 3: { 2002 // Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w"); 2003 rn_val += im_val; 2004 addr = rn_val; 2005 if (instr->HasW()) { 2006 set_register(rn, rn_val); 2007 } 2008 break; 2009 } 2010 default: { 2011 UNREACHABLE(); 2012 break; 2013 } 2014 } 2015 if (instr->HasB()) { 2016 if (instr->HasL()) { 2017 byte val = ReadBU(addr); 2018 set_register(rd, val); 2019 } else { 2020 byte val = get_register(rd); 2021 WriteB(addr, val); 2022 } 2023 } else { 2024 if (instr->HasL()) { 2025 set_register(rd, ReadW(addr, instr)); 2026 } else { 2027 WriteW(addr, get_register(rd), instr); 2028 } 2029 } 2030} 2031 2032 2033void Simulator::DecodeType3(Instr* instr) { 2034 int rd = instr->RdField(); 2035 int rn = instr->RnField(); 2036 int32_t rn_val = get_register(rn); 2037 bool shifter_carry_out = 0; 2038 int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out); 2039 int32_t addr = 0; 2040 switch (instr->PUField()) { 2041 case 0: { 2042 ASSERT(!instr->HasW()); 2043 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm"); 2044 break; 2045 } 2046 case 1: { 2047 ASSERT(!instr->HasW()); 2048 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm"); 2049 break; 2050 } 2051 case 2: { 2052 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w"); 2053 addr = rn_val - shifter_operand; 2054 if (instr->HasW()) { 2055 set_register(rn, addr); 2056 } 2057 break; 2058 } 2059 case 3: { 2060 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) { 2061 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16)); 2062 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7)); 2063 uint32_t msbit = widthminus1 + lsbit; 2064 if (msbit <= 31) { 2065 if (instr->Bit(22)) { 2066 // ubfx - unsigned bitfield extract. 2067 uint32_t rm_val = 2068 static_cast<uint32_t>(get_register(instr->RmField())); 2069 uint32_t extr_val = rm_val << (31 - msbit); 2070 extr_val = extr_val >> (31 - widthminus1); 2071 set_register(instr->RdField(), extr_val); 2072 } else { 2073 // sbfx - signed bitfield extract. 2074 int32_t rm_val = get_register(instr->RmField()); 2075 int32_t extr_val = rm_val << (31 - msbit); 2076 extr_val = extr_val >> (31 - widthminus1); 2077 set_register(instr->RdField(), extr_val); 2078 } 2079 } else { 2080 UNREACHABLE(); 2081 } 2082 return; 2083 } else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) { 2084 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7)); 2085 uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16)); 2086 if (msbit >= lsbit) { 2087 // bfc or bfi - bitfield clear/insert. 2088 uint32_t rd_val = 2089 static_cast<uint32_t>(get_register(instr->RdField())); 2090 uint32_t bitcount = msbit - lsbit + 1; 2091 uint32_t mask = (1 << bitcount) - 1; 2092 rd_val &= ~(mask << lsbit); 2093 if (instr->RmField() != 15) { 2094 // bfi - bitfield insert. 2095 uint32_t rm_val = 2096 static_cast<uint32_t>(get_register(instr->RmField())); 2097 rm_val &= mask; 2098 rd_val |= rm_val << lsbit; 2099 } 2100 set_register(instr->RdField(), rd_val); 2101 } else { 2102 UNREACHABLE(); 2103 } 2104 return; 2105 } else { 2106 // Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w"); 2107 addr = rn_val + shifter_operand; 2108 if (instr->HasW()) { 2109 set_register(rn, addr); 2110 } 2111 } 2112 break; 2113 } 2114 default: { 2115 UNREACHABLE(); 2116 break; 2117 } 2118 } 2119 if (instr->HasB()) { 2120 if (instr->HasL()) { 2121 uint8_t byte = ReadB(addr); 2122 set_register(rd, byte); 2123 } else { 2124 uint8_t byte = get_register(rd); 2125 WriteB(addr, byte); 2126 } 2127 } else { 2128 if (instr->HasL()) { 2129 set_register(rd, ReadW(addr, instr)); 2130 } else { 2131 WriteW(addr, get_register(rd), instr); 2132 } 2133 } 2134} 2135 2136 2137void Simulator::DecodeType4(Instr* instr) { 2138 ASSERT(instr->Bit(22) == 0); // only allowed to be set in privileged mode 2139 if (instr->HasL()) { 2140 // Format(instr, "ldm'cond'pu 'rn'w, 'rlist"); 2141 HandleRList(instr, true); 2142 } else { 2143 // Format(instr, "stm'cond'pu 'rn'w, 'rlist"); 2144 HandleRList(instr, false); 2145 } 2146} 2147 2148 2149void Simulator::DecodeType5(Instr* instr) { 2150 // Format(instr, "b'l'cond 'target"); 2151 int off = (instr->SImmed24Field() << 2); 2152 intptr_t pc_address = get_pc(); 2153 if (instr->HasLink()) { 2154 set_register(lr, pc_address + Instr::kInstrSize); 2155 } 2156 int pc_reg = get_register(pc); 2157 set_pc(pc_reg + off); 2158} 2159 2160 2161void Simulator::DecodeType6(Instr* instr) { 2162 DecodeType6CoprocessorIns(instr); 2163} 2164 2165 2166void Simulator::DecodeType7(Instr* instr) { 2167 if (instr->Bit(24) == 1) { 2168 SoftwareInterrupt(instr); 2169 } else { 2170 DecodeTypeVFP(instr); 2171 } 2172} 2173 2174 2175void Simulator::DecodeUnconditional(Instr* instr) { 2176 if (instr->Bits(7, 4) == 0x0B && instr->Bits(27, 25) == 0 && instr->HasL()) { 2177 // Load halfword instruction, either register or immediate offset. 2178 int rd = instr->RdField(); 2179 int rn = instr->RnField(); 2180 int32_t rn_val = get_register(rn); 2181 int32_t addr = 0; 2182 int32_t offset; 2183 if (instr->Bit(22) == 0) { 2184 // Register offset. 2185 int rm = instr->RmField(); 2186 offset = get_register(rm); 2187 } else { 2188 // Immediate offset 2189 offset = instr->Bits(3, 0) + (instr->Bits(11, 8) << 4); 2190 } 2191 switch (instr->PUField()) { 2192 case 0: { 2193 // Post index, negative. 2194 ASSERT(!instr->HasW()); 2195 addr = rn_val; 2196 rn_val -= offset; 2197 set_register(rn, rn_val); 2198 break; 2199 } 2200 case 1: { 2201 // Post index, positive. 2202 ASSERT(!instr->HasW()); 2203 addr = rn_val; 2204 rn_val += offset; 2205 set_register(rn, rn_val); 2206 break; 2207 } 2208 case 2: { 2209 // Pre index or offset, negative. 2210 rn_val -= offset; 2211 addr = rn_val; 2212 if (instr->HasW()) { 2213 set_register(rn, rn_val); 2214 } 2215 break; 2216 } 2217 case 3: { 2218 // Pre index or offset, positive. 2219 rn_val += offset; 2220 addr = rn_val; 2221 if (instr->HasW()) { 2222 set_register(rn, rn_val); 2223 } 2224 break; 2225 } 2226 default: { 2227 // The PU field is a 2-bit field. 2228 UNREACHABLE(); 2229 break; 2230 } 2231 } 2232 // Not sign extending, so load as unsigned. 2233 uint16_t halfword = ReadH(addr, instr); 2234 set_register(rd, halfword); 2235 } else { 2236 Debugger dbg(this); 2237 dbg.Stop(instr); 2238 } 2239} 2240 2241 2242// Depending on value of last_bit flag glue register code from vm and m values 2243// (where m is expected to be a single bit). 2244static int GlueRegCode(bool last_bit, int vm, int m) { 2245 return last_bit ? ((vm << 1) | m) : ((m << 4) | vm); 2246} 2247 2248 2249// void Simulator::DecodeTypeVFP(Instr* instr) 2250// The Following ARMv7 VFPv instructions are currently supported. 2251// vmov :Sn = Rt 2252// vmov :Rt = Sn 2253// vcvt: Dd = Sm 2254// vcvt: Sd = Dm 2255// Dd = vadd(Dn, Dm) 2256// Dd = vsub(Dn, Dm) 2257// Dd = vmul(Dn, Dm) 2258// Dd = vdiv(Dn, Dm) 2259// vcmp(Dd, Dm) 2260// VMRS 2261void Simulator::DecodeTypeVFP(Instr* instr) { 2262 ASSERT((instr->TypeField() == 7) && (instr->Bit(24) == 0x0) ); 2263 ASSERT(instr->Bits(11, 9) == 0x5); 2264 2265 int vm = instr->VmField(); 2266 int vd = instr->VdField(); 2267 int vn = instr->VnField(); 2268 2269 if (instr->Bit(4) == 0) { 2270 if (instr->Opc1Field() == 0x7) { 2271 // Other data processing instructions 2272 if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) { 2273 DecodeVCVTBetweenDoubleAndSingle(instr); 2274 } else if ((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) { 2275 DecodeVCVTBetweenFloatingPointAndInteger(instr); 2276 } else if (((instr->Opc2Field() >> 1) == 0x6) && 2277 (instr->Opc3Field() & 0x1)) { 2278 DecodeVCVTBetweenFloatingPointAndInteger(instr); 2279 } else if (((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) && 2280 (instr->Opc3Field() & 0x1)) { 2281 DecodeVCMP(instr); 2282 } else { 2283 UNREACHABLE(); // Not used by V8. 2284 } 2285 } else if (instr->Opc1Field() == 0x3) { 2286 if (instr->SzField() != 0x1) { 2287 UNREACHABLE(); // Not used by V8. 2288 } 2289 2290 if (instr->Opc3Field() & 0x1) { 2291 // vsub 2292 double dn_value = get_double_from_d_register(vn); 2293 double dm_value = get_double_from_d_register(vm); 2294 double dd_value = dn_value - dm_value; 2295 set_d_register_from_double(vd, dd_value); 2296 } else { 2297 // vadd 2298 double dn_value = get_double_from_d_register(vn); 2299 double dm_value = get_double_from_d_register(vm); 2300 double dd_value = dn_value + dm_value; 2301 set_d_register_from_double(vd, dd_value); 2302 } 2303 } else if ((instr->Opc1Field() == 0x2) && !(instr->Opc3Field() & 0x1)) { 2304 // vmul 2305 if (instr->SzField() != 0x1) { 2306 UNREACHABLE(); // Not used by V8. 2307 } 2308 2309 double dn_value = get_double_from_d_register(vn); 2310 double dm_value = get_double_from_d_register(vm); 2311 double dd_value = dn_value * dm_value; 2312 set_d_register_from_double(vd, dd_value); 2313 } else if ((instr->Opc1Field() == 0x4) && !(instr->Opc3Field() & 0x1)) { 2314 // vdiv 2315 if (instr->SzField() != 0x1) { 2316 UNREACHABLE(); // Not used by V8. 2317 } 2318 2319 double dn_value = get_double_from_d_register(vn); 2320 double dm_value = get_double_from_d_register(vm); 2321 double dd_value = dn_value / dm_value; 2322 set_d_register_from_double(vd, dd_value); 2323 } else { 2324 UNIMPLEMENTED(); // Not used by V8. 2325 } 2326 } else { 2327 if ((instr->VCField() == 0x0) && 2328 (instr->VAField() == 0x0)) { 2329 DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr); 2330 } else if ((instr->VLField() == 0x1) && 2331 (instr->VCField() == 0x0) && 2332 (instr->VAField() == 0x7) && 2333 (instr->Bits(19, 16) == 0x1)) { 2334 // vmrs 2335 if (instr->RtField() == 0xF) 2336 Copy_FPSCR_to_APSR(); 2337 else 2338 UNIMPLEMENTED(); // Not used by V8. 2339 } else { 2340 UNIMPLEMENTED(); // Not used by V8. 2341 } 2342 } 2343} 2344 2345 2346void Simulator::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instr* instr) { 2347 ASSERT((instr->Bit(4) == 1) && (instr->VCField() == 0x0) && 2348 (instr->VAField() == 0x0)); 2349 2350 int t = instr->RtField(); 2351 int n = GlueRegCode(true, instr->VnField(), instr->NField()); 2352 bool to_arm_register = (instr->VLField() == 0x1); 2353 2354 if (to_arm_register) { 2355 int32_t int_value = get_sinteger_from_s_register(n); 2356 set_register(t, int_value); 2357 } else { 2358 int32_t rs_val = get_register(t); 2359 set_s_register_from_sinteger(n, rs_val); 2360 } 2361} 2362 2363 2364void Simulator::DecodeVCMP(Instr* instr) { 2365 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7)); 2366 ASSERT(((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) && 2367 (instr->Opc3Field() & 0x1)); 2368 2369 // Comparison. 2370 bool dp_operation = (instr->SzField() == 1); 2371 2372 if (instr->Bit(7) != 0) { 2373 // Raising exceptions for quiet NaNs are not supported. 2374 UNIMPLEMENTED(); // Not used by V8. 2375 } 2376 2377 int d = GlueRegCode(!dp_operation, instr->VdField(), instr->DField()); 2378 int m = GlueRegCode(!dp_operation, instr->VmField(), instr->MField()); 2379 2380 if (dp_operation) { 2381 double dd_value = get_double_from_d_register(d); 2382 double dm_value = get_double_from_d_register(m); 2383 2384 Compute_FPSCR_Flags(dd_value, dm_value); 2385 } else { 2386 UNIMPLEMENTED(); // Not used by V8. 2387 } 2388} 2389 2390 2391void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instr* instr) { 2392 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7)); 2393 ASSERT((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)); 2394 2395 bool double_to_single = (instr->SzField() == 1); 2396 int dst = GlueRegCode(double_to_single, instr->VdField(), instr->DField()); 2397 int src = GlueRegCode(!double_to_single, instr->VmField(), instr->MField()); 2398 2399 if (double_to_single) { 2400 double val = get_double_from_d_register(src); 2401 set_s_register_from_float(dst, static_cast<float>(val)); 2402 } else { 2403 float val = get_float_from_s_register(src); 2404 set_d_register_from_double(dst, static_cast<double>(val)); 2405 } 2406} 2407 2408 2409void Simulator::DecodeVCVTBetweenFloatingPointAndInteger(Instr* instr) { 2410 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7)); 2411 ASSERT(((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) || 2412 (((instr->Opc2Field() >> 1) == 0x6) && (instr->Opc3Field() & 0x1))); 2413 2414 // Conversion between floating-point and integer. 2415 int vd = instr->VdField(); 2416 int d = instr->DField(); 2417 int vm = instr->VmField(); 2418 int m = instr->MField(); 2419 2420 bool to_integer = (instr->Bit(18) == 1); 2421 bool dp_operation = (instr->SzField() == 1); 2422 if (to_integer) { 2423 bool unsigned_integer = (instr->Bit(16) == 0); 2424 if (instr->Bit(7) != 1) { 2425 // Only rounding towards zero supported. 2426 UNIMPLEMENTED(); // Not used by V8. 2427 } 2428 2429 int dst = GlueRegCode(true, vd, d); 2430 int src = GlueRegCode(!dp_operation, vm, m); 2431 2432 if (dp_operation) { 2433 double val = get_double_from_d_register(src); 2434 2435 int sint = unsigned_integer ? static_cast<uint32_t>(val) : 2436 static_cast<int32_t>(val); 2437 2438 set_s_register_from_sinteger(dst, sint); 2439 } else { 2440 float val = get_float_from_s_register(src); 2441 2442 int sint = unsigned_integer ? static_cast<uint32_t>(val) : 2443 static_cast<int32_t>(val); 2444 2445 set_s_register_from_sinteger(dst, sint); 2446 } 2447 } else { 2448 bool unsigned_integer = (instr->Bit(7) == 0); 2449 2450 int dst = GlueRegCode(!dp_operation, vd, d); 2451 int src = GlueRegCode(true, vm, m); 2452 2453 int val = get_sinteger_from_s_register(src); 2454 2455 if (dp_operation) { 2456 if (unsigned_integer) { 2457 set_d_register_from_double(dst, 2458 static_cast<double>((uint32_t)val)); 2459 } else { 2460 set_d_register_from_double(dst, static_cast<double>(val)); 2461 } 2462 } else { 2463 if (unsigned_integer) { 2464 set_s_register_from_float(dst, 2465 static_cast<float>((uint32_t)val)); 2466 } else { 2467 set_s_register_from_float(dst, static_cast<float>(val)); 2468 } 2469 } 2470 } 2471} 2472 2473 2474// void Simulator::DecodeType6CoprocessorIns(Instr* instr) 2475// Decode Type 6 coprocessor instructions. 2476// Dm = vmov(Rt, Rt2) 2477// <Rt, Rt2> = vmov(Dm) 2478// Ddst = MEM(Rbase + 4*offset). 2479// MEM(Rbase + 4*offset) = Dsrc. 2480void Simulator::DecodeType6CoprocessorIns(Instr* instr) { 2481 ASSERT((instr->TypeField() == 6)); 2482 2483 if (instr->CoprocessorField() == 0xA) { 2484 switch (instr->OpcodeField()) { 2485 case 0x8: 2486 case 0xC: { // Load and store float to memory. 2487 int rn = instr->RnField(); 2488 int vd = instr->VdField(); 2489 int offset = instr->Immed8Field(); 2490 if (!instr->HasU()) { 2491 offset = -offset; 2492 } 2493 2494 int32_t address = get_register(rn) + 4 * offset; 2495 if (instr->HasL()) { 2496 // Load double from memory: vldr. 2497 set_s_register_from_sinteger(vd, ReadW(address, instr)); 2498 } else { 2499 // Store double to memory: vstr. 2500 WriteW(address, get_sinteger_from_s_register(vd), instr); 2501 } 2502 break; 2503 } 2504 default: 2505 UNIMPLEMENTED(); // Not used by V8. 2506 break; 2507 } 2508 } else if (instr->CoprocessorField() == 0xB) { 2509 switch (instr->OpcodeField()) { 2510 case 0x2: 2511 // Load and store double to two GP registers 2512 if (instr->Bits(7, 4) != 0x1) { 2513 UNIMPLEMENTED(); // Not used by V8. 2514 } else { 2515 int rt = instr->RtField(); 2516 int rn = instr->RnField(); 2517 int vm = instr->VmField(); 2518 if (instr->HasL()) { 2519 int32_t rt_int_value = get_sinteger_from_s_register(2*vm); 2520 int32_t rn_int_value = get_sinteger_from_s_register(2*vm+1); 2521 2522 set_register(rt, rt_int_value); 2523 set_register(rn, rn_int_value); 2524 } else { 2525 int32_t rs_val = get_register(rt); 2526 int32_t rn_val = get_register(rn); 2527 2528 set_s_register_from_sinteger(2*vm, rs_val); 2529 set_s_register_from_sinteger((2*vm+1), rn_val); 2530 } 2531 } 2532 break; 2533 case 0x8: 2534 case 0xC: { // Load and store double to memory. 2535 int rn = instr->RnField(); 2536 int vd = instr->VdField(); 2537 int offset = instr->Immed8Field(); 2538 if (!instr->HasU()) { 2539 offset = -offset; 2540 } 2541 int32_t address = get_register(rn) + 4 * offset; 2542 if (instr->HasL()) { 2543 // Load double from memory: vldr. 2544 set_s_register_from_sinteger(2*vd, ReadW(address, instr)); 2545 set_s_register_from_sinteger(2*vd + 1, ReadW(address + 4, instr)); 2546 } else { 2547 // Store double to memory: vstr. 2548 WriteW(address, get_sinteger_from_s_register(2*vd), instr); 2549 WriteW(address + 4, get_sinteger_from_s_register(2*vd + 1), instr); 2550 } 2551 break; 2552 } 2553 default: 2554 UNIMPLEMENTED(); // Not used by V8. 2555 break; 2556 } 2557 } else { 2558 UNIMPLEMENTED(); // Not used by V8. 2559 } 2560} 2561 2562 2563// Executes the current instruction. 2564void Simulator::InstructionDecode(Instr* instr) { 2565 if (v8::internal::FLAG_check_icache) { 2566 CheckICache(instr); 2567 } 2568 pc_modified_ = false; 2569 if (::v8::internal::FLAG_trace_sim) { 2570 disasm::NameConverter converter; 2571 disasm::Disassembler dasm(converter); 2572 // use a reasonably large buffer 2573 v8::internal::EmbeddedVector<char, 256> buffer; 2574 dasm.InstructionDecode(buffer, 2575 reinterpret_cast<byte*>(instr)); 2576 PrintF(" 0x%08x %s\n", instr, buffer.start()); 2577 } 2578 if (instr->ConditionField() == special_condition) { 2579 DecodeUnconditional(instr); 2580 } else if (ConditionallyExecute(instr)) { 2581 switch (instr->TypeField()) { 2582 case 0: 2583 case 1: { 2584 DecodeType01(instr); 2585 break; 2586 } 2587 case 2: { 2588 DecodeType2(instr); 2589 break; 2590 } 2591 case 3: { 2592 DecodeType3(instr); 2593 break; 2594 } 2595 case 4: { 2596 DecodeType4(instr); 2597 break; 2598 } 2599 case 5: { 2600 DecodeType5(instr); 2601 break; 2602 } 2603 case 6: { 2604 DecodeType6(instr); 2605 break; 2606 } 2607 case 7: { 2608 DecodeType7(instr); 2609 break; 2610 } 2611 default: { 2612 UNIMPLEMENTED(); 2613 break; 2614 } 2615 } 2616 } 2617 if (!pc_modified_) { 2618 set_register(pc, reinterpret_cast<int32_t>(instr) + Instr::kInstrSize); 2619 } 2620} 2621 2622 2623void Simulator::Execute() { 2624 // Get the PC to simulate. Cannot use the accessor here as we need the 2625 // raw PC value and not the one used as input to arithmetic instructions. 2626 int program_counter = get_pc(); 2627 2628 if (::v8::internal::FLAG_stop_sim_at == 0) { 2629 // Fast version of the dispatch loop without checking whether the simulator 2630 // should be stopping at a particular executed instruction. 2631 while (program_counter != end_sim_pc) { 2632 Instr* instr = reinterpret_cast<Instr*>(program_counter); 2633 icount_++; 2634 InstructionDecode(instr); 2635 program_counter = get_pc(); 2636 } 2637 } else { 2638 // FLAG_stop_sim_at is at the non-default value. Stop in the debugger when 2639 // we reach the particular instuction count. 2640 while (program_counter != end_sim_pc) { 2641 Instr* instr = reinterpret_cast<Instr*>(program_counter); 2642 icount_++; 2643 if (icount_ == ::v8::internal::FLAG_stop_sim_at) { 2644 Debugger dbg(this); 2645 dbg.Debug(); 2646 } else { 2647 InstructionDecode(instr); 2648 } 2649 program_counter = get_pc(); 2650 } 2651 } 2652} 2653 2654 2655int32_t Simulator::Call(byte* entry, int argument_count, ...) { 2656 va_list parameters; 2657 va_start(parameters, argument_count); 2658 // Setup arguments 2659 2660 // First four arguments passed in registers. 2661 ASSERT(argument_count >= 4); 2662 set_register(r0, va_arg(parameters, int32_t)); 2663 set_register(r1, va_arg(parameters, int32_t)); 2664 set_register(r2, va_arg(parameters, int32_t)); 2665 set_register(r3, va_arg(parameters, int32_t)); 2666 2667 // Remaining arguments passed on stack. 2668 int original_stack = get_register(sp); 2669 // Compute position of stack on entry to generated code. 2670 int entry_stack = (original_stack - (argument_count - 4) * sizeof(int32_t)); 2671 if (OS::ActivationFrameAlignment() != 0) { 2672 entry_stack &= -OS::ActivationFrameAlignment(); 2673 } 2674 // Store remaining arguments on stack, from low to high memory. 2675 intptr_t* stack_argument = reinterpret_cast<intptr_t*>(entry_stack); 2676 for (int i = 4; i < argument_count; i++) { 2677 stack_argument[i - 4] = va_arg(parameters, int32_t); 2678 } 2679 va_end(parameters); 2680 set_register(sp, entry_stack); 2681 2682 // Prepare to execute the code at entry 2683 set_register(pc, reinterpret_cast<int32_t>(entry)); 2684 // Put down marker for end of simulation. The simulator will stop simulation 2685 // when the PC reaches this value. By saving the "end simulation" value into 2686 // the LR the simulation stops when returning to this call point. 2687 set_register(lr, end_sim_pc); 2688 2689 // Remember the values of callee-saved registers. 2690 // The code below assumes that r9 is not used as sb (static base) in 2691 // simulator code and therefore is regarded as a callee-saved register. 2692 int32_t r4_val = get_register(r4); 2693 int32_t r5_val = get_register(r5); 2694 int32_t r6_val = get_register(r6); 2695 int32_t r7_val = get_register(r7); 2696 int32_t r8_val = get_register(r8); 2697 int32_t r9_val = get_register(r9); 2698 int32_t r10_val = get_register(r10); 2699 int32_t r11_val = get_register(r11); 2700 2701 // Setup the callee-saved registers with a known value. To be able to check 2702 // that they are preserved properly across JS execution. 2703 int32_t callee_saved_value = icount_; 2704 set_register(r4, callee_saved_value); 2705 set_register(r5, callee_saved_value); 2706 set_register(r6, callee_saved_value); 2707 set_register(r7, callee_saved_value); 2708 set_register(r8, callee_saved_value); 2709 set_register(r9, callee_saved_value); 2710 set_register(r10, callee_saved_value); 2711 set_register(r11, callee_saved_value); 2712 2713 // Start the simulation 2714 Execute(); 2715 2716 // Check that the callee-saved registers have been preserved. 2717 CHECK_EQ(callee_saved_value, get_register(r4)); 2718 CHECK_EQ(callee_saved_value, get_register(r5)); 2719 CHECK_EQ(callee_saved_value, get_register(r6)); 2720 CHECK_EQ(callee_saved_value, get_register(r7)); 2721 CHECK_EQ(callee_saved_value, get_register(r8)); 2722 CHECK_EQ(callee_saved_value, get_register(r9)); 2723 CHECK_EQ(callee_saved_value, get_register(r10)); 2724 CHECK_EQ(callee_saved_value, get_register(r11)); 2725 2726 // Restore callee-saved registers with the original value. 2727 set_register(r4, r4_val); 2728 set_register(r5, r5_val); 2729 set_register(r6, r6_val); 2730 set_register(r7, r7_val); 2731 set_register(r8, r8_val); 2732 set_register(r9, r9_val); 2733 set_register(r10, r10_val); 2734 set_register(r11, r11_val); 2735 2736 // Pop stack passed arguments. 2737 CHECK_EQ(entry_stack, get_register(sp)); 2738 set_register(sp, original_stack); 2739 2740 int32_t result = get_register(r0); 2741 return result; 2742} 2743 2744 2745uintptr_t Simulator::PushAddress(uintptr_t address) { 2746 int new_sp = get_register(sp) - sizeof(uintptr_t); 2747 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(new_sp); 2748 *stack_slot = address; 2749 set_register(sp, new_sp); 2750 return new_sp; 2751} 2752 2753 2754uintptr_t Simulator::PopAddress() { 2755 int current_sp = get_register(sp); 2756 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp); 2757 uintptr_t address = *stack_slot; 2758 set_register(sp, current_sp + sizeof(uintptr_t)); 2759 return address; 2760} 2761 2762} } // namespace assembler::arm 2763 2764#endif // __arm__ 2765 2766#endif // V8_TARGET_ARCH_ARM 2767