Lines Matching defs:PhysReg
185 unsigned PhysReg;
190 // Interference for PhysReg.
198 PhysReg = Reg;
218 /// Candidate info for for each PhysReg in AllocationOrder.
264 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
460 unsigned PhysReg;
461 while ((PhysReg = Order.next()))
462 if (!Matrix->checkInterference(VirtReg, PhysReg))
464 if (!PhysReg || Order.isHint())
465 return PhysReg;
467 // PhysReg is available, but there may be a better choice.
482 unsigned Cost = TRI->getCostPerUse(PhysReg);
486 return PhysReg;
488 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
491 return CheapReg ? CheapReg : PhysReg;
501 unsigned PhysReg;
502 while ((PhysReg = Order.next())) {
503 if (PhysReg == PrevReg)
506 MCRegUnitIterator Units(PhysReg, TRI);
513 // If no units have interference, break out with the current PhysReg.
517 if (PhysReg)
519 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
521 return PhysReg;
550 /// PhysReg can be evicted. When OnlyCheap is set, don't do anything
553 /// @param PhysReg Desired register for assignment.
554 /// @param IsHint True when PhysReg is VirtReg's preferred register.
558 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
561 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
578 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
625 !canReassign(*Intf, PhysReg)) {
640 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
649 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
654 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
716 while (unsigned PhysReg = Order.nextWithDups(OrderLimit)) {
717 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
722 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
724 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
729 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
733 BestPhys = PhysReg;
899 if (Cand.PhysReg)
931 // that all the through blocks have interference when PhysReg is unset.
1135 // - Candidate intervals can be assigned to Cand.PhysReg.
1193 while (unsigned PhysReg = Order.next()) {
1200 if (i == BestCand || !GlobalCand[i].PhysReg)
1215 Cand.reset(IntfCache, PhysReg);
1220 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
1223 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost);
1230 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1276 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
1285 assert(!Cand.PhysReg && "Compact region has no physreg");
1411 /// in order to use PhysReg between two entries in SA->UseSlots.
1415 void RAGreedy::calcGapWeights(unsigned PhysReg,
1431 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1466 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1578 while (unsigned PhysReg = Order.next()) {
1580 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
1581 calcGapWeights(PhysReg, GapWeight);
1584 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1603 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
1728 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1729 if (PhysReg || !NewVRegs.empty())
1730 return PhysReg;
1745 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1746 return PhysReg;
1753 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1754 if (PhysReg || !NewVRegs.empty())
1755 return PhysReg;
1771 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
1772 return PhysReg;
1782 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs))
1783 return PhysReg;
1803 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
1804 if (PhysReg || !NewVRegs.empty())
1805 return PhysReg;