Cross Reference: /external/qemu/softmmu

Lines Matching refs:mmu_idx
66                                                         int mmu_idx,
99                                                       int mmu_idx)
115     tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
122             ioaddr = env->iotlb[mmu_idx][index];
128              * mmu_idx is set to 1. */
129             if (memcheck_instrument_mmu && mmu_idx == 1 &&
140             do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
143                                                          mmu_idx, retaddr);
147              * mmu_idx is set to 1. */
148             if (memcheck_instrument_mmu && mmu_idx == 1) {
157                 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
160             addend = env->tlb_table[mmu_idx][index].addend;
168             env->tlb_table[mmu_idx][index].addr_read ^= TARGET_PAGE_MASK;
169             env->tlb_table[mmu_idx][index].addr_write ^= TARGET_PAGE_MASK;
172                 env->tlb_table[mmu_idx][index + 1].addr_read ^= TARGET_PAGE_MASK;
173                 env->tlb_table[mmu_idx][index + 1].addr_write ^= TARGET_PAGE_MASK;
182             do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
184         tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
192                                                         int mmu_idx,
203     tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
209             ioaddr = env->iotlb[mmu_idx][index];
217                                                           mmu_idx, retaddr);
219                                                           mmu_idx, retaddr);
229             addend = env->tlb_table[mmu_idx][index].addend;
234         tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
244                                                    int mmu_idx,
277                                                  int mmu_idx)
290     tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
297             ioaddr = env->iotlb[mmu_idx][index];
303              * mmu_idx is set to 1. */
304             if (memcheck_instrument_mmu && mmu_idx == 1 &&
315             do_unaligned_access(addr, 1, mmu_idx, retaddr);
318                                                    mmu_idx, retaddr);
322              * mmu_idx is set to 1. */
323             if (memcheck_instrument_mmu && mmu_idx == 1) {
333                 do_unaligned_access(addr, 1, mmu_idx, retaddr);
336             addend = env->tlb_table[mmu_idx][index].addend;
344             env->tlb_table[mmu_idx][index].addr_read ^= TARGET_PAGE_MASK;
345             env->tlb_table[mmu_idx][index].addr_write ^= TARGET_PAGE_MASK;
348                 env->tlb_table[mmu_idx][index + 1].addr_read ^= TARGET_PAGE_MASK;
349                 env->tlb_table[mmu_idx][index + 1].addr_write ^= TARGET_PAGE_MASK;
358             do_unaligned_access(addr, 1, mmu_idx, retaddr);
360         tlb_fill(addr, 1, mmu_idx, retaddr);
368                                                    int mmu_idx,
378     tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
384             ioaddr = env->iotlb[mmu_idx][index];
394                                           mmu_idx, retaddr);
397                                           mmu_idx, retaddr);
402             addend = env->tlb_table[mmu_idx][index].addend;
407         tlb_fill(addr, 1, mmu_idx, retaddr);