| /external/llvm/lib/MC/ |
| H A D | MCCodeGenInfo.cpp | 18 void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, argument
21 CMModel = CM;
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| /external/llvm/lib/Target/CppBackend/ |
| H A D | CPPTargetMachine.h | 27 Reloc::Model RM, CodeModel::Model CM,
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcMCTargetDesc.cpp | 65 CodeModel::Model CM,
70 if (CM == CodeModel::Default)
71 CM = RM == Reloc::PIC_ ? CodeModel::Medium : CodeModel::Small;
73 X->InitMCCodeGenInfo(RM, CM, OL);
78 CodeModel::Model CM,
83 if (CM == CodeModel::Default)
84 CM = CodeModel::Medium;
86 X->InitMCCodeGenInfo(RM, CM, OL);
64 createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
77 createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetMachine.cpp | 32 Reloc::Model RM, CodeModel::Model CM,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCTargetDesc.cpp | 70 CodeModel::Model CM,
75 X->InitMCCodeGenInfo(Reloc::Static, CM, OL);
69 createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430TargetMachine.cpp | 32 Reloc::Model RM, CodeModel::Model CM,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetMachine.cpp | 25 CodeModel::Model CM,
27 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
21 SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreTargetMachine.cpp | 26 Reloc::Model RM, CodeModel::Model CM,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDGPUTargetMachine.cpp | 44 Reloc::Model RM, CodeModel::Model CM,
48 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
41 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | BoolAssignmentChecker.cpp | 81 ConstraintManager &CM = C.getConstraintManager(); local
99 llvm::tie(stateGE, stateLT) = CM.assumeDual(state, *greaterThanEqualToZero);
135 llvm::tie(stateLE, stateGT) = CM.assumeDual(state, *lessThanEqToOne);
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| H A D | NonNullParamChecker.cpp | 115 ConstraintManager &CM = C.getConstraintManager(); local
117 llvm::tie(stateNotNull, stateNull) = CM.assumeDual(state, *DV);
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetMachine.cpp | 71 CodeModel::Model CM,
73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
67 HexagonTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/MSP430/MCTargetDesc/ |
| H A D | MSP430MCTargetDesc.cpp | 54 CodeModel::Model CM,
57 X->InitMCCodeGenInfo(RM, CM, OL);
53 createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXMCTargetDesc.cpp | 55 StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) {
57 X->InitMCCodeGenInfo(RM, CM, OL);
54 createNVPTXMCCodeGenInfo( StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/R600/ |
| H A D | AMDGPUTargetMachine.cpp | 54 Reloc::Model RM, CodeModel::Model CM,
58 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
51 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcTargetMachine.cpp | 31 Reloc::Model RM, CodeModel::Model CM,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
83 CodeModel::Model CM,
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
95 CodeModel::Model CM,
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| H A D | XCoreMCTargetDesc.cpp | 66 CodeModel::Model CM,
72 X->InitMCCodeGenInfo(RM, CM, OL);
65 createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDGPUTargetMachine.cpp | 44 Reloc::Model RM, CodeModel::Model CM,
48 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
41 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| H A D | AMDGPUMCTargetDesc.cpp | 57 CodeModel::Model CM,
60 X->InitMCCodeGenInfo(RM, CM, OL);
56 createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/CodeGen/ |
| H A D | LLVMTargetMachine.cpp | 79 Reloc::Model RM, CodeModel::Model CM,
82 CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
76 LLVMTargetMachine(const Target &T, StringRef Triple, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.cpp | 48 Reloc::Model RM, CodeModel::Model CM,
50 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73 Reloc::Model RM, CodeModel::Model CM,
75 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
99 Reloc::Model RM, CodeModel::Model CM,
101 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
70 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
96 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsMCTargetDesc.cpp | 107 CodeModel::Model CM,
110 if (CM == CodeModel::JITDefault)
114 X->InitMCCodeGenInfo(RM, CM, OL);
106 createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsTargetMachine.cpp | 57 Reloc::Model RM, CodeModel::Model CM,
60 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
119 Reloc::Model RM, CodeModel::Model CM,
121 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
128 Reloc::Model RM, CodeModel::Model CM,
130 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
55 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
117 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
126 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXTargetMachine.cpp | 71 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
85 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
87 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
93 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
95 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
69 NVPTXTargetMachine( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
83 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
91 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCMCTargetDesc.cpp | 83 CodeModel::Model CM,
94 if (CM == CodeModel::Default) {
98 CM = CodeModel::Medium;
100 X->InitMCCodeGenInfo(RM, CM, OL);
82 createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|