/external/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, argument 30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); 45 MachineInstr *DefMI = LastMI; local 61 DefMI = &*I; 65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 67 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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H A D | MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 96 if (DefMI->getParent() != MBB) 98 if (DefMI->isCopyLike()) { 99 Reg = DefMI->getOperand(1).getReg(); 101 DefMI = MRI->getVRegDef(Reg); 104 } else if (DefMI->isInsertSubreg()) { 105 Reg = DefMI->getOperand(2).getReg(); 107 DefMI = MRI->getVRegDef(Reg); 113 return DefMI; 148 MachineInstr *DefMI local [all...] |
H A D | ARMExpandPseudoInsts.cpp | 55 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 74 MachineInstrBuilder &DefMI) { 83 DefMI.addOperand(MO); 72 TransferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI) argument
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H A D | ARMBaseInstrInfo.cpp | 1690 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); local 1691 bool Invert = !DefMI; 1692 if (!DefMI) 1693 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1694 if (!DefMI) 1697 // Create a new predicated version of DefMI. 1700 DefMI->getDesc(), 1703 // Copy all the DefMI operands, excluding its (null) predicate. 1704 const MCInstrDesc &DefDesc = DefMI->getDesc(); 1707 NewMI.addOperand(DefMI 2273 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument 3100 adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr *DefMI, const MCInstrDesc *DefMCID, unsigned DefAlign) argument 3281 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3654 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3676 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | LiveRangeEdit.cpp | 45 const MachineInstr *DefMI, 47 assert(DefMI && "Missing instruction"); 49 if (!TII.isTriviallyReMaterializable(DefMI, aa)) 61 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); local 62 if (!DefMI) 64 checkRematerializable(VNI, DefMI, aa); 161 MachineInstr *DefMI = 0, *UseMI = 0; local 169 if (DefMI && DefMI != MI) 173 DefMI 44 checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *aa) argument [all...] |
H A D | PeepholeOptimizer.cpp | 338 MachineInstr *DefMI = MRI->getVRegDef(Src); local 339 if (!DefMI || !DefMI->isBitcast()) 343 NumDefs = DefMI->getDesc().getNumDefs(); 344 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs; 348 const MachineOperand &MO = DefMI->getOperand(i); 554 MachineInstr *DefMI = 0; local 556 FoldAsLoadDefReg, DefMI); 558 // Update LocalMIs since we replaced MI with FoldMI and deleted DefMI. 562 LocalMIs.erase(DefMI); [all...] |
H A D | TargetSchedule.cpp | 156 const MachineInstr *DefMI, unsigned DefOperIdx, 160 return TII->defaultDefLatency(&SchedModel, DefMI); 165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, 169 unsigned DefClass = DefMI->getDesc().getSchedClass(); 176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); 184 TII->defaultDefLatency(&SchedModel, DefMI)); 188 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); 189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); 212 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() 213 && !DefMI 155 computeOperandLatency( const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const argument 217 << *DefMI; local 251 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const argument [all...] |
H A D | PHIElimination.cpp | 154 MachineInstr *DefMI = *I; local 155 unsigned DefReg = DefMI->getOperand(0).getReg(); 158 LIS->RemoveMachineInstrFromMaps(DefMI); 159 DefMI->eraseFromParent(); 392 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 393 if (DefMI->isImplicitDef()) 394 ImpDefs.insert(DefMI);
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H A D | EarlyIfConversion.cpp | 244 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 245 if (!DefMI || DefMI->getParent() != Head) 247 if (InsertAfter.insert(DefMI)) 248 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); 249 if (DefMI->isTerminator()) {
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H A D | MachineCSE.cpp | 128 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 129 if (!DefMI->isCopy()) 131 unsigned SrcReg = DefMI->getOperand(1).getReg(); 134 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg()) 138 DEBUG(dbgs() << "Coalescing: " << *DefMI); 142 DefMI->eraseFromParent();
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H A D | StrongPHIElimination.cpp | 253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); local 254 if (DefMI) 255 PHISrcDefs[DefMI->getParent()].push_back(DefMI);
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H A D | TailDuplication.cpp | 236 MachineInstr *DefMI = MRI->getVRegDef(VReg); local 238 if (DefMI) { 239 DefBB = DefMI->getParent();
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H A D | TargetInstrInfo.cpp | 623 const MachineInstr *DefMI) const { 624 if (DefMI->isTransient()) 626 if (DefMI->mayLoad()) 628 if (isHighLatencyDef(DefMI->getOpcode())) 646 const MachineInstr *DefMI, 651 unsigned DefClass = DefMI->getDesc().getSchedClass(); 656 /// Both DefMI and UseMI must be valid. By default, call directly to the 660 const MachineInstr *DefMI, unsigned DefIdx, 662 unsigned DefClass = DefMI->getDesc().getSchedClass(); 671 const MachineInstr *DefMI) cons 645 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument 659 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 696 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
H A D | InlineSpiller.cpp | 112 MachineInstr *DefMI; member in struct:__anon21132::InlineSpiller::SibValueInfo 123 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {} 126 bool hasDef() const { return DefByOrigPHI || DefMI; } 334 if (SVI.DefMI) 335 OS << " def: " << *SVI.DefMI; 398 DepSV.DefMI = SV.DefMI; 486 return SVI->second.DefMI; 604 SVI->second.DefMI = MI; 625 return SVI->second.DefMI; 648 MachineInstr *DefMI = 0; local 723 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def); local [all...] |
H A D | TwoAddressInstructionPass.cpp | 407 MachineInstr *DefMI = &MI; local 413 if (!isPlainlyKilled(DefMI, Reg, LIS)) 422 DefMI = &*Begin; 427 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 919 MachineInstr *DefMI = &*DI; local 920 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike()) 922 if (DefMI == MI) 924 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI); [all...] |
H A D | RegisterCoalescer.cpp | 593 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); 594 if (!DefMI) 596 if (!DefMI->isCommutable()) 598 // If DefMI is a two-address instruction then commuting it will change the 600 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); 603 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 606 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 615 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); 641 << *DefMI); 645 MachineBasicBlock *MBB = DefMI 1422 computeWriteLanes(const MachineInstr *DefMI, bool &Redef) argument 1471 const MachineInstr *DefMI = 0; local [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 757 /// defined by the load we are trying to fold. DefMI returns the machine 763 MachineInstr *&DefMI) const { 770 /// then the caller may assume that DefMI has been erased from its parent 773 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, argument 806 const MachineInstr *DefMI, unsigned DefIdx, 813 const MachineInstr *DefMI, unsigned DefIdx, 829 const MachineInstr *DefMI) const; 832 const MachineInstr *DefMI) const; 846 const MachineInstr *DefMI, unsigned DefIdx, 855 const MachineInstr *DefMI, unsigne 844 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 810 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, argument 814 unsigned DefOpc = DefMI->getOpcode(); 817 if (!DefMI->getOperand(1).isImm()) 819 if (DefMI->getOperand(1).getImm() != 0) 873 DefMI->eraseFromParent();
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1542 MachineInstr *DefMI = I.getOperand().getParent(); local 1543 if (DefMI->getOpcode() != X86::MOVPC32r) 3616 MachineInstr *&DefMI) const { 3625 // Check whether we can move DefMI here. 3626 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 3627 assert(DefMI); 3629 if (!DefMI->isSafeToMove(this, 0, SawStore)) 3657 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI); 5011 const MachineInstr *DefMI, unsigned DefIdx, 5013 return isHighLatencyDef(DefMI 5009 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |