Searched defs:LLc (Results 1 - 7 of 7) sorted by relevance
| /external/valgrind/main/cachegrind/ |
| H A D | cg-arm.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, argument
46 *LLc = (cache_t) { 262144, 8, 64 };
|
| H A D | cg-ppc32.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, argument
46 *LLc = (cache_t) { 262144, 8, 64 };
|
| H A D | cg-ppc64.c | 40 void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc, argument
46 *LLc = (cache_t) { 262144, 8, 64 };
|
| H A D | cg-arch.c | 162 cache_t* LLc,
177 VG_(configure_caches)( I1c, D1c, LLc, all_caches_clo_defined );
184 check_cache_or_override ("LL", LLc, DEFINED(clo_LLc));
190 if (DEFINED(clo_LLc)) { *LLc = *clo_LLc; }
196 umsg_cache_img ("LL", LLc);
160 post_clo_init_configure_caches(cache_t* I1c, cache_t* D1c, cache_t* LLc, cache_t* clo_I1c, cache_t* clo_D1c, cache_t* clo_LLc) argument
|
| H A D | cg-x86-amd64.c | 59 * is returned via *LLc.
62 Int Intel_cache_info(Int level, cache_t* I1c, cache_t* D1c, cache_t* LLc) argument
72 copy it into *LLc. Hence if a L3 cache is specified, *LLc will
166 case 0x21: *LLc = (cache_t) { 256, 8, 64 }; L2_found = True; break;
169 case 0x39: *LLc = (cache_t) { 128, 4, 64 }; L2_found = True; break;
170 case 0x3c: *LLc = (cache_t) { 256, 4, 64 }; L2_found = True; break;
179 case 0x41: *LLc = (cache_t) { 128, 4, 32 }; L2_found = True; break;
180 case 0x42: *LLc = (cache_t) { 256, 4, 32 }; L2_found = True; break;
181 case 0x43: *LLc
366 AMD_cache_info(cache_t* I1c, cache_t* D1c, cache_t* LLc) argument
418 get_caches_from_CPUID(cache_t* I1c, cache_t* D1c, cache_t* LLc) argument
524 configure_caches(cache_t* I1c, cache_t* D1c, cache_t* LLc, Bool all_caches_clo_defined) argument
[all...] |
| H A D | cg_main.c | 1710 cache_t I1c, D1c, LLc; local
1728 VG_(post_clo_init_configure_caches)(&I1c, &D1c, &LLc,
1737 min_line_size = (LLc.line_size < min_line_size) ? LLc.line_size : min_line_size;
1755 cachesim_LL_initcache(LLc);
|
| /external/valgrind/main/callgrind/ |
| H A D | sim.c | 1277 cache_t I1c, D1c, LLc; local
1301 VG_(post_clo_init_configure_caches)(&I1c, &D1c, &LLc,
1315 CLG_(min_line_size) = (LLc.line_size < CLG_(min_line_size))
1316 ? LLc.line_size : CLG_(min_line_size);
1334 cachesim_initcache(LLc, &LL);
|
Completed in 112 milliseconds