Searched defs:Mask (Results 1 - 25 of 94) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.h34 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, argument
H A DMipsSEISelDAGToDAG.cpp47 unsigned Mask = MI.getOperand(1).getImm(); local
50 if (Mask & 1)
53 if (Mask & 2)
56 if (Mask & 4)
59 if (Mask & 8)
62 if (Mask & 16)
65 if (Mask & 32)
/external/chromium_org/third_party/leveldatabase/src/util/
H A Dcrc32c.h31 inline uint32_t Mask(uint32_t crc) { function in namespace:leveldb::crc32c
/external/clang/include/clang/AST/
H A DDeclAccessPair.h33 enum { Mask = 0x3 }; enumerator in enum:clang::DeclAccessPair::__anon14888
43 return (NamedDecl*) (~Mask & (uintptr_t) Ptr);
46 return AccessSpecifier(Mask & (uintptr_t) Ptr);
/external/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp92 int64_t Mask = 0xffff; local
94 Offset = OldOffset & Mask;
96 Mask >>= 1;
97 assert(Mask && "One offset must be OK");
/external/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp90 unsigned Mask; member in struct:__anon21532::FPS::LiveBundle
100 LiveBundle() : Mask(0), FixCount(0) {}
103 bool isFixed() const { return !Mask || FixCount; }
115 unsigned Mask = 0; local
121 Mask |= 1 << (Reg - X86::FP0);
123 return Mask;
296 /// Adjust the live registers to be the set in Mask.
297 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
397 const unsigned Mask = calcLiveInMask(MBB);
398 if (!Mask)
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/external/llvm/lib/Analysis/
H A DCostModel.cpp84 static bool isReverseVectorMask(SmallVectorImpl<int> &Mask) { argument
85 for (unsigned i = 0, MaskSize = Mask.size(); i < MaskSize; ++i)
86 if (Mask[i] > 0 && Mask[i] != (int)(MaskSize - 1 - i))
208 SmallVector<int, 16> Mask = Shuffle->getShuffleMask(); local
210 if (NumVecElems == Mask.size() && isReverseVectorMask(Mask))
/external/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp81 unsigned Mask = MBBI->getOperand(1).getImm(); local
87 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
573 unsigned Mask = (1 << NumBits) - 1;
574 if ((unsigned)Offset <= Mask * Scale) {
590 ImmedOffset = ImmedOffset & Mask;
603 Offset &= ~(Mask*Scale);
H A DThumb1RegisterInfo.cpp384 unsigned Mask = (1 << NumBits) - 1;
385 if (((Offset / Scale) & ~Mask) == 0) {
418 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
421 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
423 Offset = (Offset - Mask * Scale);
453 unsigned Mask = (1 << NumBits) - 1; variable
455 if ((unsigned)Offset <= Mask * Scale) {
470 Mask = (1 << NumBits) - 1;
478 ImmedOffset = ImmedOffset & Mask;
480 Offset &= ~(Mask * Scal
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H A DThumb2ITBlockPass.cpp194 unsigned Mask = 0, Pos = 3; local
208 Mask |= (NCC & 1) << Pos;
229 Mask |= (1 << Pos);
231 Mask |= (CC & 1) << 4;
232 MIB.addImm(Mask);
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.cpp138 uint64_t Mask = ((uint64_t)(-1) >> local
140 CurVal |= Value & Mask;
/external/llvm/lib/Target/R600/
H A DR600ExpandSpecialInstrs.cpp179 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); local
187 if (Mask) {
271 bool Mask = false; local
277 // Mask the write if the original instruction does not write to
279 Mask = (Chan != TRI.getHWRegChan(DstReg));
305 if (Mask) {
H A DR600TextureIntrinsicsReplacer.cpp126 Constant *Mask[] = { local
132 Value *SwizzleMask = ConstantVector::get(Mask);
/external/clang/lib/Driver/
H A DSanitizerArgs.h184 /// provides a sanitizer kind in \p Mask. For example, the argument list
203 /// a value in \p Mask. For instance, the argument
208 unsigned Mask) {
213 if (parse(A->getValue(I)) & Mask)
206 describeSanitizeArg(const llvm::opt::ArgList &Args, const llvm::opt::Arg *A, unsigned Mask) argument
/external/libnfc-nxp/src/
H A DphFriNfc_NdefRecord.c381 static uint8_t phFriNfc_NdefRecord_NdefFlag(uint8_t Flags,uint8_t Mask) argument
384 check_flag = Flags & Mask;
/external/llvm/include/llvm/ADT/
H A DBitVector.h181 // Mask off previous bits.
257 BitWord Mask = EMask - IMask; local
258 Bits[I / BITWORD_SIZE] |= Mask;
295 BitWord Mask = EMask - IMask; local
296 Bits[I / BITWORD_SIZE] &= ~Mask;
333 BitWord Mask = 1L << (Idx % BITWORD_SIZE);
334 return (Bits[Idx / BITWORD_SIZE] & Mask) != 0;
495 /// setBitsInMask - Add '1' bits from Mask to this vector. Don't resize.
496 /// This computes "*this |= Mask".
497 void setBitsInMask(const uint32_t *Mask, unsigne
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H A DSmallBitVector.h232 // Mask off previous bits.
311 uintptr_t Mask = EMask - IMask; local
312 setSmallBits(getSmallBits() | Mask);
342 uintptr_t Mask = EMask - IMask; local
343 setSmallBits(getSmallBits() & ~Mask);
523 /// setBitsInMask - Add '1' bits from Mask to this vector. Don't resize.
524 /// This computes "*this |= Mask".
525 void setBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) { argument
527 applyMask<true, false>(Mask, MaskWords);
529 getPointer()->setBitsInMask(Mask, MaskWord
534 clearBitsInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) argument
543 setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) argument
552 clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords = ~0u) argument
561 applyMask(const uint32_t *Mask, unsigned MaskWords) argument
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/external/llvm/include/llvm/CodeGen/
H A DMachineInstr.h165 unsigned Mask = BundledPred | BundledSucc; local
166 Flags = (Flags & Mask) | (flags & ~Mask);
1034 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombine.h237 Value *EvaluateInDifferentElementOrder(Value *V, ArrayRef<int> Mask);
307 bool MaskedValueIsZero(Value *V, const APInt &Mask, argument
309 return llvm::MaskedValueIsZero(V, Mask, TD, Depth);
369 Value *FoldLogicalPlusAnd(Value *LHS, Value *RHS, ConstantInt *Mask,
/external/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp28 // Mask manipulation functions.
35 static unsigned getMaskElt(unsigned Mask, unsigned Elt) { argument
36 return (Mask >> ((3-Elt)*4)) & 0xF;
39 static unsigned setMaskElt(unsigned Mask, unsigned Elt, unsigned NewVal) { argument
41 return (Mask & ~(0xF << FieldShift)) | (NewVal << FieldShift);
45 static bool isValidMask(unsigned short Mask) { argument
46 unsigned short UndefBits = Mask & 0x8888;
47 return (Mask & ((UndefBits >> 1)|(UndefBits>>2)|(UndefBits>>3))) == 0;
52 static bool hasUndefElements(unsigned short Mask) { argument
53 return (Mask
58 isOnlyLHSMask(unsigned short Mask) argument
73 getCompressedMask(unsigned short Mask) argument
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/external/llvm/include/llvm/Support/
H A DMathExtras.h59 T Mask = std::numeric_limits<T>::max() >> Shift; local
61 if ((Val & Mask) == 0) {
66 Mask >>= Shift;
/external/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp1055 uint64_t Mask = (1ULL << Num1s) - 1; local
1058 Mask = (Mask >> Rotation)
1059 | ((Mask << (Width - Rotation)) & WidthMask);
1061 Imm = Mask;
1063 Mask <<= Width;
1064 Imm |= Mask;
/external/chromium_org/chromeos/network/onc/
H A Donc_utils.cc243 static scoped_ptr<base::DictionaryValue> Mask( function in class:chromeos::onc::__anon7339::OncMaskValues
271 // Mask to insert in place of the sensitive values.
281 return OncMaskValues::Mask(signature, onc_object, mask);
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/
H A Dradeon_optimize.c40 unsigned int Mask; member in struct:src_clobbered_reads_cb_data
113 && (rc_swizzle_to_writemask(src->Swizzle) & sc_data->Mask)) {
134 sc_data.Mask = mask;
/external/llvm/include/llvm/Analysis/
H A DScalarEvolution.h192 static SCEV::NoWrapFlags maskFlags(SCEV::NoWrapFlags Flags, int Mask) { argument
193 return (SCEV::NoWrapFlags)(Flags & Mask);

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