Searched refs:CPU_TLB_ENTRY_BITS (Results 1 - 8 of 8) sorted by relevance

/external/qemu/
H A Dcpu-defs.h80 #define CPU_TLB_ENTRY_BITS 4 macro
82 #define CPU_TLB_ENTRY_BITS 5 macro
99 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
105 extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1];
/external/qemu/tcg/x86_64/
H A Dtcg-target.c587 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
593 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
782 tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
788 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
1430 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
/external/qemu/tcg/ppc/
H A Dtcg-target.c559 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
560 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
561 | ME (31 - CPU_TLB_ENTRY_BITS)
755 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
756 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
757 | ME (31 - CPU_TLB_ENTRY_BITS)
/external/qemu/tcg/ppc64/
H A Dtcg-target.c578 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
579 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
580 | ME (31 - CPU_TLB_ENTRY_BITS)
598 CPU_TLB_ENTRY_BITS,
599 63 - CPU_TLB_ENTRY_BITS);
/external/qemu/tcg/arm/
H A Dtcg-target.c954 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
988 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
998 TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
1211 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1218 TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
1788 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
/external/qemu/tcg/sparc/
H A Dtcg-target.c767 tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
774 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
978 tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
986 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
/external/qemu/tcg/i386/
H A Dtcg-target.c1021 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1026 (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);
1956 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
/external/qemu/tcg/hppa/
H A Dtcg-target.c906 r1 <<= CPU_TLB_ENTRY_BITS;
908 and place them at CPU_TLB_ENTRY_BITS. We can combine the first two
910 CPU_TLB_ENTRY_BITS is > 3, so we can't merge that shift with the
913 tcg_out_shli(s, r1, r1, CPU_TLB_ENTRY_BITS);

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