| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/ |
| H A D | r300_cb.h | 132 OUT_CB(CP_PACKET0(register, 0)); \
140 OUT_CB(CP_PACKET0(register, (count) - 1)); \
145 OUT_CB(CP_PACKET0(register, (count) - 1) | RADEON_ONE_REG_WR); \
|
| H A D | r300_cs.h | 83 OUT_CS(CP_PACKET0(register, 0)); \
90 OUT_CS(CP_PACKET0((register), ((count) - 1)))
93 OUT_CS(CP_PACKET0((register), ((count) - 1)) | RADEON_ONE_REG_WR)
|
| H A D | r300_reg.h | 3548 #define CP_PACKET0(register, count) \ macro
|
| /external/mesa3d/src/gallium/drivers/r300/ |
| H A D | r300_cb.h | 132 OUT_CB(CP_PACKET0(register, 0)); \
140 OUT_CB(CP_PACKET0(register, (count) - 1)); \
145 OUT_CB(CP_PACKET0(register, (count) - 1) | RADEON_ONE_REG_WR); \
|
| H A D | r300_cs.h | 83 OUT_CS(CP_PACKET0(register, 0)); \
90 OUT_CS(CP_PACKET0((register), ((count) - 1)))
93 OUT_CS(CP_PACKET0((register), ((count) - 1)) | RADEON_ONE_REG_WR)
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
| H A D | radeon_state_init.c | 163 return CP_PACKET0(packet[id].start, packet[id].len - 1);
243 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
245 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
254 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
372 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
376 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
379 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
383 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
385 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
390 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSE
[all...] |
| H A D | radeon_cmdbuf.h | 20 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) macro
|
| H A D | radeon_ioctl.c | 104 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
106 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
109 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
115 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
|
| H A D | radeon_blit.c | 36 return CP_PACKET0(reg, count - 1);
|
| H A D | radeon_context.c | 138 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| H A D | radeon_state_init.c | 163 return CP_PACKET0(packet[id].start, packet[id].len - 1);
243 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
245 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
254 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
372 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
376 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
379 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
383 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
385 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
390 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSE
[all...] |
| H A D | radeon_cmdbuf.h | 20 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) macro
|
| H A D | radeon_ioctl.c | 104 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
106 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
109 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
115 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
|
| H A D | radeon_blit.c | 36 return CP_PACKET0(reg, count - 1);
|
| H A D | radeon_context.c | 138 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/ |
| H A D | radeon_cmdbuf.h | 20 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) macro
|
| H A D | r200_state_init.c | 168 return CP_PACKET0(packet[id].start, packet[id].len - 1);
281 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
283 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
297 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
299 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
310 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
319 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
490 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
494 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
497 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITC
[all...] |
| H A D | r200_blit.c | 36 return CP_PACKET0(reg, count - 1);
|
| H A D | r200_cmdbuf.c | 215 OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0));
|
| H A D | r200_context.c | 173 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
|
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| H A D | radeon_cmdbuf.h | 20 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2)) macro
|
| H A D | r200_state_init.c | 168 return CP_PACKET0(packet[id].start, packet[id].len - 1);
281 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
283 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
297 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
299 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
310 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
319 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
490 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
494 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
497 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITC
[all...] |
| H A D | r200_blit.c | 36 return CP_PACKET0(reg, count - 1);
|
| H A D | r200_cmdbuf.c | 215 OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0));
|
| H A D | r200_context.c | 173 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
|