/external/llvm/lib/Target/XCore/ |
H A D | XCoreSubtarget.cpp | 27 const std::string &CPU, const std::string &FS) 28 : XCoreGenSubtargetInfo(TT, CPU, FS) 26 XCoreSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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H A D | XCoreSubtarget.h | 35 const std::string &FS); 39 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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H A D | XCoreTargetMachine.cpp | 24 StringRef CPU, StringRef FS, 28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 29 Subtarget(TT, CPU, FS), 23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430Subtarget.cpp | 28 const std::string &FS) : 29 MSP430GenSubtargetInfo(TT, CPU, FS) { 33 ParseSubtargetFeatures(CPUName, FS); 26 MSP430Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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H A D | MSP430Subtarget.h | 34 const std::string &FS); 38 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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H A D | MSP430TargetMachine.cpp | 30 StringRef FS, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 35 Subtarget(TT, CPU, FS), 27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64Subtarget.cpp | 28 AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS) argument 29 : AArch64GenSubtargetInfo(TT, CPU, FS), HasNEON(false), HasCrypto(false), 32 ParseSubtargetFeatures(CPU, FS);
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H A D | AArch64Subtarget.h | 40 AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS); 44 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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H A D | AArch64TargetMachine.cpp | 30 StringRef CPU, StringRef FS, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 35 Subtarget(TT, CPU, FS), 29 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcSubtarget.cpp | 28 const std::string &FS, bool is64Bit) : 29 SparcGenSubtargetInfo(TT, CPU, FS), 46 ParseSubtargetFeatures(CPUName, FS); 27 SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
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H A D | SparcTargetMachine.cpp | 29 StringRef CPU, StringRef FS, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 35 Subtarget(TT, CPU, FS, is64bit), 80 StringRef FS, 85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 92 StringRef FS, 97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument 78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | SparcSubtarget.h | 35 const std::string &FS, bool is64bit); 43 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXSubtarget.cpp | 24 const std::string &FS, bool is64Bit) 25 : NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0), 38 ParseSubtargetFeatures((CPU.empty() ? defCPU : CPU), FS); 40 // Get the TargetName from the FS if available 41 if (FS.empty() && CPU.empty()) 23 NVPTXSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
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H A D | NVPTXTargetMachine.cpp | 70 const Target &T, StringRef TT, StringRef CPU, StringRef FS, 73 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 74 Subtarget(TT, CPU, FS, is64bit), DL(Subtarget.getDataLayout()), 84 const Target &T, StringRef TT, StringRef CPU, StringRef FS, 87 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 92 const Target &T, StringRef TT, StringRef CPU, StringRef FS, 95 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 69 NVPTXTargetMachine( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument 83 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 91 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/clang/lib/Analysis/ |
H A D | FormatStringParsing.h | 47 bool ParseLengthModifier(FormatSpecifier &FS, const char *&Beg, const char *E, 51 T FS; member in class:clang::analyze_format_string::SpecifierResult 59 : FS(fs), Start(start), Stop(false) {} 66 return FS; 68 const T &getValue() { return FS; }
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZSubtarget.cpp | 22 const std::string &FS) 23 : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false), 30 ParseSubtargetFeatures(CPUName, FS); 20 SystemZSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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H A D | SystemZSubtarget.h | 39 const std::string &FS); 42 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/external/llvm/lib/Target/CppBackend/ |
H A D | CPPTargetMachine.h | 26 StringRef CPU, StringRef FS, const TargetOptions &Options, 29 : TargetMachine(T, TT, CPU, FS, Options) {} 25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCSubtarget.cpp | 33 const std::string &FS, bool is64Bit) 34 : PPCGenSubtargetInfo(TT, CPU, FS) 38 resetSubtargetFeatures(CPU, FS); 61 std::string FS = local 63 if (!FS.empty()) { 65 resetSubtargetFeatures(CPU, FS); 95 void PPCSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { argument 110 std::string FullFS = FS; 32 PPCSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
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/external/llvm/lib/MC/ |
H A D | MCSubtargetInfo.cpp | 25 MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) { argument 26 SubtargetFeatures Features(FS); 37 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, argument 62 InitMCProcessorInfo(CPU, FS); 74 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) { argument 76 FeatureBits = Features.ToggleFeature(FeatureBits, FS,
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUSubtarget.h | 43 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS); 47 virtual void ParseSubtargetFeatures(llvm::StringRef CPU, llvm::StringRef FS);
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H A D | AMDGPUSubtarget.cpp | 23 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : argument 24 AMDGPUGenSubtargetInfo(TT, CPU, FS), mDumpCode(false) { 35 ParseSubtargetFeatures(GPU, FS);
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUSubtarget.h | 55 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS); 58 virtual void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUSubtarget.h | 43 AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS); 47 virtual void ParseSubtargetFeatures(llvm::StringRef CPU, llvm::StringRef FS);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSubtarget.cpp | 49 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): argument 50 HexagonGenSubtargetInfo(TT, CPU, FS), 70 ParseSubtargetFeatures(CPUString, FS);
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