Searched refs:NV50_3D (Results 1 - 25 of 26) sorted by relevance

12

/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/
H A Dnv50_screen.c308 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
361 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
364 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
366 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
369 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
373 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
375 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
379 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
383 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
386 BEGIN_NV04(push, NV50_3D(CSAA_ENABL
[all...]
H A Dnv50_shader_state.c62 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
74 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
76 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
91 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
96 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
101 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
156 BEGIN_NV04(push, NV50_3D(VP_ATTR_EN(0)), 2);
159 BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_RESULT), 1);
161 BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_TEMP), 1);
163 BEGIN_NV04(push, NV50_3D(VP_START_I
[all...]
H A Dnv50_vbo.c149 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
156 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
162 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
168 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
171 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
255 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
258 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
309 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
317 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
340 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANC
[all...]
H A Dnv50_state_validate.c15 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
17 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
26 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
33 BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
36 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
41 BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
44 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
68 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
74 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
76 BEGIN_NV04(push, NV50_3D(ZETA_HORI
[all...]
H A Dnv50_surface.c281 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
290 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
292 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
298 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
304 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
308 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
314 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
318 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
343 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
349 BEGIN_NV04(push, NV50_3D(CLEAR_STENCI
[all...]
H A Dnv50_push.c77 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
89 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
110 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
122 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
143 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
155 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
168 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
273 BEGIN_NV04(ctx.push, NV50_3D(PRIM_RESTART_ENABLE), 2);
278 BEGIN_NV04(ctx.push, NV50_3D(PRIM_RESTART_ENABLE), 1);
284 BEGIN_NV04(ctx.push, NV50_3D(VERTEX_BEGIN_G
[all...]
H A Dnv50_tex.c212 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
250 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
261 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
265 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
281 BEGIN_NV04(nv50->base.pushbuf, NV50_3D(TIC_FLUSH), 1);
297 BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
311 BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
315 BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
331 BEGIN_NV04(nv50->base.pushbuf, NV50_3D(TSC_FLUSH), 1);
H A Dnv50_stateobj.h10 (so)->state[(so)->size++] = NV50_FIFO_PKHDR(NV50_3D(m), s)
H A Dnv50_query.c134 BEGIN_NV04(push, NV50_3D(QUERY_ADDRESS_HIGH), 4);
169 BEGIN_NV04(push, NV50_3D(COUNTER_RESET), 1);
171 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
205 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
333 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
345 BEGIN_NV04(push, NV50_3D(COND_ADDRESS_HIGH), 3);
H A Dnv50_winsys.h51 #define NV50_3D(n) SUBC_3D(NV50_3D_##n) macro
H A Dnv50_transfer.c406 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
410 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
412 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
H A Dnv50_context.c53 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
H A Dnv50_program.c416 BEGIN_NV04(nv50->base.pushbuf, NV50_3D(CODE_CB_FLUSH), 1);
/external/mesa3d/src/gallium/drivers/nv50/
H A Dnv50_screen.c308 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
361 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
364 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
366 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
369 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
373 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
375 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
379 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
383 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
386 BEGIN_NV04(push, NV50_3D(CSAA_ENABL
[all...]
H A Dnv50_shader_state.c62 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
74 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
76 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
91 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
96 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
101 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
156 BEGIN_NV04(push, NV50_3D(VP_ATTR_EN(0)), 2);
159 BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_RESULT), 1);
161 BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_TEMP), 1);
163 BEGIN_NV04(push, NV50_3D(VP_START_I
[all...]
H A Dnv50_vbo.c149 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
156 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
162 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
168 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
171 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
255 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
258 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
309 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
317 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
340 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANC
[all...]
H A Dnv50_state_validate.c15 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
17 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
26 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
33 BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
36 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
41 BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
44 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
68 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
74 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
76 BEGIN_NV04(push, NV50_3D(ZETA_HORI
[all...]
H A Dnv50_surface.c281 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
290 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
292 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
298 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
304 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
308 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
314 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(0)), 2);
318 BEGIN_NV04(push, NV50_3D(CLEAR_BUFFERS), 1);
343 BEGIN_NV04(push, NV50_3D(CLEAR_DEPTH), 1);
349 BEGIN_NV04(push, NV50_3D(CLEAR_STENCI
[all...]
H A Dnv50_push.c77 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
89 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
110 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
122 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
143 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
155 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
168 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
273 BEGIN_NV04(ctx.push, NV50_3D(PRIM_RESTART_ENABLE), 2);
278 BEGIN_NV04(ctx.push, NV50_3D(PRIM_RESTART_ENABLE), 1);
284 BEGIN_NV04(ctx.push, NV50_3D(VERTEX_BEGIN_G
[all...]
H A Dnv50_tex.c212 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
250 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
261 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
265 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
281 BEGIN_NV04(nv50->base.pushbuf, NV50_3D(TIC_FLUSH), 1);
297 BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
311 BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
315 BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
331 BEGIN_NV04(nv50->base.pushbuf, NV50_3D(TSC_FLUSH), 1);
H A Dnv50_stateobj.h10 (so)->state[(so)->size++] = NV50_FIFO_PKHDR(NV50_3D(m), s)
H A Dnv50_query.c134 BEGIN_NV04(push, NV50_3D(QUERY_ADDRESS_HIGH), 4);
169 BEGIN_NV04(push, NV50_3D(COUNTER_RESET), 1);
171 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
205 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
333 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
345 BEGIN_NV04(push, NV50_3D(COND_ADDRESS_HIGH), 3);
H A Dnv50_winsys.h51 #define NV50_3D(n) SUBC_3D(NV50_3D_##n) macro
H A Dnv50_transfer.c406 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
410 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
412 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
H A Dnv50_context.c53 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);

Completed in 196 milliseconds

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