| /external/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 31 const RegisterClassInfo &RegClassInfo)
35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
29 AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo) argument
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| H A D | AllocationOrder.h | 37 /// @param RegClassInfo Information about reserved and allocatable registers.
40 const RegisterClassInfo &RegClassInfo);
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| H A D | RegAllocBase.h | 66 RegisterClassInfo RegClassInfo; member in class:llvm::RegAllocBase
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| H A D | RegAllocBase.cpp | 62 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
122 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
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| H A D | CriticalAntiDepBreaker.h | 39 const RegisterClassInfo &RegClassInfo; member in class:llvm::CriticalAntiDepBreaker
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| H A D | AggressiveAntiDepBreaker.h | 122 const RegisterClassInfo &RegClassInfo; member in class:llvm::AggressiveAntiDepBreaker
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| H A D | RegAllocGreedy.cpp | 500 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
600 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
601 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
700 unsigned MinCost = RegClassInfo.getMinCost(RC);
710 OrderLimit = RegClassInfo.getLastCostChange(RC);
722 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
1044 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1311 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1362 if (!RegClassInfo.isProperSubClass(MRI->getRegClass(VirtReg.reg)))
1770 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
[all...] |
| H A D | PostRASchedulerList.cpp | 83 RegisterClassInfo RegClassInfo; member in class:__anon21167::PostRAScheduler
260 RegClassInfo.runOnMachineFunction(Fn);
289 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
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| H A D | RegAllocBasic.cpp | 230 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
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| H A D | CriticalAntiDepBreaker.cpp | 35 RegClassInfo(RCI),
366 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
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| H A D | MachineScheduler.cpp | 75 RegClassInfo = new RegisterClassInfo();
79 delete RegClassInfo;
210 RegClassInfo->runOnMachineFunction(*MF);
461 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
462 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
498 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
525 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
589 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
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| H A D | RegAllocFast.cpp | 60 RegisterClassInfo RegClassInfo; member in class:__anon21172::RAFast
535 ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
1073 RegClassInfo.runOnMachineFunction(Fn);
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| H A D | AggressiveAntiDepBreaker.cpp | 123 RegClassInfo(RCI),
602 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
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| H A D | RegisterCoalescer.cpp | 87 RegisterClassInfo RegClassInfo; member in class:__anon21179::RegisterCoalescer
1138 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
2221 RegClassInfo.runOnMachineFunction(fn);
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineScheduler.h | 57 RegisterClassInfo *RegClassInfo; member in struct:llvm::MachineSchedContext
207 RegisterClassInfo *RegClassInfo; member in class:llvm::ScheduleDAGMI
256 AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S), DFSResult(0),
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