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Searched refs:Rn (Results 1 - 13 of 13) sorted by relevance

/external/llvm/lib/Target/ARM/Disassembler/
H A D	ARMDisassembler.cpp	1210 // Writeback not allowed if Rn is in the target list. 1303 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 1348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1444 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 1463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1504 if (writeback && (Rn == 15 \|\| Rn == Rt)) 1549 unsigned Rn local 1594 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 1784 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 1815 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 1837 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2068 unsigned Rn = fieldFromInstruction(Insn, 0, 4); local 2097 unsigned Rn = fieldFromInstruction(Val, 13, 4); local 2115 unsigned Rn = fieldFromInstruction(Val, 9, 4); local 2213 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2538 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2808 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2855 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2903 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 2938 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3081 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3163 unsigned Rn = fieldFromInstruction(Val, 0, 3); local 3178 unsigned Rn = fieldFromInstruction(Val, 0, 3); local 3210 unsigned Rn = fieldFromInstruction(Val, 6, 4); local 3239 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3309 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3373 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3438 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3536 unsigned Rn = fieldFromInstruction(Val, 9, 4); local 3551 unsigned Rn = fieldFromInstruction(Val, 8, 4); local 3579 unsigned Rn = fieldFromInstruction(Val, 9, 4); local 3626 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3686 unsigned Rn = fieldFromInstruction(Val, 13, 4); local 3806 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3953 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3975 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 3998 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4023 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4051 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4076 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4101 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4168 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4234 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4301 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4365 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4435 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4499 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4580 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4726 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4763 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4821 unsigned Rn = fieldFromInstruction(Insn, 16, 4); local 4917 unsigned Rn = fieldFromInstruction(Val, 16, 4); local [all...]
/external/qemu/
H A D	trace.c	896 int Rn = (insn >> 12) & 15; local 899 result += _interlock_use(Rn); 901 if (Rn != 0) /* UNDEFINED */ 934 int Rn = (insn >> 16) & 15; local 936 result += _interlock_use(Rn) + _interlock_use(Rm); 943 int Rn = (insn >> 16) & 15; local 945 result += _interlock_use(Rn); 957 int Rn = (insn >> 16) & 15; local 959 result += _interlock_use(Rn) + _interlock_use(Rm); 970 int Rn local 1018 int Rn = (insn >> 16) & 15; local 1035 int Rn = (insn >> 12) & 15; local 1042 int Rn = (insn >> 16) & 15; local 1060 int Rn = (insn >> 16) & 15; local 1077 int Rn = (insn >> 16) & 15; local 1110 int Rn = (insn >> 16) & 15; local 1199 int Rn = (insn >> 3) & 7; local 1239 int Rn = (insn & 7) \| ((insn >> 4) & 0x8); local 1270 int Rn = (insn >> 3) & 7; local 1300 int Rn = (insn >> 3) & 7; local 1309 int Rn = (insn >> 3) & 7; local 1319 int Rn = (insn >> 3) & 7; local 1329 int Rn = (insn >> 3) & 7; local 1338 int Rn = (insn >> 3) & 7; local [all...]
H A D	arm-dis.c	`3450 unsigned int Rn = (given & 0x000f0000) >> 16; local 3458 func (stream, "[%s", arm_regnames[Rn]); 3461 else if (Rn == 15) /* 12-bit negative immediate offset */ 3517 if (Rn == 15) 3531 unsigned int Rn = (given & 0x000f0000) >> 16; local 3534 func (stream, "[%s", arm_regnames[Rn]);`
/external/llvm/lib/Target/AArch64/Disassembler/
H A D	AArch64Disassembler.cpp	475 unsigned Rn = fieldFromInstruction(Insn, 5, 5); local 495 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 500 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder); 569 unsigned Rn = fieldFromInstruction(Insn, 5, 5); local 574 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 577 DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder); 593 unsigned Rn = fieldFromInstruction(Insn, 5, 5); local 606 // Rn_wb, Rt, Rt2, Rn, Imm 607 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 616 if (Indexed && V == 0 && Rn ! 676 unsigned Rn = fieldFromInstruction(Val, 5, 5); local 756 unsigned Rn = fieldFromInstruction(Insn, 5, 5); local [all...]
/external/chromium_org/v8/src/arm/
H A D	disasm-arm.cc	117 void FormatNeonMemory(int Rn, int align, int Rm); 330 if (format[1] == 'n') { // 'rn: Rn register 443 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { argument 445 "[r%d", Rn); 742 // Rn field to encode it. 747 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 748 // Rn field to encode the Rd register and the Rd field to encode 749 // the Rn register. 753 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 754 // Rn fiel 1598 int Rn = instr->VnValue(); local 1611 int Rn = instr->VnValue(); local 1628 int Rn = instr->Bits(19, 16); local [all...]
H A D	simulator-arm.cc	2107 // Rn field to encode it. 2120 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 2121 // Rn field to encode the Rd register and the Rd field to encode 2122 // the Rn register. 2136 // when referring to the target registers. They are mapped to the Rn 2139 // RdHi == Rn (This is confusingly stored in variable rd here 2141 // Rn field to encode the Rd register. Good luck figuring 3582 int Rn = instr->VnValue(); local 3585 int32_t address = get_register(Rn); 3615 set_register(Rn, addres 3623 int Rn = instr->VnValue(); local [all...]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A D	ARMMCCodeEmitter.cpp	735 // [Rn, Rm] 737 // {2-0} = Rn 740 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); local 742 return (Rm << 3) \| Rn; 757 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 837 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. 956 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local 967 // {16-13} = Rn 975 Binary \|= Rn << 13; 986 // {17-14} Rn 991 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local 1063 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. local 1073 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local 1108 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); local [all...]
/external/llvm/lib/Target/ARM/
H A D	ARMBaseInstrInfo.cpp	`2525 unsigned Rn = MI->getOperand(2).getReg(); local 2529 return (Rt == Rn) ? 3 : 2; 2549 unsigned Rn = MI->getOperand(3).getReg(); local 2553 return (Rt == Rn) ? 4 : 3; 2558 unsigned Rn = MI->getOperand(3).getReg(); local 2559 return (Rt == Rn) ? 4 : 3; 2594 unsigned Rn = MI->getOperand(2).getReg(); local 2595 return (Rt == Rn) ? 3 : 2;`
/external/v8/src/arm/
H A D	disasm-arm.cc	`324 if (format[1] == 'n') { // 'rn: Rn register 692 // Rn field to encode it. 696 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 697 // Rn field to encode the Rd register and the Rd field to encode 698 // the Rn register. 703 // when referring to the target registers. They are mapped to the Rn 706 // RdHi == Rn field`
/external/valgrind/main/none/tests/arm/
H A D	vfp.stdout.exp	871 vldr d9, [r6, #+4] :: Dd 0x0000011a 0x00000dd3 (int) (Rn + shift) 0x0dd3 872 vldr d16, [r9, #-4] :: Dd 0x00000cc2 0x00000bb1 (int) (Rn + shift) 0x0bb1 873 vldr d30, [r12] :: Dd 0x00000dd3 0x00000cc2 (int) (Rn + shift) 0x0cc2 874 vldr d22, [r9, #+8] :: Dd 0x0000022b 0x0000011a (int) (Rn + shift) 0x011a 875 vldr d29, [r2, #-8] :: Dd 0x00000bb1 0x00000aa0 (int) (Rn + shift) 0x0aa0 876 vldr d8, [r8, #+8] :: Dd 0x0000022b 0x0000011a (int) (Rn + shift) 0x011a 877 vldr d11, [r12, #-4] :: Dd 0x00000cc2 0x00000bb1 (int) (Rn + shift) 0x0bb1 878 vldr d18, [r3] :: Dd 0x00000dd3 0x00000cc2 (int) (Rn + shift) 0x0cc2 879 vldr d5, [r10, #+8] :: Dd 0x0000022b 0x0000011a (int) (Rn + shift) 0x011a 880 vldr d17, [r10] :: Dd 0x00000dd3 0x00000cc2 (int) (Rn [all...]
H A D	v6intThumb.stdout.exp	`558 ADDS-16 Rd, Rn, #imm3 567 ADDS-16 Rd, Rn, Rm 620 SUBS-16 Rd, Rn, Rm 673 ADDS-16 Rn, #uimm8 690 SUBS-16 Rn, #uimm8 707 CMP-16 Rn, #uimm8 736 MOVS-16 Rn, #uimm8 832 (T3) ADD{S}.W Rd, Rn, #constT [allegedly] 937 (T4) ADDW Rd, Rn, #uimm12 962 (T3) CMP.W Rn, #const [all...]`
/external/llvm/lib/Target/ARM/AsmParser/
H A D	ARMAsmParser.cpp	4093 // If we have a three-operand form, make sure to set Rn to be the operand 5303 unsigned Rn = Inst.getOperand(0).getReg(); local 5308 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5702 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5724 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5748 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5774 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5800 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5822 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5846 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7127 unsigned Rn = Inst.getOperand(0).getReg(); local 7151 unsigned Rn = Inst.getOperand(0).getReg(); local [all...]
/external/chromium_org/third_party/libjingle/source/talk/media/testdata/
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