Searched refs:ShiftReg (Results 1 - 3 of 3) sorted by relevance

/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp1145 unsigned ShiftReg = RI.createVirtualRegister(RC); local
1161 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1163 // ShiftReg2 = shift ShiftReg
1165 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1172 .addReg(ShiftReg);
1180 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp407 unsigned ShiftReg; member in struct:__anon21351::ARMOperand::RegShiftedRegOp
1542 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
2261 unsigned ShiftReg,
2267 Op->RegShiftedReg.ShiftReg = ShiftReg;
2535 << " " << RegShiftedReg.ShiftReg << ">";
2689 int ShiftReg = 0; local
2694 ShiftReg = SrcReg;
2729 ShiftReg = tryParseRegister();
2730 if (ShiftReg
2259 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
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/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp5947 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); local
5992 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6001 .addReg(incr).addReg(ShiftReg);
6009 .addReg(Mask2Reg).addReg(ShiftReg);
6034 .addReg(ShiftReg);
6539 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); local
6594 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6603 .addReg(newval).addReg(ShiftReg);
6605 .addReg(oldval).addReg(ShiftReg);
6614 .addReg(Mask2Reg).addReg(ShiftReg);
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